Three-dimensional memory device and method for forming the same

Abstract

A three-dimensional (3D) memory device includes a plurality of memory stacks arranged along a first direction and a dummy block structure disposed between two adjacent memory stacks. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction. A channel structure extends through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A first isolation structure is disposed between the dummy block structure and one of the plurality of memory stacks. A substrate is disposed below the plurality of memory stacks, the dummy block structure, and the first isolation structure. A second isolation structure is disposed within the substrate extending along the second direction.

Description

Technology Field

[0001] The present application claims the benefit of priority to Chinese application No. 202111369255.1 filed on November 18, 2021, Chinese application No. 202111369252.8 filed on November 18, 2021, and Chinese application No. 202111371139.3 filed on November 18, 2021, all of which are incorporated herein by reference. Background Technology

[0002] The present disclosure relates to a memory device and a method for forming a memory device.

[0003] Planar semiconductor devices, such as memory cells, are scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches a lower limit, planar process and manufacturing technologies become challenging and costly. Three-dimensional (3D) semiconductor device architectures can address the density limitations of some planar semiconductor devices (e.g., flash memory devices).

[0004] An implementation of a 3D memory device and a method for forming the same are disclosed herein.

[0005] In one aspect, a 3D memory device is disclosed. The 3D memory device includes a plurality of memory stacks, a dummy structure, a first isolation structure, a second isolation structure, a semiconductor layer, and a trench isolation structure. The plurality of memory stacks includes a first memory stack and a second memory stack arranged along a first direction. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction, and a channel structure extending through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A dummy structure is disposed between the first memory stack and the second memory stack. The dummy structure extends along a second direction perpendicular to the first direction and a third direction perpendicular to both the first and second directions. A first isolation structure is disposed between the dummy structure and the first memory stack and extends along the second direction and the third direction. A second isolation structure is disposed between the dummy structure and the second memory stack and extends along the second direction and the third direction. The semiconductor layer is disposed below a plurality of memory stacks, a dummy structure, a first isolation structure, and a second isolation structure. The trench isolation structure includes a trench isolation structure disposed within the semiconductor layer extending along the second direction and the third direction.

[0006] In some implementations, the dummy structure includes a plurality of second conductive layers and a plurality of second dielectric layers alternately stacked along a second direction.

[0007] In some implementations, a plurality of first conductive layers and a plurality of second conductive layers include the same layer, and a plurality of first dielectric layers and a plurality of second dielectric layers are the same layer.

[0008] In some implementations, the dummy structure further includes a dummy channel structure penetrating a plurality of second conductive layers and a plurality of second dielectric layers along a second direction, and the dummy channel structure includes a semiconductor channel and a memory film formed on the semiconductor channel.

[0009] In some implementations, the dummy structure further includes a contact structure penetrating a plurality of second conductive layers and a plurality of second dielectric layers along a second direction.

[0010] In some embodiments, the contact structure comprises a contact extending through a plurality of second conductive layers and a plurality of second dielectric layers along a second direction, and a third dielectric layer extending along a second direction surrounding the contact.

[0011] In some implementations, a third conductive layer is disposed within a semiconductor layer extending along a second direction below the contact, and the third conductive layer is electrically in contact with the contact and is surrounded by a third dielectric layer.

[0012] In some implementations, trench isolation structures electrically isolate the semiconductor layer beneath each memory stack.

[0013] In some implementations, the trench isolation structure is placed below the first and second isolation structures and aligned with the first and second isolation structures.

[0014] In some implementations, the trench isolation structure is placed under the dummy structure.

[0015] In some implementations, the first isolation structure further includes a gate line slit extending along the second and third directions.

[0016] In some implementations, the first isolation structure electrically isolates a plurality of first conductive layers and a plurality of second conductive layers.

[0017] In another aspect, a system is provided. The system includes a three-dimensional (3D) memory device configured to store data and a memory controller. The 3D memory device includes a plurality of memory stacks, a dummy structure, a first isolation structure, a second isolation structure, a semiconductor layer, and a trench isolation structure. The plurality of memory stacks includes a first memory stack and a second memory stack arranged along a first direction. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction, and a channel structure penetrating the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A dummy structure is disposed between the first memory stack and the second memory stack. The dummy structure includes a dummy structure extending along a second direction perpendicular to the first direction and a third direction perpendicular to both the first and second directions. A first isolation structure is disposed between the dummy structure and the first memory stack, and the first isolation structure extends along the second direction and the third direction. A second isolation structure is disposed between a dummy structure and a second memory stack, and the second isolation structure extends along a second direction and a third direction. A semiconductor layer is disposed beneath a plurality of memory stacks, a dummy structure, a first isolation structure, and a second isolation structure. A trench isolation structure includes a trench isolation structure disposed within a semiconductor layer extending along a second direction and a third direction. A memory controller is connected to a 3D memory device and configured to control the operation of the 3D memory device.

[0018] In another aspect, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure is formed comprising a plurality of first dielectric layers and a plurality of sacrificial layers alternately arranged on a semiconductor layer. The stack structure includes a plurality of dielectric stacks arranged along a first direction. A plurality of channel structures are formed in the stack structure along a second direction perpendicular to the first direction. A first slit and a second slit are formed in the stack structure from the upper side of the stack structure along the second direction and a third direction perpendicular to the first direction and the second direction. The stack structure is partitioned into a first memory region, a second memory region, and a dummy region by the first slit and the second slit, the dummy region is positioned between the first memory region and the second memory region, the first slit is positioned between the first memory region and the dummy region, and the second slit is positioned between the second memory region and the dummy region. A plurality of sacrificial layers are replaced with a plurality of conductive layers. A first isolation structure is formed in the first slit and a second isolation structure is formed in the second slit. A third isolation structure is formed within a semiconductor layer below a first isolation structure, and a fourth isolation structure is formed within a semiconductor layer below a second isolation structure.

[0019] In some implementations, multiple channel structures are formed in a stack structure along a second direction.

[0020] In some implementations, multiple channel structures are formed along a second direction within a first memory region, a second memory region, and a dummy region. A contact structure is formed along a second direction within a dummy region.

[0021] In some implementations, a first gate line slit structure is formed in the first slit and a second gate line slit structure is formed in the second slit.

[0022] In some implementations, a second dielectric layer is formed in the first slit and a third dielectric layer is formed in the second slit.

[0023] In some implementations, an opening is formed in the semiconductor layer beneath the first isolation structure and the second isolation structure from the bottom side of the stack structure opposite the upper side. A fourth dielectric layer is formed within the opening.

[0024] In some implementations, the first isolation structure electrically isolates a plurality of conductive layers between the first memory region and the dummy region, and the second isolation structure electrically isolates a plurality of conductive layers between the second memory region and the dummy region.

[0025] In some implementations, the third isolation structure electrically isolates the semiconductor layer below the first memory region and the dummy region, and the fourth isolation structure electrically isolates the semiconductor layer below the second memory region and the dummy region. Brief explanation of the drawing

[0026] The accompanying drawings incorporated herein and forming part of the specification illustrate aspects of the present disclosure, further explain the present disclosure together with the detailed description, and serve to enable a person skilled in the art to manufacture and use the present disclosure. FIG. 1 illustrates a plan view of an exemplary 3D memory device according to some aspects of the present disclosure. FIG. 2 illustrates a cross-section of an exemplary 3D memory device according to some aspects of the present disclosure. FIG. 3 illustrates a cross-section of another exemplary 3D memory device according to some aspects of the present disclosure. FIG. 4 illustrates a cross-section of another exemplary 3D memory device according to some aspects of the present disclosure. FIG. 5 illustrates a cross-section of another exemplary 3D memory device according to some aspects of the present disclosure. FIG. 6 illustrates a plan view of another exemplary 3D memory device according to some aspects of the present disclosure. FIG. 7 illustrates a cross-section of another exemplary 3D memory device according to some aspects of the present disclosure. FIG. 8 illustrates a plan view of another exemplary 3D memory device according to some aspects of the present disclosure. FIG. 9 illustrates a cross-section of another exemplary 3D memory device according to some aspects of the present disclosure. FIG. 10 illustrates a plan view of another exemplary 3D memory device according to some aspects of the present disclosure. FIGS. 11 through 16 illustrate cross-sectional views of exemplary 3D memory devices at different stages of a manufacturing process according to some aspects of the present disclosure. FIG. 17 illustrates a flowchart of an exemplary method for forming a 3D memory device according to some aspects of the present disclosure. FIG. 18 illustrates a flowchart of another exemplary method for forming a 3D memory device according to some aspects of the present disclosure. FIG. 19 illustrates a block diagram of an exemplary system having a memory device according to some aspects of the present disclosure. FIG. 20a illustrates an exemplary memory card having a memory device according to some aspects of the present disclosure. FIG. 20b illustrates an exemplary solid-state drive (SSD) having a memory device according to some aspects of the present disclosure. The present disclosure will be described with reference to the attached drawings. Specific details for implementing the invention

[0027] While specific configurations and arrangements are discussed, it should be understood that they are for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be utilized in various other applications. Functional and structural features as described in this disclosure may be combined, adjusted, and modified in ways not specifically illustrated in the drawings, and such combinations, adjustments, and modifications fall within the scope of this disclosure.

[0028] Generally, terms may be understood at least partially from their contextual usage. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the singular form or such a term may be understood, depending on the context, to convey at least partially the singular form or the plural form. Furthermore, the term “based on” is not intended to convey an entirely exclusive set of factors, but instead may be understood, at least partially depending on the context, to allow for the existence of additional factors that are not necessarily explicitly described.

[0029] It should be readily understood that the meanings of “on,” “above,” and “over” in the present disclosure are to be interpreted in the broadest sense, and accordingly, “on” means not only “directly on” something but also includes the meaning of “on” something having a feature or layer in between them, and “above” or “over” means not only “above” or “over” something but also may include the meaning of being “above” or “over” something where no feature or layer exists in between them (i.e., being directly on something).

[0030] Additionally, spatial terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the drawings. These spatial terms are intended to include various orientations of the device in use or operation, in addition to the orientations illustrated in the drawings. The device may be oriented in other ways (it may be rotated 90 degrees or in other directions), and accordingly, the spatial descriptors used herein may be interpreted in the same manner.

[0031] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A layer may extend across the entire lower or upper structure, or may have a range smaller than that of the lower or upper structure. Additionally, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes on or between the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers within it, and / or may have one or more layers on, above, and / or below the substrate. A layer may include a plurality of layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0032] As used herein, the term “substrate” refers to a material to which a subsequent layer of material is added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or remain unpatterned. Additionally, the substrate may include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of an electrically nonconductive material such as glass, plastic, or a sapphire wafer.

[0033] As used herein, the term “3D memory device” refers to a semiconductor device having a string of memory cell transistors (referred herein to as a “memory string,” such as a NAND memory string) oriented vertically on a laterally oriented substrate. As used herein, the term “vertical” means nominally perpendicular to the side of the substrate.

[0034] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and vertically interconnecting them, so that the resulting structure functions as a single device, achieving performance improvements with reduced power and a smaller footprint compared to conventional planar processes. However, lateral charge movement is a major issue for 3D semiconductor devices. In some 3D memory devices, such as 3D NAND memory devices, the device stack includes memory array devices and peripheral devices. As the size and thickness of the device decrease, the distance between word lines becomes increasingly narrow. Therefore, the lateral charge movement problem in the channel structure is one of the bottlenecks in 3D NAND memory devices.

[0035] FIG. 1 illustrates a plan view of an exemplary 3D memory device (100) according to some aspects of the present disclosure. As illustrated in FIG. 1, the 3D memory device (100) comprises a plurality of planes, and a dummy region is formed between two adjacent planes along the y-direction. In some embodiments, the 3D memory device (100) is divided into a first memory region (102), a second memory region (104), and a dummy region (106). A first isolation structure (108) is disposed between the first memory region (102) and the dummy region (106), and a second isolation structure (109) is disposed between the second memory region (104) and the dummy region (106). The first isolation structure (108) and the second isolation structure (109) may extend along the x-direction and the z-direction. A plurality of channel structures (110) may be formed in the first memory region (102) and the second memory region (104). The channel structure (110) may be extended along the z direction perpendicular to the x and y directions. Multiple dummy channel structures (112) may be formed in the dummy area (106). Similarly, the dummy channel structures (112) may be extended along the z direction perpendicular to the x and y directions.

[0036] FIG. 2 illustrates a cross-sectional view of a 3D memory device (100) according to some aspects of the present disclosure. A first memory region (102), a dummy region (106), and a second memory region (104) are arranged along the y-direction on a substrate (118). In some embodiments, the substrate (118) may be a semiconductor layer. In some embodiments, the substrate (118) may comprise silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate (118) may be a thin substrate (e.g., a semiconductor layer) thinned by grinding, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof.

[0037] A first isolation structure (108) and a second isolation structure (109) are formed between the first memory region (102) and the dummy region (106), and between the second memory region (104) and the dummy region (106). Each of the first memory region (102) and the second memory region (104) may include a plurality of first conductive layers (114) (e.g., word lines) and a plurality of first dielectric layers (116) alternately stacked along the z-direction. In some implementations, the dummy region (106) may include a plurality of conductive layers and a plurality of dielectric layers alternately stacked along the z-direction. In some implementations, the plurality of conductive layers and the plurality of dielectric layers formed in the dummy region (106) may be formed by the same process as the first conductive layers (114) and the first dielectric layers (116) in the first memory region (102) and the second memory region (104). That is, even if the conductive layer and the dielectric layer are separated in the first memory area (102), the second memory area (104), and the dummy area (106), the conductive layer and the dielectric layer can be formed together in the manufacturing process.

[0038] In some embodiments, the first conductive layer (114) may form a word line and may comprise a conductive material comprising, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or a combination thereof. In some embodiments, the first dielectric layer (116) may comprise a dielectric material comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0039] In some embodiments, the channel structure (110) may include a semiconductor channel and a memory film formed on the semiconductor channel. Here, the meaning of "over" should be interpreted as "over" of something from the top or side, in addition to the description mentioned above. The memory film may be a multilayer structure and is an element for implementing a storage function in the 3D memory device (100). The memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). The ONO structure may be formed on the surface of the semiconductor channel, and the ONO structure (memory film) is also located between the semiconductor channel and a first conductive layer (114), such as a word line. In some embodiments, the semiconductor channel may include silicon such as amorphous silicon, polysilicon, or single-crystal silicon.

[0040] In some implementations, the dummy channel structure (112) may have the same structure as the channel structure (110) as shown in FIG. 2. In some implementations, the dummy channel structure (112) and the channel structure (110) may have different structures as shown in FIG. 5 or FIG. 9.

[0041] In some implementations, the first isolation structure (108) may extend along the z-direction and x-direction between the first memory region (102) and the dummy region (106), and the second isolation structure (109) may extend along the z-direction and x-direction between the second memory region (104) and the dummy region (106). In some implementations, the first isolation structure (108) and the second isolation structure (109) may include a gate line slit structure. The gate line slit structure may extend in the z-direction through memory stacks and may also extend in the x-direction to separate memory stacks into a plurality of blocks. In some implementations, the gate line slit structure may include a slit contact formed by filling a slit opening with a conductive material comprising, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. The gate line slit structure may further include a composite spacer disposed laterally between the slit contact and the first conductive layer (114) and the first dielectric layer (116) to electrically isolate the gate line slit structure from the surrounding first conductive layer (114) (gate conductor of the memory stack). As a result, the gate line slit structure including the first isolation structure (108) and the second isolation structure (109) electrically isolates the memory stack in the first memory region (102), the dummy region (106), and the second memory region (104).

[0042] In some implementations, the first isolation structure (108) and the second isolation structure (109) may include a barrier structure formed of a dielectric material. The barrier structure may extend vertically along the z-direction through the memory stack and also extend laterally along the x-direction to separate the memory stack into a plurality of blocks. In some implementations, the barrier structure may include one or more dielectric layers to electrically isolate the memory stack in the first memory region (102), the dummy region (106), and the second memory region (104).

[0043] As illustrated in FIG. 2, the 3D memory device (100) may further include a third isolation structure (120). In some embodiments, the third isolation structure (120) may be formed on a substrate (118) extending along the z-direction. In some embodiments, the third isolation structure (120) may be a trench isolation structure formed on the substrate (118). In some embodiments, the third isolation structure (120) may be formed by a dielectric material. The third isolation structure (120) may electrically isolate the substrate (118) from the first memory region (102), the dummy region (106), and the second memory region (104). When the substrate (118) is formed by a semiconductor material, e.g. silicon, the well regions of the semiconductor substrate under different memory stacks must be electrically isolated. In some implementations, the third isolation structure (120) may be aligned with the first isolation structure (108) and the second isolation structure (109) in the z-direction. In some implementations, the third isolation structure (120) may not be aligned with the first isolation structure (108) and the second isolation structure (109) in the z-direction, and the well region of the semiconductor substrate under the different memory stack is isolated by the third isolation structure (120). By forming the second isolation structure (120), the well region of the substrate (118) under the different memory stack can be electrically isolated without complex structures.

[0044] FIG. 3 illustrates a cross-sectional view of another exemplary 3D memory device (200) according to some aspects of the present disclosure. The structure of the 3D memory device (200) may be similar to the structure of the 3D memory device (100). However, the 3D memory device (200) may include a fourth isolation structure (220) that is not aligned with the first isolation structure (108) or the second isolation structure (109).

[0045] As illustrated in FIG. 3, a fourth isolation structure (220) may be formed on a substrate (118) extending along the z-direction. In some embodiments, the fourth isolation structure (220) may be formed from a dielectric material. The fourth isolation structure (220) may electrically isolate the substrate (118) from the first memory region (102) and the second memory region (104). In some embodiments, the fourth isolation structure (220) may be formed in a dummy region (106). In some embodiments, the fourth isolation structure (220) may be aligned with a dummy channel structure (112). In some embodiments, the fourth isolation structure (220) may not be aligned with a dummy channel structure (112). By forming the fourth isolation structure (220), the well regions of the substrate (118) under different memory stacks can be electrically isolated without complex structures.

[0046] FIG. 4 illustrates a cross-sectional view of another exemplary 3D memory device (300) according to some aspects of the present disclosure. The structure of the 3D memory device (300) may be similar to the structure of the 3D memory device (100). However, the 3D memory device (300) does not include a dummy region.

[0047] As illustrated in FIG. 4, the first memory region (102) and the second memory region (104) are arranged along the y-direction on the substrate (118). In some embodiments, the substrate (118) may comprise silicon (e.g., single-crystal silicon), SiGe, GaAs, Ge, SOI, GOI, or other suitable materials. In some embodiments, the substrate (118) may be a thin substrate (e.g., a semiconductor layer) thinned by grinding, wet / dry etching, CMP, or any combination thereof. A first isolation structure (108) is formed between the first memory region (102) and the second memory region (104). Each of the first memory region (102) and the second memory region (104) may include a first conductive layer (114) and a first dielectric layer (116) alternately stacked along the z-direction. In some implementations, the channel structure (110) may include a semiconductor channel and a memory film formed on the semiconductor channel.

[0048] In some implementations, the first isolation structure (108) may extend vertically along the z and x directions between the first memory region (102) and the second memory region. In some implementations, the first isolation structure (108) may include a gate line slit structure. The gate line slit structure may extend vertically along the z direction through the memory stack and also extend laterally along the x direction to separate the memory stack into a plurality of blocks. In some implementations, the gate line slit structure may include a slit contact formed by filling a slit opening with a conductive material comprising, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. The gate line slit structure may further include a composite spacer disposed laterally between the slit contact and the first conductive layer (114) and the first dielectric layer (116) to electrically insulate the gate line slit structure from the surrounding first conductive layer (114) (gate conductor of the memory stack). As a result, the gate line slit structure electrically isolates the memory stack in the first memory region (102) and the second memory region (104).

[0049] In some implementations, the first isolation structure (108) may include a barrier structure formed of a dielectric material. The barrier structure may extend vertically along the z-direction through the memory stack and also extend laterally along the x-direction to separate the memory stack into a plurality of blocks. In some implementations, the barrier structure may include one or more dielectric layers to electrically isolate the memory stack in the first memory region (102) and the second memory region (104).

[0050] As illustrated in FIG. 4, a third isolation structure (120) may be formed on a substrate (118) extending along the z-direction that is aligned with the first isolation structure (108). In some embodiments, the third isolation structure (120) may be formed on a substrate (118) extending along the z-direction that is not aligned with the first isolation. In some embodiments, the third isolation structure (120) may be formed of a dielectric material capable of electrically isolating well regions of a semiconductor substrate under different memory stacks. In some embodiments, the third isolation structure (120) may be formed by a conductive structure surrounded by a dielectric layer and capable of electrically isolating well regions of a semiconductor substrate under different memory stacks. By forming the second isolation structure (120), well regions of the substrate (118) under different memory stacks can be electrically isolated without complex structures.

[0051] FIG. 5 illustrates a cross-sectional view of another exemplary 3D memory device (400) according to some aspects of the present disclosure. FIG. 6 illustrates a top view of a 3D memory device (400) according to some aspects of the present disclosure. To better explain the present disclosure, the cross-sectional and top views of the 3D memory device (400) of FIG. 5 and FIG. 6 will be discussed together.

[0052] The 3D memory device (400) is divided into a first memory area (102), a second memory area (104), and a dummy area (406). A first isolation structure (108) is placed between the first memory area (102) and the dummy area (406), and a second isolation structure (109) is placed between the second memory area (104) and the dummy area (406). The first isolation structure (108) and the second isolation structure (109) may be extended along the z-direction and the x-direction. A channel structure (110) may be formed in the first memory area (102) and the second memory area (104). The channel structure (110) may be extended along the z-direction which is perpendicular to the x-direction and the y-direction.

[0053] The first memory region (102), dummy region (406), and second memory region (104) are arranged along the y-direction on the substrate (118). In some embodiments, the substrate (118) may comprise silicon (e.g., single-crystal silicon), SiGe, GaAs, Ge, SOI, GOI, or any other suitable material. In some embodiments, the substrate (118) may be a thin substrate (e.g., a semiconductor layer) thinned by grinding, wet / dry etching, CMP, or any combination thereof.

[0054] A first isolation structure (108) is formed between the first memory region (102) and the dummy region (406), and a second isolation structure (109) is formed between the second memory region (104) and the dummy region (406). The first memory region (102) and the second memory region (104) may include a first conductive layer (114) and a dielectric layer (116) (such as word lines) alternately stacked along the z-direction. In some implementations, the dummy region (406) may include a plurality of conductive layers and a plurality of dielectric layers alternately stacked along the z-direction. In some implementations, the plurality of conductive layers and a plurality of dielectric layers formed in the dummy region (406) may be formed by the same process as the first conductive layer (114) and the first dielectric layer (116) in the first memory region (102) and the second memory region (104). That is, even if the conductive layer and the dielectric layer are separated into a first memory region (102), a second memory region (104), and a dummy region (406), the conductive layer and the dielectric layer may be formed together during the manufacturing process. In some implementations, the structure and material of the first conductive layer (114), the first dielectric layer (116), the channel structure (110), the first isolation structure (108), and the second isolation structure (120) of the 3D memory device (400) may be similar to those of the 3D memory device (100).

[0055] The 3D memory device (400) further includes a contact structure (412) formed in a dummy region (406). In some embodiments, each contact structure (412) may include a first conductive contact (413) extending along the z-direction through a conductive layer (114) and a dielectric layer (116). In some embodiments, the first conductive contact (413) may include W, Co, Cu, Al, polysilicon, silicide, or other suitable material. The contact structure (412) may further include a spacer (411) disposed laterally between the first conductive contact (413), the first conductive layer (114), and the first dielectric layer (116) to be electrically insulated from the first conductive layer (114) (gate conductor of the memory stack) surrounding the first conductive contact (413).

[0056] The 3D memory device (400) further includes a second conductive contact (420) formed below the contact structure (412). In some embodiments, the first conductive contact (413) makes direct contact with the second conductive contact (420). In some embodiments, the second conductive contact (420) may include W, Co, Cu, Al, polysilicon, silicide, or other suitable materials. By forming the contact structure (412) in the dummy block region (406), the dummy block region (406) may be used not only to electrically isolate the first memory region (102) and the second memory region (104), but also to provide a conductive path through the memory stack and the silicon substrate. In some embodiments, the conductive path formed by the contact structure (412) and the second conductive contact (420) may be used to connect the 3D memory device (400) with a peripheral device. For example, the source terminal of the 3D memory device (400) may be connected to a peripheral device through a conductive path formed by a contact structure (412) and a second conductive contact (420), so that the peripheral device can control the operation of the 3D memory device (400). In some implementations, the conductive path formed by the contact structure (412) and the second conductive contact (420) is connected to another device positioned above, below, or next to the 3D memory device (400). In some implementations, the peripheral device may include one or more peripheral circuits. In some implementations, the peripheral circuit may be electrically connected to the 3D memory device (400) through a conductive wire, such as a redistribution layer.

[0057] FIG. 7 illustrates a cross-sectional view along line A of FIG. 8 of another exemplary 3D memory device (500) according to some aspects of the present disclosure. FIG. 8 illustrates a plan view of a 3D memory device (500) according to some aspects of the present disclosure. To better explain the present disclosure, the cross-sectional and plan views of the 3D memory device (500) of FIG. 7 and FIG. 8 will be discussed together.

[0058] The 3D memory device (500) is divided into a first memory area (102), a second memory area (104), and a dummy area (506). A first isolation structure (108) is placed between the first memory area (102) and the dummy area (506), and a second isolation structure (109) is placed between the second memory area (104) and the dummy area (506). Additionally, one or more fifth isolation structures (550) are also placed in the dummy area (506) as shown in FIG. 7. The first isolation structure (108), the second isolation structure (109), and the fifth isolation structure (550) may be extended along the x-direction and the z-direction. A channel structure (110) may be formed in the first memory area (102) and the second memory area (104). The channel structure (110) may be extended along the z-direction which is perpendicular to the x-direction and the y-direction. A dummy channel structure (112) can be formed in a dummy region (506). Similarly, the dummy channel structure (112) can be extended along the z-direction perpendicular to the x-direction and the y-direction.

[0059] The first memory region (102), dummy region (506), and second memory region (104) are arranged along the y-direction on the substrate (118). Each of the first memory region (102), dummy region (506), and second memory region (104) may include a first conductive layer (114) and a dielectric layer (116) alternately stacked along the z-direction (such as word lines). In some embodiments, the structure and material of the first conductive layer (114), the first dielectric layer (116), the channel structure (110), the first isolation structure (108), the second isolation structure (109), and the third isolation structure (120) of the 3D memory device (500) may be similar to that of the 3D memory device (100).

[0060] The 3D memory device (500) further includes a sixth isolation structure (558) disposed below a dummy channel structure (112). In some embodiments, the sixth isolation structure (558) may be formed on a substrate (118) extending along the z-direction. In some embodiments, the structure and material of the sixth isolation structure (558) may be similar to the structure and material of the third isolation structure (120). The 3D memory device (500) further includes a conductive contact (556) disposed below a fifth isolation structure (550) in a dummy block region (506). In some embodiments, the conductive contact (556) is surrounded by a dielectric layer.

[0061] In some implementations, the fifth isolation structure (550) may include a gate line slit structure. The gate line slit structure may extend vertically along the z-direction through the memory stack as shown in FIG. 7, and may extend transversely along the x-direction as shown in FIG. 8. In some implementations, the gate line slit structure includes a slit contact (552) formed by filling the slit opening with a conductive material comprising, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. The gate line slit structure may further include a composite spacer (554) disposed transversely between the slit contact and the first conductive layer (114) and the first dielectric layer (116) to electrically insulate the gate line slit structure from the surrounding first conductive layer (114) (gate conductor of the memory stack). As a result, the gate line slit structure electrically isolates the memory stack in the first memory area (102), the dummy area (506), and the second memory area (104).

[0062] By forming a conductive contact (556) in a dummy block region (506) that is in direct contact with the fifth isolation structure (550), the slit contact (552) is in direct contact with the conductive contact (556). Thus, in the dummy block region (506), the fifth isolation structure (550) and the conductive contact (556) can provide a conductive path through the memory stack and the silicon substrate.

[0063] FIG. 9 illustrates a cross-sectional view of another exemplary 3D memory device (600) according to some aspects of the present disclosure. FIG. 10 illustrates a top view of a 3D memory device (600) according to some aspects of the present disclosure. To better explain the present disclosure, the cross-sectional and top views of the 3D memory device (600) of FIG. 9 and FIG. 10 will be discussed together.

[0064] The 3D memory device (600) is divided into a first memory region (102), a second memory region (104), and a dummy region (906). A first isolation structure (108) is placed between the first memory region (102) and the dummy region (606), and a second isolation structure (109) is placed between the second memory region (104) and the dummy region (906). In some implementations, the first isolation structure (108) and the second isolation structure (109) may extend vertically along the z-direction between the first memory region (102) and the dummy region (906) and between the second memory region (104) and the dummy region (906). In some implementations, the first isolation structure (108) and the second isolation structure (109) may include a barrier structure formed of a dielectric material. The barrier structure may extend vertically along the z-direction through the memory stack and also extend laterally along the x-direction to separate the memory stack into multiple blocks. In some implementations, the barrier structure may include one or more dielectric layers to electrically isolate the memory stack in a first memory region (102), a dummy region (906), and a second memory region (104).

[0065] In some implementations, the structure and material of the first conductive layer (114), the first dielectric layer (116), the channel structure (110), and the third isolation structure (120) of the 3D memory device (600) may be similar to that of the 3D memory device (100). The 3D memory device (600) further comprises a seventh isolation structure (608) disposed in a dummy region (906) extending vertically along the z-direction, and a conductive contact (620) disposed below the seventh isolation structure (608) in a dummy region (506).

[0066] In some embodiments, the seventh isolation structure (608) may include a gate line slit structure. The gate line slit structure may extend vertically along the z-direction through memory stacks and also extend laterally along the x-direction. In some embodiments, the gate line slit structure may include a slit contact formed by filling a slit opening with a conductive material comprising, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. The gate line slit structure may further include a composite spacer disposed laterally between the slit contact, the first conductive layer (114), and the first dielectric layer (116) to electrically insulate the gate line slit structure from the surrounding first conductive layer (114).

[0067] A conductive contact (620) may be formed on a substrate (118) beneath a third isolation structure (608). In some embodiments, the conductive contact (620) may make direct contact with a slit contact of the seventh isolation structure (608). In some embodiments, the conductive contact (602) is surrounded by a dielectric layer. By forming the conductive contact (620) in a dummy region (906) that makes direct contact with the seventh isolation structure (608), the slit contact makes direct contact with the conductive contact (620). Thus, in the dummy region (906), the seventh isolation structure (608) and the conductive contact (620) may provide a conductive path through the memory stack and the silicon substrate.

[0068] FIGS. 11 through 16 illustrate cross-sections of a 3D memory device (100) at different stages of a manufacturing process according to some aspects of the present disclosure. FIG. 17 illustrates a flowchart of an exemplary method (700) for forming a 3D memory device (100) according to some aspects of the present disclosure. To better explain the present disclosure, the cross-sections of the 3D memory device (100) of FIGS. 11 through 16 and the method (700) of FIG. 17 will be discussed together. It should be understood that the operations illustrated in the method (700) are not complete and other operations may be performed before, after, or in between any illustrated operations. Additionally, some operations may be performed simultaneously and may be performed in a different order than that illustrated in FIGS. 11 through 16 and FIG. 17.

[0069] As illustrated in operation (702) of FIGS. 11 and FIGS. 17, a stack structure comprising a plurality of first dielectric layers (116) and a plurality of sacrificial layers (115) is formed on a substrate (118). The first dielectric layers (116) and sacrificial layers (115) are arranged alternately on the substrate (118). Dielectric / sacrificial layer pairs may extend along the y-direction. In some embodiments, each first dielectric layer (116) may comprise a silicon oxide layer, and each sacrificial layer (115) may comprise a silicon nitride layer. The first dielectric layers (116) and sacrificial layers (115) may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, a pad oxide layer (not shown) is formed between the substrate and the stack structure by depositing a dielectric material, such as silicon oxide, on the substrate.

[0070] As illustrated in the operation (704) of FIGS. 12 and FIGS. 17, the channel structure (110) and the dummy channel structure (112) are formed as a stacked structure along the z-direction. In some implementations, the channel structure (110) and the dummy channel structure (112) may have the same structure.

[0071] Each channel structure (110) or dummy channel structure (112) may include a semiconductor channel and a memory film formed on the semiconductor channel. In some embodiments, a channel hole is formed in the stack structure along the z-direction. In some embodiments, an etching process may be performed to form a channel hole in the stack structure that extends vertically (z-direction) through a dielectric / sacrificial layer inserted in the middle. In some embodiments, the manufacturing process for forming the channel hole may include wet etching and / or dry etching such as deep reactive ion etch (DRIE). In some embodiments, the channel hole may extend further above the substrate (118). Then, a blocking layer, a storage layer, a tunneling layer, and a semiconductor channel may be formed sequentially within the channel hole.

[0072] As illustrated in operation (706) of FIGS. 13 and FIGS. 17, a first slit (150) and a second slit (152) are formed along the y-direction in a stack structure. The stack structure is divided into a first memory area (102), a second memory area (104), and a dummy area (106) by the first slit (150) and the second slit (152). The dummy area (106) is positioned between the first memory area (102) and the second memory area (104). The first slit (150) is positioned between the first memory area (102) and the dummy area (106), and the second slit (152) is positioned between the second memory area (104) and the dummy area (106). In some implementations, the first slit (150) may be formed by dry etching, wet etching, or other suitable process.

[0073] As illustrated in operation (708) of FIG. 14 and FIG. 17, a plurality of sacrificial layers (115) are replaced by a plurality of word lines (first conductive layers (114)). For example, the sacrificial layers (115) may be removed by dry etching, wet etching, or other suitable process for forming a plurality of cavities. The word lines (first conductive layers (114)) may be formed within the cavity by depositing a gate conductor and a gate conductor made of tungsten. In some embodiments, the cavity may be filled with a gate dielectric layer made of a high dielectric constant dielectric material, an adhesive layer comprising titanium / titanium nitride (Ti / TiN) or tantalum / tantalum nitride (Ta / TaN).

[0074] As illustrated in step (710) of FIGS. 14 and FIGS. 17, the first isolation structure (108) and the second isolation structure (109) may be formed within the first slit (150) and the second slit (152). It will be understood that the first isolation structure (108) and the second isolation structure (109) of FIGS. 14 may be the same as or identical to the first isolation structure (108) and the second isolation structure (109) described above. In some embodiments, a spacer (107) is formed along the sidewalls of the first slit (150) and the second slit (152). In some embodiments, the spacer (107) may include one or more layers of dielectric material. Then, slit contacts are formed by filling (e.g., depositing) a conductive material into the remaining space of the first slit (150) and the second slit (152) by PVD, CVD, ALD, any other suitable process, or any combination thereof. Depending on some implementation, the slit contacts may serve as a common source contact. In some implementations, the slit contacts may include a conductive material comprising, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or a combination thereof.

[0075] As illustrated in FIG. 15, a portion of the substrate (118) is removed from the opening (154). In some embodiments, a portion of the substrate (118) may be removed by dry etching, wet etching, or other suitable process. In some embodiments, a thinning operation may be additionally performed to thin the substrate (118), and a carrier wafer (152) may be used during the thinning operation. As illustrated in operation (712) of FIG. 16 and FIG. 17, a third isolation structure (120) is formed in the opening (154) below the first isolation structure (108) and the second isolation structure (109). In some embodiments, the third isolation structure (120) may be formed by a dielectric material, and the dielectric material may also cover the substrate (118).

[0076] FIG. 18 illustrates a flowchart of another exemplary method (800) for forming a 3D memory device (300) according to some aspects of the present disclosure. As illustrated in operation (802) of FIG. 18, a stack structure comprising a plurality of first dielectric layers (116) and a plurality of sacrificial layers (115) is formed on a substrate (118). The first dielectric layers (116) and sacrificial layers (115) are arranged alternately on the substrate (118). Dielectric / sacrificial layer pairs may extend along the x-direction. In some embodiments, each first dielectric layer (116) may comprise a silicon oxide layer, and each sacrificial layer (115) may comprise a silicon nitride layer. The first dielectric layers (116) and sacrificial layers (115) may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or a combination thereof. In some implementations, a pad oxide layer (not shown) is formed between the substrate and the stack structure by depositing a dielectric material, such as silicon oxide, on the substrate.

[0077] As illustrated in operation 804 of FIG. 18, the channel structure (110) is formed as a stack structure along the y-direction. Each channel structure (110) may include a semiconductor channel and a memory film formed on the semiconductor channel. In some embodiments, a channel hole is formed in the stack structure along the y-direction. In some embodiments, an etching process may be performed to form a channel hole in the stack structure that extends vertically (in the y-direction) through a dielectric / sacrificial layer inserted in the middle. In some embodiments, the manufacturing process for forming the channel hole may include wet etching and / or dry etching such as DRIE. In some embodiments, the channel hole may extend further above the substrate (118). Then, a blocking layer, a storage layer, a tunneling layer, and a semiconductor channel may be formed sequentially within the channel hole.

[0078] As illustrated in operation (806) of FIG. 18, a slit may be formed along the y-direction in a stack structure. The stack structure is divided into a first memory block region (102) and a second memory block region (104) by the slit. In some implementations, the slit may be formed by dry etching, wet etching, or other suitable process.

[0079] As illustrated in operation (808) of FIG. 18, a plurality of sacrificial layers (115) are replaced by a plurality of word lines (first conductive layers (114)). For example, the sacrificial layers (115) may be removed by dry etching, wet etching, or other suitable process for forming a plurality of cavities. The word lines (first conductive layers (114)) may be formed within the cavities by depositing a gate conductor and a gate conductor made of tungsten. In some embodiments, the cavities may be filled with a gate dielectric layer made of a high dielectric constant dielectric material, and the adhesive layer comprises Ti / TiN or Ta / TaN.

[0080] As illustrated in operation (810) of FIG. 18, a first isolation structure (108) may be formed in the slit. In some embodiments, a spacer is formed along the sidewall of the slit. In some embodiments, the spacer may include one or more layers of dielectric material. Then, a slit contact is formed by filling (e.g., depositing) a conductive material in the remaining space of the slit by PVD, CVD, ALD, any other suitable process, or any combination thereof. Depending on some embodiments, the slit contact may serve as a common source contact. In some embodiments, the slit contact may include a conductive material comprising, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or a combination thereof.

[0081] As illustrated in operation (812) of FIG. 18, a portion of the substrate (118) is removed to form an opening (154), and a second isolation structure (120) is formed in the opening (154) below the first isolation structure (108). In some embodiments, the second isolation structure (120) may be formed by a dielectric material, and the dielectric material may cover the substrate (118).

[0082] By forming a first isolation structure (108) and a second isolation structure (120) between a first memory block region (102) and a second memory block region (104), the word lines (first conductive layer (114)) of different memory stacks can be isolated, and the well region of the substrate (118) can be electrically isolated from the well region of the substrate (118) under another memory stack without a complex structure.

[0083] FIG. 19 illustrates a block diagram of an exemplary system (900) having a memory device according to some aspects of the present disclosure. The system (900) may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having internal storage. As illustrated in FIG. 19, the system (900) may include a host (908) and a memory system (902) having one or more memory devices (904) and a memory controller (906). The host (908) may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host (908) may be configured to transmit data to the memory device (904) or receive data from the memory device (904).

[0084] The memory device (904) may be any memory device disclosed in this specification. As described above, the memory device (904), such as a NAND flash memory device, may have a predefined discharge current controlled in a discharge operation that discharges bit lines. The memory controller (906) is coupled to the memory device (904) and the host (908) according to some implementation and is configured to control the memory device (904). The memory controller (906) may manage data stored in the memory device (904) and communicate with the host (908). For example, the memory controller (906) may be coupled to the memory device (904), such as the 3D memory device (100) described above, and the memory controller (906) may be configured to control the operation of the channel structure (110) through a peripheral device. By forming a structure according to this disclosure, the area of ​​the 3D memory device (100) can be reduced using the disclosed first isolation structure.

[0085] In some implementations, the memory controller (906) is designed to operate in a low duty cycle environment, for example, on a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the memory controller (906) is designed to operate in a high duty cycle environment on an SSD, or on an embedded multi-media-card (eMMC) used as a data storage and enterprise storage array for mobile devices, for example, smartphones, tablets, laptop computers, etc. The memory controller (906) may be configured to control operations of the memory device (904), such as read, erase, and program operations. The memory controller (906) may also be configured to manage various functions related to data stored or to be stored in the memory device (904), including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller (906) is additionally configured to process error correction codes (ECCs) related to data read from or written to the memory device (904). Any other suitable function may also be performed by the memory controller (906), for example, formatting the memory device (904). The memory controller (906) may communicate with an external device (e.g., a host (908)) according to a specific communication protocol.For example, the memory controller (906) can communicate with an external device through at least one of various interface protocols such as USB protocol, MMC protocol, PCI (peripheral component interconnection) protocol, PCI-E (PCI-express) protocol, ATA (advanced technology attachment) protocol, serial ATA protocol, parallel ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, IDE (integrated drive electronics) protocol, Firewire protocol, etc.

[0086] The memory controller (906) and one or more memory devices (904) may be integrated into various types of storage devices and may be contained within the same package, for example, a universal flash storage (UFS) package or an eMMC package. That is, the memory system (902) may be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 20a, the memory controller (906) and a single memory device (904) may be integrated into a memory card (1002). The memory card (1002) may include a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card (1002) may further include a memory card connector (704) that connects the memory card (1002) to a host (e.g., the host (908) of FIG. 19). In another example as illustrated in FIG. 20b, a memory controller (906) and a plurality of memory devices (904) may be integrated into an SSD (1006). The SSD (1006) may further include an SSD connector (1008) that connects the SSD (1006) to a host (e.g., the host (608) of FIG. 19). In some implementations, the storage capacity and / or operating speed of the SSD (1006) is greater than that of the memory card (1002).

[0087] The foregoing description of a specific implementation may be easily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementation based on the teachings and guidelines set forth herein.

[0088] The breadth and scope of the present disclosure should not be limited by the exemplary embodiments described above, but should be defined only by the following claims and their equivalents.

Claims

Claim 1 A memory device comprising a plurality of memory structures including a first memory structure and a second memory structure arranged along a first direction, and a dummy structure including a plurality of second conductive layers and a plurality of second dielectric layers alternately stacked along a second direction perpendicular to the first direction—the dummy structure being disposed between the first memory structure and the second memory structure, and the dummy structure being extended along a third direction perpendicular to the first direction and the second direction—a first isolation structure disposed between the dummy structure and the first memory structure and extending along the second direction and the third direction, a second isolation structure disposed between the dummy structure and the second memory structure and extending along the second direction and the third direction, and a dummy channel structure extending through the dummy structure along the second direction. Claim 2 A memory device according to claim 1, wherein each of the first memory structure and the second memory structure comprises a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along the second direction. Claim 3 A memory device according to paragraph 2, wherein the plurality of first conductive layers and the plurality of second conductive layers comprise the same conductive material, and the plurality of first dielectric layers and the plurality of second dielectric layers comprise the same dielectric material. Claim 4 A memory device according to claim 1, wherein the dummy channel structure comprises a semiconductor channel and a memory film formed on the semiconductor channel. Claim 5 A memory device according to claim 1, further comprising a contact structure extending through the plurality of second conductive layers and the plurality of second dielectric layers along the second direction. Claim 6 In claim 5, the memory device comprises a contact structure including a contact extending through the plurality of second conductive layers and the plurality of second dielectric layers along the second direction, and a third dielectric layer extending along the second direction surrounding the contact. Claim 7 A memory device according to claim 6, comprising: a plurality of memory structures, a semiconductor layer disposed below the dummy structure, the first isolation structure and the second isolation structure, and a third conductive layer disposed within the semiconductor layer and extending along the second direction below the contact, wherein the third conductive layer is electrically in contact with the contact and is surrounded by a third dielectric layer. Claim 8 In claim 7, the memory device, wherein the contact and the third conductive layer are in electrical contact with a peripheral device. Claim 9 A memory device according to claim 8, further comprising a trench isolation structure extending along the second direction and the third direction and disposed within the semiconductor layer, wherein the trench isolation structure electrically isolates the semiconductor layer below each memory stack. Claim 10 A memory device according to claim 9, wherein the trench isolation structure is disposed below the first isolation structure and the second isolation structure and aligned with the first isolation structure and the second isolation structure. Claim 11 In claim 9, the above trench isolation structure is a memory device placed below the above dummy structure. Claim 12 A system comprising a memory device configured to store data and a memory controller connected to the memory device and configured to control the operation of the memory device, wherein the memory device comprises a plurality of memory structures including a first memory structure and a second memory structure arranged along a first direction, and a dummy structure including a plurality of second conductive layers and a plurality of second dielectric layers alternately stacked along a second direction perpendicular to the first direction—the dummy structure being positioned between the first memory structure and the second memory structure, and the dummy structure being extended along a third direction perpendicular to the first direction and the second direction—a first isolation structure positioned between the dummy structure and the first memory structure and extending along the second direction and the third direction, a second isolation structure positioned between the dummy structure and the second memory structure and extending along the second direction and the third direction, and a dummy channel structure extending through the dummy structure along the second direction. Claim 13 A method for forming a memory device, comprising: forming a stack structure including a plurality of first dielectric layers and a plurality of sacrificial layers alternately stacked along a second direction, wherein the stack structure includes a plurality of dielectric stacks arranged along a first direction perpendicular to the second direction; forming a plurality of channel structures within the stack structure along the second direction; and forming a first opening and a second opening in the stack structure from the upper side of the stack structure along the second direction and a third direction, wherein the third direction is perpendicular to the first direction and the second direction, and the plurality of dielectric stacks are partitioned into a first memory region, a second memory region and a dummy region by the first opening and the second opening, wherein the dummy region is disposed between the first memory region and the second memory region, wherein the first opening is disposed between the first memory region and the dummy region, and the second opening is disposed between the second memory region and the dummy region; and replacing the plurality of sacrificial layers with a plurality of conductive layers, and forming a first isolation structure in the first opening A method comprising the step of forming and forming a second isolation structure in the second opening. Claim 14 In claim 13, the step of forming the plurality of channel structures in the stack structure along the second direction further comprises the step of forming the plurality of channel structures along the second direction within the first memory region, the second memory region and the dummy region. Claim 15 In claim 13, the step of forming the plurality of channel structures within the stack structure along the second direction further comprises the step of forming the plurality of channel structures within the first memory region and the second memory region, and the step of forming a contact structure in the dummy region along the second direction. Claim 16 In claim 15, the step of forming the first isolation structure in the first opening and forming the second isolation structure in the second opening further comprises the step of forming the first gate line slit structure in the first opening and forming the second gate line slit structure in the second opening. Claim 17 In claim 15, the step of forming the first isolation structure in the first opening and forming the second isolation structure in the second opening further comprises the step of forming a second dielectric layer in the first opening and forming a third dielectric layer in the second opening. Claim 18 A method according to claim 17, further comprising the steps of forming a semiconductor layer disposed below the stack structure, forming a third isolation structure within the semiconductor layer below the first isolation structure, and forming a fourth isolation structure within the semiconductor layer below the second isolation structure. Claim 19 A method according to claim 18, wherein the first isolation structure electrically isolates the plurality of conductive layers between the first memory region and the dummy region, and the second isolation structure electrically isolates the plurality of conductive layers between the second memory region and the dummy region. Claim 20 A method according to claim 19, wherein the third isolation structure electrically isolates the semiconductor layer below the first memory region and the dummy region, and the fourth isolation structure electrically isolates the semiconductor layer below the second memory region and the dummy region.

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