Display device

Abstract

A display device is provided. The display device comprises a display area including a plurality of light-emitting elements each including an anode electrode, a light-emitting layer, and a cathode electrode; a sealing layer disposed on the plurality of light-emitting elements and including a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film; a dam structure surrounding the display area; a bank structure disposed on the outside of the dam structure; a power supply voltage line electrically connected to the cathode electrode; a signal transmission line overlapping with the power supply voltage line; and an etching prevention pattern disposed between the power supply voltage line and the signal transmission line, wherein the display device includes an inorganic sealing area disposed between the dam structure and the bank structure and in which the first inorganic sealing film and the second inorganic sealing film are in direct contact, and the etching prevention pattern is disposed in the inorganic sealing area.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] Various types of display devices are used, such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs). Among these, OLEDs display images using organic light-emitting elements that generate light through the recombination of electrons and holes.

[0004] An organic light-emitting display device includes pixels connected to scan lines and data lines, a scan driver that applies scan signals to scan lines, a data driver that applies data voltages to data lines, and a power voltage line that applies power voltage to pixels. The scan driver can generate scan signals according to scan driving signals input through the scan driving lines and output them to the scan lines. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a display device capable of suppressing or preventing current leakage and coupling between the two wires in the area where the power voltage wiring and the scan drive wiring overlap.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A display device according to one embodiment for solving the above problem comprises a display area including a plurality of light-emitting elements each including an anode electrode, a light-emitting layer, and a cathode electrode, a sealing layer disposed on the plurality of light-emitting elements and including a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film, a dam structure surrounding the display area, a bank structure disposed on the outside of the dam structure, a power supply voltage line electrically connected to the cathode electrode, a signal transmission line overlapping with the power supply voltage line, and an etching prevention pattern disposed between the power supply voltage line and the signal transmission line, wherein the device includes an inorganic sealing area disposed between the dam structure and the bank structure and in which the first inorganic sealing film and the second inorganic sealing film are in direct contact, and the etching prevention pattern is disposed in the inorganic sealing area.

[0008] At least a portion of the overlapping area where the power voltage line and the signal transmission line overlap may overlap with the weapon encapsulation area.

[0009] At least a portion of the above etching prevention pattern may overlap with at least a portion of the above overlapping region.

[0010] The apparatus further comprises a substrate, a first conductive layer disposed on the substrate, a first organic insulating layer disposed on the first conductive layer, a second conductive layer disposed on the first organic insulating layer, a second organic insulating layer disposed on the second conductive layer, and a third conductive layer disposed on the second organic insulating layer, wherein the power supply voltage line may be formed of the third conductive layer.

[0011] The above etching prevention pattern may be composed of either the first conductive layer or the second conductive layer.

[0012] The above power voltage line and the above etching prevention pattern can be in direct contact.

[0013] The above etching prevention pattern may include a first stacked pattern formed by the first conductive layer and a second stacked pattern formed by the second conductive layer.

[0014] The apparatus further includes a third organic insulating layer disposed on the third conductive layer, wherein the anode electrode may be disposed on the third organic insulating layer.

[0015] The apparatus further comprises an inorganic insulating film disposed between the etching prevention pattern and the signal transmission line, wherein the inorganic insulating film may have a first thickness in an area overlapping with the etching prevention pattern and a second thickness smaller than the first thickness in an area not overlapping with the etching prevention pattern.

[0016] In the above-mentioned weapon encapsulation region, the first weapon encapsulation film is a display device that is in direct contact with the power voltage line.

[0017] It may further include a scan driver connected to one end of the signal transmission line and a driver chip connected to the other end of the signal transmission line.

[0018] The above-mentioned display area may further include a non-display area disposed around the display area, wherein the power voltage line and the signal transmission line may overlap in the non-display area.

[0019] A display device according to one embodiment for solving the above problem comprises a substrate, a signal transmission line disposed on the substrate, a first inorganic insulating layer disposed on the signal transmission line, a first conductive layer disposed on the first inorganic insulating layer, a first organic insulating layer disposed on the first conductive layer, a second conductive layer disposed on the first organic insulating layer, a second organic insulating layer disposed on the second conductive layer, a third conductive layer disposed on the second organic insulating layer and including a power supply voltage line that overlaps with the signal transmission line, a third organic insulating layer disposed on the third conductive layer, a light-emitting element disposed on the third organic insulating layer and including an anode electrode, a light-emitting layer, and a cathode electrode electrically connected to the power supply voltage line, an encapsulation layer disposed on the cathode electrode and including a first inorganic encapsulation film, an organic encapsulation film, and a second inorganic encapsulation film, and an etching prevention pattern disposed in at least a portion of an overlapping region where the signal transmission line and the power supply voltage line overlap.

[0020] The first inorganic encapsulation film and the second inorganic encapsulation film are in direct contact, and further include an inorganic encapsulation region that overlaps at least partially with the overlapping region, and the etching prevention pattern includes at least one of the first conductive layer and the second conductive layer and can be disposed in the overlapping region that overlaps with the inorganic encapsulation region.

[0021] The device further includes a dam structure surrounding the light-emitting element and a bank structure disposed on the outside of the dam structure, wherein the inorganic encapsulation region may be disposed between the dam structure and the bank structure.

[0022] In the above-mentioned inorganic encapsulation region, the power voltage line and the first inorganic encapsulation film can come into direct contact.

[0023] The device further includes a display area where a screen display is made and a non-display area disposed around the display area, wherein the weapon bag area may be disposed in the non-display area.

[0024] The above power voltage line and the above etching prevention pattern can be in direct contact.

[0025] A display device according to one embodiment for solving the above problem comprises: a display area comprising a plurality of light-emitting elements each comprising an anode electrode, a light-emitting layer, and a cathode electrode; a sealing layer disposed on the plurality of light-emitting elements and comprising a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film; a dam structure surrounding the display area; a bank structure disposed on the outside of the dam structure; a power supply voltage line electrically connected to the cathode electrode; a signal transmission line overlapping with the power supply voltage line; an etching prevention pattern disposed between the power supply voltage line and the signal transmission line; and an inorganic insulating film disposed between the etching prevention pattern and the signal transmission line, wherein the inorganic insulating film has a first thickness in the area overlapping with the etching prevention pattern and a second thickness smaller than the first thickness in the area not overlapping with the etching prevention pattern.

[0026] The structure further includes an inorganic encapsulation region disposed between the dam structure and the bank structure, wherein the first inorganic encapsulation film and the second inorganic encapsulation film are in direct contact, and the overlapping region where the power voltage line and the signal transmission line overlap is at least partially disposed in the inorganic encapsulation region, and the etching prevention pattern may be disposed in the inorganic encapsulation region that overlaps with the overlapping region.

[0027] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0028] According to a display device of one embodiment, by forming an anti-etching pattern between the power voltage wiring and the scan driving wiring, current leakage and coupling between the two wirings can be suppressed or prevented in the area where the power voltage wiring and the scan driving wiring overlap.

[0029] According to a display device according to one embodiment, heat generation issues of power voltage wiring can be suppressed or prevented.

[0030] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0031] FIG. 1 is a plan view of a display device according to one embodiment. FIG. 2 is a side view of the display device of FIG. 1. Figure 2 illustrates the side profile of the display device in a state where it is bent in the thickness direction. FIG. 3 is a circuit diagram showing a pixel in detail according to one embodiment. FIG. 4 is a cross-sectional view of a pixel of a display panel according to one embodiment. Figure 5 is an enlarged view of area A of Figure 1. Figure 6 is a cross-sectional view taken along the line VI-VI' of Figure 5. Figure 7 is an enlarged view of area B of Figure 5. Figure 8 is a cross-sectional view taken along the line VIII-VIII' of Figure 7. Figure 9 is an enlarged view of area C of Figure 8. FIG. 10 is a partial plan view of a display panel according to another embodiment. FIG. 11 is a partial plan view of a display panel according to another embodiment. FIG. 12 is a cross-sectional view of a display panel according to another embodiment. FIG. 13 is a cross-sectional view of a display panel according to another embodiment. Specific details for implementing the invention

[0032] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0033] When elements or layers are referred to as being on another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components.

[0034] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0035] Specific embodiments will be described below with reference to the attached drawings.

[0036] FIG. 1 is a plan view of a display device according to one embodiment. FIG. 2 is a side view of the display device of FIG. 1. FIG. 2 illustrates a side shape of the display device in a state where it is bent in the thickness direction.

[0037] In the drawing, the first direction (DR1) represents the horizontal direction of the planar display device (1), and the second direction (DR2) represents the vertical direction of the planar display device (1). Additionally, the third direction (DR3) represents the thickness direction of the display device (1). The first direction (DR1) and the second direction (DR2) intersect perpendicularly to each other, and the third direction (DR3) intersects perpendicularly to both the first direction (DR1) and the second direction (DR2) in a direction that intersects the plane on which the first direction (DR1) and the second direction (DR2) are placed. However, the directions mentioned in the embodiment should be understood as referring to relative directions, and the embodiment is not limited to the mentioned directions.

[0038] Unless otherwise defined, in this specification, one side of the first direction (DR1) refers to the right direction in the plan view, the other side of the first direction (DR1) refers to the left direction in the plan view, one side of the second direction (DR2) refers to the upper direction in the plan view, and the other side of the second direction (DR2) refers to the lower direction in the plan view. Additionally, “upper” and “upper surface” expressed based on the third direction (DR3) refer to the display surface side based on the display panel (10), and “lower” and “lower surface” refer to the opposite side of the display surface based on the display panel (10).

[0039] Referring to FIGS. 1 and 2, the display device (1) is a device for displaying video or still images, and the display device (1) can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs (Personal Computers), smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (Portable Multimedia Players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0040] A display device (1) according to one embodiment may be formed in a substantially rectangular shape on a plane. The display device (1) may be a rectangle with vertical corners on a plane. However, it is not limited thereto, and the display device (1) may be a rectangular shape with rounded corners on a plane.

[0041] If the display device (1) includes a planar rectangular shape, the length of the two sides positioned on one side and the other side of the first direction (DR1) extending into the second direction (DR2) may be longer than the length of the two sides positioned on one side and the other side of the second direction (DR2) extending into the first direction (DR1). In other words, the two sides of the display device (1) positioned on one side and the other side of the first direction (DR1) may be long sides, and the two sides of the display device (1) positioned on one side and the other side of the second direction (DR2) may be short sides.

[0042] The display device (1) may include a display panel (10). The display panel (10) may be a flexible substrate comprising a flexible polymer material such as polyimide. Accordingly, the display panel (10) may be bent, folded, folded, or rolled.

[0043] The display panel (10) may be an organic light-emitting display panel. In the following embodiments, an organic light-emitting display panel is used as the display panel (10), but it is not limited thereto, and other types of display panels such as liquid crystal display panels, quantum dot organic light-emitting display panels, quantum dot liquid crystal displays, quantum nano light-emitting display panels, and micro LEDs may be used.

[0044] The display panel (10) may include a display area (DA) for displaying the screen and a non-display area (NDA) for which no display takes place. The display panel (10) may be divided into a display area (DA) and a non-display area (NDA) in a planar view. The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may form a bezel.

[0045] The display area (DA) may correspond to the planar shape of the display device (1). The display area (DA) may be a rectangular shape with vertical corners or a rectangular shape with rounded corners. However, the planar shape of the display area (DA) is not limited to a rectangle and may have a circular, elliptical, or various other shapes.

[0046] The display area (DA) may include a plurality of pixels. Each pixel may be arranged in a matrix shape. Each pixel may include a light-emitting layer and a circuit layer that controls the amount of light emitted by the light-emitting layer. The circuit layer may include wiring, electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed by a sealing film. The specific configuration of the pixel will be described later.

[0047] The non-display area (NDA) may surround all sides of the display area (DA) and form the border of the display area (DA). However, it is not limited thereto.

[0048] The display panel (10) may include a main area (MA) and a bending area (BA) connected to one side of the second direction (DR2) of the main area (MA). The display panel (10) may further include a sub-area (SA) connected to the bending area (BA) on one side of the second direction (DR2), bent in the thickness direction, and overlapped with the main area (MA) in the thickness direction.

[0049] A display area (DA) may be located in the main area (MA). A non-display area (NDA) may be located in the surrounding edge portion of the display area (DA) of the main area (MA).

[0050] The main area (MA) may have a shape similar to the planar external shape of the display device (1). The main area (MA) may be a flat area located on a plane. However, it is not limited thereto, and at least one of the remaining edges in the main area (MA), excluding the edge (side) connected to the bending area (BA), may be bent to form a curved surface or bent in a vertical direction.

[0051] In the case where at least one of the remaining edges, excluding the edge (side) connected to the bending area (BA) in the main area (MA), forms a curved surface or is bent, a display area (DA) may also be placed on that edge. However, not limited thereto, a non-display area (NDA) that does not display a screen may be placed on the curved or bent edge, or a display area (DA) and a non-display area (NDA) may be placed together.

[0052] The non-display area (NDA) of the main area (MA) may be placed in the area from the outer boundary of the display area (DA) to the edge of the display panel (10). Signal wiring or driving circuits for applying a signal to the display area (DA) may be placed in the non-display area (NDA) of the main area (MA).

[0053] The bending region (BA) can be connected through one side of the main region (MA). The width of the bending region (BA) (width of the first direction (DR1)) may be smaller than the width of the main region (MA) (width of the side). The connection between the main region (MA) and the bending region (BA) may have a planar L-shaped cutting form to reduce the width of the bezel.

[0054] In the bending area (BA), the display panel (10) can be bent with curvature in the opposite direction of the display surface. As the display panel (10) is bent in the bending area (BA), the surface of the display panel (10) can be reversed. That is, one side of the display panel (10) facing upward can be changed to face outward through the bending area (BA) and then back to face downward.

[0055] The sub-region (SA) extends from the bending area (BA). The sub-region (SA) may extend in a direction parallel to the main area (MA), starting from after the bending is completed. The sub-region (SA) may overlap with the main area (MA) in the thickness direction of the display panel (10). The sub-region (SA) may overlap with the non-display area (NDA) at the edge of the main area (MA), and further overlap with the display area (DA) of the main area (MA). The width of the sub-region (SA) may be the same as the width of the bending area (BA), but is not limited thereto.

[0056] A pad portion (not shown) may be disposed on a sub-region (SA) of a display panel (10). An external device may be mounted (or attached) to the pad portion (not shown). Examples of external devices include a driving chip (20), a driving board (30) made of a flexible printed circuit board or a rigid printed circuit board, and other devices such as a wiring connection film or a connector may also be mounted on the pad portion as external devices. The external device mounted on the sub-region (SA) may be one, but may be multiple. For example, as illustrated in FIGS. 1 and 2, a driving chip (20) may be disposed on a sub-region (SA) of a display panel (10), and a driving board (30) may be attached to an end of the sub-region (SA). In this case, the display panel (10) may include both a pad portion connected to the driving chip (20) and a pad portion connected to the driving board (30). In another embodiment, a driving chip may be mounted on a film, and the film may be attached to a sub-region (SA) of a display panel (10).

[0057] The driving chip (20) is mounted on one side of the display panel (10) which is the same as the display surface, and as the bending region (BA) is bent and inverted as described above, it is mounted on the side of the display panel (10) facing downward in the thickness direction so that the upper surface of the driving chip (20) can face downward.

[0058] The driving chip (20) may be attached to the display panel (10) via an anisotropic conductive film or via ultrasonic bonding. The driving chip (20) may include an integrated circuit that drives the display panel (10).

[0059] FIG. 3 is a circuit diagram showing a pixel in detail according to one embodiment.

[0060] Referring to FIG. 3, the circuit of a pixel (PX) includes a plurality of transistors (T1 to T7), a capacitor (Cst), and a light-emitting element (LE). A data signal (DATA), a first scan signal (GW), a second scan signal (GI), a third scan signal (GB), a light emission control signal (EM), a first power supply voltage (ELVDD), a second power supply voltage (ELVSS), and an initialization voltage (VINT) are applied to the circuit of a pixel (PX).

[0061] The light-emitting element (LE) may be an organic light-emitting diode comprising, for example, a first electrode (or anode electrode, see 'ANO' in FIG. 5), a light-emitting layer (see 'EL' in FIG. 5), and a second electrode (or cathode electrode, see 'CAT' in FIG. 5), although not limited thereto.

[0062] A plurality of transistors may include first to seventh transistors (T1 to T7). Each transistor (T1 to T7) includes a gate electrode, a first electrode (or, a first source / drain electrode), and a second electrode (or, a second source / drain electrode). Of the first electrode and the second electrode of each transistor (T1 to T7), one becomes the source electrode and the other becomes the drain electrode.

[0063] The first transistor (T1) acts as a driving transistor, and the second to seventh transistors (T2 to T7) can act as switching transistors. Each transistor (T1 to T7) includes a gate electrode, a first electrode, and a second electrode. Of the first electrode and the second electrode of each transistor (T1 to T7), one becomes the source electrode and the other becomes the drain electrode.

[0064] Each transistor (T1 to T7) may be a thin-film transistor. Each transistor (T1 to T7) may be either a PMOS transistor or an NMOS transistor. In one embodiment, the first transistor (T1) which is a driving transistor, the second transistor (T2) which is a data transfer transistor, the third transistor (T3) which is a compensation transistor, the fourth transistor (T4) which is a first initialization transistor, the fifth transistor (T5) which is a first light emission control transistor, the sixth transistor (T6) which is a second light emission control transistor, and the seventh transistor (T7) which is a second initialization transistor are all PMOS transistors.

[0065] However, this is not limited thereto, and for example, the third transistor (T3), which is a compensation transistor, and the fourth transistor (T4), which is a first initialization transistor, may be NMOS transistors, and the first transistor (T1), which is a driving transistor, the second transistor (T2), which is a data transfer transistor, the fifth transistor (T5), which is a first light emission control transistor, the sixth transistor (T6), which is a second light emission control transistor, and the seventh transistor (T7), which is a second initialization transistor, may be PMOS transistors. In this case, the active layer of the third transistor (T3) and the fourth transistor (T4), and the active layer of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may contain different materials. Although not limited thereto, for example, the active layers of the third transistor (T3) and the fourth transistor (T4) may comprise an oxide semiconductor, and the active layers of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6) and the seventh transistor (T7) may comprise polycrystalline silicon.

[0066] Below, each component is described in detail.

[0067] The gate electrode of the first transistor (T1) is connected to the first electrode of the capacitor (Cst). The first electrode of the first transistor (T1) is connected to the first power supply voltage line (ELVDDL) via the fifth transistor (T5). The second electrode of the first transistor (T1) is connected to the anode electrode of the light-emitting element (LE) via the sixth transistor (T6). The first transistor (T1) receives a data signal (DATA) according to the switching operation of the second transistor (T2) and supplies a driving current to the light-emitting element (LE).

[0068] The gate electrode of the second transistor (T2) is connected to the first scan signal (GW) line. The first electrode of the second transistor (T2) is connected to the data signal (DATA) line. The second electrode of the second transistor (T2) is connected to the first electrode of the first transistor (T1). The second transistor (T2) is turned on according to the first scan signal (GW) and performs a switching operation to transmit the data signal (DATA) to the first electrode of the first transistor (T1).

[0069] The third transistor (T3) may be formed as a dual transistor comprising a first sub-transistor (T3_1) and a second sub-transistor (T3_2). The gate electrode of the first sub-transistor (T3_1) is connected to a first scan signal (GW) line, and the first electrode is connected to the second electrode of the second sub-transistor (T3_2), and the second electrode is connected together with the first electrode of the capacitor (Cst), the first electrode of the third sub-transistor (T4_1), and the gate electrode of the first transistor (T1). The gate electrode of the second sub-transistor (T3_2) is connected to a first scan signal (GW) line, the first electrode is connected to the second electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the first sub-transistor (T3_1).

[0070] The first sub-transistor (T3_1) and the second sub-transistor (T3_2) are turned on by the first scan signal (GW) to connect the gate electrode of the first transistor (T1) and the second electrode, thereby diode-connecting the first transistor (T1). Accordingly, a voltage difference equal to the threshold voltage of the first transistor (T1) is generated between the first electrode and the gate electrode of the first transistor (T1), and the threshold voltage deviation of the first transistor (T1) can be compensated by supplying a data signal (DATA) with the threshold voltage compensated to the gate electrode of the first transistor (T1).

[0071] The fourth transistor (T4) may be formed as a dual transistor comprising a third sub-transistor (T4_1) and a fourth sub-transistor (T4_2). The gate electrode of the third sub-transistor (T4_1) is connected to the second scan signal (GI) line, and the first electrode is connected together with the first electrode of the capacitor (Cst), the second electrode of the first sub-transistor (T3_1), and the gate electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the fourth sub-transistor (T4_2). The gate electrode of the fourth sub-transistor (T4_2) is connected to the second scan signal (GI) line, the first electrode is connected to the second electrode of the third sub-transistor (T4_1), and the second electrode may be connected to the initialization voltage (VINT). The third sub-transistor (T4_1) and the fourth sub-transistor (T4_2) are turned on by the second scan signal (GI) to transmit an initialization voltage (VINT) to the gate electrode of the first transistor (T1) and perform the operation of initializing the voltage of the gate electrode of the first transistor (T1).

[0072] The gate electrode of the fifth transistor (T5) is connected to the light emission control signal (EM) line, the first electrode is connected to the first power supply voltage line (ELVDDL), and the second electrode is connected to the first electrode of the first transistor (T1). The fifth transistor (T5) is turned on by the light emission control signal (EM) to connect the first electrode of the first transistor (T1) with the first power supply voltage line (ELVDDL).

[0073] The sixth transistor (T6) is connected between the second electrode of the first transistor (T1) and the first electrode of the light-emitting element (LE). The gate electrode of the sixth transistor (T6) is connected to the light-emitting control signal (EM) line, the first electrode is connected to the second electrode of the first transistor (T1) and the first electrode of the second sub-transistor (T3_2), and the second electrode is connected to the first electrode of the light-emitting element (LE).

[0074] The fifth transistor (T5) and the sixth transistor (T6) are turned on simultaneously according to the light emission control signal (EM), and accordingly, a driving current flows to the light-emitting element (LE).

[0075] The gate electrode of the seventh transistor (T7) is connected to the third scan signal (GB) line. The first electrode of the seventh transistor (T7) is connected to the anode electrode of the light-emitting element (LE). The second electrode of the seventh transistor (T7) is connected to the initialization voltage (VINT) line. The seventh transistor (T7) is turned on according to the third scan signal (GB) to initialize the anode electrode of the organic light-emitting element (OLED).

[0076] In this embodiment, the case where the gate electrode of the seventh transistor (T7) receives the third scan signal (GB) has been exemplified, but in other embodiments, the circuit of the pixel (PX) may be configured so that the gate electrode of the seventh transistor (T7) receives the light emission control signal (EM) or the second scan signal (GI).

[0077] A capacitor (Cst) is formed between the gate electrode of the first transistor (T1) and the first power supply voltage line (ELVDDL) and includes a first electrode and a second electrode. The first electrode of the capacitor (Cst) is connected together to the gate electrode of the first transistor (T1), the second electrode of the third transistor (T3), and the first electrode of the fourth transistor (T4), and the second electrode of the capacitor (Cst) can be connected to the first power supply voltage line (ELVDDL). The capacitor (Cst) can serve to maintain a constant data voltage applied to the gate electrode of the first transistor (T1).

[0078] The cathode electrode of the light-emitting element (LE) is connected to the second power supply voltage line (ELVSSL) and receives the second power supply voltage (ELVSS) from the second power supply voltage line (ELVSSL). The light-emitting element (LE) receives a driving current from the first transistor (T1) and emits light to display an image.

[0079] The cross-sectional structure of the pixel (PX) described above will be explained in detail below.

[0080] FIG. 4 is a cross-sectional view of a pixel of a display panel according to one embodiment.

[0081] Referring to FIG. 4, a display panel (10) may include a substrate (SUB), a buffer layer (BF), a semiconductor layer (110), a first insulating layer (121, a first inorganic insulating layer), a first conductive layer (130), a second insulating layer (122, a second inorganic insulating layer), a second conductive layer (140), a third insulating layer (123, a third inorganic insulating layer), a third conductive layer (150), a fourth insulating layer (124, a first organic insulating layer), a fourth conductive layer (160), a fifth insulating layer (125, a second organic insulating layer), a fifth conductive layer (170), a sixth insulating layer (126, a third organic insulating layer), an anode electrode (ANO), a pixel defining layer (PDL), an emitting layer (EML), a cathode electrode (CAT), and an encapsulation layer (180). Each layer may be stacked sequentially in the order described above. Additionally, each layer may be composed of a single film, but may also be composed of a stacked film including a plurality of films. Other layers may be placed between each layer.

[0082] The substrate (SUB) supports each layer placed thereon. If the organic light-emitting display is of the back or double-sided emitting type, a transparent substrate may be used. If the organic light-emitting display is of the front emitting type, not only a transparent substrate but also a translucent or opaque substrate may be applied.

[0083] The substrate (SUB) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. Examples of materials that make up a flexible substrate include polyimide (PI), but are not limited thereto.

[0084] A buffer layer (BF) may be disposed on a substrate (SUB). The buffer layer (BF) can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and perform a surface planarization function. The buffer layer (BF) may include silicon nitride, but is not limited thereto, and may include silicon oxide or silicon oxynitride, etc. The buffer layer (BF) may be omitted depending on the type of substrate (SUB) or process conditions.

[0085] A semiconductor layer (110) is placed on a buffer layer (BF). The semiconductor layer (110) forms a channel of a thin-film transistor of a pixel. The semiconductor layer (110) may include polycrystalline silicon. However, it is not limited thereto, and the semiconductor layer (110) may include single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. The oxide semiconductor may include, for example, a binary compound (ABx), a ternary compound (ABxCy), or a quaternary compound (ABxCyDz) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc.

[0086] A first insulating layer (121) is disposed on a semiconductor layer (110). The first insulating layer (121) may be a first gate insulating film having a gate insulating function. The first insulating layer (121) may include an inorganic insulating material. The first insulating layer (121) may include a silicon compound, a metal oxide, etc. For example, the first insulating layer (121) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0087] The first conductive layer (130) is disposed on the first insulating layer (121). The first conductive layer (130) may include the gate electrode (GAT) of the thin-film transistor of the pixel, the scan line connected thereto, and the first electrode (CE1) of the holding capacitor (Cst).

[0088] The first conductive layer (130) may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0089] The second insulating layer (122) may be disposed on the first conductive layer (130). The second insulating layer (122) may be an interlayer insulating film or a second gate insulating film. The second insulating layer (122) may include an inorganic insulating material. The second insulating layer (122) may include the same material as the first insulating layer (121), but is not limited thereto.

[0090] The second conductive layer (140) is disposed on the second insulating layer (122). The second conductive layer (140) may include the second electrode (CE2) of the retaining capacitor (Cst). The second conductive layer (140) may be made of the same material as the first conductive layer (130), but is not limited thereto.

[0091] A third insulating layer (123) is disposed on the second conductive layer (140). The third insulating layer (123) may be an interlayer insulating film. The third insulating layer (123) may include an inorganic insulating material. The third insulating layer (123) may include the same material as the first insulating layer (121), but is not limited thereto.

[0092] A third conductive layer (150) is disposed on the third insulating layer (123). The third conductive layer (150) may include the first electrode (SD1) and the second electrode (SD2) of the thin-film transistor of the pixel. The first electrode (SD1) and the second electrode (SD2) of the thin-film transistor may be electrically connected to the source region and the drain region of the semiconductor layer (110) through a contact hole penetrating the third insulating layer (123), the second insulating layer (122), and the first insulating layer (121). The first power supply voltage line (ELVDDL) of the pixel may also be made of the third conductive layer (150). The first power supply voltage line (ELVDDL) may be electrically connected to the second electrode (CE2) of the retaining capacitor (Cst) through a contact hole penetrating the third insulating layer (123).

[0093] The third conductive layer (150) may include one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer (150) may include a plurality of stacked structures. For example, the third conductive layer (150) may be formed with a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0094] A fourth insulating layer (124) is disposed on the third conductive layer (150). The fourth insulating layer (124) covers the third conductive layer (150). The fourth insulating layer (124) may be a via layer. The fourth insulating layer (124) may include an organic insulating material. For example, the fourth insulating layer (124) may include polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenyleneethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB), etc.

[0095] The fourth conductive layer (160) is disposed on the fourth insulating layer (124). The fourth conductive layer (160) may include a first anode connecting electrode (CNE1). The first anode connecting electrode (CNE1) may be electrically connected to the second electrode (SD2) of the thin-film transistor through a contact hole penetrating the fourth insulating layer (124). Through the first anode connecting electrode (CNE1) and the second anode connecting electrode (CNE2), the anode electrode (ANO) and the second electrode (SD2) of the thin-film transistor may be electrically connected. The fourth conductive layer (160) may include the same material as the third conductive layer (150) or the same stacked structure, but is not limited thereto.

[0096] The fifth insulating layer (125) is disposed on the fourth conductive layer (160). The fifth insulating layer (125) covers the fourth conductive layer (160). The fifth insulating layer (125) may be a via layer. The fifth insulating layer (125) may include an organic insulating material. The fifth insulating layer (125) may include the same material as the fourth insulating layer (124), but is not limited thereto.

[0097] A fifth conductive layer (170) is disposed on the fifth insulating layer (125). The fifth conductive layer (170) may include a second anode connecting electrode (CNE2). The fifth conductive layer (170) may further include a second power supply voltage line (ELVSSL, see FIG. 3). The second anode connecting electrode (CNE2) may be electrically connected to a first anode connecting electrode (CNE1) through a contact hole penetrating the fifth insulating layer (125). The fifth conductive layer (170) may include the same material as the third conductive layer (150) or the same laminated structure, but is not limited thereto.

[0098] A sixth insulating layer (126) is disposed on the fifth conductive layer (170). The sixth insulating layer (126) covers the fifth conductive layer (170). The sixth insulating layer (126) may be a via layer. The sixth insulating layer (126) may include an organic insulating material. The sixth insulating layer (126) may include the same material as the fourth insulating layer (124), but is not limited thereto.

[0099] The anode electrode (ANO) is disposed on the sixth insulating layer (126). The anode electrode (ANO) may be a pixel electrode provided for each pixel. The anode electrode (ANO) may be connected to the second anode connecting electrode (CNE2) through a contact hole penetrating the sixth insulating layer (126). The anode electrode (ANO) may overlap at least partially with the light-emitting region (EMA) of the pixel.

[0100] The anode electrode (ANO) may have a stacked structure in which a layer of a material with a high work function, such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and a layer of a reflective material, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof, are stacked. The layer with a high work function may be positioned above the reflective material layer and close to the light-emitting layer (EML). The anode electrode (ANO) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but is not limited thereto.

[0101] A pixel defining layer (PDL) may be disposed on an anode electrode (ANO). The pixel defining layer (PDL) may include an opening that exposes the anode electrode (ANO). A light-emitting region (EMA) and a non-light-emitting region (NEM) may be separated by the pixel defining layer (PDL) and the opening. The pixel defining layer (PDL) may include organic insulating materials such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenyleneethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB). The pixel defining layer (PDL) may also include inorganic materials.

[0102] The light-emitting layer (EML) is disposed on the anode electrode (ANO) exposed by the pixel defining layer (PDL). The light-emitting layer (EML) may include an organic material layer. The organic material layer of the light-emitting layer includes an organic light-emitting layer and may further include a hole injection / transport layer and / or an electron injection / transport layer.

[0103] The cathode electrode (CAT) can be placed on the light-emitting layer (EML). The cathode electrode (CAT) may be a common electrode placed across the entire surface without distinguishing pixels. The anode electrode (ANO), the light-emitting layer (EML), and the cathode electrode (CAT) can each constitute an organic light-emitting device.

[0104] The cathode electrode (CAT) may contact not only the light-emitting layer (EML) but also the upper surface of the pixel defining film (PDL). The cathode electrode (CAT) may be formed conformally to the underlying structure to reflect the step difference of the underlying structure.

[0105] The cathode electrode (CAT) may include a layer of material with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The cathode electrode (CAT) may further include a transparent metal oxide layer disposed on the layer of material with a low work function.

[0106] The encapsulation layer (180) may be disposed on the cathode electrode (CAT). The encapsulation layer (180) may include a first inorganic encapsulation film (181), an organic encapsulation film (182), and a second inorganic encapsulation film (183). At the ends of the encapsulation layer (180), the first inorganic encapsulation film (181) and the second inorganic encapsulation film (183) may come into contact with each other. The organic encapsulation film (182) may be sealed by the first inorganic encapsulation film (181) and the second inorganic encapsulation film (183).

[0107] The first inorganic sealing film (181) and the second inorganic sealing film (183) may each include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride. The organic sealing film (182) may include an organic insulating material.

[0108] Figure 5 is an enlarged view of area A of Figure 1.

[0109] Referring to FIG. 5, the display panel (10) may further include a dam structure (DAM), a bank structure (BNK), a scan drive unit (SDU), and a scan control line (SCL).

[0110] The dam structure (DAM) is placed in the non-marked area (NDA) and may surround the marked area (DA). The marked area (DA) may be placed within the area surrounded by the dam structure (DAM). The dam structure (DAM) may serve to inhibit or prevent organic material inside the dam structure (DAM) from overflowing to the outside of the dam structure (DAM).

[0111] The bank structure (BNK) is placed in the non-display area (NDA) and can surround the dam structure (DAM). The dam structure (DAM) can be placed within the area surrounded by the bank structure (BNK). The bank structure (BNK) can serve to support a mask (e.g., a fine metal mask (FMM) mask) used in the manufacture of the display panel (10).

[0112] The display panel (10) may further include an inorganic encapsulation region (CVD). The inorganic encapsulation region (CVD) may be positioned between the dam structure (DAM) and the bank structure (BNK). In the inorganic encapsulation region (CVD), the organic encapsulation film (182, see FIG. 4) of the encapsulation layer (180, see FIG. 4) may not be positioned, and accordingly, the first inorganic film (181, see FIG. 4) and the second inorganic film (183, see FIG. 4) of the encapsulation layer (180, see FIG. 4) may be in direct contact with each other. In the inorganic encapsulation region (CVD), only the inorganic film (inorganic insulating layer and inorganic encapsulation film) may be positioned, and the organic film (organic insulating layer and organic encapsulation film) may not be positioned. A detailed description of the inorganic encapsulation region (CVD) will be provided later.

[0113] The scan driver unit (SDU) may be placed in the non-display area (NDA). The scan driver unit (SDU) may be placed on at least one side and the other side of the first direction (DR1) of the display area (DA). The scan driver unit (SDU) may be electrically connected to the driver chip (20, see FIG. 1) through the scan control line (SCL). The scan driver unit (SDU) may receive a scan timing signal from the driver chip (20, see FIG. 1). The scan driver unit (SDU) may generate scan signals according to the scan timing signal. The scan driver unit (SDU) may output the scan signal to the gate electrode (GAT) of the thin-film transistor of the pixel through the scan line.

[0114] The scan control line (SCL) may be placed in the non-display area (NDA). The scan control line (SCL) may be placed on the other side of the second direction (DR2) of the display area (DA). The scan control line (SCL) may extend from the lower side of the scan drive unit (SDU) to the drive chip (20, see FIG. 1). The scan control line (SCL) may overlap with the dam structure (DAM). In other words, the scan control line (SCL) extending from the scan drive unit (SDU) may extend in the first direction (DR1) inside the dam structure (DAM), then extend across the dam structure (DAM) to the other side of the second direction (DR2), and be connected to the drive chip (20, see FIG. 1). At the point where the scan control line (SCL) intersects the dam structure (DAM), the scan control line (SCL) may overlap with the dam structure (DAM).

[0115] The first power supply voltage line (ELVDDL) may be separated and spaced apart from the second power supply voltage line (ELVSSL). The first power supply voltage line (ELVDDL) may be placed on the other side of the second direction (DR2) of the display area (DA).

[0116] The second power voltage line (ELVSSL) may be placed in the non-display area (NDA). The second power voltage line (ELVSSL) may extend from the driver chip (20, see FIG. 1), bypass the display area (DA), and extend back to the driver chip (20, see FIG. 1). In other words, one end and the other end of the second power voltage line (ELVSSL) are connected to the driver chip (20, see FIG. 1), and the second power voltage line (ELVSSL) may extend by bypassing three sides of the display area (DA) (one side and the other side of the first direction (DR1) and one side of the second direction (DR2). The second power voltage line (ELVSSL) may be placed outside the scan driver unit (SDU). However, it is not limited thereto, and the second power voltage line (ELVSSL) may overlap with the scan driver unit (SDU).

[0117] The second power voltage line (ELVSSL) may overlap with the dam structure (DAM) and the bank structure (BNK). The second power voltage line (ELVSSL) may generally be placed inside the bank structure (BNK). The second power voltage line (ELVSSL) overlaps with the dam structure (DAM) inside the bank structure (BNK) and extends along the dam structure (DAM), then extends to the other side of the second direction (DR2) and can be connected to the driver chip (20, see FIG. 1). The second power voltage line (ELVSSL) extends to one side of the first direction (DR1) from the lower side of the display area (DA), then extends to the other side of the second direction (DR2), and can intersect with the bank structure (BNK). In the area where the second power voltage line (ELVSSL) intersects with the bank structure (BNK), the second power voltage line (ELVSSL) may overlap with the bank structure (BNK).

[0118] Referring to FIG. 6, the cross-sectional structure of the second power voltage line (ELVSSL), dam structure (DAM), and bank structure (BNK) will be described.

[0119] Figure 6 is a cross-sectional view taken along the line VI-VI' of Figure 5.

[0120] Referring to FIGS. 5 and 6, the dam structure (DAM) may include a first sub-dam structure (DAM1), a second sub-dam structure (DAM2), a third sub-dam structure (DAM3), a fourth sub-dam structure (DAM4), and a dam spacer (DAM5) stacked sequentially. The bank structure (BNK) may include a first sub-bank structure (BNK1), a second sub-bank structure (BNK2), a third sub-bank structure (BNK3), a fourth sub-bank structure (BNK4), and a bank spacer (BNK5) stacked sequentially.

[0121] The first sub-dam structure (DAM1) and the first sub-bank structure (BNK1) may be composed of a fourth insulating layer (124). In other words, since the first sub-dam structure (DAM1) and the first sub-bank structure (BNK1) are formed by the same process as the fourth insulating layer (124), the first sub-dam structure (DAM1) and the first sub-bank structure (BNK1) may contain substantially the same material as the fourth insulating layer (124). Additionally, the first sub-dam structure (DAM1), the first sub-bank structure (BNK1), and the fourth insulating layer (124) may be substantially the same layer. The first sub-dam structure (DAM1) and the first sub-bank structure (BNK1) may be placed on a third insulating layer (123).

[0122] The second sub-dam structure (DAM2) and the second sub-bank structure (BNK2) may be composed of a fifth insulating layer (125). In other words, since the second sub-dam structure (DAM2) and the second sub-bank structure (BNK2) are formed by the same process as the fifth insulating layer (125), the second sub-dam structure (DAM2) and the second sub-bank structure (BNK2) may contain substantially the same material as the fifth insulating layer (125). Additionally, the second sub-dam structure (DAM2) and the second sub-bank structure (BNK2) may be placed on the same layer as the fifth insulating layer (125). The second sub-dam structure (DAM2) and the second sub-bank structure (BNK2) may be placed on the first sub-dam structure (DAM1) and the first sub-bank structure (BNK1), respectively. A second power voltage line (ELVSSL) may be placed on the second sub-dam structure (DAM2) and the second sub-bank structure (BNK2). The second power voltage line (ELVSSL) may be made of a fifth conductive layer (170).

[0123] The third sub-dam structure (DAM3) and the third sub-bank structure (BNK3) may be made of the sixth insulating layer (126). In other words, since the third sub-dam structure (DAM3) and the third sub-bank structure (BNK3) are formed by the same process as the sixth insulating layer (126), the third sub-dam structure (DAM3) and the third sub-bank structure (BNK3) may contain substantially the same material as the sixth insulating layer (126). Each of the third sub-dam structure (DAM3) and the third sub-bank structure (BNK3) may be placed on the second sub-dam structure (DAM2) and the second sub-bank structure (BNK2) with the second power voltage line (ELVSSL) in between.

[0124] The fourth sub-dam structure (DAM4) and the fourth sub-bank structure (BNK4) may be composed of a pixel defining film (PDL). In other words, since the fourth sub-dam structure (DAM4) and the fourth sub-bank structure (BNK4) are formed by the same process as the pixel defining film (PDL), the fourth sub-dam structure (DAM4) and the fourth sub-bank structure (BNK4) may contain substantially the same material as the pixel defining film (PDL). Additionally, the fourth sub-dam structure (DAM4) and the fourth sub-bank structure (BNK4) may be placed on the same layer as the pixel defining film (PDL). The fourth sub-dam structure (DAM4) and the fourth sub-bank structure (BNK4) may be placed on the third sub-dam structure (DAM3) and the third sub-bank structure (BNK3), respectively.

[0125] The dam spacer (DAM5) may protrude upward from the fourth sub-dam structure (DAM4) in the thickness direction (third direction (DR3)). The bank spacer (BNK5) may protrude upward from the fourth sub-bank structure (BNK4) in the thickness direction (third direction (DR3)). The dam spacer (DAM5) and the bank spacer (BNK5) may serve to support a mask (e.g., an FMM (fine metal mask) mask).

[0126] In the inorganic encapsulation region (CVD), the second power voltage line (ELVSSL) may be exposed by the sixth insulating layer (126) and the pixel defining film (PDL). In other words, the second power voltage line (ELVSSL) may be exposed by the third sub-dam structure (DAM3) and the third sub-bank structure (BNK3) made of the sixth insulating layer (126), and the fourth sub-dam structure (DAM4) and the fourth sub-bank structure (BNK4) made of the pixel defining film (PDL).

[0127] In the inorganic encapsulation region (CVD), the second power voltage line (ELVSSL) can be in direct contact with the first inorganic encapsulation film (181). In the inorganic encapsulation region (CVD), the first inorganic encapsulation film (181) can be in direct contact with the second inorganic encapsulation film (183). In the inorganic encapsulation region (CVD), organic films, such as the fourth insulating layer (124), the fifth insulating layer (125), the sixth insulating layer (126), the pixel defining film (PDL), and the organic encapsulation film (182), may not be placed. That is, the encapsulation layer (180) can seal the organic encapsulation film (182) in the inorganic encapsulation region (CVD). By the inorganic encapsulation region (CVD), external air and moisture that could penetrate into the interior of the display panel (10) along the organic film can be blocked.

[0128] The second power supply voltage line (ELVSSL) may overlap with the signal transmission line in the inorganic encapsulation region (CVD). For example, the second power supply voltage line (ELVSSL) may overlap with the scan control line (SCL). At least a portion of the area where the second power supply voltage line (ELVSSL) and the scan control line (SCL) overlap may be placed in the inorganic encapsulation region (CVD). In other words, the second power supply voltage line (ELVSSL) may overlap with the scan control line (SCL) in the inorganic encapsulation region (CVD). In this case, an anti-etching pattern (EST, see FIG. 7) may be further placed between the second power supply voltage line (ELVSSL) and the scan control line (SCL) in the inorganic encapsulation region (CVD), thereby suppressing or preventing defects such as current leakage between the second power supply voltage line (ELVSSL) and the scan control line (SCL).

[0129] However, the signal transmission line is not limited to the scan control line (SCL). The second power voltage line (ELVSSL) may overlap with the data signal wiring that transmits the data signal.

[0130] FIG. 7 is an enlarged view of region B of FIG. 5. FIG. 8 is a cross-sectional view taken along the line VIII-VIII' of FIG. 7. FIG. 9 is an enlarged view of region C of FIG. 8.

[0131] Referring to FIGS. 7 through 9, the display panel (10) may further include an etch-prevention pattern (EST). The etch-prevention pattern (EST) may overlap with at least a portion of the second power supply voltage line (ELVSSL). At least a portion of the etch-prevention pattern (EST) may be positioned between the second power supply voltage line (ELVSSL) and the scan control line (SCL) with respect to the thickness direction (third direction (DR3)) in the inorganic encapsulation region (CVD).

[0132] In other words, the display panel (10) may further include an overlapping area (OA) in which the second power voltage line (ELVSSL) and the scan control line (SCL) overlap in the thickness direction (third direction (DR3)). At least a portion of the overlapping area (OA) may be located within the inorganic encapsulation area (CVD). At least a portion of the etch-resistant pattern (EST) may be placed within the overlapping area (OA). At least a portion of the etch-resistant pattern (EST) may be placed within the inorganic encapsulation area (CVD).

[0133] In the inorganic encapsulation region (CVD), the etch prevention pattern (EST) can be in direct contact with the second power supply voltage line (ELVSSL). The etch prevention pattern (EST) may be formed by the fourth conductive layer (160). However, it is not limited thereto, and the etch prevention pattern (EST) may also be formed by the third conductive layer (150, see FIG. 4).

[0134] The etching prevention pattern (EST) can suppress or prevent the thickness of the inorganic film below the second power voltage line (ELVSSL) from being reduced by etching. For example, if the etching prevention pattern (EST) is formed by the fourth conductive layer (160), the thickness of the third insulating layer (123) in the portion that does not overlap with the fourth conductive layer (160) may be reduced by etching the upper portion together during the patterning process of the fourth conductive layer (160). When the thickness of the third insulating layer (123) is reduced, the distance between the second power voltage line (ELVSSL) and the scan control line (SCL) (or the thickness of the inorganic film between the second power voltage line (ELVSSL) and the scan control line (SCL)) may be reduced.

[0135] In particular, when the thickness of the third insulating layer (123) is reduced in the inorganic encapsulation region (CVD) where only an inorganic film is disposed between the second power voltage line (ELVSSL) and the scan control line (SCL), defects such as short circuits between the second power voltage line (ELVSSL) and the scan control line (SCL) caused by air gaps that may occur on the side of the scan control line (SCL), current leakage caused by short circuits, and coupling caused by parasitic capacitance formed between the second power voltage line (ELVSSL) and the scan control line (SCL) may occur.

[0136] However, in the overlapping area (OA) where the second power supply voltage line (ELVSSL) and the scan control line (SCL) overlap, if an etching prevention pattern (EST) is placed between the second power supply voltage line (ELVSSL) and the scan control line (SCL), even if the fourth conductive layer (160) is patterned, the thickness of the third insulating layer (123) overlapping with the etching prevention pattern (EST) may not decrease.

[0137] In other words, the third insulating layer (123) may include a first region (AR1) that overlaps with the etch prevention pattern (EST) in the thickness direction (third direction (DR3)) and a second region (AR2) that does not overlap with the etch prevention pattern (EST). The third insulating layer (123) may have a first thickness (TH1) in the first region (AR1) and a second thickness (TH2) in the second region (AR2). The size of the first thickness (TH1) may be larger than the size of the second thickness (TH2). Here, the second region (AR2) may refer to a region that does not overlap with the entire area of ​​the fourth conductive layer (160), as well as the etch prevention pattern (EST).

[0138] Accordingly, by means of an etching prevention pattern (EST), the reduction in thickness of the inorganic insulating film placed between the second power supply voltage line (ELVSSL) and the scan control line (SCL) in the inorganic encapsulation region (CVD) can be suppressed or prevented, and defects such as current leakage and coupling between the second power supply voltage line (ELVSSL) and the scan control line (SCL) can be suppressed or prevented.

[0139] In the foregoing, the case where the second power supply voltage line (ELVSSL) and the signal transmission line overlap has been described, but it is not limited thereto, and the description of the second power supply voltage line (ELVSSL) can be applied in the same way to the first power supply voltage line (ELVDDL).

[0140] Other embodiments are described below. In the following embodiments, descriptions of components identical to those already described are omitted or simplified, and the explanation focuses on the differences.

[0141] FIG. 10 is a partial plan view of a display panel according to another embodiment.

[0142] Referring to FIG. 10, the etching prevention pattern (EST_1) of the display panel (10_1) according to the present embodiment differs from the embodiment of FIG. 7 in that it is placed only within the inorganic encapsulation region (CVD). The etching prevention pattern (EST_1) is placed only within the inorganic encapsulation region (CVD) and can be placed within an overlapping region (OA) where the scan control line (SCL) and the second power supply voltage line (ELVSSL) overlap.

[0143] In this case as well, defects such as current leakage between the second power supply voltage line (ELVSSL) and the scan control line (SCL) can be suppressed or prevented by the etching prevention pattern (EST_1). Furthermore, various designs of the etching prevention pattern (EST_1) are possible as needed.

[0144] FIG. 11 is a partial plan view of a display panel according to another embodiment.

[0145] Referring to FIG. 11, the etching prevention pattern (EST_2) of the display panel (10_2) according to the present embodiment differs from the embodiment of FIG. 7 in that it overlaps with the entire area of ​​the second power supply voltage line (ELVSSL). The etching prevention pattern (EST_2) includes a pattern shape identical to the planar second power supply voltage line (ELVSSL) and can overlap with the entire area of ​​the second power supply voltage line (ELVSSL). Alternatively, the etching prevention pattern (EST_2) may have a larger area than the planar second power supply voltage line (ELVSSL). In other words, the etching prevention pattern (EST_2) overlaps with the entire area of ​​the second power supply voltage line (ELVSSL), and the second power supply voltage line (ELVSSL) can overlap with a part of the etching prevention pattern (EST_2).

[0146] In this case as well, defects such as current leakage between the second power supply voltage line (ELVSSL) and the scan control line (SCL) can be suppressed or prevented by the etching prevention pattern (EST_2). Furthermore, in the inorganic encapsulation region (CVD), the second power supply voltage line (ELVSSL) comes into direct contact with the etching prevention pattern (EST_2), which can have the effect of increasing the thickness of the second power supply voltage line (ELVSSL) and reducing the resistance of the wiring through which current flows due to the second power supply voltage (ELVSS).

[0147] Referring further to FIG. 5, the thickness of the second power voltage line (ELVSSL) may be smaller in the portion located on the other side of the second direction (DR2) of the display area (DA) than in the portion located on the other side of the first direction (DR1) of the display area (DA). In this case, by placing an etching prevention pattern (EST_2), even if the thickness is reduced in the portion located on the other side of the second direction (DR2) of the display area (DA), defects such as heat generation of the second power voltage line (ELVSSL) can be suppressed or prevented.

[0148] FIG. 12 is a cross-sectional view of a display panel according to another embodiment.

[0149] Referring to FIG. 12, the etching prevention pattern (EST_3) of the display panel (10_3) according to the present embodiment differs from the embodiment of FIG. 8 in that it can be formed of a third conductive layer (150). In this case as well, defects such as current leakage between the second power supply voltage line (ELVSSL) and the scan control line (SCL) can be suppressed or prevented by the etching prevention pattern (EST_3). Furthermore, as the etching prevention pattern (EST_3) is formed of the third conductive layer (150), the third insulating layer (123) may not undergo etching due to patterning of the fourth conductive layer (160), nor etching due to patterning of the third conductive layer (150). Therefore, the thickness of the third insulating layer (123) between the etching prevention pattern (EST_3) and the second power supply voltage line (ELVSSL) can be maintained more smoothly.

[0150] FIG. 13 is a cross-sectional view of a display panel according to another embodiment.

[0151] Referring to FIG. 13, the etching prevention pattern (EST_4) of the display panel (10_4) according to the present embodiment differs from the embodiment of FIG. 8 in that it may include a plurality of stacked structures. The etching prevention pattern (EST_4) may include a first stacked pattern (ST1) and a second stacked pattern (ST2) that are sequentially stacked. The first stacked pattern (ST1) may be composed of a third conductive layer (150), and the second stacked pattern (ST2) may be composed of a fourth conductive layer (160).

[0152] In this case as well, defects such as current leakage between the second power supply voltage line (ELVSSL) and the scan control line (SCL) can be suppressed or prevented by the etching prevention pattern (EST_4). Furthermore, as the etching prevention pattern (EST_4) is formed by the third conductive layer (150), the third insulating layer (123) may not undergo etching due to the patterning of the fourth conductive layer (160), nor etching due to the patterning of the third conductive layer (150). Therefore, the thickness of the third insulating layer (123) between the etching prevention pattern (EST_4) and the second power supply voltage line (ELVSSL) can be maintained more smoothly.

[0153] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0154] 1: Display device 10: Display panel DA: Display area NDA: Non-display area 130: 1st Challenge Floor 140: 2nd Challenge Floor 150: 3rd Challenge Floor 160: 4th Challenge Floor 170: 6th conductive layer ELVSSL: 2nd power supply voltage line DAM: Dam structure BNK: Bank structure CVD: Inorganic encapsulation region EST: Anti-etch pattern

Claims

Claim 1 A display device comprising: a plurality of light-emitting elements each comprising an anode electrode, a light-emitting layer, and a cathode electrode; a sealing layer disposed on the plurality of light-emitting elements and comprising a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film; a dam structure surrounding the display area; a bank structure disposed on the outside of the dam structure; a power supply voltage line electrically connected to the cathode electrode; a signal transmission line overlapping with the power supply voltage line; and an etching prevention pattern disposed between the power supply voltage line and the signal transmission line, wherein the device includes an inorganic sealing region disposed between the dam structure and the bank structure and in which the first inorganic sealing film and the second inorganic sealing film are in direct contact, the etching prevention pattern is disposed in the inorganic sealing region, and at least one insulating layer is interposed between the etching prevention pattern and the signal transmission line. Claim 2 A display device according to claim 1, wherein at least a portion of the overlapping area where the power supply voltage line and the signal transmission line overlap overlaps with the inorganic encapsulation area. Claim 3 A display device according to claim 2, wherein at least a portion of the etching prevention pattern overlaps with at least a portion of the overlapping area. Claim 4 A display device according to claim 1, further comprising a substrate, a first conductive layer disposed on the substrate, a first organic insulating layer disposed on the first conductive layer, a second conductive layer disposed on the first organic insulating layer, a second organic insulating layer disposed on the second conductive layer, and a third conductive layer disposed on the second organic insulating layer, wherein the power supply voltage line is formed on the third conductive layer. Claim 5 In claim 4, the etching prevention pattern is a display device comprising either the first conductive layer or the second conductive layer. Claim 6 In claim 5, the power supply voltage line and the etching prevention pattern are in direct contact with the display device. Claim 7 In claim 4, the etching prevention pattern comprises a first stacked pattern formed by the first conductive layer and a second stacked pattern formed by the second conductive layer, in a display device. Claim 8 A display device according to claim 4, further comprising a third organic insulating layer disposed on the third conductive layer, wherein the anode electrode is disposed on the third organic insulating layer. Claim 9 A display device according to claim 1, further comprising an inorganic insulating film disposed between the etching prevention pattern and the signal transmission line, wherein the inorganic insulating film has a first thickness in an area overlapping with the etching prevention pattern and a second thickness smaller than the first thickness in an area not overlapping with the etching prevention pattern. Claim 10 In claim 1, the first inorganic sealing film in the inorganic sealing region is a display device that is in direct contact with the power voltage line. Claim 11 A display device according to claim 1, further comprising a scan driving unit connected to one end of the signal transmission line and a driving chip connected to the other end of the signal transmission line. Claim 12 A display device according to claim 1, further comprising a non-display area disposed around the display area, wherein the power voltage line and the signal transmission line overlap in the non-display area. Claim 13 A display device comprising: a substrate; a signal transmission line disposed on the substrate; a first inorganic insulating layer disposed on the signal transmission line; a first conductive layer disposed on the first inorganic insulating layer; a first organic insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first organic insulating layer; a second organic insulating layer disposed on the second conductive layer; a third conductive layer disposed on the second organic insulating layer and including a power supply voltage line that overlaps with the signal transmission line; a third organic insulating layer disposed on the third conductive layer; a light-emitting element disposed on the third organic insulating layer and including an anode electrode, a light-emitting layer, and a cathode electrode electrically connected to the power supply voltage line; an encapsulation layer disposed on the cathode electrode and including a first inorganic encapsulation film, an organic encapsulation film, and a second inorganic encapsulation film; and an etching prevention pattern disposed in at least a portion of an overlapping region where the signal transmission line and the power supply voltage line overlap, wherein the first inorganic insulating layer is interposed between the etching prevention pattern and the signal transmission line. Claim 14 A display device according to claim 13, wherein the first inorganic encapsulation film and the second inorganic encapsulation film are in direct contact, and further comprises an inorganic encapsulation region that overlaps at least partially with the overlapping region, and wherein the etching prevention pattern comprises at least one of the first conductive layer and the second conductive layer, and is disposed in the overlapping region that overlaps with the inorganic encapsulation region. Claim 15 In claim 14, the display device further comprises a dam structure surrounding the light-emitting element and a bank structure disposed on the outside of the dam structure, wherein the inorganic encapsulation area is disposed between the dam structure and the bank structure. Claim 16 In claim 15, a display device in which the power voltage line and the first inorganic encapsulation film are in direct contact in the inorganic encapsulation region. Claim 17 In claim 14, the display device further comprises a display area where a screen display is performed and a non-display area disposed around the display area, wherein the weapon bag area is disposed in the non-display area. Claim 18 In claim 13, the power supply voltage line and the etching prevention pattern are in direct contact with the display device. Claim 19 A display device comprising: a plurality of light-emitting elements each including an anode electrode, a light-emitting layer, and a cathode electrode; a sealing layer disposed on the plurality of light-emitting elements and including a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film; a dam structure surrounding the display area; a bank structure disposed on the outside of the dam structure; a power supply voltage line electrically connected to the cathode electrode; a signal transmission line overlapping with the power supply voltage line; an etching prevention pattern disposed between the power supply voltage line and the signal transmission line; and an inorganic insulating film disposed between the etching prevention pattern and the signal transmission line, wherein the inorganic insulating film has a first thickness in the area overlapping with the etching prevention pattern and a second thickness smaller than the first thickness in the area not overlapping with the etching prevention pattern. Claim 20 A display device according to claim 19, further comprising an inorganic encapsulation region disposed between the dam structure and the bank structure, wherein the first inorganic encapsulation film and the second inorganic encapsulation film are in direct contact, wherein at least a portion of the overlapping region where the power voltage line and the signal transmission line overlap is disposed in the inorganic encapsulation region, and the etching prevention pattern is disposed in the inorganic encapsulation region that overlaps with the overlapping region.

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