Class-d amplifier and operation method thereof with delay-line method for slew rate control

Abstract

A Class D amplifier is disclosed comprising: a p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; and a driving circuit connected to the gate of the p-type output transistor and the gate of the n-type output transistor. The driving circuit receives an input signal, generates a p-type output transistor control signal applied to the gate of the p-type output transistor, and generates an n-type output transistor control signal applied to the gate of the n-type output transistor. When the input signal changes to logic high, the n-type output transistor control signal changes rapidly to logic low, but the p-type output transistor control signal changes gradually to logic low. When the input signal changes to logic low, the p-type output transistor control signal changes rapidly to logic high, but the n-type output transistor control signal changes gradually to logic high.

Description

Technology Field

[0001] The present invention relates to the field of electronic circuits in audio systems, and in particular, to automatic correction control of a Class D amplifier driving circuit. Background Technology

[0003] A Class D amplifier (also known as a switching amplifier) ​​is an electronic amplifier in which transistors act as binary switches, being fully energized or completely de-energized during operation. Class D amplifiers employ rail-to-rail output switching, and preferably, the output transistors of these amplifiers consistently deliver virtually zero current or zero voltage. Consequently, these Class D amplifiers consume very little power and provide high efficiency over a wide range of power levels. The high efficiency of these Class D amplifiers has facilitated their use in various audio applications, ranging from cellular phones to flat-screen televisions and home theater receivers. Class D audio power amplifiers are more efficient than Class AB audio power amplifiers. Because Class D amplifiers are more efficient, they require smaller power supplies and do not require heat sinks, significantly reducing the overall system cost, size, and weight. The problem to be solved

[0005] According to one embodiment, a Class D amplifier is provided. According to another embodiment, a method for operating a Class D amplifier is provided. means of solving the problem

[0007] According to one embodiment, a class-D amplifier is provided. The class-D amplifier includes a p-type output transistor. The class-D amplifier further includes an n-type output transistor connected in series with the p-type output transistor. The class-D amplifier includes a drive circuit connected to the gate of the p-type output transistor and the gate of the n-type output transistor. In this case, the drive circuit receives an input signal, and the drive circuit generates a p-type output transistor control signal that is applied to the gate of the p-type output transistor in response to the input signal, and the drive circuit generates an n-type output transistor control signal that is applied to the gate of the n-type output transistor in response to the input signal. When the input signal changes to logic high, the n-type output transistor control signal changes to logic low quickly, but the p-type output transistor control signal changes to logic low gradually. When the input signal changes to logic low, the p-type output transistor control signal changes to logic high quickly, but the n-type output transistor control signal changes to logic high gradually. According to one embodiment, when the input signal changes to logic high, the n-type output transistor control signal changes to logic low quickly, but the p-type output transistor control signal changes to logic low gradually, so that the p-type output transistor is gradually turned on after the n-type output transistor is turned off.According to one embodiment, when the input signal changes to logic high, the p-type output transistor control signal changes to logic low in a stepwise manner. According to one embodiment, when the input signal changes to logic low, the p-type output transistor control signal changes rapidly to logic high, but the n-type output transistor control signal changes gradually to logic high, so that the n-type output transistor is gradually turned on after the p-type output transistor is turned off. According to one embodiment, when the input signal changes to logic low, the n-type output transistor control signal changes to logic high in a stepwise manner. According to one embodiment, the driving circuit comprises a pulse width modulation (PWM) signal generator for generating the input signal, a multibit delay line circuit for receiving the input signal and generating a plurality of delayed input signals, an n-type current digital-to-analog converter (IDAC) for generating a first current in response to the plurality of delayed input signals, an n-type transistor connected between the p-type output transistor and the n-type IDAC, a p-type IDAC for generating a second current in response to the plurality of delayed input signals, and the It includes a p-type transistor connected between an n-type output transistor and the p-type IDAC. According to one embodiment, when the input signal changes to logic high, the p-type transistor is turned off, thereby turning off the connection between the p-type IDAC and the n-type output transistor, and at the same time, the n-type output transistor control signal changes to logic low. According to one embodiment, when the input signal changes to logic high, the n-type transistor is turned on, thereby connecting the n-type IDAC to the p-type output transistor, and the p-type output transistor control signal decreases as the first current increases.According to one embodiment, when the input signal changes to logic low, the n-type transistor is turned off, thereby turning off the connection between the n-type IDAC and the p-type output transistor, and at the same time, the p-type output transistor control signal changes to logic high. According to one embodiment, when the input signal changes to logic low, the p-type transistor is turned on, thereby connecting the p-type IDAC to the n-type output transistor, and the n-type output transistor control signal increases as the second current increases. According to one embodiment, the input signal is a PWM signal. According to one embodiment, the multibit delay line circuit includes a plurality of delay units connected in series, and each of the plurality of delay units provides a delay time. According to one embodiment, the delay times of the plurality of delay units are different from each other. According to one embodiment, the p-type IDAC includes a first current source, a first p-type transistor, and a plurality of current branches, and the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current amounts. According to one embodiment, the n-type IDAC includes a second current source, a first n-type It includes a transistor and a plurality of current branches, wherein the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current amounts.

[0008] According to another aspect, a method for operating a Class D amplifier is provided. In some embodiments, the Class D amplifier comprises a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor. The method comprises the steps of: receiving an input signal; generating a p-type output transistor control signal in response to the input signal using a driving circuit connected to the gate of the n-type output transistor and the gate of the p-type output transistor; generating an n-type output transistor control signal in response to the input signal using the driving circuit; applying the p-type output transistor control signal to the gate of the p-type output transistor; and applying the n-type output transistor control signal to the gate of the n-type output transistor. When the input signal changes to a logic high, the n-type output transistor control signal changes rapidly to a logic low, while the p-type output transistor control signal changes gradually to a logic low. When the input signal changes to a logic low, the p-type output transistor control signal changes rapidly to a logic high, while the n-type output transistor control signal changes gradually to a logic high.

[0009] According to one embodiment, when the input signal changes to logic high, the p-type output transistor control signal changes to logic low in stages. According to one embodiment, when the input signal changes to logic low, the n-type output transistor control signal changes to logic high in stages, thereby operating a Class D amplifier. According to one embodiment, the method further comprises the steps of generating a plurality of delayed input signals using a multibit delay line circuit, generating a first current in response to the plurality of delayed input signals using an n-type current digital-to-analog converter (IDAC), and generating a second current in response to the plurality of delayed input signals using a p-type IDAC. According to one embodiment, when the input signal changes to logic high: turning off the connection between the p-type IDAC and the n-type output transistor; and connecting the n-type IDAC to the p-type output transistor, wherein the p-type output transistor control signal decreases as the first current increases; and when the input signal changes to logic low: the connection between the n-type IDAC and the p-type output transistor is turned off, and the p-type IDAC is connected to the n-type output transistor, and the n-type output transistor control signal increases as the second current increases. Brief explanation of the drawing

[0010] The present disclosure is described in detail below with reference to the accompanying drawings to best understand the embodiments. However, it should be noted that, in accordance with standard practice in the art, various features are not depicted in proportion. For the sake of substantial clarity of description, the size of various features may be arbitrarily increased or decreased. FIG. 1A is a simple schematic diagram illustrating a conventional Class D amplifier. FIG. 1B is a waveform diagram illustrating the signal modulation of the Class D amplifier of FIG. 1A. FIG. 2 is a schematic block diagram illustrating a Class D amplifier with an improved slew rate. FIG. 3A is a schematic diagram illustrating the operation of a Class D amplifier when a p-type output transistor is gradually turned on. FIG. 3B is a schematic diagram illustrating the operation of a Class D amplifier when an n-type output transistor is gradually turned on. FIG. 4 is a drawing illustrating a section of a Class D amplifier according to some embodiments. FIG. 5 is a drawing illustrating another section of a Class D amplifier according to some embodiments. FIG. 6 is a diagram illustrating an exemplary multibit delay line circuit. FIG. 7 is a diagram illustrating a p-type output transistor control signal, an n-type output transistor control signal, an input signal, and an output signal when the input signal changes to logic high. FIG. 8 is a diagram illustrating a p-type output transistor control signal, an n-type output transistor control signal, an input signal, and an output signal when the input signal changes to logic low. FIG. 9 is a flowchart illustrating an exemplary method of operating a Class D amplifier. Specific details for implementing the invention

[0011] The present disclosure provides many different embodiments or examples for implementing various features of the gist of the invention presented. The present disclosure has been simplified in describing specific examples of components and arrangements. Naturally, such components and arrangements are merely examples and are not intended to be limiting. Meanwhile, the present disclosure may duplicate reference numerals and / or characters among the various examples. Such duplication is for simplicity and clarity and does not indicate a relationship between the various embodiments and / or configurations described.

[0012] Meanwhile, for the convenience of explanation, the relationship between one component or feature shown in the drawings and another component or feature may be described herein using, for example, "... below," "... downward," "lower," "... upward," "upper," and other similar spatially relative terms. In addition to the directions shown in the drawings, spatially relative terms are also intended to encompass different directions when the device is in use or operating. The device may be oriented in other directions (rotated 90 degrees or positioned in other directions), and likewise, the spatially relative descriptive terms used herein may be interpreted accordingly.

[0013] Meanwhile, the source / drain ("S / D") region may refer to a source or a drain individually or collectively depending on the context. For example, the device may include a first source / drain region, a second source / drain region, and other components. The first source / drain region may be a source region, the second source / drain region may be a drain region, and vice versa. Such various changes, modifications, and substitutions are obvious to those skilled in the art.

[0014] Some embodiments of the present disclosure are described. Additional operations may be provided prior to, during, and / or after the steps described in these embodiments. In various embodiments, some of the described steps may be substituted or omitted. In various embodiments, some of the features described below may be substituted or omitted, and additional features may be added. Although some embodiments describe a combination of operations performed in a specific order, these operations may be performed in a different logical order.

[0015] Class D audio power amplifiers convert audio input signals into high-frequency pulses that switch output transistors according to the audio input signal. Some Class D amplifiers use pulse width modulators (PWM) to generate a series of modulating pulses whose width varies according to the amplitude of the audio input signal. These width-varying pulses switch the output transistors via a fixed frequency. Other Class D amplifiers may rely on other types of pulse modulators. While the following discussion primarily focuses on pulse width modulators, those with ordinary knowledge in the field will understand that Class D amplifiers can be configured with other types of modulators.

[0016] FIG. 1A is a simplified schematic diagram illustrating a Class D amplifier (100), which is a conventional Class D amplifier. As shown in FIG. 1A, the Class D amplifier (100) is a differential amplifier. A pair of differential audio input signals (INP and INM) (i.e., a first audio input signal (INP) and a second audio input signal (INM)) are input to a first comparator (101) and a second comparator (102), respectively. Each of the pair of differential audio input signals (INP and INM) is compared with a triangular wave signal (VREF) (i.e., a signal having a triangular waveform; triangular signal) generated by an oscillator (103) to generate a first PWM signal (106) and a second PWM signal (107), respectively. The first audio input signal (INP) and the second audio input signal (INM) are differential signals, and since they use the same triangular wave signal (VREF) as a reference signal, the first PWM signal (106) and the second PWM signal (107) also correspond to differential signals (i.e., opposite directions).

[0017] The first PWM signal (106) is connected to the gate of the electrically connected output transistors (191, 192). Thus, the first PWM signal (106) controls the On / Off state of the output transistors (191, 192). The second PWM signal (107) is connected to the gate of the electrically connected output transistors (193, 194). Thus, the second PWM signal (107) controls the On / Off state of the output transistors (193, 194). Therefore, the first output signal (OUTM) and the second output signal (OUTP) of the Class D amplifier (100) are also differential output signals. As shown in FIG. 1A, the first output signal (OUTM) and the second output signal (OUTP) are applied to both ends of the speaker load (110), which are denoted as the inductor (L1) and resistor (R1) in FIG. 1A.

[0018] FIG. 1B is a waveform diagram illustrating the signal modulation of the Class D amplifier (100) of FIG. 1A. As shown in FIG. 1B, the first audio input signal (INP) and the second audio input signal (INM) are compared with a triangular wave signal (VREF). This is as described above together with FIG. 1A. The output signals of the first comparator (101) and the second comparator (102) are pulse signals of a fixed frequency (i.e., a fixed period), and the pulse width of these pulse signals is proportional to the corresponding audio input signals. Thus, the first output signal (OUTM) and the second output signal (OUTP) are two PWM signals, as shown in FIG. 1B.

[0019] When a rail-to-rail output voltage amplitude is adopted in a Class D amplifier, the technique according to the present disclosure helps improve the output slew rate during switching of the Class D amplifier. The present disclosure aims to minimize any overshoot or undershoot that degrades the power efficiency of the Class D amplifier. Typically, a Class D amplifier provides an efficiency of over 90%, or even about 95%. To maintain efficiency as high as possible, the slew rate must be closely controlled.

[0020] Slew rate is defined as the change in voltage (or current, or in other cases, any other electric quantity) per unit time. When expressed in SI units, the measurement unit of slew rate is volts per second (V / s) or volts per microsecond (V / μs). When applied to the output of a circuit, such as an amplifier (e.g., a Class D amplifier), the slew rate standard ensures that the output signal changes at a rate ranging from a predetermined minimum value to a predetermined maximum value. When applied to the input of a circuit, it implies that the external driving circuit system must satisfy such limitations to ensure the accurate operation of the receiving device. Violation of these limitations may result in a predetermined error and may result in failure to ensure accurate operation.

[0021] FIG. 2 is a schematic block diagram illustrating a Class D amplifier (200) with improved slew rate. As shown in FIG. 2, the output terminal of the Class D amplifier (200) is connected to an output load (e.g., speaker load) (210), said output load is denoted by an inductor (L1) and a resistor (R1) (inductor and resistor shown in FIG. 1A).

[0022] In the example illustrated in FIG. 2, the Class D amplifier (200) includes a PWM signal generator (226), a p-type bias current generator (222; also referred to as the 'first bias current generator') and an n-type bias current generator (224; also referred to as the 'second bias current generator'), a multibit delay line circuit (246), an n-type current digital-to-analog converter (IDAC) (242; also referred to as the 'first IDAC'), a p-type IDAC (244; also referred to as the 'second IDAC'), a p-type output transistor (291), an n-type output transistor (292), and other components. In another aspect, the Class D amplifier (200) includes a driving circuit (201), a p-type output transistor (291) and an n-type output transistor (292), and other components. The driving circuit (201) includes a PWM signal generator (226), a p-type bias current generator (222), an n-type bias current generator (224), a multi-bit delay line circuit (246), an n-type IDAC (242), a p-type IDAC (224), and other components.

[0023] The P-type output transistor (291) and the n-type output transistor (292) are connected in series between a lower power rail (e.g., ground) and a higher power rail (e.g., VDD). Compared to other transistors in the Class D amplifier (200), the p-type output transistor (291) and the n-type output transistor (292) are characterized by large dimensions (e.g., channel length, channel width, etc.), thereby driving the output load (210) to meet the required power efficiency. Accordingly, the parasitic capacitors (293, 294) are characterized by large capacitance, thereby allowing for a smaller slew rate (i.e., a lower slew rate). In one embodiment, the p-type output transistor (291) is a PMOS transistor, and the n-type output transistor (292) is an NMOS transistor. Naturally, other types of transistors may also be adopted for the p-type output transistor (291) and the n-type output transistor (292). Such various changes, modifications, and substitutions are obvious to those skilled in the art.

[0024] The PWM signal generator (226) generates an input signal (indicated as "IN" in FIG. 2). The PWM signal generator (226) may further generate an inverted input signal (which may be referred to as the "INB" signal and is illustrated in FIG. 4 and 5) as a supplementary signal to the input signal. In one embodiment, the PWM signal generator (226) may include a comparator and an oscillator that generates a triangular wave. This is as described above together with FIG. 1A and 1B. It is obvious that in other embodiments, a PWM signal generator of a different structure may be selected.

[0025] A multibit delay line circuit (246) receives an input signal (IN) and generates a plurality of delayed input signals, said plurality of delayed input signals are supplied to an n-type IDAC (242) and a p-type IDAC (244). Each of said plurality of delayed input signals is delayed by a delay time relative to a previous delayed input signal. FIG. 6 is a diagram illustrating an exemplary multibit delay line circuit (246). In the example illustrated in FIG. 6, the multibit delay line circuit (246) includes a plurality of serially connected delay units (602-0, 602-1, 602-N, 602-N (collectively referred to as "602")). A first delay unit (602-0) receives an input signal (IN) from a PWM signal generator (226) and generates a first delayed input signal by delaying it by a first delay time (in FIG. 6, "SEL <0> (Notated as "). The second delay unit (602-1) receives the output signal from the first delay unit (602-0) (i.e., the first delayed input signal (SEL <0> )) is received and delayed by a second delay time to generate a second delayed input signal (in FIG. 6, "SEL <1> (Indicated as ""). The final delay unit (602-N) receives the final delayed input signal (in Fig. 6, "SEL"). <n>The above process continues until the (indicated as) is generated, and the final delayed input signal is delayed (N+1) times with respect to the input signal (IN). Therefore, the final delay unit (602-N) may also be referred to as the "(N+1) delay unit (602-N)". As described below by combining FIGS. 4 and 5, the width of the n-type IDAC (242) and the width of the p-type IDAC (244) are determined by the number of delay units (602).

[0026] In the embodiment illustrated in FIG. 6, each delay unit may include a first inverter (612-1) and a second inverter (612-2) connected in series. Both the first inverter (612-1) and the second inverter (612-2) may be NOT gates. A parasitic capacitor (614) is connected between the output terminal of the first inverter (612-1) and ground. It is obvious that in other embodiments, different types of delay units may be selected. In some embodiments, the delay times of each delay unit (602) are the same. In other embodiments, the delay times of each delay unit (602) are different.

[0027] Referring again to FIG. 2, the p-type bias current generator (222) is controlled by an input signal (IN) (and an inverted input signal (INB)). The p-type bias current generator (222) and the n-type IDAC (242) operate to provide a p-type output transistor control signal (labeled "PGATE" in FIG. 2), said p-type output transistor control signal is applied to the gate of the p-type output transistor (291). Likewise, the n-type bias current generator (224) is controlled by an input signal (IN) (and an inverted input signal (INB)). The n-type bias current generator (224) and the p-type IDAC (244) operate to provide an n-type output transistor control signal (labeled "NGATE" in FIG. 2), said n-type output transistor control signal is applied to the gate of the n-type output transistor (292).

[0028] Hereinafter, exemplary embodiments of a p-type bias current generator (222) and an n-type IDAC (242) are described with reference to FIG. 4. Additionally, exemplary embodiments of an n-type bias current generator (224) and a p-type IDAC (244) are described with reference to FIG. 5.

[0029] FIG. 3A is a schematic diagram illustrating the operation of a Class D amplifier (200) when a p-type output transistor (291) is gradually energized. FIG. 3B is a schematic diagram illustrating the operation of a Class D amplifier (200) when an n-type output transistor (292) is gradually energized.

[0030] As illustrated in FIG. 3A, when the output signal (OUT) changes from logic low (i.e., "0") to logic high (i.e., "1") (labeled 304 in FIG. 3A), the n-type output transistor (292) is turned off and the p-type output transistor (291) is turned on, so the output signal (OUT) is pulled to a higher power rail (e.g., VDD). In particular, the turning off of the n-type output transistor (292) is fast (i.e., the n-type output transistor control signal (NGATE) rapidly decreases from logic high to logic low); the turning on of the p-type output transistor (291) is gradual (i.e., the p-type output transistor control signal (PGATE) decreases or pulls down step by step from logic high to logic low (labeled 302 in FIG. 3A)). Therefore, when the p-type output transistor (291) is gradually turned on, the breakdown current flowing through the n-type output transistor (292) is lowered because the n-type output transistor (292) is turned off before the p-type output transistor (291) is gradually turned on. In some embodiments, about 25 ns is required to turn on the p-type output transistor (291) (i.e., "gradual On" or "slow On" as indicated in FIG. 3A), while about 1 ns is required to turn off the n-type output transistor (292) (i.e., "quick Off" or "fast Off" as indicated in FIG. 3A). In some embodiments, the ratio of the On time of the p-type output transistor (291) to the Off time of the n-type output transistor (292) corresponds to a first ratio. In some examples, the first ratio is greater than 50. In some examples, the first ratio is greater than 30. In some examples, the first ratio is greater than 25. In some examples, the first ratio is greater than 20. As described below with reference to FIG. 4, this is implemented by a multibit delay line circuit (246), an n-type IDAC (242), and a p-type bias current generator (222).

[0031] As illustrated in FIG. 3B, when the output signal (OUT) changes from logic high to logic low (labeled 308 in FIG. 3B), the p-type output transistor (291) is turned off and the n-type output transistor (292) is turned on, so the output signal (OUT) is pulled to a lower power rail (e.g., ground). In particular, the turning off of the p-type output transistor (291) is fast (i.e., the p-type output transistor control signal (PGATE) increases rapidly from logic low to logic high); The On of the n-type output transistor (292) is gradual (i.e., the n-type output transistor control signal (NGATE) is incremented or pulled up step by step from logic low to logic high (indicated as 306 in FIG. 3B). Therefore, when the n-type output transistor (292) is gradually turned On, the breakdown current flowing through the p-type output transistor (291) is lowered, because the p-type output transistor (291) is turned Off before the n-type output transistor (292) is gradually turned On. In some embodiments, about 25ns is required to turn On the n-type output transistor (292) (i.e., "gradual On" or "slow On" indicated in FIG. 3B), while about 1ns is required to turn Off the p-type output transistor (291) (i.e., "quick Off" or "fast Off" indicated in FIG. 3B). In some embodiments, the ratio of the On time of the n-type output transistor (292) to the Off time of the p-type output transistor (291) is to the second ratio This applies. In some examples, the second ratio is greater than 50. In some examples, the second ratio is greater than 30. In some examples, the second ratio is greater than 25. In some examples, the second ratio is greater than 20. As described below with reference to FIG. 5, this is implemented by a multibit delay line circuit (246), a p-type IDAC (244), and an n-type bias current generator (224).

[0032] Meanwhile, the Class D amplifier (200) illustrated in FIG. 2 can be considered to include three blocks. The first block (220) includes a PWM signal generator (226), a p-type bias current generator (222), and an n-type bias current generator (224). The first block (220) operates to generate the input signal (IN) (and inverted input signal (INB)) and bias current required by the second block (240). The second block (240) includes a multibit delay line circuit (246), an n-type IDAC (242), and a p-type IDAC (244). The second block (240) operates to generate a p-type output transistor control signal (PGATE) and an n-type output transistor control signal (NGATE) provided to the third block (290). The third block (290) includes a p-type output transistor (291) and an n-type output transistor (292). The third block (290) operates to generate an output signal (OUT) based on a p-type output transistor control signal (PGATE) and an n-type output transistor control signal (NGATE). Naturally, this is provided transparently in the drawing of the Class D amplifier (200), and all components of the Class D amplifier (200) function as a single unit.

[0033] FIG. 4 is a drawing illustrating a section (400) of a Class D amplifier (200) according to some embodiments. As previously mentioned, the section (400) serves as a p-type bias current generator (222) and an n-type IDAC (242) as illustrated in FIG. 2. Such various changes, modifications, and substitutions are obvious to those skilled in the art.

[0034] In the example illustrated in FIG. 4, section (400) receives an input signal (IN) and an inverted input signal (INB) and generates a p-type output transistor control signal (PGATE) that is applied to the gate of a p-type output transistor (291). As previously mentioned, the inverted input signal (INB) is a supplementary signal of the input signal (IN).

[0035] Section (400) includes a p-type bias current generator (222), a p-type pre-driver (404), an n-type IDAC (242), and other components. In the example shown in FIG. 4, the p-type bias current generator (222) includes an n-type transistor (412) and three p-type transistors (414, 416, and 418) having the topology shown in FIG. 4. The n-type transistor (412) and the p-type transistors (414 and 416) are connected in series between ground and a positive voltage (e.g., VCCH). In one example, VCCH is 12V, but in other embodiments, it may be a different value. The gate of the n-type transistor (412) receives an inverted input signal (INB). The gates of the p-type transistors (416 and 418) are connected together. The p-type bias current generator (222) acts as a current mirror.

[0036] In the example illustrated in FIG. 4, the p-type pre-driver (404) includes an n-type transistor (422) and a p-type transistor (420) having the topology illustrated in FIG. 4, connected in series between a positive voltage (e.g., VCCH) and an n-type IDAC (242). The gate of the n-type transistor (422) receives an input signal (IN).

[0037] The p-type transistors (418 and 420) are connected in parallel. The first source / drain (S / D) terminal of the p-type transistor (420) is connected to a positive voltage (e.g., VCCH), and the second S / D terminal of the p-type transistor (420) is connected to both its gate and the first S / D terminal of the p-type transistor (420).

[0038] In the example illustrated in FIG. 4, the n-type IDAC (242) comprises a current source (424), an n-type transistor (427) connected in series with the current source (424), and a plurality of current branches (432-0, 432-1, 432-3, 432-N; collectively referred to as "432"). Each current branch comprises an access transistor (430-0, 430-1, 430-3, 430-N; collectively referred to as "430") and an n-type current generating transistor (428-0, 428-1, 428-3, 428-N; collectively referred to as "428"). The n-type current generating transistor (428) has a common gate configuration. The access transistor (430) corresponds to the delay unit (602) of the multibit delay line circuit (246) shown in FIG. 6. The gate of each access transistor (430) corresponds to a plurality of delayed input signals (SEL) generated by the multibit delay line circuit (246) shown in FIG. 6. <0> to SEL <n>One of the following is received. If the delayed input signal is logic high, the corresponding current branch (432) is selected, and the current flowing through the corresponding n-type current generating transistor (428) at the node (C) shown in FIG. 4 is collected.

[0039] In the example illustrated in FIG. 4, the n-type current generating transistors (428) are characterized by having different sizes, and the current generated from them is 2(N+1) times the current flowing through the n-type transistor (427). Here, N is 0, 1, 2, 3, ⪋⪋, N. Thus, the more current branches (432) there are, the higher the grain or resolution the n-type IDAC (242) can provide.

[0040] In the example illustrated in FIG. 4, when the input signal (IN) is logic low, the inverted input signal (INB) is logic high. Thus, the n-type transistor (422) is turned off and the n-type transistor (412) is turned on. The p-type transistors (414, 416, and 418) are turned on and the voltage at node (D) is pulled up to a positive voltage (e.g., VCCH). The current flowing through the p-type transistors (414 and 416) is mirrored to the current flowing through the p-type transistor (418).

[0041] Therefore, the p-type transistor (420) is turned on, because the gate of the p-type transistor (420) is connected to node (D). Consequently, the p-type output transistor (291) and the n-type IDAC (242) are disconnected, and the p-type output transistor control signal (PGATE) is pulled up to the power supply voltage (e.g., VCCH), so the p-type output transistor (291) is turned off. As described below with reference to FIG. 5, when the input signal (IN) is logic low, the n-type output transistor control signal (NGATE) gradually increases, so the n-type output transistor (292) is gradually turned on. Consequently, the output signal (OUT) is logic low.

[0042] On the other hand, when the input signal (IN) is logic high, the inverted input signal (INB) is logic low. Thus, the n-type transistor (422) is turned on, connecting the p-type output transistor (291) to the n-type IDAC (242), and the n-type transistor (412) is turned off. The p-type transistors (414, 416, and 418) are turned off. The p-type transistor (420) is a diode-connected transistor (e.g., a diode-connected MOSFET). Thus, the p-type output transistor control signal (PGATE) is equal to the voltage across the p-type transistor (420) subtracted from the power supply voltage (e.g., VCCH), and the voltage across the p-type transistor (420) is determined by the current provided by the n-type IDAC (242) and the magnitude of the p-type transistor (420).

[0043] As described above, the n-type IDAC (242) has a plurality of delayed input signals (SEL <0> to SEL <n>It includes a plurality of current branches (432) that can be independently controlled by, and the plurality of delayed input signals are generated from the multibit delay line circuit (246) shown in FIG. 6. Thus, the current provided by the n-type IDAC (242) at node (C) can be changed one step at a time. Accordingly, the p-type output transistor control signal (PGATE) is gradually reduced, as shown in FIG. 3A. That is, the p-type output transistor (291) is gradually turned on. As described below with reference to FIG. 5, when the input signal (IN) is logic high, the n-type output transistor control signal (NGATE) changes rapidly to logic high, so the n-type output transistor (292) is rapidly turned off. Therefore, the output signal (OUT) is logic high.

[0044] In one example, the n-type output transistor control signal (NGATE) varies in the range of about 7V to about 12V. In other embodiments, it is obvious that the range can be fine-tuned according to the needs of specific design requirements.

[0045] FIG. 5 is a drawing illustrating a section (500) of a Class D amplifier (200) according to some embodiments. As previously mentioned, the section (500) serves as an n-type bias current generator (224) and a p-type IDAC (244) as illustrated in FIG. 2. Such various changes, modifications, and substitutions are obvious to those skilled in the art.

[0046] In the example illustrated in FIG. 5, the section (500) receives an input signal (IN) and generates an n-type output transistor control signal (NGATE) that is applied to the gate of an n-type output transistor (292).

[0047] Section (500) includes an n-type bias current generator (224), an n-type pre-driver (504), a p-type IDAC (244), and other components. In the example illustrated in FIG. 5, the n-type bias current generator (224) includes an n-type transistor (512) and a p-type transistor (522), the gates of which are connected together. The n-type transistor (512) and the p-type transistor (522) form an inverter. The n-type transistor (512) and the p-type transistor (522) are connected in series between ground and a node (C'). The gate of the n-type transistor (512) and the gate of the p-type transistor (522) both receive an inverted input signal (INB). The n-type bias current generator (224) acts as an inverter.

[0048] In the example illustrated in FIG. 5, the n-type pre-driver (504) includes a p-type transistor (522) and an n-type transistor (520) connected in series between ground and the p-type IDAC (244) and having the topology illustrated in FIG. 5. The gate of the p-type transistor (522) receives an input signal (IN).

[0049] The n-type transistors (512 and 520) are connected in parallel. The first source / drain (S / D) terminal of the n-type transistor (520) is connected to ground, and the second S / D terminal of the n-type transistor (520) is connected to its own gate.

[0050] In the example illustrated in FIG. 5, the p-type IDAC (244) includes a current source (524), a p-type transistor (427) connected in series with the current source (524), and a plurality of current branches (532-0, 532-1, 532-3, ..., 532-N; collectively referred to as "532"). Each current branch includes an access transistor (530-0, 530-1, 530-3, ..., 530-N; collectively referred to as "530") and a p-type current generating transistor (528-0, 528-1, 528-3, ..., 528-N; collectively referred to as "528"). The access transistor (530) corresponds to the delay unit (602) of the multibit delay line circuit (246) illustrated in FIG. 6. The gate of each access transistor (530) is a plurality of delayed input signals (SEL) generated by the multibit delay line circuit (246) shown in FIG. 6. <0> to SEL <n>One of the following is received. If the delayed input signal is logic high, the corresponding current branch (532) is selected, and the current flowing through the corresponding current generating transistor (528) at the node (C') shown in FIG. 5 is collected.

[0051] In the example illustrated in FIG. 5, the p-type current generating transistors (428) are characterized by having different sizes, and the current generated from them is 2(N+1) times the current flowing through the p-type transistor (527). Here, N is 0, 1, 2, 3, ..., N. Thus, the more current branches (532) there are, the higher the grain or resolution the p-type IDAC (244) can provide.

[0052] In the example illustrated in FIG. 5, when the input signal (IN) is logic high, the p-type transistor (522) is turned off and the n-type transistor (512) is turned on, and the voltage at node (D') is pulled up to ground.

[0053] Accordingly, the n-type output transistor (292) and the p-type IDAC (244) are disconnected, and the n-type output transistor control signal (NGATE) is pulled up to ground, so the n-type output transistor (292) is turned off. As described above with reference to FIG. 4, when the input signal (IN) is logic high, the p-type output transistor control signal (PGATE) is gradually reduced, and accordingly, the p-type output transistor (291) is gradually turned on. Therefore, the output signal (OUT) is logic high.

[0054] On the other hand, when the input signal (IN) is logic low, the p-type transistor (522) is turned on so that the n-type output transistor (292) is connected to the p-type IDAC (244), and the n-type transistor (512) is turned off. The n-type transistor (520) is a diode-connected transistor (e.g., a diode-connected MOSFET). Therefore, the n-type output transistor control signal (NGATE) is equal to the voltage across the n-type transistor (520), and the voltage across the n-type transistor (520) is determined by the current provided by the p-type IDAC (244) and the magnitude of the n-type transistor (520).

[0055] As described above, the p-type IDAC (244) has a plurality of delayed input signals (SEL <0> to SEL <n>It includes a plurality of current branches (532) that can be independently controlled by, and the plurality of delayed input signals are generated from the multibit delay line circuit (246) shown in FIG. 6. Thus, the current provided by the p-type IDAC (244) at node (C') can be changed one step at a time. Thus, as shown in FIG. 3B, the n-type output transistor control signal (NGATE) increases gradually. Thus, the n-type output transistor (292) is gradually turned on. As described above with reference to FIG. 4, when the input signal (IN) is logic low, the p-type output transistor control signal (PGATE) changes rapidly to logic high, so the p-type output transistor (291) is rapidly turned off. Thus, the output signal (OUT) is logic low.

[0056] In one example, the n-type output transistor control signal (NGATE) varies in the range of about 0V to about 4.5V. In other embodiments, it is obvious that the range can be fine-tuned according to the needs of specific design requirements.

[0057] FIG. 7 illustrates the p-type output transistor control signal (PGATE), n-type output transistor control signal (NGATE), input signal, and output signal when the input signal changes to logic high. In the example illustrated in FIG. 7, the input signal (IN) changes to logic high at time t1. Consequently, the n-type output transistor control signal (NGATE) changes rapidly to logic low, and the p-type output transistor control signal (PGATE) changes gradually to logic low. Consequently, the n-type output transistor (292) is quickly turned off, and the p-type output transistor (291) is gradually turned on. Thus, when the p-type output transistor control signal (PGATE) reaches logic low, the output signal (OUT) begins to change to logic high at time t2. As illustrated in FIG. 7, the slew rate is improved.

[0058] FIG. 8 illustrates the p-type output transistor control signal (PGATE), n-type output transistor control signal (NGATE), input signal, and output signal when the input signal changes to logic low. In the example illustrated in FIG. 8, the input signal (IN) changes to logic low at time t1. Consequently, the n-type output transistor control signal (NGATE) gradually changes to logic high, and the p-type output transistor control signal (PGATE) changes rapidly to logic high. Consequently, the p-type output transistor (291) is rapidly turned off, and the n-type output transistor (292) is gradually turned on. Thus, when the n-type output transistor control signal (NGATE) reaches logic high, the output signal (OUT) begins to change to logic low at time t2. As illustrated in FIG. 8, the slew rate is improved.

[0059] FIG. 9 is a flowchart illustrating an exemplary method (900) for operating a Class D amplifier (e.g., the Class D amplifier (200) shown in FIG. 2). The method (900) begins at step 902, where an input signal (e.g., the input signal (IN) shown in FIG. 2) is received. At step 904, a p-type output transistor control signal (e.g., PGATE shown in FIG. 2) is generated in response to the input signal. In one embodiment, the p-type output transistor control signal is generated using a driving circuit (e.g., the driving circuit (201) shown in FIG. 2) connected to the gate of the n-type output transistor and the gate of the p-type output transistor. At step 906, an n-type output transistor control signal (e.g., NGATE shown in FIG. 2) is generated in response to the input signal. Likewise, the n-type output transistor control signal is generated using a driving circuit (e.g., the driving circuit (201) shown in FIG. 2). In step 908, a p-type output transistor control signal is applied to the gate of the p-type output transistor (e.g., labeled 291 in FIG. 2). In step 910, an n-type output transistor control signal is applied to the gate of the n-type output transistor (e.g., labeled 292 in FIG. 2). When the input signal changes to logic high, the n-type output transistor control signal changes rapidly to logic low, while the p-type output transistor control signal changes gradually to logic low (e.g., as illustrated in FIG. 3A). When the input signal changes to logic low, the p-type output transistor control signal changes rapidly to logic high, while the n-type output transistor control signal changes gradually to logic high (e.g., as illustrated in FIG. 3B). It is obvious that additional steps may be adopted. Furthermore, in other embodiments, the order of the steps may be changed.

[0060] The features of various embodiments have been described above to enable those skilled in the art to fully understand the aspects of the present disclosure. Those skilled in the art will understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same effect as the embodiments described herein. Furthermore, such equivalent configurations do not depart from the spirit and scope of the present disclosure. Those skilled in the art may make various modifications, substitutions, and changes in the present specification without departing from the spirit of the present disclosure. Explanation of the symbols

[0062] 100,200: Class D amplifier 101: First comparator 102: Second comparator 103: Oscillator 106: 1st PWM signal 107: 2nd PWM signal 110: Speaker load 191, 192, 193, 194: Output transistors 201: Driving circuit 210: Output load 220: Block 1 222: p-type bias current generator 224: n-type bias current generator 226: PWM signal generator 240: Block 2 242: n-type current digital-to-analog converter (IDAC) 244: p-type IDAC 246: Multibit delay line circuit 290: Block 3 291: p-type output transistor 292: n-type output transistor 293, 294: Parasitic capacitors 302: Operate 304: Operate 306: Operation 308: Operation 400,500: Section 404: Type P pre-actuator 412: n-type transistor 414, 416, 418, 420, 522, 527: p-type transistor 422, 427, 512, 520: n-type transistors 424, 524: current source 428-0, 428-1, 428-2, 428-3, 428-N: n-type current generating transistor 430-0,430-1,430-2,430-3,430-N,530-0,530-1,530-2,530-3,530-N: Access transistor 432-0,432-1,432-2,432-3,432-N,532-0,532-1,532-2,532-3,532-N: Current branch 504: n-type pre-actuator 528-0, 528-1, 528-2, 528-3, 528-N: p-type current generating transistor 602-0: 1st Delay Unit 602-1: 2nd Delay Unit 602-N: Final delay unit 612-1: First inverter 612-2: Second Inverter 614: Parasitic Capacitor 900: Method 902,904,906,908,910: Step C,C',D,D': Node IN: Input signal INB: Inverted input signal INM: Second audio input signal / Differential audio input signal INP: First audio input signal / Differential audio input signal L1: Inductor NGATE: n-type output transistor control signal OUT: Output signal OUTM: 1st output signal OUTP: 2nd output signal PGATE: p-type output transistor control signal R1: Resistor SEL <0> : First delayed input signal SEL <1> : Second delayed input signal SEL <2> ,SEL <3> ,SEL <n>: Delayed input signal VREF: Triangle wave signal< / n> < / n> < / n> < / n> < / n> < / n>

Claims

Claim 1 A Class D amplifier comprises: a p-type output transistor; an n-type output transistor connected in series with the p-type output transistor; and a driving circuit connected to the gate of the p-type output transistor and the gate of the n-type output transistor, wherein the driving circuit receives an input signal and generates a p-type output transistor control signal applied to the gate of the p-type output transistor in response to the input signal, wherein the driving circuit generates an n-type output transistor control signal applied to the gate of the n-type output transistor in response to the input signal, wherein when the input signal changes to logic high, the n-type output transistor control signal changes rapidly to logic low, but the p-type output transistor control signal changes gradually to logic low, and when the input signal changes to logic low, the p-type output transistor control signal changes rapidly to logic high, but the n-type output transistor control signal changes gradually to logic high, and wherein the driving circuit includes a multi-bit delay line circuit for receiving the input signal and generating a plurality of delayed input signals; A Class D amplifier comprising: an n-type current digital-to-analog converter (IDAC) for generating a first current in response to a plurality of delayed input signals; and a p-type IDAC for generating a second current in response to a plurality of delayed input signals. Claim 2 A Class D amplifier according to claim 1, wherein when the input signal changes to logic high, the n-type output transistor control signal changes rapidly to logic low, but the p-type output transistor control signal changes gradually to logic low, so that the p-type output transistor is gradually turned on after the n-type output transistor is turned off. Claim 3 A Class D amplifier according to claim 1, wherein when the input signal changes to logic high, the p-type output transistor control signal changes to logic low in steps. Claim 4 A Class D amplifier according to claim 1, wherein when the input signal changes to logic low, the p-type output transistor control signal changes rapidly to logic high, but the n-type output transistor control signal changes gradually to logic high, so that the n-type output transistor is gradually turned on after the p-type output transistor is turned off. Claim 5 A Class D amplifier according to claim 1, wherein when the input signal changes to logic low, the n-type output transistor control signal changes to logic high in steps. Claim 6 In claim 1, the driving circuit further comprises: a pulse width modulation (PWM) signal generator for generating the input signal; an n-type transistor connected between the p-type output transistor and the n-type IDAC; and a p-type transistor connected between the n-type output transistor and the p-type IDAC, wherein the D-class amplifier further comprises Claim 7 A Class D amplifier according to claim 6, wherein when the input signal changes to logic high, the p-type transistor is turned off, thereby turning off the connection between the p-type IDAC and the n-type output transistor, and at the same time, the n-type output transistor control signal changes to logic low. Claim 8 A Class D amplifier according to claim 7, wherein when the input signal changes to logic high, the n-type transistor is turned on to connect the n-type IDAC to the p-type output transistor, and the p-type output transistor control signal decreases as the first current increases. Claim 9 A Class D amplifier according to claim 6, wherein when the input signal changes to logic low, the n-type transistor is turned off, thereby turning off the connection between the n-type IDAC and the p-type output transistor, and at the same time, the p-type output transistor control signal changes to logic high. Claim 10 A Class D amplifier according to claim 9, wherein when the input signal changes to logic low, the p-type transistor is turned on to connect the p-type IDAC to the n-type output transistor, and the n-type output transistor control signal increases as the second current increases. Claim 11 In paragraph 6, the above input signal is a PWM signal, a Class D amplifier. Claim 12 In claim 6, the multibit delay line circuit comprises a plurality of delay units connected in series, each of the plurality of delay units providing a delay time, a Class D amplifier. Claim 13 In Clause 12, a Class D amplifier in which the delay times of the plurality of delay units are different. Claim 14 In claim 6, the p-type IDAC comprises a first current source; a first p-type transistor; and a plurality of current branches, wherein the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current amounts, a Class D amplifier. Claim 15 In claim 6, the n-type IDAC comprises a second current source; a first n-type transistor; and a plurality of current branches, wherein the plurality of current branches correspond to the plurality of delayed input signals and provide a plurality of current amounts, a Class D amplifier. Claim 16 A method for operating a Class D amplifier comprising a p-type output transistor and an n-type output transistor connected in series with the p-type output transistor, comprising: receiving an input signal; generating a p-type output transistor control signal in response to the input signal using a driving circuit connected to the gate of the n-type output transistor and the gate of the p-type output transistor; generating an n-type output transistor control signal in response to the input signal using the driving circuit; applying the p-type output transistor control signal to the gate of the p-type output transistor; applying the n-type output transistor control signal to the gate of the n-type output transistor; generating a plurality of delayed input signals using a multi-bit delay line circuit; and generating a first current in response to the plurality of delayed input signals using an n-type current digital-to-analog converter (IDAC). A method for operating a Class D amplifier, comprising the step of generating a second current in response to a plurality of delayed input signals using a p-type IDAC, wherein when the input signal changes to logic high, the n-type output transistor control signal changes rapidly to logic low but the p-type output transistor control signal changes gradually to logic low, and when the input signal changes to logic low, the p-type output transistor control signal changes rapidly to logic high but the n-type output transistor control signal changes gradually to logic high. Claim 17 A method for operating a Class D amplifier according to claim 16, wherein when the input signal changes to logic high, the p-type output transistor control signal changes to logic low in steps. Claim 18 A method for operating a Class D amplifier according to claim 16, wherein when the input signal changes to logic low, the n-type output transistor control signal changes to logic high in stages. Claim 19 A method for operating a Class D amplifier according to claim 16, further comprising: a step of turning off the connection between the p-type IDAC and the n-type output transistor when the input signal changes to logic high; a step of connecting the n-type IDAC to the p-type output transistor and decreasing the p-type output transistor control signal as the first current increases; and a step of turning off the connection between the n-type IDAC and the p-type output transistor when the input signal changes to logic low; and a step of connecting the p-type IDAC to the n-type output transistor and increasing the n-type output transistor control signal as the second current increases. Claim 20 delete

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