Electronic device and method controlling the same

Abstract

An electronic device is disclosed comprising a memory and a processor connected to the memory, wherein, when executed by the processor, the memory stores instructions for changing the memory margin configuration by performing memory training for the memory based on the identification of defects, wherein the memory includes information regarding driving voltage and information regarding latency related to data transmission. In addition to this, various other embodiments identified through the specification are possible.

Description

Technology Field

[0001] The various embodiments disclosed in this document relate to electronic devices and methods for controlling the same. Background Technology

[0002] In an electronic device, memory can store data. When a processor requests the transfer of data stored in memory, the memory can transfer the data to the processor in accordance with the processor's request. Within a set range of reference voltage and a set range of latency, the memory can communicate data with the processor. If the memory's reference voltage falls outside the set range of reference voltage and / or the memory's latency falls outside the set range of latency, data communication between the memory and the processor may fail. The processor can perform memory training based on the environment of the electronic device to adjust the range of reference voltage and latency in which data communication between the memory and the processor is performed. The problem to be solved

[0003] Before a user uses an electronic device, memory training for the memory included in the device is performed in the memory's production environment. The memory's production environment may differ from the device's actual usage environment. Therefore, the range of reference voltage and delay time set in the memory's production environment may differ from the range of reference voltage and delay time used for data communication in the actual usage environment. Consequently, data communication between the memory and the processor may fail at specific reference voltages and delay times.

[0004] The present invention aims to improve software defects by determining whether the software defect occurs in relation to the reference voltage and / or delay time of the memory when a software defect occurs in an electronic device in an actual usage environment, and by performing memory training based on the actual usage environment. means of solving the problem

[0005] An electronic device according to one embodiment disclosed in this document includes a memory and a processor connected to the memory, wherein the memory stores instructions for changing the memory margin configuration by performing memory training for the memory based on the identification of the defect, wherein, when executed by the processor, the electronic device identifies whether attribute data set in relation to the memory margin of the electronic device corresponds to a specified value when a software error occurs in the electronic device, and if the attribute data corresponds to the specified value, identifies a history of software error occurrence stored in the memory, and based on the software error and the history of software error occurrence, identifies a defect related to the memory margin configuration set for the memory, and based on the identification of the defect, the memory margin may include information regarding the driving voltage and information regarding the latency related to data transmission.

[0006] A method for controlling an electronic device according to an embodiment disclosed in this document comprises, when a software error occurs in the electronic device, identifying whether attribute data set in relation to the memory margin of the electronic device corresponds to a specified value; if the attribute data corresponds to the specified value, identifying a history of software error occurrence stored in memory; identifying a defect related to a memory margin configuration set for the memory based on the software error that occurred and the history of software error occurrence; and changing the memory margin configuration by performing memory training for the memory based on the identification of the defect, wherein the memory margin may include information regarding the driving voltage and information regarding the latency related to data transmission. Effects of the invention

[0007] According to the embodiments disclosed in this document, in an actual usage environment of an electronic device that is different from the production environment of the memory, the electronic device can identify defects related to memory margin settings. By identifying defects related to memory margin settings in the actual usage environment, the electronic device can improve defects related to memory margin settings even after the production stage of the memory.

[0008] According to the embodiments disclosed in this document, an electronic device can improve the memory margin of a memory by performing memory training. By improving the memory margin, the electronic device can resolve defects related to memory margin setting and ensure that data transfer between the memory and the processor is performed stably.

[0009] In addition, various effects that can be identified directly or indirectly through this document may be provided. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram illustrating the hardware of an electronic device according to one embodiment. FIG. 2 is a diagram illustrating the software layer and hardware of an electronic device according to one embodiment. FIG. 3 is a diagram of a margin graph showing the memory margin of a memory according to one embodiment. FIG. 4 is a signal flow diagram of components included in an electronic device according to one embodiment. FIG. 5 is a signal flow diagram of components included in an electronic device according to one embodiment. FIG. 6 is a flowchart illustrating the process of identifying a weak device according to one embodiment. FIG. 7 is a flowchart illustrating the process of identifying a memory margin defect and performing memory training according to one embodiment. FIG. 8 is a flowchart illustrating a method for controlling an electronic device according to one embodiment. FIG. 9 is a block diagram of an electronic device in a network environment according to various embodiments. In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components. Specific details for implementing the invention

[0011] Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments and should be understood to include various modifications, equivalents, and / or alternatives of the embodiments of the present invention.

[0012] FIG. 1 is a block diagram illustrating the hardware of an electronic device (101) according to one embodiment.

[0013] Referring to FIG. 1, the electronic device (101) may include a memory (130) and a processor (120). The memory (130) may be operatively connected to the processor (120).

[0014] The processor (120) can, for example, execute software (e.g., a program) to control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) and can perform various data processing or operations. As at least part of the data processing or operations, the processor (120) can store instructions or data received from the other component in volatile memory, process the instructions or data stored in volatile memory, and / or store the resulting data in non-volatile memory.

[0015] The memory (130) can store various data used by at least one component (e.g., processor (120)) of the electronic device (101). The data may include, for example, input data or output data for software and related instructions. The memory (130) may include volatile memory or non-volatile memory.

[0016] The memory (130) can store memory training results. The memory training results may include information about a margin graph corresponding to the memory margin after memory training. The memory margin may include information about the conditions under which data communication between the memory and the processor is performed (e.g., the reference voltage of the memory and the delay time of the memory). The memory margin may correspond to a user-specified area or a system-pre-set area among the areas on the margin graph where data communication between the memory and the processor is successful.

[0017] Information regarding the margin graph may include information regarding a margin area (e.g., the first margin area (311), the second margin area (321), or the third margin area (331) of FIG. 3), a spare margin area (e.g., the first spare margin area (315), the second spare margin area (325), or the third spare margin area (335) of FIG. 3), and a defect margin area (e.g., the first defect margin area (313), the second defect margin area (323), or the third defect margin area (333) of FIG. 3). A specific description of the information regarding the margin graph is provided later in FIG. 3.

[0018] The memory (130) may store attribute data. The attribute data may include information regarding whether the electronic device (101) corresponds to a vulnerable device. A vulnerable device may correspond to an electronic device (101) in which the memory margin for the memory (130) does not satisfy a specified condition. For example, a vulnerable device may correspond to an electronic device (101) in which data communication between the memory (130) and the processor (120) fails at any reference voltage within the margin area and at any delay time within the margin area. The memory (130) may store the attribute data as either true or false depending on whether the electronic device (101) is a vulnerable device. A specific description of the specified condition is provided later in FIG. 3.

[0019] The memory (130) can store a history of software errors. The history of software errors may include information about software errors that occurred in the electronic device (101). The information about software errors that occurred in the electronic device (101) may include register information, snapshots, and / or logs.

[0020] The processor (120) can determine whether the electronic device (101) corresponds to a vulnerable device based on the memory training results stored in the memory (130). The memory training results may include information about a margin graph corresponding to the memory margin after memory training. The information about the margin graph may include a margin area, a free margin area, and / or a defective margin area.

[0021] For example, if the margin area includes a defective margin area and the margin area does not include a free margin area, the processor (120) may determine that the electronic device (101) corresponds to a vulnerable device. As another example, if the margin area included in the information regarding the margin graph includes both a defective margin area and a free margin area, the processor (120) may determine that the electronic device (101) does not correspond to a vulnerable device. As yet another example, if the margin area does not include both a defective margin area and a free margin area, the processor (120) may determine that the memory (130) included in the electronic device (101) is defective.

[0022] The processor (120) may store a vulnerable device identification result (e.g., attribute data) containing information on whether the electronic device (101) corresponds to a vulnerable device in memory (130). The vulnerable device identification result may correspond to either a true or a false value depending on whether the electronic device (101) corresponds to a vulnerable device. For example, if the electronic device (101) corresponds to a vulnerable device, the value of the vulnerable device identification result may be true. As another example, if the electronic device (101) corresponds to a vulnerable device, the value of the vulnerable device identification result may be false.

[0023] The processor (120) can determine whether the electronic device (101) corresponds to a vulnerable device based on the value of the vulnerable device identification result stored in the memory (130).

[0024] The processor (120) can generate a margin graph that represents the success or failure of data transfer between the memory (130) and the processor (120) as a two-dimensional graph for any delay time and any reference voltage. The processor (120) can identify a margin region on the margin graph where data transfer between the memory (130) and the processor (120) has been successful. The margin region may include at least one pass cell. The pass cell may correspond to a unit cell where data transfer between the memory (130) and the processor (120) has been successful for any reference voltage and any delay time. The unit cell may correspond to a rectangular area where the minimum unit of delay time on the horizontal axis of the margin graph is the horizontal length, and the minimum unit of reference voltage on the vertical axis of the margin graph is the vertical length.

[0025] The processor (120) can improve the memory margin by performing memory training on the memory (130). The processor (120) can improve the memory margin by moving the defective margin area and the free margin area through memory training so that all unit cells within the defective margin area correspond to pass cells and the free margin area contains as many pass cells as possible. The processor (120) can perform data communication between the memory (130) and the processor (120) using a reference voltage and delay time corresponding to pass cells included in either the defective margin area and / or the free margin area after moving. The processor (120) can perform the memory training to ensure that data communication between the memory (130) and the processor (120) is performed stably.

[0026] A defect margin area may be established based on the characteristics of the processor (120), the characteristics of the memory (130), and / or a combination of the characteristics of the processor (120) and the characteristics of the memory (130). If the margin area includes a defect margin area, that is, if all unit cells within the defect margin area correspond to pass cells, the memory (130) may operate normally. If the margin area does not include a defect margin area, that is, if there are unit cells that are not pass cells within the defect margin area, the memory (130) may be determined to be defective.

[0027] The margin area may correspond to an area in which the length along the horizontal axis of the defect margin area is increased by a first ratio and the length along the vertical axis of the defect margin area is increased by a second ratio, based on the center point of the defect margin area. If the margin area includes the margin area, that is, if all unit cells within the margin area correspond to pass cells, the electronic device (101) may not correspond to a vulnerable device. If the margin area does not include the margin area, that is, if unit cells that are not pass cells exist within the margin area, the electronic device (101) may correspond to a vulnerable device.

[0028] The processor (120) may store information about software errors that occurred in the electronic device (101) under specified conditions in memory (130) as a history of software error occurrences. For example, the specified conditions may correspond to cases where a software error occurs in the electronic device (101) and the electronic device (101) is a vulnerable device. For example, information about software errors that occurred in the electronic device (101) may include register information, snapshots, and / or logs.

[0029] The processor (120) can identify defects related to memory margin settings. In identifying defects related to memory margin settings, the processor (120) can refer to the history of software errors related to memory margins that occurred in the electronic device (101).

[0030] The processor (120) may transmit a signal to the memory (130) requesting a history of software errors related to memory margins that occurred in the electronic device (101) in order to refer to the history of software errors related to memory margins that occurred in the electronic device (101). The processor (120) may receive a history of software errors related to memory margins from the memory (130).

[0031] The processor (120) can identify defects related to memory margin settings based on the history of software errors received from memory (130) and software errors that occurred in the electronic device (101).

[0032] The processor (120) can identify the number of software errors related to memory margin based on the history of software errors and software errors that occurred in the electronic device (101). For example, the processor (120) can identify the number of software errors related to memory margin by adding 1, which is the number of software errors that occurred in the electronic device, to the number of software errors included in the history of software errors.

[0033] The processor (120) determines whether the number of software errors related to memory margins is greater than or equal to a threshold number, and if the number of software errors related to memory margins is greater than or equal to the threshold number, it can determine that a defect related to memory margin settings has occurred in the memory (130). The threshold number may be a number specified by the system or a number specified by the user. For example, the threshold number may be 3 times.

[0034] The processor (120) can determine whether a defect related to memory margin setting has occurred in the memory (130) based on a first defect state that occurred in the memory (130) due to a software error (e.g., a first software error) that occurred in the electronic device (101) and a second defect state that occurred in the memory (130) due to a software error (e.g., a second software error) included in the history of software errors.

[0035] If the first defect state and the second defect state are identical, and the first log stored in memory (130) regarding the history of occurrence of the first software error and the second log stored in memory (130) regarding the history of occurrence of the second software error are different, the processor (120) may determine that a defect related to memory margin setting has occurred in memory (130). For example, if both the first defect state and the second defect state are list corruption states, and the call stack of the first log and the call stack of the second log are different, the processor (120) may determine that a defect related to memory margin setting has occurred in memory (130).

[0036] If the first defect state and the second defect state are different, the processor (120) may determine that a defect related to memory margin setting has occurred in the memory (130). For example, if the first defect state is list corruption and the second defect state is paging request fail, the processor (120) may determine that a defect related to memory margin setting has occurred in the memory (130).

[0037] The processor (120) can determine whether a defect related to the memory margin setting has occurred in the memory (130) based on the number of occurrences of software errors related to the memory margin and the error state of the memory (130) caused by software errors that occurred in the electronic device (101).

[0038] The processor (120) may store a defect identification result related to memory margin settings in memory (130) with different values ​​(e.g., true or false) depending on whether a defect related to memory margin settings has occurred in memory (130). For example, if the processor (120) determines that a defect related to memory margin settings has occurred in memory (130), the processor (120) may store a value of the defect identification result related to memory margin settings as true in memory (130). As another example, if the processor (120) determines that a defect related to memory margin settings has occurred in memory (130), the processor (120) may store a value of the defect identification result related to memory margin settings as false in memory (130).

[0039] The processor (120) can improve the defects related to memory margin settings by identifying defects related to memory margin settings in the actual usage environment of the electronic device (101) in an environment different from the production environment of the memory (130), and by performing memory training on the memory (130) even after the production stage of the memory (130).

[0040] The processor (120) can improve the memory margin by performing memory training on the memory (130). The processor (120) can improve the memory margin by moving the fault margin area and the free margin area through memory training so that all unit cells within the fault margin area correspond to pass cells and the free margin area contains as many pass cells as possible. The processor can perform data communication between the memory and the processor using a reference voltage and a delay time corresponding to pass cells included in either the fault margin area after moving and / or the free margin area after moving. The processor can perform the memory training to ensure that data communication between the memory and the processor is performed stably.

[0041] FIG. 2 is a drawing illustrating the software layer and hardware of an electronic device (201) (e.g., the electronic device (101) of FIG. 1) according to one embodiment.

[0042] The operation of one module (e.g., first module) included in FIG. 2 transmitting a signal to another module (e.g., second module) may include the first module directly transmitting the signal to the second module, the first module transmitting the signal to a processor (not shown) (e.g., processor (120) of FIG. 1) and the processor transmitting the signal to the second module, the first module storing information related to the signal in a memory (230) (e.g., memory (130) of FIG. 1) and the second module reading information related to the signal from the memory (230) to perform an operation on said signal, and / or the first module storing information related to the signal in the memory (230) and the processor reading information related to the signal from the memory (230) to command the second module to perform an operation on said signal.

[0043] The electronic device (201) may include a software layer and hardware on which the software runs. For example, the software layer may include a bootloader layer (210) and a kernel layer (220). The bootloader layer (210) may correspond to a layer that runs before the operating system of the electronic device (201) starts when a user boots the electronic device (201). The bootloader layer (210) may perform tasks necessary for the kernel layer (220) to start normally and may start the operating system. The kernel layer (220) may correspond to a layer that connects the hardware and the processor of the electronic device (201). The kernel layer (220) may distribute hardware resources to processes that require resources, control processes and memory, and execute commands that a program requires from the operating system. As another example, the hardware may include memory (230) and a processor. The software layer is not limited to the layers described above and may include additional layers. For example, the software layer may further include at least one of a library layer, an Android runtime layer, an Android framework layer, or an application layer.

[0044] The bootloader layer (210) may include a weak device identification module (211) and a memory training module (213). The aforementioned modules are for illustrative purposes only, and the bootloader layer (210) may include additional modules to the aforementioned modules.

[0045] The vulnerable device identification module (211) can determine whether the electronic device (201) corresponds to a vulnerable device based on the memory training results stored in the memory (230). A vulnerable device may correspond to an electronic device (201) in which the memory margin for the memory (230) does not satisfy specified conditions. For example, a vulnerable device may correspond to an electronic device (201) in which data communication between the memory (230) and the processor fails at any reference voltage within the margin area and at any delay time within the margin area. The memory training results may include information on a margin graph corresponding to the memory margin after memory training. The information on the margin graph may include a margin area, a margin area, and / or a defective margin area.

[0046] For example, the vulnerable device identification module (211) may determine that the electronic device (201) corresponds to a vulnerable device if the margin area includes a defective margin area and the margin area does not include a free margin area. As another example, the vulnerable device identification module (211) may determine that the electronic device (201) does not correspond to a vulnerable device if the margin area included in the information regarding the margin graph includes both a defective margin area and a free margin area. As yet another example, the vulnerable device identification module (211) may determine that the memory (230) included in the electronic device (201) is defective if the margin area does not include both a defective margin area and a free margin area.

[0047] The vulnerable device identification module (211) may return a vulnerable device identification result (e.g., attribute data) containing information on whether the electronic device (201) corresponds to a vulnerable device to the processor. The vulnerable device identification result may correspond to either a true or a false value depending on whether the electronic device (201) corresponds to a vulnerable device. For example, if the electronic device (201) corresponds to a vulnerable device, the value of the vulnerable device identification result may be true. As another example, if the electronic device (201) corresponds to a vulnerable device, the value of the vulnerable device identification result may be false.

[0048] The memory training module (213) can generate a margin graph that represents the success or failure of data transfer between the memory (230) and the processor as a two-dimensional graph for any delay time and any reference voltage. The memory training module (213) can identify a margin area on the margin graph where data transfer between the memory (230) and the processor has been successful. The margin area may include at least one pass cell. A pass cell may correspond to a unit cell where data transfer between the memory (230) and the processor has been successful for any reference voltage and any delay time. A unit cell may correspond to a rectangular area where the minimum unit of delay time on the horizontal axis of the margin graph is the horizontal length, and the minimum unit of reference voltage on the vertical axis of the margin graph is the vertical length.

[0049] The defect margin area may be set based on the characteristics of the processor, the characteristics of the memory (230), and / or a combination of the characteristics of the processor and the characteristics of the memory (230). If the margin area includes the defect margin area, that is, if all unit cells within the defect margin area correspond to pass cells, the memory (230) may operate normally. If the margin area does not include the defect margin area, that is, if there are unit cells that are not pass cells within the defect margin area, the memory (230) may be determined to be defective.

[0050] The margin area may correspond to an area in which the length along the horizontal axis of the defect margin area is increased by a first ratio and the length along the vertical axis of the defect margin area is increased by a second ratio, based on the center point of the defect margin area. If the margin area includes the margin area, that is, if all unit cells within the margin area correspond to pass cells, the electronic device (201) may not correspond to a vulnerable device. If the margin area does not include the margin area, that is, if unit cells that are not pass cells exist within the margin area, the electronic device (201) may correspond to a vulnerable device.

[0051] The memory training module (213) can improve the memory margin by performing memory training on the memory (230). The memory training module (213) can improve the memory margin by moving the defect margin area and the free margin area through memory training so that all unit cells within the defect margin area correspond to pass cells and the free margin area contains as many pass cells as possible. The memory training module (213) can perform data communication between the memory (230) and the processor using a reference voltage and delay time corresponding to pass cells included in either the defect margin area after moving and / or the free margin area after moving. The memory training module (213) can ensure that data communication between the memory (230) and the processor is performed stably by performing the memory training.

[0052] The kernel layer (220) may include a panic handler (221) and a margin defect identification module (223). The aforementioned modules are merely for illustrative purposes, and the kernel layer (220) may include additional modules to the aforementioned modules.

[0053] The panic handler (221) may store information about a software error that occurred in the electronic device (201) under specified conditions in memory (230) as a history of software error occurrences. For example, the specified conditions may correspond to a case where a software error occurs in the electronic device (201) and the electronic device (201) is a vulnerable device. For example, information about a software error that occurred in the electronic device (201) may include register information, a snapshot, and / or a log.

[0054] The margin defect identification module (223) can identify defects related to memory margin settings. In identifying defects related to memory margin settings, the margin defect identification module (223) can refer to the history of software errors related to memory margins that occurred in the electronic device (201).

[0055] The margin defect identification module (223) can receive the history of software errors related to memory margins from the memory (230) by transmitting a signal requesting the history of software errors related to memory margins to the memory (230) in order to refer to the history of software errors related to memory margins that occurred in the electronic device (201).

[0056] The margin defect identification module (223) can identify defects related to memory margin settings based on the history of software errors received from memory (230) and software errors that occurred in the electronic device (201).

[0057] The margin defect identification module (223) can identify the number of occurrences of software errors related to memory margin based on the history of software errors and software errors that occurred in the electronic device (201). For example, the margin defect identification module (223) can identify the number of occurrences of software errors related to memory margin by adding 1 to the number of software errors included in the history of software errors.

[0058] The margin defect identification module (223) determines whether the number of occurrences of software errors related to memory margins is greater than or equal to a threshold number, and if the number of occurrences of software errors related to memory margins is greater than or equal to the threshold number, it can determine that a defect related to memory margin settings has occurred in the memory (230). The threshold number may be a number specified by the system or a number specified by the user. For example, the threshold number may be 3 times.

[0059] The margin defect identification module (223) can determine whether a defect related to memory margin setting has occurred in the memory (230) based on a first defect state of the memory (230) caused by a software error (e.g., a first software error) that occurred in the electronic device (201) and a second defect state of the memory (230) that was caused by a software error (e.g., a second software error) included in the history of software errors. The first defect state corresponds to an error phenomenon that occurred in the memory (230) due to the first software error, and the second defect state corresponds to an error phenomenon that occurred in the memory (230) due to the second software error.

[0060] For example, if the first defect state and the second defect state are identical, and the first log stored in memory (230) regarding the history of occurrence of the first software error and the second log stored in memory (230) regarding the history of occurrence of the second software error are different, the margin defect identification module (223) may determine that a defect related to the memory margin setting has occurred in memory (230). As another example, if the first defect state and the second defect state are different, the margin defect identification module (223) may determine that a defect related to the memory margin setting has occurred in memory (230).

[0061] The margin defect identification module (223) can determine whether a defect related to the memory margin setting has occurred in the memory (230) based on the number of occurrences of software errors related to the memory margin and the error state of the memory (230) caused by software errors that occurred in the electronic device (201).

[0062] The margin defect identification module (223) may store a defect identification result related to a memory margin setting of different values ​​(e.g., true or false) in the memory (230) depending on whether a defect related to a memory margin setting has occurred in the memory (230). For example, if the margin defect identification module (223) determines that a defect related to a memory margin setting has occurred in the memory (230), the margin defect identification module (223) may store a value of the defect identification result related to a memory margin setting as true in the memory (230). As another example, if the margin defect identification module (223) determines that a defect related to a memory margin setting has occurred in the memory (230), the margin defect identification module (223) may store a value of the defect identification result related to a memory margin setting as false in the memory (230).

[0063] The margin defect identification module (223) identifies defects related to memory margin settings in the actual usage environment of the electronic device (201) in an environment different from the production environment of the memory (230), thereby allowing the memory training module (213) to perform memory training for the memory (230) even after the production stage of the memory (230), so that defects related to memory margin settings can be improved.

[0064] The memory (230) can store memory training results. The memory training results may include information about a margin graph corresponding to the memory margin after memory training. The information about the margin graph may include information about a margin area, a free margin area, and a defective margin area.

[0065] The memory (230) can store attribute data. The memory (230) can store attribute data as either true or false depending on whether the electronic device (201) is a vulnerable device.

[0066] The memory (230) can store a history of software errors. The history of software errors may include information about software errors that occurred in the electronic device (201). The information about software errors that occurred in the electronic device (201) may include register information, snapshots, and / or logs.

[0067] FIG. 3 is a diagram of a margin graph showing the memory margin of a memory according to one embodiment.

[0068] The margin graph can correspond to a two-dimensional graph indicating whether the data transfer between the memory (not shown) (e.g., the memory (130) of FIG. 1 or the memory (230) of FIG. 2) is successful (pass) by using the reference voltage of the memory (not shown) (e.g., the memory (130) of FIG. 1 or the memory (230) of FIG. 2) and the delay time of the memory as variables.

[0069] The horizontal axis of the margin graph represents the delay time for data transfer between memory and the processor, and the unit of the delay time may be picoseconds (ps). The vertical axis of the margin graph represents the reference voltage for data transfer between memory and the processor, and the unit of the reference voltage may be millivolts (mV).

[0070] The margin region of the margin graph may correspond to an area where data transfer between the memory and the processor has been successful. The margin region may include at least one pass cell (301). The pass cell (301) may correspond to a unit cell where data transfer between the memory and the processor has been successful for any reference voltage and any delay time. The unit cell may correspond to a rectangular area where the minimum unit of delay time, which is the horizontal axis of the margin graph, is the horizontal length, and the minimum unit of reference voltage, which is the vertical axis of the margin graph, is the vertical length.

[0071] For example, with respect to the first reference voltage and the first delay time, if data transfer between the memory and the processor is successful, the unit cell to which the first reference voltage and the first delay time belong may correspond to the pass cell (301). As another example, with respect to the second reference voltage and the second delay time, if data transfer between the memory and the processor fails, the unit cell to which the second reference voltage and the second delay time belong may not correspond to the pass cell (301).

[0072] The fault margin region of the margin graph can be set based on processor characteristics, memory characteristics, and / or a combination of processor characteristics and memory characteristics.

[0073] The processor can determine whether the memory is defective based on whether the margin area includes a defective margin area. For example, if the margin area includes a defective margin area, that is, if all unit cells within the defective margin area correspond to pass cells (301), the processor can determine that the memory is normal. As another example, if the margin area does not include a defective margin area, that is, if there are unit cells that are not pass cells (301) within the defective margin area, the processor can determine that the memory is defective. If the margin area includes a defective margin area, the processor can determine that the memory margin satisfies the first condition.

[0074] The margin area of ​​the margin graph can correspond to an area in which the length in the horizontal axis direction of the defect margin area is increased by a first ratio and the length in the vertical axis direction of the defect margin area is increased by a second ratio, based on the center point of the defect margin area. For example, if the length in the horizontal axis direction of the defect margin area is 40 ps, ​​the length in the vertical axis direction of the defect margin area is 60 mV, the first ratio is 15%, and the second ratio is 15%, the margin area can correspond to an area in which the center point coincides with the center point of the defect margin area, the length in the horizontal axis direction is 46 ps, and the length in the vertical axis direction is 69 mV.

[0075] The processor can determine whether the electronic device is a vulnerable device based on whether the margin area includes a free margin area. For example, if the margin area includes a free margin area, that is, if all unit cells within the free margin area correspond to pass cells (301), the processor can determine that the electronic device is not a vulnerable device. As another example, if the margin area does not include a free margin area, that is, if there are unit cells that are not pass cells (301) within the free margin area, the processor can determine that the electronic device is a vulnerable device. If the margin area includes a free margin area, the processor can determine that the memory margin satisfies the second condition.

[0076] The margin graph may include a first margin graph (310), a second margin graph (320), and a third margin graph (330). The first margin graph (310), the second margin graph (320), and the third margin graph (330) may each be a margin graph corresponding to the memory margin of the memory at different points in time.

[0077] The first margin graph (310) may be a margin graph corresponding to the memory margin after memory training is performed in the memory production environment. The first margin region (311) of the first margin graph (310) may include a pass cell (301) where data transfer between the memory and the processor in the memory production environment has been successful.

[0078] The first margin region (311) may include the first defect margin region (313) and may not include the first margin region (315). Based on the fact that the first margin region (311) includes the first defect margin region (313), the processor may determine that the memory margin corresponding to the first margin graph (310) satisfies the first condition and does not satisfy the second condition. The processor may determine that an electronic device having a memory margin that satisfies the first condition and does not satisfy the second condition is a vulnerable device.

[0079] The second margin graph (320) may be a margin graph corresponding to the memory margin in an environment where the user actually uses the electronic device (hereinafter referred to as the “actual use environment”). The actual use environment of the electronic device and the production environment of the memory may have different environmental conditions. For example, environmental conditions may include ambient temperature, ambient humidity, or the usage time of the electronic device.

[0080] Because the production environment of the memory and the actual usage environment of the electronic device are different, the physical characteristics of the memory change, and thus the success of data transfer between the memory and the processor in any one unit cell may vary. In other words, the pass cell on the margin graph in the memory production environment and the pass cell on the margin graph in the actual usage environment of the electronic device are different, so the margin area in the memory production environment (e.g., first margin area (311)) and the margin area in the actual usage environment of the electronic device (e.g., second margin area (321)) may be different.

[0081] The second margin area (321) may not include the second defect margin area (323). In other words, there may be unit cells other than pass cells (301) within the second defect margin area (323). The processor may determine that the memory margin corresponding to the second margin graph (320) does not satisfy the first condition. As the second margin area (321) does not include the second defect margin area (323), a software error related to the memory margin may occur in the electronic device.

[0082] The third margin graph (330) may be a margin graph corresponding to an improved memory margin after memory training is performed in the actual usage environment of the electronic device. The processor can improve the memory margin through memory training. The third margin area (331) may correspond to the second margin area (321).

[0083] For example, the processor can perform memory training so that the second fault margin region (323) of the second margin graph (320) corresponds to the third fault margin region (333) of the third margin graph (330). As another example, the processor can perform memory training so that the second free margin region (325) of the second margin graph (320) corresponds to the third free margin region (335) of the third margin graph (330).

[0084] Through memory training, the processor can improve the memory margin of the memory. By improving the memory margin, the processor can ensure that data transfer between the memory and the processor is performed reliably.

[0085] FIG. 4 is a signal flow diagram of components included in an electronic device according to one embodiment.

[0086] Referring to FIG. 4, a series of operations for an electronic device (not shown) (e.g., electronic device (101) of FIG. 1, electronic device (201) of FIG. 2, or electronic device (not shown) of FIG. 3) to store attribute data in memory (430) (e.g., memory (130) of FIG. 1, memory (230) of FIG. 2, or memory (not shown) of FIG. 3) may be described. The electronic device may store the value of the attribute data as true or false in memory (430) depending on whether the electronic device is a vulnerable device (e.g., vulnerable device of FIG. 3).

[0087] A processor (420) (e.g., processor (120) of FIG. 1, processor (not shown) of FIG. 2, or processor (not shown) of FIG. 3) may transmit a signal requesting memory training for memory (430) to a memory training module (413) (e.g., memory training module (213) of FIG. 2). The memory training module (413) may receive the signal requesting memory training from the processor (420) and perform memory training for memory (430). The memory training module (413) may return the memory training results according to the performed memory training to the processor (420). The memory training results may include information regarding a margin graph corresponding to the memory margin after memory training. The information regarding the margin graph may include information regarding a margin area, a free margin area, and a defective margin area.

[0088] The processor (420) can transmit a signal to a vulnerable device identification module (411) (e.g., vulnerable device identification module (211)) to identify whether the electronic device is a vulnerable device based on the memory training results received from the memory training module (413). The processor (420) can transmit the signal to identify whether the device is a vulnerable device, along with information about the margin graph received from the memory training module (413), to the vulnerable device identification module (411).

[0089] The vulnerable device identification module (411) can determine whether an electronic device is a vulnerable device based on a signal received from the processor (420) that identifies whether the electronic device is a vulnerable device. The vulnerable device identification module (411) can determine whether an electronic device is a vulnerable device based on information regarding a margin graph received from the processor (420).

[0090] For example, the vulnerable device identification module (411) may determine that the electronic device corresponds to a vulnerable device if the margin area included in the information regarding the margin graph includes a defective margin area and the margin area does not include a free margin area. As another example, the vulnerable device identification module (411) may determine that the electronic device does not correspond to a vulnerable device if the margin area included in the information regarding the margin graph includes both a defective margin area and a free margin area. As yet another example, the vulnerable device identification module (411) may determine that the memory (430) included in the electronic device is defective if the margin area included in the information regarding the margin graph does not include both a defective margin area and a free margin area.

[0091] The vulnerable device identification module (411) may return a vulnerable device identification result to the processor (420) that includes information on whether the electronic device corresponds to a vulnerable device. The vulnerable device identification result may correspond to either a true or a false value depending on whether the electronic device corresponds to a vulnerable device. For example, if the electronic device corresponds to a vulnerable device, the value of the vulnerable device identification result may be true. As another example, if the electronic device corresponds to a vulnerable device, the value of the vulnerable device identification result may be false. For convenience of explanation, the value of the vulnerable device identification result is assumed to be true in the following description when the electronic device corresponds to a vulnerable device.

[0092] If the vulnerable device identification result received from the vulnerable device identification module (411) is true, the processor (420) can store attribute data as true in memory (430). The attribute data can be stored as true or false in memory (430) depending on whether the electronic device is a vulnerable device. For example, if the electronic device is a vulnerable device, the processor (420) can store attribute data as true in memory (430). As another example, if the electronic device is a vulnerable device, the processor (420) can store attribute data as false in memory (430). For convenience of explanation, it is assumed below that if the electronic device is a vulnerable device, the processor (420) stores attribute data as true in memory (430).

[0093] FIG. 5 is a signal flow diagram of components included in an electronic device according to one embodiment.

[0094] Referring to FIG. 5, when a software error occurs in an electronic device (not shown) (e.g., electronic device (101) of FIG. 1, electronic device (201) of FIG. 2, electronic device (not shown) of FIG. 3, or electronic device (not shown) of FIG. 4), a series of operations can be described for the electronic device to determine whether the software error is an error related to memory margin, and if the software error is an error related to memory margin, to perform memory training to improve the memory margin.

[0095] A processor (520) (e.g., processor (120) of FIG. 1, processor (not shown) of FIG. 2, processor (not shown) of FIG. 3, or processor (420) of FIG. 4) can identify software errors that occur in an electronic device. Software errors may include errors that occur in relation to memory margins and / or errors that occur independently of memory margins. For example, errors that occur in relation to memory margins may include list corruption, paging request fail, and / or zram decompression fail.

[0096] The processor (520) may transmit a signal requesting attribute data to memory (530) (e.g., memory (130) of FIG. 1, memory (230) of FIG. 2, memory (not shown) of FIG. 3, or memory (430) of FIG. 4) as a prerequisite for determining whether a software error has occurred in relation to memory margins, in order to determine whether the electronic device is a vulnerable device. Based on the signal requesting attribute data received from the processor (520), the memory (530) may return attribute data to the processor (520).

[0097] The processor (520) can determine whether the electronic device is a vulnerable device based on the value of the attribute data. For example, the processor (520) can determine that the electronic device is a vulnerable device if the value of the attribute data is true. As another example, the processor (520) can determine that the electronic device is a vulnerable device if the value of the attribute data is false. For convenience of explanation, it is assumed below that the processor (520) determines that the electronic device is a vulnerable device if the value of the attribute data is true.

[0098] If the processor (520) determines that the electronic device is a vulnerable device, the processor (520) may transmit a signal to the margin defect identification module (523) (e.g., the margin defect identification module (223) of FIG. 2) requesting identification of a defect related to the memory margin setting.

[0099] If the processor (520) determines that the electronic device is a vulnerable device, a panic handler (not shown) (e.g., the panic handler (221) of FIG. 2) may store information about software errors that occurred in the electronic device in memory (530) as a history of software errors. For example, information about software errors that occurred in the electronic device may include register information, snapshots, and / or logs.

[0100] The margin defect identification module (523) receives a signal from the processor (520) requesting identification of whether there is a defect in the margin, and can identify a defect related to the memory margin setting. The margin defect identification module (523) can identify a defect related to the memory margin setting by referring to the history of software errors related to the memory margin that occurred in the electronic device.

[0101] The margin defect identification module (523) may transmit a signal requesting a history of software errors to the memory (530) in order to refer to the history of software errors related to memory margins that occurred in the electronic device. Based on the signal requesting a history of software errors received from the margin defect identification module (523), the memory (530) may return a history of software errors to the margin defect identification module (523).

[0102] The margin defect identification module (523) can identify defects related to memory margin settings based on the history of software errors received from memory (530) and software errors that occurred in the electronic device.

[0103] The margin defect identification module (523) can identify the number of occurrences of software errors related to memory margin based on the history of software errors and software errors that occurred in the electronic device. For example, the margin defect identification module (523) can identify the number of occurrences of software errors related to memory margin by adding 1 to the number of software errors included in the history of software errors.

[0104] The margin defect identification module (523) determines whether the number of occurrences of software errors related to memory margins is greater than or equal to a threshold number, and if the number of occurrences of software errors related to memory margins is greater than or equal to the threshold number, it can determine that a defect related to memory margin settings has occurred in the memory (530). The threshold number may be a number specified by the system or a number specified by the user. For example, the threshold number may be 3 times.

[0105] The margin defect identification module (523) can determine whether a defect related to memory margin setting has occurred in the memory (530) based on a first defect state of the memory (530) caused by a software error (e.g., a first software error) that occurred in the electronic device and a second defect state of the memory (530) that was caused by a software error (e.g., a second software error) included in the history of software errors. The first defect state corresponds to an error phenomenon that occurred in the memory (530) due to the first software error, and the second defect state corresponds to an error phenomenon that occurred in the memory (530) due to the second software error.

[0106] For example, if the first defect state and the second defect state are identical, and the first log stored in memory (530) regarding the history of occurrence of the first software error and the second log stored in memory (530) regarding the history of occurrence of the second software error are different, the margin defect identification module (523) may determine that a defect related to the memory margin setting has occurred in memory (530). As another example, if the first defect state and the second defect state are different, the margin defect identification module (523) may determine that a defect related to the memory margin setting has occurred in memory (530).

[0107] The margin defect identification module (523) can determine whether a defect related to the memory margin setting has occurred in the memory (530) based on the number of occurrences of software errors related to the memory margin and the error state of the memory (530) caused by software errors that occurred in the electronic device.

[0108] The margin defect identification module (523) can return a defect identification result related to memory margin settings to the processor (520). The defect identification result related to memory margin settings may correspond to either a true or false value when the margin defect identification module (523) determines that a defect related to memory margin settings has occurred in the memory (530). For example, when the margin defect identification module (523) determines that a defect related to memory margin settings has occurred in the memory (530), the value of the defect identification result related to memory margin settings may correspond to true. As another example, when the margin defect identification module (523) determines that a defect related to memory margin settings has occurred in the memory (530), the value of the defect identification result related to memory margin settings may correspond to false. For convenience of explanation, in the following, when the margin defect identification module (523) determines that a defect related to memory margin setting has occurred in the memory (530), it is assumed that the value of the defect identification result related to memory margin setting corresponds to true.

[0109] The margin defect identification module (523) identifies defects related to memory margin settings in the actual usage environment of the electronic device in an environment different from the production environment of the memory (530), thereby allowing the memory training module (513) to perform memory training for the memory (530) even after the production stage of the memory (530), so as to improve defects related to memory margin settings.

[0110] If the value of the defect identification result related to the memory margin setting received from the margin defect identification module (523) is true, the processor (520) can transmit a signal requesting memory training to the memory training module (513) (e.g., the memory training module (213) of FIG. 2, or the memory training module (413) of FIG. 4).

[0111] The memory training module (513) can receive a signal requesting memory training from the processor (520) and perform memory training for the memory (530). By performing memory training, the memory training module (513) can improve the memory margin of the memory (530). By improving the memory margin, the memory training module (513) can ensure that data transfer between the memory (530) and the processor (520) is performed stably.

[0112] FIG. 6 is a flowchart illustrating the process of identifying a weak device according to one embodiment.

[0113] In operation 610, the processor can perform memory training on the memory. By performing memory training, the processor can improve the memory margin of the memory. By improving the memory margin, the processor can ensure that data transfer between the memory and the processor is performed reliably.

[0114] In operation 620, the processor can identify the memory margin of the memory. The memory margin may include information about the conditions under which data communication between the memory and the processor is performed (e.g., the reference voltage of the memory and the latency of the memory). The memory margin may correspond to a user-specified area or a system-pre-configured area among the areas on the margin graph where data communication between the memory and the processor is successful.

[0115] In operation 630, the processor can determine whether the memory margin of the memory satisfies the first condition. The processor can determine that the memory margin satisfies the first condition if the margin area included in the margin graph corresponding to the memory margin includes a defective margin area. For example, if all unit cells within the defective margin area (e.g., unit cells of FIG. 3) correspond to pass cells (e.g., pass cells of FIG. 3), the processor can determine that the memory margin satisfies the first condition. If the memory margin does not satisfy the first condition (operation 630 - N), the processor can determine that the memory is defective in operation 640.

[0116] If the memory margin satisfies the first condition (operation 630 - Y), the processor can determine in operation 650 whether the memory margin satisfies the second condition. The processor can determine that the memory margin satisfies the second condition if the margin area included in the margin graph corresponding to the memory margin includes the free margin area. For example, if all unit cells within the free margin area (e.g., unit cells in FIG. 3) correspond to pass cells (e.g., pass cells in FIG. 3), the processor can determine that the memory margin satisfies the second condition.

[0117] If the memory margin does not satisfy the second condition (Operation 650 - N), the processor may store attribute data in memory in Operation 660. The attribute data may contain information regarding whether the electronic device is a vulnerable device. The processor may store attribute data in memory as either true or false depending on whether the electronic device is a vulnerable device. After performing Operation 660, or if the memory margin satisfies the second condition (Operation 650 - Y), the processor may boot the electronic device in Operation 670.

[0118] FIG. 7 is a flowchart illustrating the process of identifying a memory margin defect and performing memory training according to one embodiment.

[0119] In operation 710, the processor can identify software errors that have occurred in the electronic device. Software errors may include errors that have occurred in relation to memory margins and / or errors that have occurred independently of memory margins. For example, errors that have occurred in relation to memory margins may include list corruption, paging request fail, and / or zram decompression fail.

[0120] In operation 720, the processor may read attribute data stored in memory to determine whether the software error of operation 710 occurred in relation to a defect in memory margin settings. The attribute data may contain information regarding whether the electronic device is a vulnerable device. The processor may store the attribute data in memory as either true or false depending on whether the electronic device is a vulnerable device. For convenience of explanation, it is assumed below that if the electronic device is a vulnerable device, the value of the attribute data corresponds to true.

[0121] In operation 730, the processor can determine whether the value of the read attribute data is true. If the value of the attribute data is false (operation 730 - N), the processor can boot the electronic device in operation 770.

[0122] If the value of the attribute data is true (Operation 730 - Y), the processor may read the software error history stored in memory in Operation 740. The software error history may include information about software errors that occurred in the electronic device. The information about software errors that occurred in the electronic device may include register information, snapshots, and / or logs.

[0123] The processor can determine whether a defect related to memory margin setting has occurred in operation 750. The processor can identify defects related to memory margin setting based on the history of software errors received from memory and software errors that have occurred in the electronic device. The processor can determine whether a defect related to memory margin setting has occurred in memory based on the number of occurrences of software errors related to memory margin and the error state of memory caused by software errors that have occurred in the electronic device. The description of the specific method for the processor to determine whether a defect related to memory margin setting has occurred is replaced by the operation of the processor in FIG. 2 and the operation of the margin defect identification module in FIG. 4.

[0124] By identifying defects related to memory margin settings in the actual usage environment of electronic devices that differ from the memory production environment, the processor can perform memory training on the memory even after the memory production stage, thereby improving defects related to memory margin settings.

[0125] If a fault related to memory margin setting occurs (Operation 750 - Y), the processor may perform memory training on the memory in Operation 760. By performing memory training, the processor may improve the memory margin of the memory. By improving the memory margin, the processor may ensure that data transfer between the memory and the processor is performed reliably. If no fault related to memory margin setting occurs (Operation 750 - Y), the processor may boot the electronic device in Operation 770.

[0126] FIG. 8 is a flowchart illustrating a method for controlling an electronic device according to one embodiment.

[0127] In operation 810, the processor can identify whether attribute data set in relation to the memory margin of the electronic device corresponds to a specified value when a software error occurs in the electronic device. In operation 820, if the attribute data corresponds to a specified value, the processor can identify the history of software error occurrence stored in memory. In operation 830, based on the software error that occurred and the history of software error occurrence, the processor can identify a defect related to the memory margin configuration set for the memory. In operation 840, based on the identification of the defect, the processor can change the memory margin configuration by performing memory training for the memory.

[0128] FIG. 9 is a block diagram of an electronic device (901) in a network environment (900) according to various embodiments (e.g., electronic device (101) of FIG. 1, electronic device (201) of FIG. 2, electronic device (not shown) of FIG. 3, electronic device (not shown) of FIG. 4, electronic device (not shown) of FIG. 5, electronic device (not shown) of FIG. 6, electronic device (not shown) of FIG. 7, or electronic device (not shown) of FIG. 8). Referring to FIG. 9, in the network environment (900), the electronic device (901) may communicate with an electronic device (902) through a first network (998) (e.g., a short-range wireless communication network) or communicate with at least one of an electronic device (904) or a server (908) through a second network (999) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (901) can communicate with the electronic device (904) through the server (908). According to one embodiment, the electronic device (901) may include a processor (920), a memory (930) (e.g., memory (130) of FIG. 1, memory (230) of FIG. 2, memory (not shown) of FIG. 3, memory (430) of FIG. 4, memory (530) of FIG. 5, memory (not shown) of FIG. 6, memory (not shown) of FIG. 7, or memory (not shown) of FIG. 8), an input module (950), an audio output module (955), a display module (960), an audio module (970), a sensor module (976), an interface (977), a connection terminal (978), a haptic module (979), a camera module (980), a power management module (988), a battery (989), a communication module (990), a subscriber identification module (996), or an antenna module (997). In some embodiments, at least one of these components (e.g., connection terminal (978)) may be omitted from the electronic device (901), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (976), camera module (980), or antenna module (997)) may be integrated into a single component (e.g., display module (960)).

[0129] The processor (920) can control at least one other component (e.g., a hardware or software component) of the electronic device (901) connected to the processor (920) by executing software (e.g., a program (940)), for example, and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (920) can store commands or data received from other components (e.g., a sensor module (976) or a communication module (990)) in volatile memory (932), process the commands or data stored in volatile memory (932), and store the resulting data in non-volatile memory (934). According to one embodiment, the processor (920) may include a main processor (921) (e.g., a central processing unit or an application processor) or an auxiliary processor (923) that can operate independently or together with it (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device (901) includes a main processor (921) and an auxiliary processor (923), the auxiliary processor (923) may be configured to use lower power than the main processor (921) or to be specialized for a designated function. The auxiliary processor (923) may be implemented separately from the main processor (921) or as part thereof.

[0130] The auxiliary processor (923) may control at least some of the functions or states associated with at least one component of the electronic device (901) (e.g., display module (960), sensor module (976), or communication module (990)) on behalf of the main processor (921) while the main processor (921) is in an inactive (e.g., sleep) state, or together with the main processor (921) while the main processor (921) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (923) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (980) or communication module (990)). According to one embodiment, the auxiliary processor (923) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (901) itself where the artificial intelligence model is executed, or through a separate server (e.g., server (908)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0131] The memory (930) can store various data used by at least one component of the electronic device (901) (e.g., processor (920) or sensor module (976)). The data may include, for example, software (e.g., program (940)) and input or output data for related commands. The memory (930) may include volatile memory (932) or non-volatile memory (934).

[0132] The program (940) may be stored as software in memory (930) and may include, for example, an operating system (942), middleware (944), or an application (946).

[0133] The input module (950) can receive commands or data to be used for a component of the electronic device (901) (e.g., processor (920)) from outside the electronic device (901) (e.g., user). The input module (950) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0134] The sound output module (955) can output a sound signal to the outside of the electronic device (901). The sound output module (955) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0135] The display module (960) can visually provide information to an external (e.g., user) of the electronic device (901). The display module (960) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (960) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0136] The audio module (970) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (970) can acquire sound through the input module (950) or output sound through the sound output module (955) or an external electronic device (e.g., electronic device (902)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (901).

[0137] The sensor module (976) can detect the operating state of the electronic device (901) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (976) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0138] The interface (977) may support one or more specified protocols that can be used for the electronic device (901) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (902)). According to one embodiment, the interface (977) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0139] The connection terminal (978) may include a connector through which the electronic device (901) can be physically connected to an external electronic device (e.g., electronic device (902)). According to one embodiment, the connection terminal (978) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0140] The haptic module (979) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (979) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0141] The camera module (980) can capture still images and video. According to one embodiment, the camera module (980) may include one or more lenses, image sensors, image signal processors, or flashes.

[0142] The power management module (988) can manage the power supplied to the electronic device (901). According to one embodiment, the power management module (988) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0143] The battery (989) can supply power to at least one component of the electronic device (901). According to one embodiment, the battery (989) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0144] The communication module (990) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (901) and an external electronic device (e.g., electronic device (902), electronic device (904), or server (908)), and the performance of communication through the established communication channel. The communication module (990) may include one or more communication processors that operate independently of the processor (920) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (990) may include a wireless communication module (992) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (994) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (904) through a first network (998) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (999) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (992) can identify or authenticate the electronic device (901) within a communication network such as the first network (998) or the second network (999) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (996).

[0145] The wireless communication module (992) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (992) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (992) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (992) can support various requirements specified in the electronic device (901), external electronic device (e.g., electronic device (904)), or network system (e.g., second network (999)). According to one embodiment, the wireless communication module (992) can support a Peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mMTC, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for realizing URLLC.

[0146] An antenna module (997) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (997) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (997) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (998) or a second network (999), may be selected from the plurality of antennas, for example, by a communication module (990). A signal or power may be transmitted or received between the communication module (990) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (997).

[0147] According to various embodiments, the antenna module (997) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0148] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0149] According to one embodiment, commands or data may be transmitted or received between the electronic device (901) and an external electronic device (904) through a server (908) connected to a second network (999). Each of the external electronic devices (902, or 904) may be the same or a different type of device as the electronic device (901). According to one embodiment, all or part of the operations performed on the electronic device (901) may be performed on one or more of the external electronic devices (902, 904, or 908). For example, if the electronic device (901) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (901) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (901). The electronic device (901) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (901) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device (904) may include an Internet of Things (IoT) device. The server (908) may be an intelligent server using machine learning and / or neural networks. According to one embodiment, the external electronic device (904) or the server (908) may be included within a second network (999).The electronic device (901) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0150] An electronic device (e.g., the electronic device (101) of FIG. 1) comprises a memory (e.g., the memory (130) of FIG. 1) and a processor (e.g., the processor (120) of FIG. 1) connected to the memory (130), and the memory (130) comprises instructions that, when executed by the processor (120), cause the electronic device (101) to identify whether attribute data set in relation to the memory margin of the electronic device (101) corresponds to a specified value when a software error occurs in the electronic device (101), and if the attribute data corresponds to the specified value, identify a history of software error occurrence stored in the memory (130), identify a defect related to the memory margin configuration set for the memory (130) based on the software error that occurred and the history of software error occurrence, and change the memory margin configuration by performing memory training for the memory (130) based on the identification of the defect. It stores, and the memory margin may include information about the driving voltage and information about the latency related to data transmission.

[0151] The above instructions may enable the electronic device (101) to identify the number of occurrences of a software error based on the software error that occurred and the history of the software error occurrence, and to determine that a defect related to the memory margin setting has occurred in the memory (130) if the number of occurrences is greater than or equal to a threshold number.

[0152] The software error that occurred above corresponds to the first software error, and

[0153] The above software error occurrence history may include a history of a second software error occurrence.

[0154] The above instructions may allow the electronic device (101) to determine that a defect related to the memory margin has occurred in the memory (130) if the first defect state related to the memory margin setting that occurred in the memory (130) due to the first software error and the second defect state related to the memory margin setting that occurred in the memory (130) due to the second software error are identical, and if the first log stored in the memory (130) due to the occurrence of the first software error and the second log stored in the memory (130) due to the occurrence of the second software error are different.

[0155] The above instructions may allow the electronic device (101) to determine that a defect related to the memory margin has occurred in the memory (130) if the first defect state related to the memory margin setting, which occurred in the memory (130) due to the first software error, and the second defect state related to the memory margin setting, which occurred in the memory (130) due to the second software error, are different.

[0156] The above instructions can enable the electronic device (101) to resolve a defect related to the memory margin setting that occurred in the memory (130) by changing the memory margin setting.

[0157] The above memory margin setting may include at least one setting among the setting of the driving voltage or the setting of the delay time.

[0158] The above instructions may enable the electronic device (101) to determine whether the data transmission performed based on the driving voltage and the delay time measured in the production stage of the memory (130) satisfies a specified condition, and based on the determination, to store the attribute data corresponding to the specified value.

[0159] The above instructions may cause the electronic device (101) to determine that the data transmission satisfies the specified condition if at least one of the data transmissions performed at any driving voltage included in a specified first range and any delay time included in a specified second range fails.

[0160] The above instructions may cause the electronic device (101) to store a history of software error occurrences in the memory (130) when the software error occurs.

[0161] A method for controlling an electronic device (101) includes, when a software error occurs in the electronic device (101), identifying whether attribute data set in relation to the memory margin of the electronic device (101) corresponds to a specified value; if the attribute data corresponds to the specified value, identifying a history of software error occurrence stored in the memory (130); based on the software error that occurred and the history of software error occurrence, identifying a defect related to a memory margin configuration set for the memory (130); and based on the identification of the defect, changing the memory margin configuration by performing memory training for the memory (130), wherein the memory margin may include information regarding the driving voltage and information regarding the latency related to data transmission.

[0162] The operation of identifying the above defect may include the operation of identifying the number of occurrences of a software error based on the software error that occurred and the history of the software error occurrence, and the operation of determining that a defect related to the memory margin setting has occurred in the memory (130) if the number of occurrences is greater than or equal to a threshold number.

[0163] The software error that occurred above corresponds to a first software error, and the history of the software error occurrence may include a history of a second software error occurrence.

[0164] The operation of identifying the above defect may include determining that a defect related to the memory margin has occurred in the memory (130) if the first defect state related to the memory margin setting that occurred in the memory (130) due to the first software error and the second defect state related to the memory margin setting that occurred in the memory (130) due to the second software error are identical, and if the first log stored in the memory (130) due to the occurrence of the first software error and the second log stored in the memory (130) due to the occurrence of the second software error are different.

[0165] The operation of identifying the above defect may include determining that a defect related to the memory margin has occurred in the memory (130) if the first defect state related to the memory margin setting that occurred in the memory (130) due to the first software error and the second defect state related to the memory margin setting that occurred in the memory (130) due to the second software error are different.

[0166] The operation of changing the memory margin setting may include an operation to resolve a defect related to the memory margin setting that occurred in the memory (130).

[0167] The above memory margin setting may include at least one setting among the setting of the driving voltage or the setting of the delay time.

[0168] The method for controlling the electronic device (101) may further include an operation of determining whether the data transmission performed based on the driving voltage and the delay time measured in the production stage of the memory (130) satisfies a specified condition, and an operation of storing the attribute data corresponding to the specified value based on the determination.

[0169] The operation of determining whether the above data transmission satisfies the specified conditions may include the operation of determining that the data transmission satisfies the specified conditions when at least one of the data transmissions performed at any driving voltage included in a specified first range and any delay time included in a specified second range fails.

[0170] The method of controlling the electronic device (101) may further include the operation of storing a history of software error occurrence in the memory (130) when the software error occurs.

[0171] The electronic device according to the various embodiments disclosed in this document may be of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0172] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as “coupled” or “connected” to another (e.g., 2nd) component, with or without the terms “functionally” or “communicationly,” it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0173] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0174] Various embodiments of the present document may be implemented as software (e.g., program (140)) comprising one or more instructions stored in a storage medium (e.g., internal memory (136) or external memory (138)) readable by a machine (e.g., electronic device (101)). For example, a processor (e.g., processor (120)) of the machine (e.g., electronic device (101)) may call at least one of the one or more instructions stored in the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0175] According to one embodiment, the method according to the various embodiments disclosed herein may be provided as included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0176] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

Claim 1 An electronic device comprising: a memory; and a processor connected to the memory; wherein, when executed by the processor, the memory stores instructions for changing the memory margin configuration by performing memory training for the memory based on the identification of the defects, wherein the memory margin includes information regarding driving voltage and information regarding latency related to data transmission. Claim 2 An electronic device according to claim 1, wherein the instructions enable the electronic device to identify the number of occurrences of a software error based on the software error that occurred and the history of the software error occurrence, and to determine that a defect related to the memory margin setting has occurred in the memory if the number of occurrences is greater than or equal to a threshold number. Claim 3 An electronic device according to claim 1, wherein the software error that occurred corresponds to a first software error, and the software error occurrence history includes a second software error occurrence history. Claim 4 An electronic device according to claim 3, wherein the instructions determine that a defect related to the memory margin has occurred in the memory if the first defect state related to the memory margin setting that occurred in the memory due to the first software error and the second defect state related to the memory margin setting that occurred in the memory due to the second software error are identical, and the first log stored in the memory due to the occurrence of the first software error and the second log stored in the memory due to the occurrence of the second software error are different. Claim 5 An electronic device according to claim 3, wherein the instructions are such that if the first defect state related to the memory margin setting that occurred in the memory due to the first software error and the second defect state related to the memory margin setting that occurred in the memory due to the second software error are different, the electronic device determines that a defect related to the memory margin has occurred in the memory. Claim 6 The electronic device of claim 1, wherein the instructions enable the electronic device to resolve a defect related to the memory margin setting that occurred in the memory by changing the memory margin setting. Claim 7 An electronic device according to claim 6, wherein the memory margin setting comprises at least one setting of the driving voltage setting or the delay time setting. Claim 8 An electronic device according to claim 1, wherein the instructions determine whether the data transmission performed based on the driving voltage and the delay time measured in the production stage of the memory satisfies a specified condition, and based on the determination, store the attribute data corresponding to the specified value. Claim 9 An electronic device according to claim 8, wherein the instructions enable the electronic device to determine that the data transmission satisfies the specified condition when at least one of the data transmissions performed at any driving voltage included in a specified first range and any delay time included in a specified second range fails. Claim 10 The electronic device of claim 1, wherein the instructions enable the electronic device to store a history of software error occurrence in the memory when the software error occurs. Claim 11 A method for controlling an electronic device comprises: an action of identifying whether attribute data set in relation to the memory margin of the electronic device corresponds to a specified value when a software error occurs in the electronic device; an action of identifying a history of software error occurrence stored in memory when the attribute data corresponds to the specified value; an action of identifying a defect related to a memory margin configuration set for the memory based on the software error that occurred and the history of software error occurrence; and an action of changing the memory margin configuration by performing memory training for the memory based on the identification of the defect, wherein the memory margin includes information regarding a driving voltage and information regarding a latency related to data transmission. Claim 12 A method according to claim 11, wherein the operation of identifying the defect comprises: an operation of identifying the number of occurrences of a software error based on the software error that occurred and the history of the software error occurrence; and an operation of determining that a defect related to the memory margin setting has occurred in the memory if the number of occurrences is greater than or equal to a threshold number. Claim 13 A method according to claim 11, wherein the software error that occurred corresponds to a first software error, and the software error occurrence history includes a second software error occurrence history. Claim 14 A method according to claim 13, wherein the operation of identifying the defect comprises: determining that a defect related to the memory margin has occurred in the memory if the first defect state related to the memory margin setting that occurred in the memory due to the first software error and the second defect state related to the memory margin setting that occurred in the memory due to the second software error are identical, and if the first log stored in the memory due to the occurrence of the first software error and the second log stored in the memory due to the occurrence of the second software error are different. Claim 15 A method according to claim 13, wherein the operation of identifying the defect comprises: determining that a defect related to the memory margin has occurred in the memory if the first defect state related to the memory margin setting, which occurred in the memory due to the first software error, and the second defect state related to the memory margin setting, which occurred in the memory due to the second software error, are different. Claim 16 A method according to claim 11, wherein the operation of changing the memory margin setting comprises the operation of resolving a defect related to the memory margin setting that occurred in the memory. Claim 17 A method according to claim 11, wherein the memory margin setting comprises at least one setting of the driving voltage setting or the delay time setting. Claim 18 A method according to claim 11 further comprising: an operation of determining whether the data transmission performed based on the driving voltage and the delay time measured at the production stage of the memory satisfies a specified condition; and an operation of storing the attribute data corresponding to the specified value based on the determination. Claim 19 A method according to claim 18, wherein the operation of determining whether the data transmission satisfies a specified condition comprises: determining that the data transmission satisfies the specified condition when at least one of the data transmissions performed at any driving voltage included in a specified first range and any delay time included in a specified second range fails. Claim 20 A method according to claim 11, further comprising the operation of storing a history of software error occurrence in the memory when the software error occurs.

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