Stress-relieved semiconductor 3D multi-layer structure and Semiconductor Memory using the 3D multi-layer structure and Method for building Stress-relieved semiconductor 3D multi-layer structure.

Abstract

The present invention relates to a semiconductor three-dimensional stacked structure with relieved interlayer stress and a method for forming the same, and more specifically, to a semiconductor three-dimensional stacked structure with relieved interlayer stress in which a two-dimensional material layer is interposed between a plurality of film layers and a method for forming the same. A semiconductor three-dimensional stacked structure according to the present invention comprises a plurality of film layers; and at least one two-dimensional material layer; wherein the plurality of film layers and the at least one two-dimensional material layer are stacked to form a semiconductor three-dimensional stacked structure, and wherein at least one two-dimensional material layer is interposed between the plurality of film layers.

Description

Technology Field

[0001] The present invention relates to a semiconductor three-dimensional stacked structure with relieved interlayer stress and a method for forming the same, and more specifically, to a semiconductor three-dimensional stacked structure with relieved interlayer stress in which a two-dimensional material layer is interposed between a plurality of film layers and a method for forming the same. Background Technology

[0002] In the current semiconductor industry, there is a great deal of interest in high-capacity memory and high-density systems for transmitting large amounts of data at high speeds, and research on three-dimensional semiconductor stacking structures is particularly active.

[0003] A semiconductor three-dimensional stacked structure is a high-density semiconductor structure in which multiple layers of semiconductor material are stacked vertically in a three-dimensional structure. The stacking technology used to form such a semiconductor structure is utilized to implement high-density, high-performance semiconductor chips in NAND Flash memory, as well as in DRAM and system semiconductors.

[0004] In particular, semiconductor three-dimensional stacked structures can overcome the limitations of traditional memory structures, such as the von Neumann architecture, where data storage and computational processing share a single memory space by stacking multiple independent layers to form a single system. In addition, they are suitable for processing large volumes of data, such as big data, where the amount of data is vast and complex computations are required.

[0005] However, in such semiconductor three-dimensional stacked structures, interlayer stress may occur due to different physical properties, such as the thermal expansion coefficients of the materials forming each layer or the distance between molecules.

[0006] FIG. 1 illustrates a SiO2-Si3N4 stacked structure (10) in which SiO2 and Si3N4 used in NAND flash memory are stacked adjacently as an example of a semiconductor three-dimensional stacked structure in which the above-mentioned interlayer stress occurs. Taking the above-mentioned SiO2-Si3N4 stacked structure (10) as an example, as shown in FIG. 1, compressive stress occurs in SiO2, tensile stress occurs in Si3N4, and warpage occurs.

[0007] The aforementioned interlayer stress problem causes many problems during the stacked structure process, including directly, wafer misalignment and warpage, and indirectly, overlay problems in subsequent exposure processes, degradation of Degree of Freedom (DoF) performance, and defects during the etching process.

[0008] The aforementioned interlayer stress problem is a major factor causing yield reduction and system performance degradation; however, since the issue stems from the different physical properties of the materials, there were limitations in solving the problem through improvements in process methods. The problem to be solved

[0009] The present invention relates to a semiconductor three-dimensional stacked structure with relieved interlayer stress and a method for forming the same, and more specifically, aims to provide a semiconductor three-dimensional stacked structure with relieved interlayer stress through a two-dimensional material layer interposed between a plurality of film layers and a method for forming the same. means of solving the problem

[0010] A semiconductor three-dimensional stacked structure with relieved interlayer stress according to one embodiment of the present invention for achieving the above-mentioned purpose comprises: a plurality of film layers; and at least one two-dimensional material layer.

[0011] Here, the plurality of film layers and the at least one two-dimensional material layer are stacked to form a semiconductor three-dimensional stacked structure, and at least one two-dimensional material layer is interposed between the plurality of film layers.

[0012] In addition, the plurality of film layers are divided into a plurality of film layer groups with the two-dimensional material layer in between, and each of the plurality of film layer groups may include at least one film layer.

[0013] In addition, the plurality of film layers may include a first material film layer and a second material film layer of different types.

[0014] Additionally, each of the above film layer groups includes at least one of the first material film layer and the second material film layer, and when both the first material film layer and the second material film layer are included, the first material film layer and the second material film layer may be formed in a manner in which they are alternately stacked.

[0015] In addition, the first material film layer may be a silicon dioxide (SiO2) film layer, and the second material film layer may be a silicon nitride (Si3N4) film layer.

[0016] In addition, the two-dimensional material forming the above two-dimensional material layer may include any one of graphene, molybdenum diselenide (MoSe2), platinum chalcogenide (PtSe2), and molybdenum disulfide (MoS2).

[0017] In addition, the two-dimensional material forming the above two-dimensional material layer may be a polycrystalline material.

[0018] In addition, the two-dimensional material forming the above-mentioned two-dimensional material layer is arranged in a plane of one layer through interatomic covalent bonding, and forms weak interatomic van der Waals bonds in a direction perpendicular to the plane, and may be composed of one or three atoms.

[0019] In addition, the two-dimensional material layer may be formed by a method in which the two-dimensional material grows on the surface of any one of the plurality of film layers.

[0020] In addition, the two-dimensional material layer can be stacked in multiple layers between the plurality of film layers.

[0021] In addition, at least one damaged section may be formed in the above-mentioned two-dimensional material layer.

[0022] In addition, the above two-dimensional material layer can be deposited using any one of the following methods: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Liquid Exfoliation, and Wet Chemical Synthesis.

[0023] In addition, the above two-dimensional material layer can be deposited using Low Temperature Chemical Vapor Deposition, which performs chemical vapor deposition at a low temperature of less than 300°C.

[0024] In addition, the above two-dimensional material layer may be provided as any one of a molybdenum diselenide layer formed at 200°C or lower, a platinum chalcogenide layer formed at 400°C or lower, and a molybdenum disulfide layer formed at 500°C or lower.

[0025] The semiconductor memory according to the present invention includes a semiconductor three-dimensional stacked structure in which interlayer stress is relieved as described above.

[0026] A method for forming a semiconductor three-dimensional stacked structure with interlayer stress relieved according to the present invention is a method for forming a semiconductor three-dimensional stacked structure by stacking a plurality of film layers including a first film layer and a second film layer, comprising: a) a step of providing the first film layer; b) a step of stacking at least one two-dimensional material layer on the first film layer; and c) a step of stacking the second film layer on the two-dimensional material layer.

[0027] In addition, the plurality of film layers are divided into a plurality of film layer groups, each comprising at least one film layer, and the plurality of film layer groups may comprise a first film layer group comprising the first film layer and a second film layer group comprising the second film layer.

[0028] In addition, step a) is a step in which at least one film layer included in the first film layer group is sequentially stacked, and the first film layer may be stacked on the top of the first film layer group.

[0029] Additionally, step b) may be a step in which the two-dimensional material layer is stacked on the first film layer group.

[0030] Additionally, step c) is a step in which at least one film layer included in the second film layer group is sequentially stacked on the two-dimensional material layer, and the first film layer may be stacked at the bottom of the second film layer group.

[0031] In addition, the plurality of film layers may include a first material film layer and a second material film layer of different types.

[0032] Additionally, each of the above film layer groups includes at least one of the first material film layer and the second material film layer, and when both the first material film layer and the second material film layer are included, the above steps a) and b) may be steps in which the first material film layer and the second material film layer are alternately stacked.

[0033] In addition, the first material film layer may be a silicon dioxide (SiO2) film layer, and the second material film layer may be a silicon nitride (Si3N4) film layer.

[0034] In addition, the two-dimensional material forming the above two-dimensional material layer may include any one of graphene, molybdenum diselenide (MoSe2), platinum chalcogenide (PtSe2), and molybdenum disulfide (MoS2).

[0035] In addition, the two-dimensional material forming the above two-dimensional material layer may be a polycrystalline material.

[0036] In addition, the two-dimensional material forming the above-mentioned two-dimensional material layer is arranged in a plane of one layer through interatomic covalent bonding, and forms weak interatomic van der Waals bonds in a direction perpendicular to the plane, and may be composed of one or three atoms.

[0037] In addition, step b) may be a step of growing a two-dimensional material on the surface of the first film layer to form the two-dimensional material layer.

[0038] Additionally, step b) may be a step in which the two-dimensional material layer is stacked in multiple layers on the first film layer group.

[0039] Additionally, between step b) and step c), a step of damaging the two-dimensional material layer to form at least one damaged section may be further included.

[0040] In addition, in step b) above, the two-dimensional material layer can be deposited using any one of the following methods: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Liquid Exfoliation, and Wet Chemical Synthesis.

[0041] In addition, the above two-dimensional material layer can be deposited using Low Temperature Chemical Vapor Deposition, which performs chemical vapor deposition at a low temperature of less than 300°C.

[0042] In addition, step b) may be a step of forming a molybdenum diselenide layer at 200°C or lower, a step of forming a platinum chalcogenide layer at 400°C or lower, or a step of forming a molybdenum disulfide layer at 500°C or lower. Effects of the invention

[0043] According to the semiconductor three-dimensional stacked structure with relieved interlayer stress and the method for forming the same according to the present invention, the interlayer stress of the semiconductor 3D stacked structure can be minimized through a two-dimensional material interposed between a plurality of film layers.

[0044] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art to which the present invention pertains (referred to as "person skilled in the art") from the description in the claims. Brief explanation of the drawing

[0045] Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein similar reference numerals indicate similar elements, but are not limited thereto. Figure 1 is an example to show interlayer stress occurring in a semiconductor three-dimensional stacked structure according to the prior art. FIG. 2 is a schematic diagram showing a semiconductor three-dimensional stacked structure in which interlayer stress is relieved by the present invention. FIG. 3 is a drawing showing at least a part of a semiconductor three-dimensional stacked structure in which interlayer stress is relieved according to a first embodiment of the present invention. FIG. 4 is a drawing showing at least a portion of a semiconductor three-dimensional stacked structure in which interlayer stress is relieved according to a second embodiment of the present invention. FIG. 5 is a drawing showing at least a portion of a semiconductor three-dimensional stacked structure in which interlayer stress is relieved according to a third embodiment of the present invention. FIG. 6 is a drawing showing at least a portion of a semiconductor three-dimensional stacked structure in which interlayer stress is relieved according to the fourth embodiment of the present invention. FIG. 7 is a flowchart illustrating a method for forming a semiconductor three-dimensional stacked structure with interlayer stress relieved according to an embodiment of the present invention. Specific details for implementing the invention

[0046] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding widely known functions or configurations will be omitted if there is a risk of unnecessarily obscuring the essence of the present invention.

[0047] In the attached drawings, identical or corresponding components are assigned the same reference numerals. Additionally, in the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0048] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to fully inform a person skilled in the art of the scope of the invention.

[0049] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0050] For example, the term “technique” may refer to systems, methods, computer-readable instructions, modules, algorithms, hardware logic, and / or operations throughout the document as permitted by the context described above.

[0051] The terms used in this specification will be briefly explained, and the disclosed embodiments will be described in detail. The terms used in this specification have been selected to be as generally used as possible, taking into account their functions in the present invention; however, these terms may vary depending on the intent of those skilled in the relevant field, case law, or the emergence of new technologies. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall content of the invention.

[0052] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0053] In the present invention, terms such as 'comprising', 'comprising', etc. may indicate the presence of features, steps, actions, elements and / or components, but do not exclude the addition of one or more other functions, steps, actions, elements, components and / or combinations thereof.

[0054] In the present invention, where a specific component is described as being 'combined,' 'combined,' 'connected,' 'associated,' or 'reacted' to any other component, the specific component may be directly combined, combined, connected, and / or associated with, or reacted to the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Additionally, in the present invention, "and / or" may include each of the one or more listed items or a combination of at least some of the one or more items.

[0055] In the present invention, terms such as 'first', 'second', etc., are used to distinguish a specific component from another component, and the components described above are not limited by these terms. For example, the 'first' component may be used to refer to an element of the same or similar form as the 'second' component.

[0056] The system described below constitutes one embodiment and is not intended to limit the scope of the claims to any single specific operating environment. It may be used in other environments without departing from the technical spirit and scope of the claimed essence.

[0057] A semiconductor three-dimensional stacked structure with relieved interlayer stress according to an embodiment of the present invention is described with reference to FIG. 2.

[0058] Referring to FIG. 2, a semiconductor three-dimensional stacked structure (3D Multi-layer structure; 100) according to the present invention comprises a plurality of film layers (L) and at least one two-dimensional material layer (2-Dimension material layer; l).

[0059] In addition, according to the present invention, a plurality of film layers (L) and at least one two-dimensional material layer (l) are stacked to form a semiconductor three-dimensional stacked structure (100), and at least one two-dimensional material layer (l) is interposed between the plurality of film layers (L).

[0060] In addition, according to the present invention, a plurality of film layers (L) may be divided into a plurality of film layer groups (G) with a two-dimensional material layer (l) in between. Here, each film layer group (G) may be configured to include at least one film layer (L).

[0061] A membrane is a material that exists in the form of a thin film, and in the semiconductor field, it can refer to a layer of material formed on a substrate.

[0062] Films influence the operation and performance of semiconductor devices and play a role in controlling properties such as electrical, optical, and mechanical characteristics. They are also used for purposes such as surface protection, barrier formation, insulation, resistance, and reflection. For example, surface protection films can protect the substrate surface through chemical or physical methods to reduce corrosion or the influence of the external environment, while barrier films can be used to maintain material stability or control desired reactions by blocking the diffusion or transmission of other substances.

[0063] Films are generally formed through deposition, infiltration, or coating processes, but are not limited to these and can be formed by various other methods. The film formation method is selected based on the material and application of the constituent substances of each film, and can be adjusted according to the desired film thickness and characteristics.

[0064] In the semiconductor three-dimensional stacked structure (100) of the present invention, a plurality of film layers (L) may include at least two types of film layers, and various electrical, optical, and mechanical properties can be controlled through the selection of materials of each film layer (L), stacking order, and inter-layer interface management.

[0065] The two-dimensional material forming the two-dimensional material layer (l) is a crystalline material in which small atoms of nanometer size are arranged in a single plane through interatomic covalent bonds and van der Waals interactions (V) are formed perpendicular to the plane, and may consist of one or three atoms.

[0066] Two-dimensional materials have two-dimensional characteristics due to their limited structure in the thickness direction, and they have high flexibility and strength. In particular, they are suitable as interlayer stress relievers for semiconductor three-dimensional stacked structures formed by high-density intensive technology because they are very thin with a thickness of less than 1 nm.

[0067] Examples of two-dimensional materials include graphene, which consists of one atom of about 0.3 nm or less, and molybdenum disulfide (MoS2) and molybdenum diselenide (MoSe2), which consist of three atoms of about 0.7 nm or less.

[0068] The semiconductor three-dimensional stacked structure (100) of the present invention utilizes the basic physical properties of a two-dimensional material that forms van der Waals bonds (V) in the vertical direction, and aims to reduce interlayer stress by interposing a two-dimensional material layer (l) that forms van der Waals bonds (V) between adjacent film layers between a plurality of film layers (L).

[0069] Here, since the bonding force of the van der Waals bond (V) is generally significantly weaker compared to the bonding force between the film layers forming the semiconductor three-dimensional stacked structure (100), the interlayer stress of the semiconductor three-dimensional stacked structure (100) can be greatly reduced simply by interposing a two-dimensional material layer (l) between a plurality of film layers (L).

[0070] The present invention utilizes the basic physical properties of a two-dimensional material that generates van der Waals bonds (V) in the vertical direction as described above, and has the advantage of having very low dependence on the quality of the two-dimensional material.

[0071] That is, according to the present invention, the problem of interlayer stress in a semiconductor three-dimensional stacked structure (100) can be solved using a low-quality two-dimensional material, so there is a high efficiency, and the process difficulty is low, making it highly accessible, and there is an advantage of being able to save a large amount of cost and energy required for the process.

[0072] For example, the two-dimensional material layer (l) may be composed of a low-quality material formed at a low temperature, considering the typical formation temperature of each two-dimensional material. For example, the two-dimensional material layer (l) may be provided as a molybdenum diselenide (MoSe2) layer formed at about 200°C or lower, may be provided as a platinum chalcogenide (PtSe2) layer formed at about 400°C or lower, or may be provided as a molybdenum disulfide (MoS2) layer formed at about 500°C or lower.

[0073] As another example, the two-dimensional material layer (l) may be a material layer grown directly on a large-area substrate and may be made of a single-crystal material or a lower-quality polycrystalline material.

[0074] In addition, according to the present invention, a semiconductor three-dimensional stacked structure (100) can be formed in such a way that a two-dimensional material layer (l) is stacked on one of a plurality of film layer groups (G), and another film layer group is stacked on the stacked two-dimensional material layer (l).

[0075] As a method for stacking a two-dimensional material layer (l), any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Liquid Exfoliation, and Wet Chemical Synthesis may be used.

[0076] Preferably, the two-dimensional material layer (l) can be deposited using a low-temperature chemical vapor deposition method that performs chemical vapor deposition at a low temperature of less than 300°C.

[0077] In addition, the two-dimensional material layer (l) may be formed by directly growing the two-dimensional material on the surface of the film layer to be stacked.

[0078] Additionally, the semiconductor three-dimensional stacked structure (100) can be formed by inserting a two-dimensional material layer (l) between a plurality of previously stacked film layers (L), but is not limited thereto and can be formed in various ways.

[0079] Hereinafter, various embodiments of the present invention will be described with reference to FIGS. 3 to 6.

[0080] Here, the configurations illustrated in FIGS. 3 to 6 may be at least part of the semiconductor three-dimensional stacked structure (100) according to the present invention, and the descriptions in relation to FIGS. 3 to 6 may be extended to the remaining part of the semiconductor three-dimensional stacked structure not illustrated in the drawings.

[0081] FIG. 3 illustrates a semiconductor three-dimensional stacked structure (100-1) according to a first embodiment of the present invention.

[0082] Referring to FIG. 3, the semiconductor three-dimensional stacked structure (100-1) includes a first film layer group (G1) and a second film layer group (G2) adjacent to each other, and a first two-dimensional material layer (l1) interposed between the first film layer group (G1) and the second film layer group (G2).

[0083] Additionally, the first film layer group (G1) includes a first film layer (L1) stacked adjacent to one side of the first two-dimensional material layer (l1), and the second film layer group (G2) includes a second film layer (L2) stacked adjacent to the other side of the first two-dimensional material layer (l1).

[0084] Accordingly, van der Waals bonds are formed between the first membrane layer (L1) and the first two-dimensional material layer (l1), and between the first two-dimensional material layer (l1) and the second membrane layer (L2), and very small interlayer stress is generated.

[0085] Here, generally, the semiconductor three-dimensional stacked structure is sequentially stacked in the vertical direction, in which case one side and the other side of the first two-dimensional material layer (l1) may be the lower side and the upper side, respectively.

[0086] Additionally, the first film layer group (G1) and the second film layer group (G2) may be configured to include at least one of a first material film layer made of any first material (A) and a second material film layer made of any second material (B).

[0087] In addition, if the first film layer group (G1) or the second film layer group (G2) includes both the first material film layer and the second material film layer, the film layer group may be provided in a manner in which the first material film layer and the second material film layer are alternately stacked.

[0088] For example, the first material (A) and the second material (B) may be either silicon dioxide (SiO2) or silicon nitride (Si3N4). In this case, the semiconductor three-dimensional stacked structure (100) may be a silicon dioxide-silicon nitride (SiO2-Si3N4) structure in which at least one silicon dioxide (SiO2) and at least one silicon nitride (Si3N4) are alternately stacked, with a two-dimensional material layer (l) interposed therein.

[0089] Additionally, the first film layer (L1) and the second film layer (L2) may be made of the same material or different materials. The first embodiment is illustrated in which the first film layer (L1) and the second film layer (L2) are made of the same first material (A).

[0090] FIG. 4 illustrates a semiconductor three-dimensional stacked structure (100-2) according to a second embodiment of the present invention.

[0091] The second embodiment follows the first embodiment described above, but differs in that the first film layer (L1) and the second film layer (L2) are made of different materials.

[0092] According to the second embodiment, the first film layer (L1) and the second film layer (L2) may be either one of the different first material (A) and the different second material (B), and in this case, the interlayer stress can be minimized as a two-dimensional material layer (L1) is interposed between the film layers of different materials.

[0093] FIG. 5 illustrates a semiconductor three-dimensional stacked structure (100-3) according to a third embodiment of the present invention.

[0094] The third embodiment follows the first embodiment described above, but differs in that multiple layers of two-dimensional material (l1, l2) are interposed between the first film layer group (G1) and the second film layer group (G2). In the third embodiment, the first two-dimensional material layer (l1) and the second two-dimensional material layer (l2) are presented as examples of the multiple layers of two-dimensional material (l1, l2).

[0095] According to the third embodiment, van der Waals bonds are formed between the first membrane layer (L1) and the first two-dimensional material layer (l1), between the first two-dimensional material layer (l1) and the second two-dimensional material layer (l2), and between the second two-dimensional material layer (l2) and the second membrane layer (L2).

[0096] Here, since the atoms of a two-dimensional material are arranged in a single plane, the van der Waals bonds between two-dimensional materials generally have a weaker bonding force than the van der Waals bonds between a two-dimensional material and another material.

[0097] Accordingly, as in the third embodiment, the interlayer stress of the semiconductor three-dimensional stacked structure (100) can be further relieved by stacking multiple layers of two-dimensional material layers (l1, l2) between the first film layer group (G1) and the second film layer group (G2).

[0098] In addition, depending on the degree of defects in the two-dimensional material layers (l1, l2), interlayer stress relief using the two-dimensional material layers (l1, l2) may not be sufficiently achieved, but this problem can be solved by stacking multiple layers of the two-dimensional material layers (l1, l2) between the first film layer group (G1) and the second film layer group (G2) as in the third embodiment.

[0099] FIG. 6 illustrates a semiconductor three-dimensional stacked structure (100-4) according to the fourth embodiment of the present invention.

[0100] The fourth embodiment follows the first embodiment described above, but differs in that at least one damage section (D) is formed in the first two-dimensional material layer (l1).

[0101] The damage section (D) is formed by partially artificially damaging the first two-dimensional material layer (l1) to create a defect in the two-dimensional material structure, and can be formed using physical or chemical methods.

[0102] As an example of a physical method for forming a damage section (D), a scratching method may be used to damage atoms or molecules by applying physical force to the surface of a two-dimensional material layer using a scratching tool or other high-hardness object. Additionally, as an example of a chemical method, a doping method may be used to change the chemical properties of the surface or form new bonds by supplying any chemical substance to the surface of a two-dimensional material layer.

[0103] According to the fourth embodiment, between the first film layer group (G1) and the second film layer group (G2) and the first two-dimensional material layer (l1), a bond (D-Bonding) is formed by a damage section (D) as well as a van der Waals bond (V) based on the properties of the two-dimensional material.

[0104] Here, the bonding by the damage section (D) (D-Bonding) may be an atomic bonding or molecular bonding other than a van der Waals bond, and is generally stronger than a van der Waals bond.

[0105] Accordingly, by forming a damage section (D) in the first two-dimensional material layer (l1) as in the fourth embodiment, the interlayer stress of the semiconductor three-dimensional stacked structure (100) of the present invention, which significantly relieves interlayer stress using van der Waals bonding, can be slightly strengthened.

[0106] In addition, problems that may occur due to the interlayer bonding strength of the semiconductor three-dimensional stacked structure (100) being weakened by the inclusion of a two-dimensional material layer, such as wafer tearing, can be resolved.

[0107] In addition, the interlayer bonding strength of the semiconductor three-dimensional stacked structure (100) can be controlled by adjusting the area, location, and number of damage sections (D) on the two-dimensional material layer.

[0108] Hereinafter, a method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress according to the present invention will be described with reference to FIGS. 7 and 8.

[0109] FIG. 7 schematically illustrates the process of forming a semiconductor three-dimensional stacked structure with reduced interlayer stress according to an embodiment of the present invention, and FIG. 8 illustrates a flowchart of a method for forming a semiconductor three-dimensional stacked structure with reduced interlayer stress according to an embodiment of the present invention.

[0110] Step S10 is a step in which a semiconductor substrate (not shown) is prepared.

[0111] Step S20 is a step in which at least one film layer (L) is deposited. (See FIG. 7 (a))

[0112] Step S20 may be a step in which at least one film layer (L) is laminated on the semiconductor substrate prepared in Step S10.

[0113] The above at least one film layer (L) may be sequentially stacked from the bottom to the top, and the at least one film layer (L) stacked in step S20 may form a film layer group (G).

[0114] Step S30 is a step in which at least one two-dimensional material layer (l) is deposited on the film layer group (G) prepared in step S10. (See FIG. 7 (b))

[0115] According to step S30, a single layer of two-dimensional material (l1) or multiple layers of two-dimensional material (l1, l2) may be stacked on the first layer (L1) stacked on the top of the group of film layers (G) prepared in step S10.

[0116] Step S40 is the step of forming a damaged section (D) on a two-dimensional material layer (l). (See FIG. 7 (c))

[0117] According to step S40, a defect can be formed in the two-dimensional material structure by partially applying artificial damage to the two-dimensional material layer (l) stacked in step S30.

[0118] Here, if a plurality of two-dimensional material layers (l1, l2) are stacked in step S30, a damage section (D) may be formed in part or all of the plurality of two-dimensional material layers (l1, l2) as needed. For example, a first two-dimensional material layer (l1) may be stacked through step S30, and then a damage section (D) may be formed in the first two-dimensional material layer (l1) through step S40, and then a second two-dimensional material layer (l2) may be stacked through step S30, and then a damage section (D) may be formed in the second two-dimensional material layer (l2) through step S40.

[0119] Additionally, this step S40 may be omitted as needed.

[0120] Step S50 is a step in which at least one film layer (L) is deposited on at least one two-dimensional material layer (l) deposited in Step S30. (See FIG. 7 (d))

[0121] At least one film layer (L) stacked in step S50 can form one film layer group (G).

[0122] Step S60 is a step for determining whether the total number of stacked film layers (L) has reached the target number of stacked layers (N). If the number of stacked accumulated film layers (L) has reached the target number of stacked layers (N), the formation of the semiconductor three-dimensional stacked structure can be terminated. Additionally, if the number of stacked accumulated film layers (L) has not reached the target number of stacked layers (N), steps S40 through S60 can be performed again to further stack two-dimensional material layers (l) and film layer groups (G).

[0123] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0124] Accordingly, the scope of the present invention is not limited to the embodiments described above, and all modifications equivalent to or equivalent to the claims set forth below, as well as the claims described below, shall be considered to fall within the scope of the scope of the present invention. Explanation of the symbols

[0125] A: First material B: Second material D: Damage Section G: Membranous layer group G1: First membranous layer group G2: Second membranous layer group L: Membranous layer L1: First membranous layer L1: Second membranous layer l: Two-dimensional membrane layer l1: First two-dimensional membranous layer l2: Second two-dimensional membranous layer 100,100-2,100-2,100-3,100-4: Semiconductor three-dimensional stacked structure

Claims

Claim 1 A semiconductor three-dimensional stacked structure with relieved interlayer stress, comprising: a plurality of film layers; and at least one two-dimensional material layer; wherein the plurality of film layers and the at least one two-dimensional material layer are stacked to form a semiconductor three-dimensional stacked structure, and at least one of the two-dimensional material layers is interposed between the plurality of film layers. Claim 2 A semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein, in claim 1, the plurality of film layers are divided into a plurality of film layer groups with the two-dimensional material layer in between, and each of the plurality of film layer groups includes at least one film layer. Claim 3 In paragraph 2, the plurality of film layers comprises a first material film layer and a second material film layer of different types, forming a semiconductor three-dimensional stacked structure with relieved interlayer stress. Claim 4 A semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein each of the film layer groups comprises at least one of the first material film layer and the second material film layer, and when both the first material film layer and the second material film layer are included, the first material film layer and the second material film layer are formed in a manner in which they are alternately stacked. Claim 5 A semiconductor three-dimensional stacked structure with reduced interlayer stress, wherein the first material film layer is a silicon dioxide (SiO2) film layer and the second material film layer is a silicon nitride (Si3N4) film layer. Claim 6 In claim 1, the two-dimensional material forming the two-dimensional material layer comprises any one of graphene, molybdenum diselenide (MoSe2), platinum chalcogenide (PtSe2), and molybdenum disulfide (MoS2), forming a semiconductor three-dimensional stacked structure with relieved interlayer stress. Claim 7 In claim 1, the two-dimensional material forming the two-dimensional material layer is a polycrystalline material, a semiconductor three-dimensional stacked structure with relieved interlayer stress. Claim 8 In claim 1, the two-dimensional material forming the two-dimensional material layer is arranged in a plane of one layer through interatomic covalent bonding, has weak interatomic van der Waals bonding in a direction perpendicular to the said plane, and is composed of one or three atoms, a semiconductor three-dimensional stacked structure with relieved interlayer stress. Claim 9 In claim 1, the semiconductor three-dimensional stacked structure with relieved interlayer stress is formed such that the two-dimensional material layer is formed by growing the two-dimensional material on the surface of any one of the plurality of film layers. Claim 10 In claim 1, the two-dimensional material layer is a semiconductor three-dimensional stacked structure with interlayer stress relieved, which is stacked in multiple layers between the plurality of film layers. Claim 11 A semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein at least one damage section is formed in the two-dimensional material layer according to claim 1. Claim 12 In claim 1, the two-dimensional material layer is a semiconductor three-dimensional stacked structure with reduced interlayer stress, stacked using any one of the methods of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Liquid Exfoliation, and Wet Chemical Synthesis. Claim 13 In claim 12, the two-dimensional material layer is a semiconductor three-dimensional stacked structure with relieved interlayer stress, stacked using Low Temperature Chemical Vapor Deposition, which performs chemical vapor deposition at a low temperature of less than 300°C. Claim 14 A semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein the two-dimensional material layer is provided as any one of a molybdenum diselenide layer formed at 200°C or lower, a platinum chalcogenide layer formed at 400°C or lower, and a molybdenum disulfide layer formed at 500°C or lower. Claim 15 A semiconductor memory comprising a semiconductor three-dimensional stacked structure with relieved interlayer stress as described in any one of claims 1 to 14. Claim 16 A method for forming a semiconductor three-dimensional stacked structure by stacking a plurality of film layers, including a first film layer and a second film layer, comprising: a) a step of providing the first film layer; b) a step of stacking at least one two-dimensional material layer on the first film layer; and c) a step of stacking the second film layer on the two-dimensional material layer; wherein the method comprises: a) a step of providing the first film layer; b) a step of stacking at least one two-dimensional material layer on the first film layer; and c) a step of stacking the second film layer on the two-dimensional material layer. Claim 17 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein, in claim 16, the plurality of film layers are divided into a plurality of film layer groups each comprising at least one film layer, and the plurality of film layer groups include a first film layer group comprising the first film layer and a second film layer group comprising the second film layer, wherein step a) is a step of sequentially stacking at least one film layer included in the first film layer group, wherein the first film layer is stacked on the top of the first film layer group, step b) is a step of stacking the two-dimensional material layer on the first film layer group, and step c) is a step of sequentially stacking at least one film layer included in the second film layer group on the two-dimensional material layer, wherein the first film layer is stacked on the bottom of the second film layer group. Claim 18 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein, in claim 17, the plurality of film layers include a first material film layer and a second material film layer of different types. Claim 19 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein, in claim 18, each of the film layer groups comprises at least one of the first material film layer and the second material film layer, and when both the first material film layer and the second material film layer are included, the steps a) and b) are steps in which the first material film layer and the second material film layer are alternately stacked. Claim 20 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress according to claim 19, wherein the first material film layer is a silicon dioxide (SiO2) film layer and the second material film layer is a silicon nitride (Si3N4) film layer. Claim 21 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress according to claim 16, wherein the two-dimensional material forming the two-dimensional material layer comprises any one of graphene, molybdenum diselenide (MoSe2), platinum chalcogenide (PtSe2), and molybdenum disulfide (MoS2). Claim 22 In claim 16, the two-dimensional material forming the two-dimensional material layer is a polycrystalline material, a method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress. Claim 23 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein the two-dimensional material forming the two-dimensional material layer is arranged in a plane of one layer through interatomic covalent bonding, has weak interatomic van der Waals bonding in a direction perpendicular to the said plane, and is composed of one or three atoms. Claim 24 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein step b) is a step of growing a two-dimensional material on the surface of the first film layer to form the two-dimensional material layer. Claim 25 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein step b) is a step in which the two-dimensional material layer is stacked in multiple layers on the first film layer group. Claim 26 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein, in step b) above, the two-dimensional material layer is stacked using any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Liquid Exfoliation, and Wet Chemical Synthesis. Claim 27 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein the two-dimensional material layer is stacked using Low Temperature Chemical Vapor Deposition, which performs chemical vapor deposition at a low temperature of less than 300°C. Claim 28 A method for forming a semiconductor three-dimensional stacked structure with relieved interlayer stress, wherein step b) is a step of forming a molybdenum diselenide layer at 200°C or lower, a step of forming a platinum chalcogenide layer at 400°C or lower, or a step of forming a molybdenum disulfide layer at 500°C or lower.

Images