Method for manufacturing an image sensor

Abstract

The present invention relates to a method for manufacturing an image sensor, wherein the method is: - A step of providing a receiver substrate (1) comprising an active layer including a base substrate (10) and a pixel (11), wherein each pixel includes a doped region (12) for collecting charges generated in the pixel, and the receiver substrate (1) does not have metal interconnects. - A step of providing a donor substrate (2) including a weakened region (200) demarcating a single-crystal semiconductor layer (201), - A step of bonding the above donor substrate (2) to the above receiver substrate (1), - A step of separating the donor substrate (2) along the weakened zone (200) to transfer the semiconductor layer (201) to the receiver substrate (1), - A step of implementing a finishing treatment for the above-described semiconductor layer (201), wherein the finishing treatment comprises (i) a step of thinning the above-described layer by chemical etching following sacrificial oxidation and (ii) a step of smoothing the above-described semiconductor layer by at least one rapid annealing.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing an image sensor. Background Technology

[0002] The manufacture of an image sensor by three-dimensional (3D) integration involves stacking various layers, particularly including photodiodes, in succession, and each of the image sensors defines a pixel of the image sensor, a component of a readout circuit for reading the pixel, and an interconnection between said component and the pixel.

[0003] For a description of an image sensor formed by 3D integration, refer to, for example, [Mansoorian 2009].

[0004] Figure 1 schematically illustrates a cross-section of an image sensor.

[0005] The above sensor continuously:

[0006] - Base substrate (10),

[0007] - An active layer comprising a plurality of pixels (11); each pixel comprises a doped region (12) suitable for collecting charges generated in each pixel; and the pixels are separated from each other by electrical insulation trenches (13), the active layer

[0008] - For example, one or more dielectric or electrical insulating layers (14) which are silicon nitride or silicon oxide,

[0009] - Includes a silicon layer (22) containing a component (25) of a pixel reading circuit.

[0010] An interconnection part (26) is connected through a layer (14) to electrically connect the component (25) and the pixel (11).

[0011] However, 3D integration methods have significant limitations. Therefore, in conventional approaches that bond and consume sacrificial substrates, the method incurs the cost of consuming these substrates. For example, in an approach involving layer transfer using the SmartCut™ method, the thermal budget of successive steps must be controlled to avoid damaging active zones or previously formed components. Generally, and according to references available in the literature, an excessively high thermal budget is prone to causing abnormal diffusion from doped regions configured to collect photogenerated charges in pixels, which can affect the performance of the sensor. Similarly, metal interconnects between sensor elements are susceptible to damage due to an excessively high thermal budget.

[0012] However, implementing steps with a low thermal budget can be disadvantageous, particularly in terms of the duration and / or cost of the method.

[0013] The object of the present invention is to design a method for manufacturing an image sensor using three-dimensional integration technology, wherein the thickness control of the added layer is compatible with FDSOI-type substrates, which can be rapidly industrialized and is cost-effective while preventing the diffusion of dopants present in the charge collection region and the doped layer of amorphous silicon.

[0014] A "semiconductor-on-insulator" (SOI) substrate is a substrate comprising a semiconductor layer, for example, made of silicon, on the substrate, wherein an electrical insulating layer is inserted between the semiconductor layer and the substrate. In an "fully depleted semiconductor-on-insulator" (FDSOI) substrate, the thickness of the semiconductor layer is sufficiently thin to allow for the complete depletion of the conduction channels of the transistors formed in the layer. Such a layer typically has a thickness of tens of nanometers.

[0015] To this end, the present invention proposes a method for manufacturing an image sensor, and the method is:

[0016] - A step of providing a receiver substrate (1) comprising a base substrate and an active layer including pixels, wherein each pixel includes a doped region for collecting charges generated in the pixel, and the receiver substrate does not have metal interconnects.

[0017] - A step of providing a donor substrate including a weakened region demarcating a single-crystal semiconductor layer,

[0018] - Step of bonding the donor substrate to the receiver substrate,

[0019] - A step of separating a donor substrate along a weakened zone to transfer a semiconductor layer to a receiver substrate,

[0020] - A step of implementing a finishing treatment for a transferred semiconductor layer, wherein the finishing treatment comprises (i) a step of thinning the transferred layer by chemical etching following sacrificial oxidation and (ii) a step of smoothing the transferred semiconductor layer by at least one rapid annealing.

[0021] In this text, "rapid annealing" refers to a heat treatment that exhibits a temperature ramp-up at a rate of more than 10°C per second, preferably about 50°C per second or more.

[0022] The fact that the receiver substrate contains only doped regions and does not contain metal interconnects allows for specific heat treatment to be performed, thereby enabling the smoothing of the transferred semiconductor layer; however, said heat treatment must have a sufficiently suitable thermal budget so as not to cause diffusion of the dopant present in the receiver substrate. Rapid annealing as implemented in the present invention satisfies these constraints.

[0023] In addition, controlled chemical etching provides thickness uniformity required for the intended application. This thickness uniformity is similar to the thickness uniformity of the FDSOI substrate, and the standard of uniformity can be expressed, on the one hand, as the variability of the thickness of the layer transferred within a single and identical substrate or wafer, which is typically 10 Å or less, and on the other hand, as the variability of the mean thickness of the layer transferred between different wafers, which is typically ±2 Å at most.

[0024] Particularly advantageously, each rapid annealing is controlled to prevent the diffusion of dopants from the doped area of ​​the pixel.

[0025] To this end, each rapid annealing can be performed at a temperature of 1100 to 1250 °C for a duration of 15 to 60 seconds.

[0026] In some embodiments, sacrificial oxidation and chemical etching are controlled to thin the transferred single-crystal semiconductor layer to a thickness of 10 to 100 nm.

[0027] Chemical etching to thin the transferred single-crystal semiconductor layer can be implemented by wet etching, plasma dry etching, ion-beam dry etching, or cluster-ion-beam dry etching.

[0028] In some embodiments, the method further includes the step of forming a component of a read circuit for reading pixels inside or above the transferred semiconductor layer after finishing the transferred single-crystal semiconductor layer.

[0029] In some embodiments, the method further includes the step of forming an interconnection between the component of the pixel readout circuit and the pixel after finishing the transferred single-crystal semiconductor layer.

[0030] In some embodiments, the method includes the step of forming a weakened layer by injecting atomic species into a donor substrate.

[0031] In some embodiments, the finishing process is performed continuously:

[0032] (i) 1st rapid annealing,

[0033] (ii) Removal of defects associated with injection by sacrificial oxidation of the transferred layer,

[0034] (iii) Second rapid annealing, and

[0035] (iv) Includes thinning of the delivered layer.

[0036] In some embodiments, the donor substrate further comprises a silicon oxide layer preferably deposited via tetraethyl orthosilicate (TEOS) on a single-crystal semiconductor layer.

[0037] The donor substrate may further comprise one or more electrical insulating or semiconductor layers (or a stack of both types of layers) on a silicon oxide layer. In the case of the semiconductor layer, it may be crystalline or amorphous, doped (n+ or p+), or undoped.

[0038] In some embodiments, a layer of silicon oxide, or a layer or stack of layers arranged on a layer of silicon oxide, is deposited on a donor substrate before injection.

[0039] In some embodiments, the receiver substrate further comprises one or more electrical insulating or semiconductor layers (or a stack of both of these types of layers) on the active layer. Preferably, at least one electrical insulating layer is a layer of silicon oxide and the semiconductor layer may be crystalline or amorphous, doped (n+ or p+) or undoped.

[0040] Particularly advantageously, each rapid annealing has a temperature rise rate of more than 10°C per second, preferably more than 50°C per second.

[0041] Preferably, the smoothing step does not include any heat treatment having a temperature rise rate of less than 10°C per second.

[0042] In some embodiments, the smoothing step is implemented individually for each structure including the semiconductor layer and the receiver substrate. Brief explanation of the drawing

[0043] Further features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings, wherein: - FIG. 1 schematically illustrates an image sensor in cross-section. - FIG. 2 schematically illustrates a receiver substrate and a donor substrate used in a method for manufacturing an image sensor according to one embodiment of the present invention in cross-section. - FIG. 3 schematically illustrates the receiver substrate and donor substrate of FIG. 2 in cross-section after the donor substrate has been separated along a weakened zone. - FIG. 4 schematically illustrates an image sensor formed from the donor and receiver substrates of FIG. 3 in cross-section after the finishing of the transferred semiconductor layer and the formation of a readout circuit and interconnects for reading pixels. - FIG. 5 is a SIMS profile of phosphorus concentration within an SOI structure comprising a phosphorus-doped layer after rapid annealing and heat treatment as implemented during the manufacture of an FDSOI substrate as implemented in the present invention. Identical reference numerals from one figure to the next indicate elements that are identical or perform the same function. To make the drawings clearer, various elements must It is not depicted on a scale. Specific details for implementing the invention

[0044] The present invention proposes manufacturing an image sensor by transferring a thin layer from a donor substrate to a receiver substrate.

[0045] The receiver substrate includes a base substrate and an active layer comprising a plurality of pixels.

[0046] The base substrate is generally, for example, a silicon semiconductor substrate. The base substrate acts as a mechanical carrier, particularly for an image sensor.

[0047] The active layer is, for example, a single-crystal semiconductor layer of silicon or silicon-germanium.

[0048] Pixels are separated from each other by electrical isolation trenches. These trenches are known as DTI, short for "deep trench isolation," or CDTI, short for "capacitor deep trench isolation."

[0049] Each pixel contains a doped area suitable for collecting the charge generated in each pixel.

[0050] Particularly advantageously, the receiver board does not include metal interconnects between the corresponding components.

[0051] The manufacture of such receiver substrates is within the capabilities of a person skilled in the art. Accordingly, a method for manufacturing receiver substrates will not be described in detail in this text.

[0052] The donor substrate includes a weakened region demarcating the single-crystal semiconductor thin layer. In some embodiments, the donor substrate may be a bulk substrate composed of a single single-crystal semiconductor material. Alternatively, the donor substrate may be a composite substrate composed of at least two layers of different materials, each comprising at least one single-crystal semiconductor layer. The single-crystal thin layer may be a layer of silicon or other semiconductor material.

[0053] A weakened region is advantageously formed by implanting atomic species, such as hydrogen and / or helium atoms, into a donor substrate. Determining the dose and energy for implantation to form a weakened region at a given depth of the donor substrate is within the ability of a person skilled in the art. During implantation, the surface of the donor substrate may be potentially protected by a dielectric layer, such as a silicon oxide (SiO2) layer. Subsequently, said layer may be removed, for example, by selective etching.

[0054] After that, the donor substrate is bonded to the receiver substrate. In some embodiments, bonding can be performed through a dielectric layer such as a silicon oxide layer.

[0055] The crack in the donor substrate starts at a site in the weakened zone and leads to the separation of the donor substrate along the weakened zone. Upon completion of this separation, the semiconductor thin layer is transferred to the receiver substrate.

[0056] This method is known as the SmartCut™ method.

[0057] The final product including the receiver substrate and the semiconductor thin layer will be referred to as a wafer in this text.

[0058] Since the transferred semiconductor thin layer exhibits a certain degree of roughness, a finishing treatment is implemented on the wafer to smooth the layer while providing the required thickness uniformity.

[0059] To avoid diffusion of dopants from the active layer, this overall finishing treatment is implemented with a moderate thermal budget lower than that typically used to manufacture FDSOI substrates. However, given that the receiver substrate does not contain metal, there is no need to use the low-temperature treatment, which has the disadvantage of being long and complex, as described in [Schwarzenbach 2019].

[0060] The target thickness of the transferred semiconductor layer is 10 nm to 100 nm with a maximum deviation of ±5 Å from the target value within each wafer manufactured using the method and between different wafers. While such a standard of uniformity is generally required for the fabrication of FDSOI substrates, it cannot be achieved for target image sensors using typical finishing treatments for FDSOI substrates with excessively high thermal budgets. Specifically, finishing treatments for FDSOI substrates typically involve a "batch annealing" method, which is a long-temperature smoothing method and is performed in a furnace that advantageously allows multiple substrates to be processed simultaneously (hence the term "batch"). Such "batch annealing" is typically implemented at a temperature of 1150 to 1200 °C for a duration of a few minutes, generally longer than 15 minutes. Furthermore, the furnace temperature ramp-up is relatively slow, at a ramp-up of only a few °C per minute, which contributes to increasing the thermal budget received by the substrate. This smoothing allows the transferred semiconductor layer to have a surface roughness level compatible with the fabrication of transistors. However, it has been proven that this "batch annealing" has the effect of degrading the uniformity of the thickness of the transferred semiconductor layer within a single and identical wafer.

[0061] Specifically, the finishing treatment implemented in the present invention comprises, on the one hand, thinning of the layer delivered by sacrificial oxidation and subsequent chemical etching, and on the other hand, smoothing by one or more rapid annealings that provide a lower thermal budget than the thermal budget of "batch annealing," said thermal budget being suitable for maintaining the integrity of the pixel.

[0062] Regarding thinning, the process first involves the oxidation of the transferred layer to form a thin oxide layer on the surface of the layer. This oxide is preferably formed by thermal oxidation of the material of the semiconductor layer, wherein the transferred semiconductor layer undergoes heat treatment in an oxidizing atmosphere containing oxygen and / or water vapor to consume the surface portion of the layer. By adjusting the conditions of this thermal oxidation (particularly its duration, the atmosphere (dry or wet), its pressure, and its temperature), the thickness of the transferred layer consumed, and thus the degree of thinning of the layer, can be controlled. The oxidation is carried out at a temperature of less than 1000 °C, preferably 950 °C or less, so as not to cause diffusion of the dopant within the wafer. The duration of the oxidation is selected according to the thickness of the oxide to be formed, which depends on the initial thickness of the transferred layer and the target thickness of the layer. This oxidation may be carried out simultaneously for one or more batches of wafers.

[0063] Next, the thickness of the transferred layer covered with an oxide layer is measured at a specific number of points distributed on the wafer surface. Thus, measurements by ellipsometric or reflectometric methods provide the thickness of the semiconductor layer.

[0064] To define the treatment to be applied to the semiconductor layer transferred to make its thickness uniform, a map of the thickness of the layer obtained by ellipsometric or reflectometric methods is used. From the thickness measured at various points on the wafer, the mean thickness of the semiconductor layer may also be determined.

[0065] This thickness map and / or these average thicknesses make it possible to determine one or more regions of the transferred layer that represent excess thickness relative to the target thickness and consequently need to undergo thinning to improve the uniformity of the thickness of the transferred semiconductor layer.

[0066] Depending on the situation, the uniformity of interest may be "intra-wafer" uniformity (i.e., across the surface of one and the same structure, said structure generally takes the shape of a circular wafer) and / or "inter-wafer" uniformity (i.e., uniformity between all structures belonging to all production batches).

[0067] In the case of wafer-in-wafer uniformity, the measured thickness is compared to the target thickness of the desired final product at each point, and said target thickness is less than or equal to the average thickness. In this case, one or more regions to be thinned are, accordingly, one or more regions where the thickness of the semiconductor layer is greater than the target thickness, and one or more excess thicknesses correspond to the difference between the measured thickness and the target thickness. Thus, this is a matter of one or more "local" excess thicknesses of the wafer.

[0068] In the case of wafer-to-wafer uniformity, the average of the semiconductor layer thicknesses measured at various measurement points is compared to the target average thickness. In this case, the wafer to be thinned is one in which the average thickness of the semiconductor layer is greater than the target average thickness, and the excess thickness corresponds to the difference between these two average thicknesses. Therefore, this is a matter of the "overall" excess thickness of the wafer here.

[0069] Of course, these uniformity rules can be combined.

[0070] To thin these regions locally within a single wafer and / or to thin the entire wafer, selective etching of the sacrificial oxide layer is first implemented. To this end, an etchant suitable for etching the sacrificial oxide without attacking the semiconductor material of the layer is used. Typically, when the sacrificial oxide layer is made of silicon oxide and the transferred layer is made of silicon, a solution of hydrofluoric acid (HF) is used as the etchant. Of course, a person skilled in the art may select any other suitable etchant depending on the respective materials of the sacrificial oxide layer and the semiconductor layer.

[0071] When the sacrificial oxide layer is removed, chemical etching of the semiconductor layer itself is achieved.

[0072] In some embodiments, the etching is wet etching, that is, etching in which the transferred semiconductor layer is exposed to an etching solution. Exposure can be achieved by immersing the wafer in the solution or by spraying the etching solution onto the wafer surface by means of a nozzle, which may allow the etching to be limited to the area that needs to be thinned relative to other areas of the wafer.

[0073] Such etching can be implemented at ambient temperatures, i.e., about 20 to 25°C, or higher temperatures, but generally at temperatures below 80°C.

[0074] In other embodiments, the etching may be plasma dry etching, ion-beam dry etching (or RIE, where RIE refers to "reactive-ion etching") or cluster-ion-beam dry etching (or GCIB etching, where GCIB refers to "gas cluster ion beam"). These steps do not involve a significant thermal budget.

[0075] The implementation parameters of these various types of etching allow the transferred semiconductor layer to be thinned in a whole and / or local manner.

[0076] A method for thinning and making uniform an FDSOI substrate, which solves the problem of reduced thickness uniformity of a transferred semiconductor layer due to smoothing by "batch annealing," is described in Patent FR 2 991 099 filed by the applicant.

[0077] With respect to smoothing, in the present invention, this is performed by one or two high-temperature RTAs (RTA refers to "rapid thermal annealing"). Each annealing is typically performed at a temperature of 1100 to 1250 °C for a duration of 15 to 60 seconds, which allows for the rearrangement of atoms on the surface of the transferred semiconductor layer to smooth it. In contrast to "batch annealing," each rapid annealing is performed with a rapid temperature ramp-up of several tens of °C per second. Furthermore, while "batch annealing" is performed simultaneously on multiple wafers, rapid annealing is performed individually on each wafer.

[0078] The thermal budget implemented in these one or more annealing steps is low enough to avoid the diffusion of dopants within the wafer.

[0079] Preferably, the method includes two rapid annealing steps to obtain an optimal surface state of the transferred layer.

[0080] Therefore, unlike known methods for manufacturing FDSOI substrates, the smoothing implemented in the present invention does not involve "batch annealing." More generally, the smoothing does not involve slow heat treatment, i.e., heat treatment having a temperature rise rate of less than 10°C per second. Thus, the integrity of the pixels is maintained during smoothing.

[0081] According to one preferred embodiment, the method comprises two steps of sacrificial oxidation, each implemented between the first rapid annealing and the second rapid annealing and after the second rapid annealing, respectively, when two rapid annealing steps are implemented. The first sacrificial oxidation advantageously enables the removal of defects linked to weakening implantation by oxidizing a surface region of the transferred layer and then removing the oxidized region, and the second sacrificial oxidation, followed by chemical etching of the transferred layer, enables the transfer layer to be uniformly thinned to a target thickness. The rapid annealing steps are preferably implemented before thinning of the transferred layer to maintain the stability of the layer. It may be devised to omit the first rapid annealing, but this would come at the cost of reduced roughness.

[0082] After finishing the transferred semiconductor layer, components of a pixel readout circuit can be manufactured within or on this layer.

[0083] The above components are also electrically connected to the pixel by an interconnect. The interconnect may be made of metal, but there is no risk of damage given that it is formed after the finishing process of the transferred semiconductor layer.

[0084] To create an image sensor, it may be useful to insert one or more additional semiconductor and / or electrical insulating layers between the semiconductor layer containing components of the readout circuit and the active layer.

[0085] These additional layers can be integrated into the image sensor in various ways.

[0086] According to one embodiment, the additional layer may be formed on the active layer of the receiver substrate before bonding the donor substrate. This layer may be formed, for example, by deposition. Regardless of which formation method is selected, it does not involve a thermal budget that facilitates the diffusion of the dopant in the active layer.

[0087] According to another embodiment, at least one of the additional layers may be formed by deposition on the active layer of the receiver substrate, and at least one of the additional layers is formed by deposition on the single-crystal semiconductor layer of the donor substrate before bonding the substrate. As mentioned above, the deposition of each additional layer on the active layer of the receiver substrate must be performed with a thermal budget low enough not to cause diffusion of the dopant.

[0088] According to another embodiment, the additional layer is formed on the donor substrate. Preferably, the layer is formed by deposition before the injection of atomic species to form the weakened zone. Thus, the thermal budget of such deposition does not pose a risk of causing premature cracking of the donor substrate along the weakened zone. If the additional layer is deposited after the formation of the weakened zone, the applied thermal budget should be limited to avoid such premature cracking.

[0089] FIG. 2 is a schematic diagram of a cross-section of a donor substrate and a receiver substrate before bonding in one embodiment of the present invention.

[0090] The receiver substrate (1) continuously comprises the following:

[0091] - Base substrate (10),

[0092] - An active layer comprising a plurality of pixels (11), wherein each pixel comprises a doped region (12) suitable for collecting charges generated in each pixel; and the pixels are separated from each other by electrical insulation trenches (13).

[0093] - First additional layer (15), e.g., semiconductor layer, and

[0094] - A second additional layer (16), e.g., an electrical insulation layer.

[0095] The donor substrate (2) includes a weakened region (200) that borders the semiconductor thin layer (201).

[0096] As mentioned above, layers (16) and potentially layers (15) can be formed on a donor substrate (2) instead of a receiver substrate (1). In this case, each of the associated layers is intended to be transferred to a receiver substrate having layers (201).

[0097] Referring to FIG. 3, after the donor substrate is bonded to the receiver substrate, the donor substrate is separated along a weakened region to transfer the semiconductor layer (201) to the receiver substrate (1).

[0098] As schematically illustrated, the surface (S) of the layer (201) after separation is rough.

[0099] Therefore, the finishing process described above is implemented.

[0100] Once the delivered single-crystal semiconductor layer is uniformly thinned to a target thickness, a component (25) of the reading circuit is formed within or on the layer (see FIG. 4). An interconnection portion (26) between the component (25) and the pixel (11) is also formed.

[0101] FIG. 5 is a SIMS (secondary ion mass spectrometry) profile of phosphorus concentration within an SOI structure, comprising, from its surface, a layer of undoped single-crystal silicon with a thickness of 42 nm, a layer of silicon oxide with a thickness of 190 nm, a phosphorus-doped silicon layer extending to a depth of 3500 nm, and a base substrate made of silicon that is intentionally undoped and followed by two rapid annealing cycles at 1200 °C for 30 seconds (curve a) as implemented in the present invention and a heat treatment ("batch annealing") at 1200 °C for 5 minutes (curve b) as implemented in the fabrication of FDSOI substrates. The horizontal axis provides the depth (nm) from the surface of the SOI structure, and the vertical axis represents the phosphorus concentration (at / cm²). 2 It provides ).

[0102] The sharp transition (practically vertical slope) between the doped layer and the base substrate visible in the curve indicates that there was virtually no dopant diffusion during rapid annealing. Conversely, the more gradual transition visible in curve b indicates dopant diffusion from the doped layer to the base substrate.

[0103] Therefore, these curves show the protective effect of one or more rapid annealings compared to conventional heat treatment of the doped region.

[0104] References

[0105] [Mansoorian 2009]: Mansoorian, B., and D. Shaver, Suntharalingam, V. et al., Lin Ping Ang. "A 4-side Tileable Back Illuminated 3D-integrated Mpixel CMOS Image Sensor". Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. 2009. 38-39, 39a.

[0106] [Schwarzenbach 2019]: W. Schwarzenbach et al., "Low Temperature SmartCut™ enables High Density 3D SoC Applications", Proc. ICICDT Conf., June 17-19, 2019

[0107] FR 2 991 099

Claims

Claim 1 A method for manufacturing an image sensor, comprising the steps of: providing a receiver substrate (1) comprising a base substrate (10), an active layer disposed on the base substrate (10) and including pixels (11), a semiconductor layer (15) disposed on the pixels (11), and an electrical insulating layer (16) disposed on the semiconductor layer (15), wherein each pixel includes a doped region (12) for collecting charges generated in the pixel, and the receiver substrate (1) has no metal interconnects; providing a donor substrate (2) comprising a weakened region (200) demarcating a single-crystal semiconductor layer (201); bonding the donor substrate (2) to the receiver substrate (1); separating the donor substrate (2) along the weakened region (200) to transfer the semiconductor layer (201) to the receiver substrate (1); and transferring the semiconductor. A method for manufacturing the image sensor comprising the step of implementing a finishing treatment for a layer (201), wherein the finishing treatment comprises (i) thinning the transferred layer by chemical etching following sacrificial oxidation and (ii) smoothing the transferred semiconductor layer by at least one rapid annealing, and wherein the method comprises the step of forming the weakened region (200) by injecting atomic species into the donor substrate (2), and wherein the finishing treatment comprises: (i) a first rapid annealing, (ii) removal of defects associated with the injection by sacrificial oxidation of the transferred layer, (iii) a second rapid annealing, and (iv) thinning of the transferred layer. Claim 2 A method in which, in claim 1, each rapid annealing is controlled to prevent the diffusion of dopants from the doped regions (12) of the pixels (11). Claim 3 A method according to claim 1 or 2, wherein each rapid annealing is performed at a temperature of 1100 to 1250 ℃ for a duration of 15 to 60 seconds. Claim 4 A method according to claim 1 or 2, wherein the sacrificial oxidation and the chemical etching are controlled to thin the transferred single-crystal semiconductor layer (201) to a thickness of 10 to 100 nm. Claim 5 A method according to claim 1 or 2, wherein the chemical etching for thinning the transferred single-crystal semiconductor layer (201) is implemented by wet etching, plasma dry etching, ion-beam dry etching, or cluster-ion-beam dry etching. Claim 6 A method according to claim 1 or 2, further comprising the step of forming components (25) of a reading circuit for reading pixels inside or above the transferred semiconductor layer (201) after the transfer of the transferred single-crystal semiconductor layer (201). Claim 7 A method according to claim 6, further comprising the step of forming interconnection portions (26) between the components (25) of a reading circuit for reading the pixels and the pixels (11) after the finishing of the transferred single-crystal semiconductor layer (201). Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 A method according to claim 1 or 2, wherein each rapid annealing has a temperature rise rate of more than 10°C per second or more than 50°C per second. Claim 16 A method according to claim 1 or 2, wherein the smoothing step does not include a heat treatment having a temperature rise rate of less than 10°C per second. Claim 17 A method according to claim 1 or 2, wherein the smoothing step is implemented individually for each structure including the semiconductor layer (201) and the receiver substrate (1).

Images