Semiconductor Package

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a base substrate of a conductive material having a first lower trench and a second lower trench on a lower surface and a first upper trench overlapping with the first lower trench on an upper surface; a first resin disposed in the first lower trench; a second resin disposed in the second lower trench; a first semiconductor chip disposed on a flat upper surface of the base substrate; and a second semiconductor chip disposed corresponding to the first upper trench.

Description

Technology Field

[0001] Embodiments of the present invention relate to a semiconductor package having a plurality of semiconductor chips mounted on a semiconductor package substrate. Background Technology

[0002] Semiconductor chips are packaged on semiconductor package substrates for use, and the semiconductor package substrates used for such packaging have microcircuit patterns and / or I / O terminals.

[0003] Semiconductor chips can be provided in various ways on semiconductor package substrates, and as the performance and / or integration of semiconductor chips, as well as the miniaturization and / or performance of electronic devices using them, progress, the complexity of semiconductor package substrates is also increasing.

[0004] Accordingly, in recent years, a method of manufacturing semiconductor package substrates by filling a conductive base substrate with an insulating material has been introduced to simplify the manufacturing process of such semiconductor package substrates. The problem to be solved

[0005] Embodiments of the present invention aim to provide a semiconductor package with a simple process and excellent reliability.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description of the present invention. means of solving the problem

[0007] One embodiment of the present invention provides a semiconductor package comprising: a base substrate of a conductive material having a first lower trench and a second lower trench on a lower surface and a first upper trench overlapping with the first lower trench on an upper surface; a first resin disposed in the first lower trench; a second resin disposed in the second lower trench; a first semiconductor chip disposed on a flat upper surface of the base substrate; and a second semiconductor chip disposed corresponding to the first upper trench.

[0008] In one embodiment, the second semiconductor chip may be disposed in direct contact with the upper surface of the first resin.

[0009] In one embodiment, an epoxy of a conductive material may be disposed between the first semiconductor chip and the upper surface of the base substrate.

[0010] In one embodiment, the width of the first lower trench corresponding to the lower surface of the base substrate may be larger than the width of the first upper trench corresponding to the upper surface of the base substrate.

[0011] In one embodiment, the thickness of the first resin may be 80 μm to 160 μm.

[0012] In one embodiment, the first resin may include an epoxy resin.

[0013] In one embodiment, the width of the first upper trench may be smaller than the width of the first lower trench.

[0014] In one embodiment, a mold resin covering the first semiconductor chip and the second semiconductor chip may be further included.

[0015] In one embodiment, the apparatus further comprises a first upper resin disposed in the first upper trench; and the second semiconductor chip may be disposed on the upper surface of the first upper resin.

[0016] In one embodiment, the thickness of the first upper resin may be 80 μm to 160 μm.

[0017] One embodiment of the present invention provides a semiconductor package comprising: a base substrate of a conductive material having a first upper trench and a second upper trench on an upper surface; a second upper resin disposed in the second upper trench; a first semiconductor chip disposed on a flat upper surface of the base substrate; and a second semiconductor chip disposed corresponding to the first upper trench.

[0018] In one embodiment, the apparatus further comprises: a first lower trench provided on the lower surface of the base substrate and overlapping with the first upper trench; and a first resin disposed in the first lower trench, wherein the upper surface of the first resin is exposed by the first upper trench, and the second semiconductor chip may be disposed on the upper surface of the first resin.

[0019] In one embodiment, the apparatus further comprises a first upper resin disposed in the first upper trench; and the second semiconductor chip may be disposed on the upper surface of the first upper resin.

[0020] In one embodiment, the apparatus further comprises a first upper resin disposed in the first upper trench; and the second semiconductor chip may be disposed on the upper surface of the first upper resin.

[0021] In one embodiment, a mold resin covering the first semiconductor chip and the second semiconductor chip may be further included. Effects of the invention

[0022] As described above, the semiconductor package according to the embodiments of the present invention includes a semiconductor chip directly disposed in a resin filled in a base substrate, thereby providing a semiconductor package with a simple process and excellent reliability.

[0023] Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0024] FIG. 1 is a schematic cross-sectional view of a semiconductor package according to one embodiment of the present invention. FIGS. 2 to 7 are cross-sectional views sequentially illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of a semiconductor package according to one embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a semiconductor package according to one embodiment of the present invention. Specific details for implementing the invention

[0025] Since the embodiments are capable of various modifications, specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the embodiments and the methods for achieving them will become clear by referring to the details described below in conjunction with the drawings. However, the embodiments are not limited to those disclosed below and can be implemented in various forms.

[0026] Hereinafter, the following embodiments will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0027] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another.

[0028] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0029] In the following examples, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0030] In the following embodiments, when a part such as a membrane, region, or component is described as being above (or on top of) or below (below) another part, this includes not only cases where it is directly above or below the other part, but also cases where another membrane, region, or component is interposed in between. The criteria for above and below are explained based on the drawings.

[0031] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the following embodiments are not necessarily limited to those illustrated.

[0032] FIG. 1 is a schematic cross-sectional view of a semiconductor package according to one embodiment of the present invention. In this embodiment, the semiconductor package may refer to a structure in which a portion of a semiconductor chip is mounted on a semiconductor package substrate.

[0033] Referring to FIG. 1, a semiconductor package (100) according to one embodiment of the present invention is provided such that trenches (111, 112, 113, 114) are formed in a conductive base substrate (110), and a resin (121, 123) is filled in at least a portion of the trenches (111, 112, 113, 114). Additionally, the semiconductor package (100) may include a first semiconductor chip (210) and a second semiconductor chip (230). The first semiconductor chip (210) may be disposed on a flat upper surface of the base substrate (110), and the second semiconductor chip (230) may be disposed corresponding to the first upper trench (113).

[0034] A semiconductor package (100) has a first resin (121) and a second resin (123) made of an insulating material filled on the lower surface (110a) of a base substrate (110) made of a conductive material.

[0035] Here, the upper surface (110b) of the base substrate (110) may refer to the side on which a semiconductor chip is provided when a semiconductor package is manufactured using the base substrate (110), and the lower surface (110a) may refer to the side opposite to the upper surface (110b).

[0036] The base substrate (110) forms part of the semiconductor package (100), and after processing, it can form circuit patterns such as a mounting portion where a semiconductor chip is mounted, a wiring pattern, and a terminal portion connected to the outside.

[0037] The base substrate (110) is made of an electrically conductive material and may have a flat shape. The base substrate (110) may be made of a single material such as Cu or Fe, or may be made of various materials such as copper alloys such as Cu-Sn, Cu-Zr, Cu-Fe, and Cu-Zn, and iron alloys such as Fe-Ni and Fe-Ni-Co. Additionally, commercial lead frame materials may be applied as the material of the base substrate (110).

[0038] A first lower trench (111) and a second lower trench (112) may be provided on the lower surface (110a) of the base substrate (110), and a first upper trench (113) and a second upper trench (114) may be provided on the upper surface (110b) of the base substrate (110). The portion of the base substrate (110) that is exposed and not covered by the first resin (121) and the second resin (123) and where the trenches (111-114) are not formed may function as a terminal for electrical connection with a semiconductor chip or an external circuit board.

[0039] The first lower trench (111) and the second lower trench (112) may refer to grooves formed from the lower surface (110a) of the base substrate (110) toward the upper surface (110b). Since the first lower trench (111) and the second lower trench (112) do not penetrate the base substrate (110), the depth of the first lower trench (111) and the second lower trench (112) may be smaller than the thickness of the base substrate (110). In one embodiment, the thickness of the base substrate (110) may be about 150 to 200 μm, and the depth of the first lower trench (111) and the second lower trench (112) may be about 80 to 160 μm.

[0040] The first resin (121) can be placed in the first lower trench (111). That is, the first resin (121) can fill the interior of the first lower trench (111). The first resin (121) forms a semiconductor package substrate together with the base substrate (110). The first resin (121) may be a component for mounting the second semiconductor chip (230). The thickness (Tb) of the first resin (121) may be set so as to withstand pressure during the molding process covering the mold resin (150). Since unevenness may occur between the upper and lower surfaces during the molding process if the thickness (Tb) of the first resin (121) is less than 80 μm or greater than 160 μm, the thickness (Tb) of the first resin (121) may be approximately 80 to 160 μm.

[0041] The second resin (123) can be placed in the second lower trench (112). That is, the second resin (123) can fill the interior of the second lower trench (112). The second resin (123) forms a semiconductor package substrate together with the base substrate (110). The second resin (123) protects the base substrate (110) and can serve to maintain the strength of the base substrate (110).

[0042] The first resin (121) and the second resin (123) may be thermoplastic resins or thermosetting resins. In some embodiments, the first resin (121) and the second resin (123) may contain 80 to 90 percent or more of silica to minimize thermal expansion. The filling of the first resin (121) and the second resin (123) may be done using a liquid resin material or using a solid tape containing resin components.

[0043] In some embodiments, the first resin (121) and the second resin (123) may include an epoxy resin. Accordingly, the adhesion to the second semiconductor chip (230) disposed on the upper surface of the first resin (121) may be improved.

[0044] The first upper trench (113) and the second upper trench (114) may refer to grooves formed from the upper surface (110b) of the base substrate (110) toward the lower surface (110a). The first upper trench (113) overlaps with the first lower trench (111) and may expose the upper surface of the first resin (121).

[0045] The widths (Wt, Wb) of the first upper trench (113) and the first lower trench (111) can be set so that the upper surface of the first resin (121) is provided flat and can withstand pressure during the molding process covering the mold resin (150).

[0046] In some embodiments, the width (Wt) of the first upper trench (113) and the width (Wb) of the first lower trench (111) are provided to be larger than the width of the second semiconductor chip (230), but the width (Wt) of the first upper trench (113) may be provided to be smaller than the width (Wb) of the first lower trench (111). In this case, the width (Wt) of the first upper trench (113) is based on the upper surface (110b) of the base substrate (110), and the width (Wb) of the first lower trench (111) is based on the lower surface (110a) of the base substrate (110).

[0047] If the width (Wt) of the first upper trench (113) is provided small so that the pattern on the upper surface of the conductive base substrate (110) is formed thinly, defects such as cracks may occur due to pressure during the molding process. In this embodiment, the width (Wt) of the first upper trench (113) is provided smaller than the width (Wb) of the first lower trench (111), thereby securing the width of the circuit pattern on the upper surface (110a) of the base substrate (110), so that defects caused by pressure during the molding process can be minimized.

[0048] The second upper trench (114) overlaps with the second lower trench (112) and can expose the upper surface of the second resin (123). The second upper trench (114) can separate the mounting portion and the lead portion where the first semiconductor chip (210) is mounted. That is, the second upper trench (114) is placed between the circuit patterns and can serve to electrically insulate the circuit patterns from each other.

[0049] The first semiconductor chip (210) can be placed on the flat upper surface (110b) of the base substrate (110). At this time, the portion where the first semiconductor chip (210) is mounted can be called a die pad. The first semiconductor chip (210) can be attached by epoxy (211) of a conductive material. That is, epoxy (211) of a conductive material can be provided between the first semiconductor chip (210) and the upper surface (110b) of the base substrate (110). The first semiconductor chip (210) can be electrically connected to the base substrate (110) in a flip-chip form. Alternatively, the first semiconductor chip (210) may be connected to the base substrate (110) by wire bonding.

[0050] The second semiconductor chip (230) may be positioned corresponding to the first upper trench (113). The second semiconductor chip (230) may be positioned inside the first upper trench (113) and may be positioned on the upper surface of the first resin (121). In some embodiments, the second semiconductor chip (230) may be provided in direct contact with the first resin (121). Alternatively, the second semiconductor chip (230) may be attached to the upper surface of the first resin (121) by a non-conductive epoxy.

[0051] The second semiconductor chip (230) is placed inside the first upper trench (113), so that the position of the second semiconductor chip (230) up to the lower surface (110a) of the base substrate (110) can be placed closer than that of the first semiconductor chip (210). That is, the first semiconductor chip (210) and the second semiconductor chip (230) can be placed at different heights from the lower surface (110a).

[0052] The second semiconductor chip (230) may be a semiconductor chip that is placed insulated from the base substrate (110). In order to insulate the second semiconductor chip (230) from the base substrate (110), there may be a method of forming a separate insulating film on the flat upper surface of the base substrate (110) and then mounting it. However, since a complex process must be undergone to form a separate insulating film, the process time and cost may increase. In addition, if bubbles or the like occur in the insulating film, insulation failure may occur. In the present invention, the second semiconductor chip (230) is placed directly on the first resin (121), so insulation failure does not occur, and the process is simple and process costs can be reduced.

[0053] A mold resin (150) may be provided on the upper surface of the base substrate (110) to cover the first semiconductor chip (210) and the second semiconductor chip (230). The mold resin (150) is intended to cover and protect the first semiconductor chip (210) and the second semiconductor chip (230), and may be provided by including an epoxy molding compound containing an epoxy material. According to the present embodiment, the mold resin (150) includes an epoxy material, but the present invention is not limited thereto. That is, there are no particular limitations on the material of the mold resin (150) according to the present invention. That is, the material of the mold resin (150) according to the present invention may be made of a material other than epoxy, provided that it has non-conductive properties and can protect the semiconductor chip, etc.

[0054] FIGS. 2 to 6 are schematic cross-sectional views sequentially illustrating a process for manufacturing a semiconductor package (100) according to one embodiment of the present invention.

[0055] First, as illustrated in FIG. 2, a base substrate (110) is prepared. The base substrate (110) is provided with an electrically conductive material. The base substrate (110) may include Cu, Cu alloys such as Cu-Sn, Cu-Zr, Cu-Fe, Cu-Zn, etc., Fe, Fe alloys such as Fe-Ni, Fe-Ni-Co, etc. The base substrate (110) has an upper surface (110b) on which a semiconductor chip is mounted and a lower surface (110a) on which the opposite surface is opposite. In some embodiments, the thickness of the base substrate (110) may be 150 μm to 200 μm.

[0056] Next, the lower surface (110a) of the base substrate (110) is processed to form a first lower trench (111) and a second lower trench (112) as shown in FIG. 3. Here, the term "trech" means that it does not completely penetrate the base substrate (110).

[0057] The method of processing the lower surface (110a) of the base substrate (110) may use an etching method. In one embodiment, wet etching may be applied as the etching method. As a specific example of the etching method, a dry film resist made of a photosensitive material is placed on the lower surface (110a) of the base substrate (110), and the dry film resist is exposed and developed to form a resist pattern with the dry film resist. Then, the base substrate (110) may be etched using a spray method with an etching solution such as copper chloride or iron chloride to form a first lower trench (111) and a second lower trench (112).

[0058] The depth of the first lower trench (111) and the second lower trench (112) may be approximately 50% to 80% of the thickness of the base substrate (110). In some embodiments, the depth of the first lower trench (111) and the second lower trench (112) may be formed to be approximately 80 μm to 160 μm. The depth of the first lower trench (111) and the second lower trench (112) may be adjusted in consideration of the ease of handling of the semiconductor package substrate in subsequent processes and process conditions for patterning the upper surface (110b).

[0059] Next, as shown in FIG. 4, a resin is applied to the lower surface (110a) of the base substrate (110) so that the first resin (121) is placed in the first lower trench (111) and the second resin (123) is placed in the second lower trench (112).

[0060] It is sufficient that the first resin (121) and the second resin (123) are made of an insulating material that is not electrically conductive. For example, the first resin (121) and the second resin (123) may be thermosetting resins that are polymerized and hardened by heat treatment. The first resin (121) and the second resin (123) may be liquid resins. Alternatively, the first resin (121) and the second resin (123) may be formed using a solid tape containing resin components. The first resin (121) and the second resin (123) may include epoxy resin. Accordingly, the adhesion to the second semiconductor chip (230) placed on the upper surface of the first resin (121) may be improved.

[0061] In one embodiment, the first resin (121) and the second resin (123) can be cured through a curing process after application. The curing process can be performed using an oven or an infrared heater.

[0062] The first resin (121) and the second resin (123) may be formed such that there is a portion covering a part of the lower surface as well as a portion located in the lower trench (111, 112). In that case, the lower surface (110a) of the base substrate (110) can be exposed through a laser process, a brushing process, a polishing process, an etching process, etc., as shown in FIG. 4. Accordingly, the first resin (121) may be located only inside the first lower trench (111), and the second resin (123) may be located only inside the second lower trench (112).

[0063] Before filling the first resin (121) and the second resin (123) into the first lower trench (111) and the second lower trench (112), a roughing process may be performed to roughen the inner surface of the first lower trench (111) and the second lower trench (112). Through this, the bonding strength between the base substrate (110) and the resins (121, 123) can be increased. Plasma treatment, ultraviolet treatment, or a sulfuric acid-based solution may be used to roughen the inner surface of the first lower trench (111) and the second lower trench (112) of the base substrate (110), and in this case, the roughness of the inner surface of the first lower trench (111) and the second lower trench (112) of the base substrate (110) may be 150 nm or more (rms).

[0064] Next, as shown in FIG. 5, the upper surface (110b) of the base substrate (110) is processed to form the first upper trench (113) and the second upper trench (114).

[0065] The method of processing the upper surface (110b) of the base substrate (110) may use an etching method. In one embodiment, wet etching may be applied as the etching method. As a specific example of the etching method, a dry film resist made of a photosensitive material is placed on the upper surface (110b) of the base substrate (110), and the dry film resist is exposed and developed to form a resist pattern with the dry film resist. Then, the first upper trench (113) and the second upper trench (114) can be formed by etching the base substrate (110) using a spray method with an etching solution such as copper chloride or iron chloride.

[0066] The first upper trench (113) is formed to overlap with the first lower trench (111), and the second upper trench (114) can be formed to overlap with the second lower trench (112).

[0067] The first upper trench (113) can be formed so that the first resin (121) is exposed to the upper surface of the base substrate (110). The second upper trench (114) can be formed so that the second resin (123) is exposed to the upper surface of the base substrate (110). Accordingly, circuit patterns that are insulated from each other can be formed on the upper surface of the base substrate (110).

[0068] Since the second semiconductor chip (230) is placed in the first upper trench (113), the width (Wt) of the first upper trench (113) may be larger than the width of the second upper trench (114). The width (Wt) of the first upper trench (113) is larger than the width of the second semiconductor chip (230) and may be provided in a size such that the upper surface of the first resin (121) can be provided flat. Meanwhile, the width (Wt) of the first upper trench (113) may be smaller than the width (Wb) of the first lower trench (111). This may be to minimize defects during the subsequent molding process.

[0069] Next, referring to FIG. 6, a first semiconductor chip (210) is placed on the flat upper surface (110b) of the base substrate (110), and a second semiconductor chip (230) is placed on the first resin (121) exposed by the first upper trench (113).

[0070] In the area where the first semiconductor chip (210) is placed, an epoxy (211) of a conductive material may be placed. Various variations are possible, such as the epoxy (211) of the conductive material being placed first on the flat upper surface (110b) of the base substrate (110), or being placed on the lower surface of the first semiconductor chip (210) and then attached to the base substrate (110). The epoxy (211) of the conductive material may also be omitted.

[0071] Next, as illustrated in FIG. 7, a mold resin (150) is placed on the upper surface of the base substrate (110) to cover the first semiconductor chip (210) and the second semiconductor chip (230), thereby encapsulating the upper surface of the base substrate (110). The mold resin (150) may be provided with a resin such as an epoxy mold compound. External pressure may be applied when forming the mold resin (150). In this embodiment, the size of the first upper trench (113) and the thickness of the first resin are set so that defects do not occur in the semiconductor package (100) due to such pressure.

[0072] FIG. 8 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention. In FIG. 8, the same reference numerals as in FIG. 1 indicate the same components, so a redundant description thereof is omitted.

[0073] Referring to FIG. 8, a semiconductor package (200) according to one embodiment of the present invention is provided such that trenches (111, 112, 113, 114) are formed in a conductive base substrate (110), and a resin (121, 123) is filled in at least a portion of the trenches (111, 112, 113, 114). Additionally, the semiconductor package (200) may include a first semiconductor chip (210) and a second semiconductor chip (230). The first semiconductor chip (210) may be disposed on a flat upper surface of the base substrate (110), and the second semiconductor chip (230) may be disposed corresponding to the first upper trench (113).

[0074] In the present embodiment, the first upper trench (113) may be filled with and arranged a first upper resin (131), and the second upper trench (114) may be filled with and arranged a second upper resin (133). Accordingly, the second semiconductor chip (230) may be placed on the upper surface of the first upper resin (131). The second semiconductor chip (230) may be placed in direct contact with the first upper resin (131). Alternatively, the second semiconductor chip (230) may be attached to the upper surface of the first upper resin (131) by means of a non-conductive epoxy.

[0075] The first upper resin (131) and the second upper resin (133) may be formed from the same material as the first resin (121). For example, the first upper resin (131) and the second upper resin (133) may be made of a thermoplastic resin or a thermosetting resin. In some embodiments, the first upper resin (131) and the second upper resin (133) may contain 80 to 90 percent or more of silica to minimize thermal expansion. The filling of the first upper resin (131) and the second upper resin (133) may be performed using a liquid resin material or using a solid tape containing a resin component. The first upper resin (131) and the second upper resin (133) may include an epoxy resin. Accordingly, the adhesion to the second semiconductor chip (230) placed on the upper surface of the first upper resin (131) may be improved.

[0076] When the first upper resin (131) and the first resin (121) are made of the same type of resin, the resins placed on both sides of the base substrate (110) are made of the same type, so there is no difference in the coefficient of thermal expansion between both sides of the semiconductor package (100), thus preventing bending of the semiconductor package (100) more effectively.

[0077] FIG. 9 is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention. In FIG. 9, the same reference numerals as in FIG. 1 indicate the same components, so a redundant description thereof is omitted.

[0078] Referring to FIG. 9, a semiconductor package (300) according to one embodiment of the present invention has trenches (112, 113, 114) formed in a conductive base substrate (110), and a resin (123, 131, 133) filled in at least a portion of the trenches (112, 113, 114), and a first semiconductor chip (210) and a second semiconductor chip (230) are mounted on the upper surface of the base substrate (110). The first semiconductor chip (210) is disposed on the flat upper surface of the base substrate (110), and the second semiconductor chip (230) may be disposed corresponding to the first upper trench (113).

[0079] In this embodiment, the semiconductor package (300) may not be provided with a first lower trench (111, see FIG. 1) and a first resin (121) that overlap with the first upper trench (113).

[0080] In the present embodiment, the first upper trench (113) may be filled with and arranged a first upper resin (131), and the second upper trench (114) may be filled with and arranged a second upper resin (133). Accordingly, the second semiconductor chip (230) may be placed on the upper surface of the first upper resin (131). The second semiconductor chip (230) may be placed in direct contact with the first upper resin (131). Alternatively, the second semiconductor chip (230) may be attached to the upper surface of the first upper resin (131) by means of a non-conductive epoxy.

[0081] The first upper resin (131) and the second upper resin (133) may be formed from the same material as the second resin (123). For example, the first upper resin (131) and the second upper resin (133) may be thermoplastic resins or thermosetting resins. In some embodiments, the first upper resin (131) and the second upper resin (133) may contain 80 to 90 percent or more of silica to minimize thermal expansion. The filling of the first upper resin (131) and the second upper resin (133) may be performed using a liquid resin material or using a solid tape containing resin components. The first upper resin (131) and the second upper resin (133) may include epoxy resin. Accordingly, the adhesion to the second semiconductor chip (230) placed on the upper surface of the first upper resin (131) may be improved.

[0082] The thickness (Tt) of the first upper resin (131) can be set to withstand pressure during the molding process covering the mold resin (150). Since unevenness may occur during the molding process if the thickness (Tb) of the first upper resin (131) is less than 80 μm or greater than 160 μm, the thickness (Tb) of the first upper resin (131) can be provided to be approximately 80 to 160 μm.

[0083] In this way, in embodiments of the present invention, the second semiconductor chip (230) is placed on the upper surface of the first resin (121) or the first upper resin (131), thereby minimizing the risk of insulation failure and reducing the time and cost of the process.

[0084] Some aspects of the present invention have been described with reference to embodiments illustrated in the accompanying drawings, but this is merely illustrative and will be understood by those skilled in the art that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true scope of protection of the present invention should be determined only by the appended claims. Explanation of the symbols

[0085] 100, 200, 300: Semiconductor package 110: Base board 111, 112: 1st and 2nd lower trenches 113, 114: 1st to 2nd upper trenches 121: 1st Suji 123: 2nd Suji 131: 1st upper resin 133: Second upper resin 210: The first semiconductor chip 230: Second semiconductor chip

Claims

Claim 1 A semiconductor package comprising: a base substrate of a conductive material having a first lower trench and a second lower trench on a lower surface and a first upper trench overlapping with the first lower trench on an upper surface; a first resin disposed in the first lower trench; a second resin disposed in the second lower trench; a first semiconductor chip disposed on a flat upper surface of the base substrate; and a second semiconductor chip disposed corresponding to the first upper trench; wherein the area of ​​the upper surface of the first resin exposed by the first upper trench is larger than the area of ​​the lower surface of the second semiconductor chip. Claim 2 In claim 1, the second semiconductor chip is disposed in direct contact with the upper surface of the first resin, forming a semiconductor package. Claim 3 A semiconductor package according to claim 1, wherein an epoxy of a conductive material is disposed between the first semiconductor chip and the upper surface of the base substrate. Claim 4 A semiconductor package according to claim 1, wherein the width of the first lower trench corresponding to the lower surface of the base substrate is greater than the width of the first upper trench corresponding to the upper surface of the base substrate. Claim 5 A semiconductor package according to claim 1, wherein the thickness of the first resin is 80 μm to 160 μm. Claim 6 A semiconductor package according to claim 1, wherein the first resin comprises an epoxy resin. Claim 7 A semiconductor package according to claim 1, wherein the width of the first upper trench is smaller than the width of the first lower trench. Claim 8 A semiconductor package according to claim 1, further comprising a mold resin covering the first semiconductor chip and the second semiconductor chip. Claim 9 A semiconductor package according to claim 1, further comprising a first upper resin disposed in the first upper trench, wherein the second semiconductor chip is disposed on the upper surface of the first upper resin. Claim 10 A semiconductor package according to claim 9, wherein the thickness of the first upper resin is 80 μm to 120 μm. Claim 11 A semiconductor package comprising: a base substrate of a conductive material having a first upper trench and a second upper trench on its upper surface; a first upper resin disposed in the first upper trench; a second upper resin disposed in the second upper trench; a first semiconductor chip disposed on a flat upper surface of the base substrate; and a second semiconductor chip disposed corresponding to the first upper resin; wherein the area of ​​the upper surface of the first upper resin is larger than the area of ​​the lower surface of the second semiconductor chip. Claim 12 A semiconductor package according to claim 11, further comprising: a first lower trench provided on the lower surface of the base substrate and overlapping with the first upper trench; and a first resin disposed in the first lower trench. Claim 13 delete Claim 14 delete Claim 15 A semiconductor package further comprising, in claim 11, a mold resin covering the first semiconductor chip and the second semiconductor chip.

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