Semiconductor device capable of performing write training without read training, and memory system including the same

Abstract

An input / output interface is disclosed. The input / output interface includes data input / output pins comprising a first data input / output pin and a plurality of second data input / output pins, and a write clock signal pin for receiving a write clock signal from a memory controller. The first data input / output pin receives light training data for light training from the memory controller, and the plurality of second data input / output pins feed back result values ​​of the light training performed using the write clock signal and the light training data to the memory controller. The input / output interface may be used in a DRAM or an LPDDR SRAM.

Description

Technology Field

[0001] An embodiment according to the concept of the present invention relates to a semiconductor device for performing light training, and in particular, to a semiconductor device capable of performing light training without first performing lead training, and a memory system including the same. Background Technology

[0002] In the case of mobile DRAM (mobile Dynamic Random-Access Memory (DRAM)) after LPDDR4 (Low-Power Double Data Rate 4), or DRAM used in PCs or servers after DDR5, instead of forming a circuit within individual data pads to compensate for data delay caused by a write clock tree (e.g., write clock-to-data offset (tWCK2DQI)), the host outputting the data delays the data by a delay equal to the delay and transmits it to the DRAM.

[0003] Since the delay for each semiconductor die may differ due to process variation of the DRAM or supply voltage variation of the system including the DRAM, light training to measure the delay is performed individually.

[0004] However, in order to proceed with write training for the DRAM, a read operation is required to verify whether data has been properly written to the DRAM in advance. To perform write training for the DRAM, read training must be performed first. In other words, write training for the DRAM is performed after read training for the DRAM has been performed first.

[0005] In order to perform write training on the DRAM, read training on the DRAM must be performed first; however, to perform the read training accurately, various data patterns must be written to the DRAM in advance. The problem to be solved

[0006] The technical problem to be achieved by the present invention is to provide a semiconductor device capable of performing light training without lead training and a memory system including the same, by asynchronously feeding back the result values ​​of the light training to a memory controller so as to perform the light training without a read operation. means of solving the problem

[0007] An input / output interface according to an embodiment of the present invention includes data input / output pins comprising a first data input / output pin and a plurality of second data input / output pins, and a light clock signal pin that receives a light clock signal from a memory controller, wherein the first data input / output pin receives light training data for light training from the memory controller, and the plurality of second data input / output pins feed back result values ​​of the light training performed using the light clock signal and the light training data to the memory controller.

[0008] The above input / output interface further includes a sampling circuit that generates sampling values ​​by sampling using sampling light clock signals corresponding to the last m toggling edges of the light clock signal that toggles the light training pattern included in the light training data n times, and generates result values ​​of the light training using the sampling values.

[0009] The above sampling circuit feeds back the result values ​​of the light training to the memory controller through the plurality of second data input / output pins while the light clock signal is not toggling.

[0010] A memory device according to an embodiment of the present invention includes a first data input / output pin for receiving light training data for light training, a second data input / output pin, a third data input / output pin, a light clock signal pin for receiving a light clock signal, and an input / output interface for transmitting each of the result values ​​of the light training performed using the light clock signal and the light training data to the second data input / output pin and the third data input / output pin, respectively.

[0011] A memory system according to an embodiment of the present invention comprises a memory device and a memory controller that transmits a light clock signal and light training data for light training to the memory device. The memory device comprises a first data input / output pin for receiving the light training data, a second data input / output pin, a third data input / output pin, a light clock signal pin for receiving the light clock signal, and an input / output interface that feeds back result values ​​of the light training performed using the light clock signal and the light training data to the memory controller through the second data input / output pin and the third data input / output pin.

[0012] The above input / output interface generates sampling values ​​by sampling the light training data using sampling light clock signals associated with the light clock signal, generates a first detection signal indicating whether the light training data was received earlier than the scheduled time and a second detection signal indicating whether the light training data was received at the scheduled time using the sampling values, feeds back the logical OR result of the first detection signal and the second detection signal to the memory controller through the second data input / output pin, and feeds back the second detection signal to the memory controller through the third data input / output pin. Effects of the invention

[0013] A semiconductor device according to an embodiment of the present invention can perform light training without read training and asynchronously feed back the result values ​​of the light training to a memory controller, thereby having the effect of rapidly performing the light training without read operation. Brief explanation of the drawing

[0014] Detailed descriptions of each drawing are provided to help to more fully understand the drawings cited in the detailed description of the present invention. FIG. 1 is a block diagram of a memory system including a memory device and a memory controller according to an embodiment of the present invention. Figure 2 is a block diagram of a memory system including a detailed circuit of the input / output interface shown in Figure 1. Figure 3 is a circuit diagram of the frequency divider shown in Figure 2. FIG. 4a is an example of a circuit diagram of the first data input / output circuit shown in FIG. 2 used for light training. FIG. 4b is an example of a circuit diagram of the second data input / output circuit shown in FIG. 2 used for light training. FIG. 4c is an example of a circuit diagram of the fifth data input / output circuit shown in FIG. 2 used for light training. Figure 5 is a circuit diagram of the fifth phase detector shown in Figure 3. FIG. 6 is a timing diagram for explaining a first case of light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c. FIG. 7 is a timing diagram for explaining a second case of light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c. FIG. 8 is a timing diagram for explaining a third case of light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c. FIG. 9 is a timing diagram of data according to light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c. FIG. 10a is another embodiment of the circuit diagram of the first data input / output circuit shown in FIG. 2 used for light training. FIG. 10b is another embodiment of the circuit diagram of the second data input / output circuit shown in FIG. 2 used for light training. FIG. 10c is another embodiment of the circuit diagram of the fifth data input / output circuit shown in FIG. 2 used for light training. FIG. 11 is a circuit diagram of the fifth phase detector shown in FIG. 10c. FIG. 12 is an example of a data multiplexer illustrated in FIG. 4a to 4c, or FIG. 10a to 10c. FIG. 13 is a block diagram of a memory system including a plurality of memory devices and a memory controller according to an embodiment of the present invention. Specific details for implementing the invention

[0015] FIG. 1 is a block diagram of a memory system including a memory device and a memory controller according to an embodiment of the present invention, and FIG. 2 is a block diagram of a memory system including a detailed circuit of an input / output interface shown in FIG. 1.

[0016] The memory system (100) includes a memory device (10) and a memory controller (also called a host, 400).

[0017] The memory system (100) may be a mobile device, a PC (personal computer), a server computer, or a data storage device. The mobile device may be a smartphone, a PDA (Personal Digital Assistant), a laptop computer also called a notebook computer, an Internet of Things (IoT) device, a wearable device, or a drone, etc.

[0018] The memory system (100) may be a system on chip (SoC). The memory system (100) may be an in-car entertainment (ICE) system, also known as an in-vehicle infotainment (IVI) system.

[0019] The memory device (10) may be a semiconductor die, a die, or an integrated circuit (IC). The memory device (10) may be a Dynamic Random-Access Memory (DRAM) or a Synchronous Dynamic Random-Access Memory (SDRAM) according to JEDEC standards, and the memory device (10) may have a structure applicable to LPDDR6. The semiconductor package or memory module may include at least one DRAM (10).

[0020] A memory device (10) according to an embodiment of the present invention has a structure that performs light training on one of a plurality of data input / output pins (201_1 to 201_x, where x is a natural number greater than or equal to 2) included in an input / output interface (200), and asynchronously feeds back (or outputs) the result values ​​of the light training to a memory controller (400) through at least two data input / output pins excluding one of the data input / output pins among the plurality of data input / output pins (201_1 to 201_x).

[0021] At this time, the light training data for the corresponding data input / output pin is not written to the memory cell array (20) of the memory device (10). Therefore, the memory device (10) does not require a read operation for the light training data.

[0022] In this specification, a data input / output pin refers to a pin used for inputting and outputting data in a DDR circuit (also referred to as a 'pad').

[0023] The memory device (10) includes a memory cell array (20), a control logic circuit (30), and an input / output interface (200) which will be described in detail with reference to FIG. 2.

[0024] A memory cell array (20) includes memory cells (e.g., DRAM cells) arranged in a matrix form. A control logic circuit (30) capable of interpreting (or decoding) commands (CA) or addresses (CA) output from an input / output interface (200) writes write data (DQ[x:1]) transmitted from a memory controller (400) to the memory cell array (20) during a write operation, reads data (DQ[x:1]) from the memory cell array (20) during a read operation, and transmits the read data (DQ[x:1]) to the memory controller (400).

[0025] The input / output interface (200) exchanges input / output data (DQ[x:1]) with the memory controller (400) via a bidirectional data bus (104), receives a write clock signal (WCK) output from the memory controller (400) via a write clock signal bus (103), receives a clock signal (CK) output from the memory controller (400) via a clock signal bus (102), and receives commands (CA) or addresses (CA) output from the memory controller (400) via a command / address bus (101).

[0026] According to an embodiment, the light clock signal (WCK) of FIG. 1 may mean complementary light clock signals, and the clock signal (CK) may mean complementary clock signals.

[0027] Referring to FIG. 2, the input / output interface (200) includes a plurality of data input / output pins (201_1 to 201_x), a write clock signal pin (203), a plurality of data input / output circuits (210_1 to 210_x), a write clock signal processing circuit (250), and a plurality of OR gates (OR1 to ORy, where y is a natural number greater than or equal to 2).

[0028] As illustrated in FIGS. 4a, 4b, and 4c, the structure of each of the data input / output circuits (also referred to as 'data input / output modules', 210_1 to 210_x) is identical to one another. Also, as illustrated in FIGS. 10a, 10b, and 10c, the structure of each of the data input / output circuits (210_1 to 210_x) is identical to one another.

[0029] Each data input / output circuit (210_1 to 210_x) illustrated in FIGS. 2, FIGS. 4a, FIGS. 4b, and FIGS. 4c includes each phase detector (220_1 to 220_x). Each data input / output circuit (210_1 to 210_x) illustrated in FIGS. 2, FIGS. 10a, FIGS. 10b, and FIGS. 10c includes each phase detector (220_1B to 220_xB).

[0030] Among the phase detectors (220_1~220_x or 220_1B~220_xB), only the phase detector that receives the light training data (DQ[C]=DQ[5]=TP) transmitted from the memory controller (400) generates the first detection signal (EARLY) and the second detection signal (JUST).

[0031] Each OR gate (OR1~ORy) performs a logical OR operation on the first detection signal (EARLY) and the second detection signal (JUST) output from the phase detector that received the light training data (DQ[C]=DQ[5]=TP), and transmits the result of the logical OR operation to the odd-numbered data input / output circuits (210_1, 210_3, 210_5,..., 210_(x-1)).

[0032] The second detection signal (JUST) output from the phase detector that received the light training data (DQ[C]=DQ[5]=TP) is transmitted to the even-numbered data input / output circuits (210_2, 210_4, 210_6, ..., 210_x).

[0033] For example, when x is 12 and y is 6, the output signal of the first OR gate (OR1) is transmitted to the first data input / output circuit (210_1), the output signal of the second OR gate is transmitted to the third data input / output circuit, the output signal of the third OR gate (OR3) is transmitted to the fifth data input / output circuit (210_5), and the output signal of the sixth OR gate (OR6) is transmitted to the eleventh data input / output circuit (210_11).

[0034] The light clock signal processing circuit (250) includes a buffer (251) that buffers a light clock signal (WCK) received through a light clock signal pin (203) and a frequency divider (260).

[0035] Referring to FIGS. 2 and 3, the frequency divider (260) divides a light clock signal (WCK) having a first frequency (f1) according to a frequency division ratio, generates sampling light clock signals (WCK0, WCK90, WCK180, and WCK270) having different phases and each having a second frequency (f2) divided according to the frequency division ratio, and outputs the sampling light clock signals (WCK0, WCK90, WCK180, and WCK270) to each data input / output circuit (210_1 to 210_x).

[0036] The phase difference between the sampling light clock signals (WCK0 and WCK90, WCK90 and WCK180, WCK180 and WCK270, and WCK270 and WCK0) is 90 degrees, the phase difference between the sampling light clock signals (WCK0 and WCK180, and WCK90 and WCK270) is 180 degrees, and the phase difference between the sampling light clock signals (WCK0 and WCK270) is 270 degrees. For example, when the first frequency (f1) is 4.8 GHz and the frequency division ratio is 2, the second frequency (f2) is 2.4 GHz.

[0037] The memory controller (400) includes each data input / output pin (201_1 to 201_x) paired with each data input / output pin (401_1 to 401_x, collectively referred to as '401'), a light clock signal pin (403) paired with the light clock signal pin (203), a switch circuit (405), a delay controller (410), a light training data generator (420), a light clock signal generator (430), a clock signal generator (440), and a control logic circuit (450).

[0038] The switch circuit (405) connects the input terminals of the delay controller (410) and the output terminals of the light training data generator (420) to the data input / output pins related to light training among the data input / output pins (401_1~401_x) in response to the switch control signal (SCTL) output from the control logic circuit (450).

[0039] For example, when performing light training using three data input / output pins (401_1, 401_2, and 401_5), the switch circuit (405) may connect the input terminals of the delay controller (410) to the data input / output pins (401_1 and 401_2) to receive two result values ​​(DQ[A] and DQ[B]) for light training in response to a switch control signal (SCTL) output from the control logic circuit (450), and connect the output terminal of the light training data generator (420) that outputs light training data (DQ[C]) to the data input / output pin (401_5).

[0040] According to another example, when light training is to be performed using three data input / output pins (401_1, 401_5, and 401_6), the switch circuit (405) may connect the input terminals of the delay controller (410) to the data input / output pins (401_5 and 401_6) to receive two result values ​​(DQ[A] and DQ[B]) for light training in response to a switch control signal (SCTL) output from the control logic circuit (450), and connect the output terminal of the light training data generator (420) that outputs light training data (DQ[C]) to the data input / output pin (401_1).

[0041] The light training data generator (420) transmits light training data (DQ[C]) through the switch circuit (405) only to the data input / output pin set as the light training target among the plurality of data input / output pins (201_1~201_x), and the delay controller (410) receives two result values ​​(DQ[A] and DQ[B]) for the light training through the switch circuit (405) only to the two data input / output pins excluding the data input / output pin among the plurality of data input / output pins (201_1~201_x).

[0042] Figure 3 is a circuit diagram of the frequency divider shown in Figure 2.

[0043] The frequency divider (260) includes a first transmission gate (TG1), a first latch (LT1), a second transmission gate (TG2), a second latch (LT2), an inverter (261), a first phase sampling light clock signal generator (263), a second phase sampling light clock signal generator (265), a third phase sampling light clock signal generator (267), and a fourth phase sampling light clock signal generator (269).

[0044] The light clock signals (WCK and WCKb) are complementary signals or differential signals.

[0045] The inverter inverts the light clock signal (WCK(f1), simply referred to as WCK) to generate an inverted light clock signal (WCKb(f1), simply referred to as WCKb). According to an embodiment, the light clock signal (WCK) is the light clock true signal (WCK_t) shown in FIGS. 6 to 8, and the inverted light clock signal (WCKb) is the light clock complement signal (WCK_c) shown in FIGS. 6 to 8.

[0046] When the light clock signal (WCK) having the first frequency (f1) is at a low level, the first transmission gate (TG1) transmits the output signal of the inverter (261) to the first latch (LT1) according to the complementary light clock signals (WCK and WCKb). The first latch (LT1) includes inverters (INV1 and INV2).

[0047] When the light clock signal (WCK) having the first frequency (f1) is at a high level, the second transmission gate (TG2) transmits the output signal of the first latch (LT1) to the second latch (LT2) according to the complementary light clock signals (WCK and WCKb). The second latch (LT2) includes inverters (INV3 and INV4).

[0048] The inverter (261) inverts the output signal of the second latch (LT2) to transmit the inverted signal (WCK / 2) having the second frequency (f2) to the first transmission gate (TG1). The frequency divider (260) can generate sampling light clock signals (WCK0, WCK90, WCK180, and WCK270) that each oscillate.

[0049] The first phase sampling light clock signal generator (263) buffers the output signal of the second latch (LT2) to generate a first phase sampling light clock signal (WCK0(f2)) having a second frequency (f2).

[0050] The second phase sampling light clock signal generator (265) buffers the output signal of the first latch (LT1) to generate a second phase sampling light clock signal (WCK90(f2)) having a second frequency (f2).

[0051] The third phase sampling light clock signal generator (267) inverts the output signal of the second latch (LT2) to generate a third phase sampling light clock signal (WCK180(f2)) having a second frequency (f2).

[0052] The fourth phase sampling light clock signal generator (269) inverts the output signal of the first latch (LT1) to generate a fourth phase sampling light clock signal (WCK270(f2)) having a second frequency (f2).

[0053] Each sampling light clock signal generator (267 and 269) may be an inverter.

[0054] Hereinafter, each phase sampling light clock signal (WCK0(f2), WCK90(f2), WCK180(f2), and WCK270(f2)) is simply referred to as each phase sampling light clock signal (WCK0, WCK90, WCK180, and WCK270) for convenience of explanation.

[0055] FIG. 4a is an example of a circuit diagram of the first data input / output circuit shown in FIG. 2 used for light training, FIG. 4b is an example of a circuit diagram of the second data input / output circuit shown in FIG. 2 used for light training, and FIG. 4c is an example of a circuit diagram of the fifth data input / output circuit shown in FIG. 2 used for light training.

[0056] The process of a memory device (10) performing light training on a fifth data input / output pin (201_5) and asynchronously feeding back the result values ​​(DQ[1] and DQ[2]) of the light training to a memory controller (400) through two data input / output pins (201_1 and 201_2) is described in detail with reference to FIGS. 1 to 9.

[0057] Since each data input / output pin (201_1~201_x) of the memory device (10) and each data input / output pin (401_1~401_x) of the memory controller 400 are connected via a bidirectional data bus (104), light training is described as being performed through each data input / output pin (201_1~201_x).

[0058] The light training data generator (420) of the memory controller (400) transmits light training data (DQ[C]=DQ[5]=TP=00001100) to the fifth data input / output pin (201_5), and the delay controller (410) receives the result values ​​of the light training (DQ[1]=DQ[A], and DQ[2]=DQ[B]) through two data input / output pins (201_1 and 201_2).

[0059] The fifth data input / output circuit (210_5) connected to the fifth data input / output pin (201_5) that receives light training data (TP) performs the function of a sampling circuit.

[0060] Referring to FIG. 1, the control logic circuit (450) of the memory controller (400) transmits commands related to light training (hereinafter referred to as 'light training commands') to the input / output interface (200) through the command / address bus (101).

[0061] Here, it is assumed that the light training command is a command to perform light training on the fifth data input / output circuit (210_5) connected to the fifth data input / output pin (201_5) and to asynchronously feed back two result values ​​(DQ[1]=DQ[A] and DQ[2]=DQ[B]) for the light training to the memory controller (400) through the two data input / output pins (201_1 and 201_2).

[0062] The control logic circuit (30) writes (or sets) the corresponding data to each memory device (228_1, 228_2, and 228_5) according to the write training command transmitted from the input / output interface (200).

[0063] For example, each memory device (228_1, 228_2, and 228_5) may be a register, a Special Function Register (SFR), or a mode register set, but is not limited thereto.

[0064] It is assumed that in write training mode, the first selection signal (TRAIN_ON1) is at a high level according to the first data stored in the first memory device (228_1), and in normal operation mode, the second selection signal (TRAIN_ON1) is at a low level according to the first data stored in the first memory device (228_1).

[0065] In the light training mode for the fifth data input / output pin (201_5), the first selection circuit (226_1) of the first data input / output circuit (210_1) transmits the output signal of the first OR gate (OR1) (indicated as 'EARLY or JUST') to the first data input / output pin (201_1) through the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a high level.

[0066] It is assumed that in the light training mode for the fifth data input / output pin (201_5), the plurality of samplers (212_1, 214_1, 216_1, and 218_1) included in the first data input / output circuit (210_1) and the first phase detector (220_1) are disabled.

[0067] It is assumed that in light training mode, the second selection signal (TRAIN_ON2) is at a high level according to the second data stored in the second memory device (228_2), and in normal operation mode, the second selection signal (TRAIN_ON2) is at a low level according to the second data stored in the second memory device (228_2).

[0068] In the light training mode for the fifth data input / output pin (201_5), the second selection circuit (226_2) of the second data input / output circuit (210_2) transmits a second detection signal (JUST) to the second data input / output pin (201_2) through the second driver (230_2) according to a second selection signal (TRAIN_ON2) having a high level.

[0069] It is assumed that in the light training mode for the fifth data input / output pin (201_5), the plurality of samplers (212_2, 214_2, 216_2, and 218_2) included in the second data input / output circuit (210_2) and the second phase detector (220_2) are disabled.

[0070] According to embodiments, it is assumed that a plurality of samplers and phase detectors included in each of the remaining data input / output circuits (220_1 to 220_4, and 210_6 to 210_x), excluding the fifth data input / output circuit (210_5) which is the subject of light training among the data input / output circuits (210_1 to 210_x), are disabled.

[0071] It is assumed that in light training mode, the output signal of the fifth selection circuit (226_5) is high impedance according to the fifth data stored in the fifth memory device (228_5), and in normal operation mode, the fifth selection signal (TRAIN_ON5) is low level according to the fifth data stored in the fifth memory device (228_5).

[0072] According to the embodiments, in the light training mode for the fifth data input / output pin (201_5), it is assumed that the fifth selection circuit (226_5) of the fifth data input / output circuit (210_5) is disabled according to the fifth data stored in the fifth memory device (228_5).

[0073] It is assumed that in the light training mode for the fifth data input / output pin (201_5), the plurality of samplers (212_5, 214_5, 216_5, and 218_5) of the fifth data input / output circuit (210_5) and the fifth phase detector (220_5) are enabled. A sampler may also be called a sampling circuit.

[0074] The light training data generator of the memory controller (400) (also called a 'test pattern generator', 420) generates light training data (DQ[C]=DQ[5]=TP=00001100) containing a light training pattern (e.g., binary 1100) and transmits it to the fifth data input / output pin (201_5) through the switch circuit (405) and the bidirectional data bus (104).

[0075] The light clock signal generator (430) of the memory controller (400) generates a light clock signal (WCK) having a toggling count corresponding to the toggling count control signal (CTL) output from the control logic circuit (450) and transmits it to the light clock signal pin (203) through the light clock signal bus (103).

[0076] For example, as illustrated in FIGS. 6 to 8, when the data processing unit (e.g., burst length) is 8-bit, the light clock signal generator (430) generates a light clock signal (WCK) that toggles only for 7.5 tWCK according to the toggling count control signal (CTL).

[0077] After the toggling time (tWCKTGL = 7.5tWCK) of the light clock signal (WCK) has elapsed, the light clock signal (WCK) no longer toggles. At this time, the light clock signal (WCK) refers collectively to the light clock signals (WCK_t and WCK_c).

[0078] As illustrated in FIGS. 6 to 8, when the light clock signal (WCK) is not toggling, the light clock true signal (WCK_t) maintains a low level and the light clock complementary signal (WCK_c) maintains a high level. However, depending on the embodiment, the opposite may be true.

[0079] According to another embodiment, when the data processing unit (e.g., burst length) is 16-bit, the light clock signal generator (430) generates a light clock signal (WCK) that toggles only for 15.5 tWCK according to the toggling count control signal (CTL).

[0080] For example, when the light training data (TP) or data processing unit (e.g., burst length) is W-bit, the number of toggles (n, e.g., 7.5 or 15.5) may be a rational number less than W (e.g., 8 or 16) and greater than (W-1), but is not limited thereto.

[0081] The clock signal generator (440) of the memory controller (400) generates a clock signal (CK) and transmits it to the input / output interface (200) via the clock signal bus (102). The clock signal (CK) includes a clock true signal (CK_t) and a clock complementary signal (CK_c), and these (CK_t and CK_c) are complementary clock signals or differential clock signals.

[0082] The first sampler (212_5) of the fifth data input / output circuit (210_5) of FIG. 4c samples the corresponding bit value included in the light training data (TP=00001100) using the edge of the first phase sampling light clock signal (WCK0) (e.g., at least one of a rising edge and a falling edge) and outputs the first sampling data (SD0). Here, the bit value may be logic (or data) 0 or logic (or data) 1.

[0083] The second sampler (214_5) of the fifth data input / output circuit (210_5) samples the corresponding bit value included in the light training data (TP=00001100) using the edge of the second phase sampling light clock signal (WCK90) and outputs the second sampling data (SD90).

[0084] The third sampler (216_5) of the fifth data input / output circuit (210_5) samples the corresponding bit value included in the light training data (TP=00001100) using the edge of the third phase sampling light clock signal (WCK180) and outputs the third sampling data (SD180).

[0085] The fourth sampler (218_5) of the fifth data input / output circuit (210_5) samples the corresponding bit value included in the light training data (TP=00001100) using the edge of the fourth phase sampling light clock signal (WCK270) and generates the fourth sampling data (SD270).

[0086] Each sampler (212_5, 214_5, 216_5, and 218_5) can be a D-flip-flop.

[0087] Figure 5 is a circuit diagram of the fifth phase detector shown in Figure 3.

[0088] The structure and operation of each phase detector included in each data input / output circuit (210_1 to 210_x) are identical. Accordingly, with reference to FIG. 5, the fifth phase detector (220_5) of the fifth data input / output circuit (210_5) that is the subject of light training operation is described as a representative example.

[0089] The fifth phase detector (220_5) includes a plurality of internal samplers (310_1, 310_2, 310_3, and 310_4), a first detection signal generator (312_1A), and a second detection signal generator (314_1A). Each of the plurality of internal samplers (310_1, 310_2, 310_3, and 310_4) may be a D-flip-flop.

[0090] Each internal sampler (310_1, 310_2, 310_3, and 310_4) of the fifth phase detector (220_5) latches each sampling data (SD0, SD90, SD180, and SD270) input to each input terminal (D) in response to the edge of the fourth phase sampling write clock signal (WCK270), and outputs each latched sampling data (SD0, SD90, SD180, and SD270) to each output terminal (Q).

[0091] The first detection signal generator (312_1A) generates a first detection signal (EARLY) by logically ANDing each inverted sampling data ( / SD90, / SD180, and / SD270).

[0092] For example, the first detection signal generator (312_1A) detects whether each inverted internal sampling data ( / SD90, / SD180, and / SD270) is the same as each of the first reference values ​​(e.g., binary X000, where X is don't care).

[0093] The second detection signal generator (314_1A) generates a second detection signal (JUST) by logically ANDing the first sampling data (SD0), the second sampling data (SD90), the inverted third sampling data ( / SD180), and the inverted fourth sampling data ( / SD270).

[0094] For example, the second detection signal generator (314_1A) detects whether each input internal sampling data (SD0, SD90, / SD180, and / SD270) is the same as each of the second reference values ​​(e.g., binary 1100).

[0095] Each detection signal generator (312_1A and 314_1A) may be an AND gate.

[0096] FIG. 6 is a timing diagram for explaining a first case of light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c.

[0097] After the time (tWLMRD) shown in FIGS. 6 to 8, the memory controller (400) supplies a write clock signal (WCK) to the memory device (10). tWCK2CK represents the skew (or phase offset) between the write clock signal (WCK) and the clock signal (CK). tWLO is the output delay of the result values ​​of the light training. After tWLO, the light training result values ​​(DQ[1] and DQ[2]) are fed back to the memory controller (400).

[0098] The goal of light training is to ensure that second reference values ​​(e.g., binary 1100) are sampled from the last m (where m is a natural number and m is 4) edges (EG1, EG2, EG3, and EG4) among all edges of the light clock true signal (WCK_t) and / or light clock complementary signal (WCK_c) contained within the light clock signal toggling time (tWCKTGL).

[0099] According to embodiments, the second reference values ​​(e.g., binary 1100) may be changed to other bit values, and accordingly, the structure of the fifth phase detector (220_5) of FIG. 5 may also be changed. The second reference values ​​(e.g., binary 1100) may represent a light training pattern.

[0100] It is assumed that when the light clock signals (WCK_t and WCK_c) stop toggling, with respect to the first phase sampling light clock signal (WCK0) having a low level (L) as in the first case (CASE1), the first edge (EG1) corresponds to the rising edge of the first phase sampling light clock signal (WCK0), the second edge (EG2) corresponds to the rising edge of the second phase sampling light clock signal (WCK90), the third edge (EG3) corresponds to the rising edge of the third phase sampling light clock signal (WCK180), and the fourth edge (EG4) corresponds to the rising edge of the fourth phase sampling light clock signal (WCK270).

[0101] When the first sampling data (SD0) sampled at the first edge (EG1) is logic 0 (also called a 'bit value'), the second sampling data (SD90) sampled at the second edge (EG2) is logic 0, the third sampling data (SD180) sampled at the third edge (EG3) is logic 0, and the fourth sampling data (SD270) sampled at the fourth edge (EG4) is logic 0, the first detection signal generator (312_1A) of FIG. 5 generates a first detection signal (EARLY) having a high level, and the second detection signal generator (314_1A) generates a second detection signal (JUST) having a low level.

[0102] Regardless of the logic of the first sampling data (SD0) sampled at the first edge (EG1), when the second sampling data (SD90) is logic 0, the third sampling data (SD180) is logic 0, and the fourth sampling data (SD270) is logic 0, the first detection signal generator (312_1A) of FIG. 5 generates a first detection signal (EARLY) having a high level, and the second detection signal generator (314_1A) generates a second detection signal (JUST) having a low level.

[0103] The first OR gate (OR1) logically ORs the first detection signal (EARLY) having a high level (H) and the second detection signal (JUST) having a low level, and transmits the logical OR result having a high level to the first selection circuit (226_1).

[0104] The first selection circuit (226_1) outputs the output signal of the first OR gate (OR1) having a high level to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a high level, and the first driver (230_1) drives (or transmits) the first data output signal (DQ[1]) having a high level to the delay controller (410) of the memory controller (400) through the components (201_1, 104, 401_1, and 405). At this time, the first input signal (DQ[A]) of the delay controller (410) is the first data output signal (DQ[1]) having a high level.

[0105] The second selection circuit (226_2) outputs a second detection signal (JUST) having a low level to the second driver (230_2) according to a second selection signal (TRAIN_ON2) having a high level, and the second driver (230_2) drives a second data output signal (DQ[2]) having a low level to the delay controller (410) of the memory controller (400) through the components (201_2, 104, 401_2, and 405). At this time, the second input signal (DQ[B]) of the delay controller (410) is the second data output signal (DQ[2]) having a low level.

[0106] The input signals (DQ[A] and DQ[B]) are the result values ​​(DQ[1] and DQ[2]) of light training for the 5th data input / output pin (201_5) (i.e., light training performed using the light clock signal (WCK) and light training data (TP)).

[0107] The delay controller (410) uses (interprets or decodes) the first data output signal (DQ[1]=DQ[A]) having a high level and the second data output signal (DQ[2]=DQ[B]) having a low level to determine that the light training data (TP=00001100) has been transmitted to the fifth data input / output pin (201_5) earlier than the desired timing or on schedule, generates a delay control signal (DCTL) according to the result of the determination, and transmits the delay control signal (DCTL) to the light training data generator (420).

[0108] The light training data generator (420) controls the transmission timing of the light training data (TP=00001100) according to the delay control signal (DCTL) (e.g., delay) and transmits the light training data (TP=00001100) back to the fifth data input / output pin (201_5) through the configurations (405, 401_5, and 104) at the timing exemplified in FIG. 7.

[0109] FIG. 7 is a timing diagram for explaining a second case of light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c.

[0110] Referring to FIGS. 1 through 5 and FIG. 7, when the light clock signals (WCK_t and WCK_c) stop toggling, with respect to a first phase sampling light clock signal (WCK0) having a low level (L), when the first sampling data (SD0) sampled at the first edge (EG1) is logic 1, the second sampling data (SD90) sampled at the second edge (EG2) is logic 1, the third sampling data (SD180) sampled at the third edge (EG3) is logic 0, and the fourth sampling data (SD270) sampled at the fourth edge (EG4) is logic 0, the first detection signal generator (312_1A) of FIG. 5 generates a first detection signal (EARLY) having a low level, and the second detection signal generator (314_1A) generates a second detection signal (JUST) having a high level Creates.

[0111] The first OR gate (OR1) logically ORs a first detection signal (EARLY) having a low level and a second detection signal (JUST) having a high level (H), and transmits the logical OR result having a high level to the first selection circuit (226_1).

[0112] The first selection circuit (226_1) outputs the output signal of the first OR gate (OR1) having a high level according to the first selection signal (TRAIN_ON1) having a high level to the first driver (230_1), and the first driver (230_1) drives the first data output signal (DQ[1]) having a high level to the delay controller (410) of the memory controller (400) through the configurations (201_1, 104, 401_1, and 405).

[0113] The second selection circuit (226_2) outputs a second detection signal (JUST) having a high level to the second driver (230_2) according to a second selection signal (TRAIN_ON2) having a high level, and the second driver (230_2) drives a second data output signal (DQ[2]) having a high level to the delay controller (410) of the memory controller (400) through the components (201_2, 104, 401_2, and 405).

[0114] The delay controller (410) can determine that light training data (TP=00001100) has been accurately transmitted to the fifth data input / output pin (201_5) at the desired timing (or time) by using a first data output signal (DQ[1]]DQ[A]) having a high level and a second data output signal (DQ[2]=DQ[B]) having a high level, and can terminate light training according to the result of the determination.

[0115] FIG. 8 is a timing diagram for explaining a third case of light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c.

[0116] Referring to FIGS. 1 through 5 and FIG. 8, when the light clock signals (WCK_t and WCK_c) stop toggling, with respect to a first phase sampling light clock signal (WCK0) having a low level (L), when the first sampling data (SD0) sampled at the first edge (EG1) is logic 0, the second sampling data (SD90) sampled at the second edge (EG2) is logic 1, the third sampling data (SD180) sampled at the third edge (EG3) is logic 1, and the fourth sampling data (SD270) sampled at the fourth edge (EG4) is logic 0, the first detection signal generator (312_1A) of FIG. 5 generates a first detection signal (EARLY) having a low level, and the second detection signal generator (314_1A) generates a second detection having a low level Generates a signal (JUST).

[0117] The first OR gate (OR1) logically ORs the first detection signal (EARLY) having a low level and the second detection signal (JUST) having a low level, and transmits the logical OR result having a low level to the first selection circuit (226_1).

[0118] The first selection circuit (226_1) outputs the output signal of the first OR gate (OR1) having a low level to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a high level, and the first driver (230_1) drives the first data output signal (DQ[1]) having a low level to the delay controller (410) of the memory controller (400) through the configurations (201_1, 104, 401_1, and 405).

[0119] The second selection circuit (226_2) outputs a second detection signal (JUST) having a low level to the second driver (230_2) according to a second selection signal (TRAIN_ON2) having a high level, and the second driver (230_2) drives a second data output signal (DQ[2]) having a low level to the delay controller (410) of the memory controller (400) through the configurations (201_2, 104, 401_2, and 405).

[0120] The delay controller (410) determines, using a first data output signal (DQ[1]=DQ[A]) having a low level and a second data output signal (DQ[2]=DQ[B]) having a low level, that the light training data (TP=00001100) has been transmitted to the fifth data input / output pin (201_5) later than the desired timing (or time), generates a delay control signal (DCTL) according to the result of the determination, and transmits the delay control signal (DCTL) to the light training data generator (420).

[0121] The light training data generator (420) adjusts the transmission timing of the light training data (TP=00001100) according to the delay control signal (DCTL) and transmits the light training data (TP=00001100) back to the fifth data input / output pin (201_5) through the configurations (405, 401_5, and 104) at the adjusted timing.

[0122] As described with reference to FIGS. 6 to 8, the memory controller (400) controls the transmission timing of light training data (DQ[5]=TP=00001100) to be transmitted to the fifth data input / output pin (201_5), which is the target of light training, until the level of the first data output signal (DQ[1]=DQ[a]) and the level of the second data output signal (DQ[2]=DQ[B]) both become high.

[0123] FIG. 9 is a timing diagram of data according to light training performed using data input / output circuits illustrated in FIG. 4a to 4c, or FIG. 10a to 10c.

[0124] In FIG. 9, it is assumed that the second time point (TJ) is the exact timing (or on time), the first time point (TE) is earlier than the second time point (TJ), and the third time point (TL) is later than the second time point (TJ). At the second time point (TJ), the edges of the right clock signals (WCK_t and WCK_c) are aligned with the center of each data (BL1 to BL4).

[0125] When the second case (JUST CASE) of FIG. 9 corresponds to the second case (JUST CASE) of FIG. 7, the second case (JUST CASE) of FIG. 9 is an example of 4-bit data (BL1, BL2, BL3, and BL4) output from the fifth data input / output circuit (210_5) in normal read operation.

[0126] Here, BL1 collectively represents BL1_1, BL2_1, and BL5_1, etc., BL2 collectively represents BL1_2, BL2_2, and BL5_2, etc., BL3 collectively represents BL1_3, BL2_3, and BL5_3, etc., and BL4 collectively represents BL1_4, BL2_4, and BL5_4, etc.

[0127] When the first case (EARLY CASE) of FIG. 9 corresponds to the first case (EARLY CASE) of FIG. 6, the first case (EARLY CASE) of FIG. 9 is an example of 4-bit data (BL1, BL2, BL3, and BL4) output from the fifth data input / output circuit (210_5) in normal read operation.

[0128] When the third case (LATE CASE) of FIG. 9 corresponds to the third case (LATE CASE) of FIG. 8, the third case (LATE CASE) of FIG. 9 is an example of 4-bit data (BL1, BL2, BL3, and BL4) output from the fifth data input / output circuit (210_5) in normal read operation.

[0129] FIG. 10a is another embodiment of the circuit diagram of the first data input / output circuit shown in FIG. 2 used for light training, FIG. 10b is another embodiment of the circuit diagram of the second data input / output circuit shown in FIG. 2 used for light training, and FIG. 10c is another embodiment of the circuit diagram of the fifth data input / output circuit shown in FIG. 2 used for light training.

[0130] Referring to FIGS. 2, FIGS. 10a, FIGS. 10b, and FIGS. 10c, each data input / output circuit (210_1 to 210_x) includes each phase detector (220_1B to 220_xB). Among the phase detectors (220_1B to 220_xB), only the phase detector that receives light training data (TP) transmitted from the memory controller (400) generates a first detection signal (EARLY) and a second detection signal (JUST).

[0131] The process of performing light training on the fifth data input / output pin (201_5) and asynchronously feeding back the result values ​​(DQ[1] and DQ[2]) of the light training to the memory controller (400) through two data input / output pins (201_1 and 201_2) is described in detail with reference to FIGS. 1, 2, 3, and FIGS. 6 through 11.

[0132] Only the fourth phase sampling light clock signal (WCK270) is supplied to the phase detectors (220_1, 220_2, and 220_5) shown in FIGS. 4a, 4b, and 4c, but the first phase sampling light clock signal (WCK0) and the fourth phase sampling light clock signal (WCK270) are supplied together to the phase detectors (220_1, 220_2, and 220_5) shown in FIGS. 10a, 10b, and 10c.

[0133] FIG. 11 is a circuit diagram of the fifth phase detector shown in FIG. 10c.

[0134] As illustrated in FIGS. 6 to 8, at the point when the toggling of the light clock signals (WCK_t and WCK_c) begins, the frequency divider (260) of FIG. 3 may fail to operate due to inter-symbol interference (ISI), resulting in a miss of one edge of the light clock true signal (WCK_t).

[0135] If the frequency divider (260) of FIG. 3 does not miss even one edge (e.g., the first rising edge) of the light clock true signal (WCK_t), it is assumed that the first phase sampling light clock signal (WCK0) is at a low level when the toggling of the light clock signals (WCK_t and WCK_c) stops, as in the first case (CASE1) of FIG. 6 to 8.

[0136] However, if the frequency divider (260) of FIG. 3 misses one edge (e.g., the first rising edge) of the light clock true signal (WCK_t), it is assumed that the first phase sampling light clock signal (WCK0) is at a high level when the toggling of the light clock signals (WCK_t and WCK_c) stops, as in the second case (CASE2) of FIG. 6 to 8.

[0137] For example, a memory device (10), for example, a control logic circuit (30) can determine whether the frequency divider (260) has missed one edge (e.g., the first rising edge) of the light clock true signal (WCK_t) based on the level of the first phase sampling light clock signal (WCK0) when the toggling of the light clock signals (WCK_t and WCK_c) has stopped.

[0138] When the toggling of the light clock signals (WCK_t and WCK_c) stops, if the level of the first phase sampling light clock signal (WCK0) is low (WCK0=L) as in the first case (CASE1) of FIGS. 6 to 8, the sampling order of the samplers (212_5, 214_5, 216_5, and 218_5) of FIG. 4c is assumed to be WCK0→WCK90→WCK180→WCK270.

[0139] However, when the toggling of the light clock signals (WCK_t) stops, if the level of the first phase sampling light clock signal (WCK0) is high (WCK0=H) as in the second case (CASE2) of FIGS. 6 to 8, the sampling order of the samplers (212_5, 214_5, 216_5, and 218_5) of FIG. 4c is assumed to be WCK180→WCK270→WCK0→WCK90.

[0140] Referring to FIG. 2 and FIG. 11, the structure and operation of the phase detectors (220_1B to 220_xB) included in each data input / output circuit (210_1 to 210_x) are identical. Accordingly, with reference to FIG. 11, the fifth phase detector (220_5B) of the fifth data input / output circuit (210_5) that is the subject of light training operation is described as a representative example.

[0141] The fifth phase detector (220_5B) of FIG. 11 includes a plurality of internal samplers (310_1, 310_2, 310_3, and 310_4), a first detection signal generator (312_1A), a second detection signal generator (314_1A), a third detection signal generator (312_1B), a fourth detection signal generator (314_1B), a first selection circuit (316), and a second selection circuit (318). Each selection circuit (316 and 318) may be a multiplexer.

[0142] Each of the multiple internal samplers (310_1, 310_2, 310_3, and 310_4) can be a D-flip-flop.

[0143] Each internal sampler (310_1, 310_2, 310_3, and 310_4) of the fifth phase detector (220_5B) latches each sampling data (SD0, SD90, SD180, and SD270) input to each input terminal (D) in response to the edge of the fourth phase sampling write clock signal (WCK270), and outputs each latched sampling data (SD0, SD90, SD180, and SD270) to each output terminal (Q).

[0144] Each detection signal generator (312_1A, 312_1B, 314_1A, and 314_1B) may be an AND gate.

[0145] The first detection signal generator (312_1A) generates a first AND signal (P_EARLY) by logically ANDing each inverted sampling data ( / SD90, / SD180, and / SD270).

[0146] The second detection signal generator (314_1A) generates a second AND signal (P_JUST) by logically ANDing the first sampling data (SD0), the second sampling data (SD90), the inverted third sampling data ( / SD180), and the inverted fourth sampling data ( / SD270).

[0147] The third detection signal generator (312_1B) generates a third AND signal (F_EARLY) by logically ANDing each inverted sampling data ( / SD0, / SD90, and / SD270).

[0148] The fourth detection signal generator (314_1B) generates a fourth logical AND signal (F_JUST) by logically ANDing the inverted first sampling data ( / SD0), the inverted second sampling data ( / SD90), the third sampling data (SD180), and the fourth sampling data (SD270).

[0149] The first selection circuit (316) can output a first logical AND signal (P_EARLY) or a third logical AND signal (F_EARLY) as a first detection signal (EARLY) depending on the level of the first phase sampling write clock signal (WCK0).

[0150] For example, when the level of the first phase sampling write clock signal (WCK0) is low (L), the first selection circuit (316) outputs the first logic AND signal (P_EARLY) as the first detection signal (EARLY), and when the level of the first phase sampling write clock signal (WCK0) is high (H), the first selection circuit (316) can output the third logic AND signal (F_EARLY) as the first detection signal (EARLY).

[0151] The second selection circuit (318) can output a second logical AND signal (P_JUST) or a fourth logical AND signal (F_JUST) as a second detection signal (JUST) depending on the level of the first phase sampling write clock signal (WCK0).

[0152] For example, when the level of the first phase sampling write clock signal (WCK0) is low (L), the second selection circuit (318) outputs a second logic AND signal (P_JUST) as a second detection signal (JUST), and when the level of the first phase sampling write clock signal (WCK0) is high (H), the second selection circuit (318) can output a fourth logic AND signal (F_JUST) as a second detection signal (JUST).

[0153] Referring again to FIGS. 6 to 8, with respect to the first phase sampling light clock signal (WCK0=H) having a high level (H) when the light clock signals (WCK_t and WCK_c) stop toggling, it is assumed that the first edge (EG1) corresponds to the rising edge of the third phase sampling light clock signal (WCK180), the second edge (EG2) corresponds to the rising edge of the fourth phase sampling light clock signal (WCK270), the third edge (EG3) corresponds to the rising edge of the first phase sampling light clock signal (WCK0), and the fourth edge (EG4) corresponds to the rising edge of the second phase sampling light clock signal (WCK90).

[0154] Referring to FIG. 6, when the third sampling data (SD180) sampled at the first edge (EG1) is logic 0, the fourth sampling data (SD270) sampled at the second edge (EG2) is logic 0, the first sampling data (SD0) sampled at the third edge (EG3) is logic 0, and the second sampling data (SD90) sampled at the fourth edge (EG4) is logic 0, the first detection signal generator (312_1A) of FIG. 11 generates a first AND signal (P_EARLY) having a high level, the third detection signal generator (312_1B) generates a third AND signal (F_ERALY) having a high level, the second detection signal generator (314_1A) generates a second AND signal (P_JUST) having a low level, and the fourth detection signal The generator (314_1B) generates a fourth AND signal (F_JUST) having a low level.

[0155] According to the first phase sampling write clock signal (WCK0=H) having a high level (H), the first selection circuit (316) outputs a third logic AND signal (F_ERALY) having a high level as the first detection signal (EARLY). Additionally, according to the first phase sampling write clock signal (WCK0=H) having a high level, the second selection circuit (316) outputs a fourth logic AND signal (F_JUST) having a low level as the second detection signal (JUST).

[0156] The first OR gate (OR1) of Fig. 2 logically ORs a first detection signal (EARLY) having a high level (H) and a second detection signal (JUST) having a low level, and transmits the logical OR result having a high level to the first selection circuit (226_1).

[0157] The first selection circuit (226_1) of FIG. 10a outputs the output signal of the first OR gate (OR1) having a high level to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a high level, and the first driver (230_1) drives the first data output signal (DQ[1]) having a high level to the delay controller (410) of the memory controller (400) through the components (201_1, 104, 401_1, and 405). At this time, the first input signal (DQ[A]) of the delay controller (410) is the first data output signal (DQ[1]) having a high level.

[0158] The second selection circuit (226_2) of FIG. 10b outputs a second detection signal (JUST) having a low level to the second driver (230_2) according to a second selection signal (TRAIN_ON2) having a high level, and the second driver (230_2) drives a second data output signal (DQ[2]) having a low level to the delay controller (410) of the memory controller (400) through the components (201_2, 104, 401_2, and 405). At this time, the second input signal (DQ[B]) of the delay controller (410) is the second data output signal (DQ[2]) having a low level.

[0159] The delay controller (410) of FIG. 1 uses (analyzes or decodes) a first data output signal (DQ[1]=DQ[A]) having a high level and a second data output signal (DQ[2]=DQ[B]) having a low level to determine that light training data (TP=00001100) has been transmitted to the fifth data input / output pin (201_5) earlier than the desired timing (or time), generates a delay control signal (DCTL) according to the result of the determination, and transmits the delay control signal (DCTL) to the light training data generator (420).

[0160] The light training data generator (420) controls the transmission timing of the light training data (TP=00001100) according to the delay control signal (DCTL) (e.g., delay) and transmits the light training data (TP=00001100) to the fifth data input / output pin (201_5) through the configurations (405, 401_5, and 104) at the timing exemplified in FIG. 7.

[0161] Referring to FIGS. 2, FIG. 7, FIG. 10a, FIG. 10b, FIG. 10c, and FIG. 11, when the write clock signals (WCK_t and WCK_c) stop toggling, with respect to a first phase sampling write clock signal (WCK0=H) having a high level (H), when the third sampling data (SD180) sampled at the first edge (EG1) is logic 1, the fourth sampling data (SD270) sampled at the second edge (EG2) is logic 1, the first sampling data (SD0) sampled at the third edge (EG3) is logic 0, and the second sampling data (SD90) sampled at the fourth edge (EG4) is logic 0, the first detection signal generator (312_1A) of FIG. 11 generates a first logical AND signal (P_EARLY) having a low level, and the third detection signal The generator (312_1B) generates a third AND signal (F_ERALY) having a low level, the second detection signal generator (314_1A) generates a second AND signal (P_JUST) having a low level, and the fourth detection signal generator (314_1B) generates a fourth AND signal (F_JUST) having a high level.

[0162] According to the first phase sampling write clock signal (WCK0=H) having a high level (H), the first selection circuit (316) outputs a third logic AND signal (F_ERALY) having a low level as the first detection signal (EARLY). Additionally, according to the first phase sampling write clock signal (WCK0=H) having a high level (H), the second selection circuit (316) outputs a fourth logic AND signal (F_JUST) having a high level as the second detection signal (JUST).

[0163] The first OR gate (OR1) of Fig. 2 logically ORs a first detection signal (EARLY) having a low level and a second detection signal (JUST) having a high level (H), and transmits the logical OR result having a high level to the first selection circuit (226_1).

[0164] The first selection circuit (226_1) of FIG. 10a outputs the output signal of the first OR gate (OR1) having a high level to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a high level, and the first driver (230_1) drives the first data output signal (DQ[1]) having a high level to the delay controller (410) of the memory controller (400) through the components (201_1, 104, 401_1, and 405).

[0165] The second selection circuit (226_2) of FIG. 10b outputs a second detection signal (JUST) having a high level to the second driver (230_2) according to a second selection signal (TRAIN_ON2) having a high level, and the second driver (230_2) drives a second data output signal (DQ[2]) having a high level to the delay controller (410) of the memory controller (400) through the components (201_2, 104, 401_2, and 405).

[0166] The delay controller (410) of FIG. 1 determines that light training data (TP=00001100) has been accurately transmitted to the fifth data input / output pin (201_5) at the desired timing (or time) according to the first data output signal (DQ[1]=DQ[A]) having a high level and the second data output signal (DQ[2]=DQ[B]) having a high level, and can terminate the light training according to the result of the determination.

[0167] Referring to FIGS. 2, FIG. 8, FIG. 10a, FIG. 10b, FIG. 10c, and FIG. 11, when the write clock signals (WCK_t and WCK_c) stop toggling, with respect to a first phase sampling write clock signal (WCK0=H) having a high level (H), when the third sampling data (SD180) sampled at the first edge (EG1) is logic 0, the fourth sampling data (SD27) sampled at the second edge (EG2) is logic 1, the first sampling data (SD0) sampled at the third edge (EG3) is logic 1, and the second sampling data (SD90) sampled at the fourth edge (EG4) is logic 0, the first detection signal generator (312_1A) of FIG. 11 generates a first logical AND signal (P_EARLY) having a low level, and the third detection signal The generator (312_1B) generates a third AND signal (F_ERALY) having a low level, the second detection signal generator (314_1A) generates a second AND signal (P_JUST) having a low level, and the fourth detection signal generator (314_1B) generates a fourth AND signal (F_JUST) having a low level.

[0168] The first OR gate (OR1) of Fig. 2 logically ORs a first detection signal (EARLY) having a low level and a second detection signal (JUST) having a low level, and transmits the logical OR result having a low level to the first selection circuit (226_1).

[0169] The first selection circuit (226_1) of FIG. 10a outputs the output signal of the first OR gate (OR1) having a low level to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a high level, and the first driver (230_1) drives the first data output signal (DQ[1]) having a low level to the delay controller (410) of the memory controller (400) through the components (201_1, 104, 401_1, and 405).

[0170] The second selection circuit (226_2) of FIG. 10b outputs a second detection signal (JUST) having a low level to the second driver (230_2) according to a second selection signal (TRAIN_ON2) having a high level, and the second driver (230_2) drives a second data output signal (DQ[2]) having a low level to the delay controller (410) of the memory controller (400) through the components (201_2, 104, 401_2, and 405).

[0171] The delay controller (410) of FIG. 1 determines, in response to a first data output signal (DQ[1]=DQ[A]) having a low level and a second data output signal (DQ[2]=DQ[B]) having a low level, that the light training data (TP=00001100) has been transmitted to the fifth data input / output pin (201_5) later than the desired timing (or time), generates a delay control signal (DCTL) according to the result of the determination, and transmits the delay control signal (DCTL) to the light training data generator (420).

[0172] The light training data generator (420) adjusts the transmission timing of the light training data (TP=00001100) according to the delay control signal (DCTL) and transmits the light training data (TP=00001100) with adjusted transmission timing back to the fifth data input / output pin (201_5) through the configurations (405, 401_5, and 104).

[0173] As described with reference to FIGS. 2, FIGS. 6 to 8, FIGS. 10a, FIGS. 10b, FIGS. 10c, and FIG. 11, the memory controller (400) controls the transmission timing of light training data (DQ[C]=DQ[5]=TP=00001100) transmitted to the fifth data input / output pin (201_5), which is the target of light training, until the level of the first data output signal (DQ[1]=DQ[A]) and the level of the second data output signal (DQ[2]=DQ[B]) both become high.

[0174] FIG. 12 is an example of a data multiplexer illustrated in FIG. 4a to 4c, or FIG. 10a to 10c.

[0175] Since the structure of the data multiplexers (224_1 to 224_x) included in each data input / output circuit (210_1 to 210_x) is identical, the structure and operation of the first data multiplexer (224_1) included in the first data input / output circuit (210_1) is explained with reference to FIG. 12.

[0176] The first data multiplexer (224_1) includes a plurality of AND gates (330_1, 330_2, 330_3, and 330_4), a plurality of inverters (332_1, 332_2, 332_3, and 332_4), and a plurality of transmission gates (TG1_1, TG1_2, TG1_3, and TG1_4).

[0177] The first AND gate (330_1) generates a first AND signal (WCK_MUX0b) by logically ORing the first phase sampling write clock signal (WCK0) and the fourth phase sampling write clock signal (WCK270), and the first inverter (332_1) generates an inverted first AND signal (WCK_MUX0) by inverting the first AND signal (WCK_MUX0b).

[0178] The first transmission gate (TG1_1) outputs the first data (BL1_1) output from the first serializer (222_1) to the first selection circuit (226_1) according to the first AND signal (WCK_MUX0b) and the inverted first AND signal (WCK_MUX0). The first AND signal (WCK_MUX0b) and the inverted first AND signal (WCK_MUX0) are complementary signals or differential signals.

[0179] Since the operation of the serializer included in each data input / output circuit (210_1~210_x) of FIG. 2 is the same, the operation of the first serializer (222_1) is described as a representative example.

[0180] According to embodiments, the first serializer (222_1) can sequentially output 16-bit data (DATA1) in 4-bit units. For example, each data (DATA1, DATA2, and DATA5) illustrated in FIGS. 4a to 4c can be output from the memory cell array (20) during a read operation.

[0181] In normal operation mode, the first selection circuit (226_1) outputs the output signal (BL1_1) of the first data multiplexer (224_1) to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a low level. The first driver (230_1) drives the output signal (BL1_1) to the first data input / output pin (201_1).

[0182] The second AND gate (330_2) generates a second AND signal (WCK_MUX90b) by logically ORing the first phase sampling write clock signal (WCK0) and the second phase sampling write clock signal (WCK90), and the second inverter (332_2) generates an inverted second AND signal (WCK_MUX90) by inverting the second AND signal (WCK_MUX90b).

[0183] The second transmission gate (TG1_2) outputs the second data (BL1_2) output from the first serializer (222_1) to the first selection circuit (226_1) according to the second AND signal (WCK_MUX90b) and the inverted second AND signal (WCK_MUX90). The second AND signal (WCK_MUX90b) and the inverted second AND signal (WCK_MUX90) are complementary signals or differential signals.

[0184] In normal operation mode, the first selection circuit (226_1) outputs the output signal (BL1_2) of the first data multiplexer (224_1) to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a low level. The first driver (230_1) drives the output signal (BL1_2) to the first data input / output pin (201_1).

[0185] The third AND gate (330_3) generates a third AND signal (WCK_MUX180b) by logical ORing the second phase sampling write clock signal (WCK90) and the third phase sampling write clock signal (WCK180), and the third inverter (332_3) generates an inverted third AND signal (WCK_MUX180) by inverting the third AND signal (WCK_MUX180b).

[0186] The third transmission gate (TG1_3) outputs the third data (BL1_3) output from the first serializer (222_1) to the first selection circuit (226_1) according to the third AND signal (WCK_MUX180b) and the inverted third AND signal (WCK_MUX180). The third AND signal (WCK_MUX180b) and the inverted third AND signal (WCK_MUX180) are complementary signals or differential signals.

[0187] In normal operation mode, the first selection circuit (226_1) outputs the output signal (BL1_3) of the first data multiplexer (224_1) to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a low level. The first driver (230_1) drives the output signal (BL1_3) to the first data input / output pin (201_1).

[0188] The fourth AND gate (330_4) generates a fourth AND signal (WCK_MUX270b) by logical ORing the third phase sampling write clock signal (WCK180) and the fourth phase sampling write clock signal (WCK270), and the fourth inverter (332_4) generates an inverted fourth AND signal (WCK_MUX270) by inverting the fourth AND signal (WCK_MUX270b).

[0189] The fourth transmission gate (TG1_4) outputs the fourth data (BL1_4) output from the first serializer (222_1) to the first selection circuit (226_1) according to the fourth AND signal (WCK_MUX270b) and the inverted fourth AND signal (WCK_MUX270). The fourth AND signal (WCK_MUX270b) and the inverted fourth AND signal (WCK_MUX270) are complementary signals or differential signals.

[0190] In normal operation mode, the first selection circuit (226_1) outputs the output signal (BL1_4) of the first data multiplexer (224_1) to the first driver (230_1) according to the first selection signal (TRAIN_ON1) having a low level. The first driver (230_1) drives the output signal (BL1_4) to the first data input / output pin (201_1).

[0191] FIG. 13 is a block diagram of a data processing system including a plurality of memory devices and a memory controller according to an embodiment of the present invention.

[0192] Referring to FIGS. 1 through 13, the data processing system (500) includes a memory system (510) and a memory controller (400).

[0193] The memory system (510) includes memory devices (10_1 and 10_2). The structure and operation of each memory device (10_1 and 10_2) are substantially the same as the structure and operation of the memory device (10) described with reference to FIGS. 1 to 12. Each memory device (10_1 and 10_2) may be a DRAM.

[0194] The memory controller (400) supplies a first write clock signal (WCK1) to the first memory device (10_1), and the first memory device (10_1) performs write training on one of the multiple data input / output pins (201_1 to 201_x) included in the input / output interface (200), and has a structure for asynchronously transmitting (or feeding back) the result values ​​of the write training to the memory controller (400) through at least two data input / output pins excluding the one of the multiple data input / output pins (201_1 to 201_x).

[0195] The memory controller (400) supplies a second write clock signal (WCK2) to the second memory device (10_2), and the second memory device (10_2) performs write training on one of the multiple data input / output pins (201_1 to 201_x) included in the input / output interface (200), and has a structure for asynchronously transmitting (or feeding back) the result values ​​of the write training to the memory controller (400) through at least two data input / output pins excluding the one of the multiple data input / output pins (201_1 to 201_x).

[0196] The present invention has been described with reference to embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0197] 100: Memory System 10: Memory device, DRAM 200: Input / Output Interface 201_1~201_x: Data I / O pins 210_1~210_x: Data Input / Output Circuits 220_1~220_x: Phase detectors 220_1B~220_xB: Phase detectors 226_1: First selection circuit 226_2: Second selection circuit 226_5: Fifth selection circuit 212_5, 214_5, 216_5, 218_5: Samplers 260: Frequency divider

Claims

Claim 1 In an input / output interface, data input / output pins including a first data input / output pin and a plurality of second data input / output pins; The input / output interface includes a light clock signal pin that receives a light clock signal from a memory controller, wherein the first data input / output pin receives light training data for light training from the memory controller, and the plurality of second data input / output pins feed back result values ​​of the light training performed using the light clock signal and the light training data to the memory controller, and the input / output interface generates sampling values ​​by sampling the light training data using sampling light clock signals associated with the light clock signal, generates a first detection signal indicating whether the light training data was received before the scheduled time and a second detection signal indicating whether the light training data was received at the scheduled time using the sampling values, feeds back the logical OR result of the first detection signal and the second detection signal to the memory controller through one of the plurality of second data input / output pins, and feeds back the second detection signal to the memory controller through another of the plurality of second data input / output pins. Claim 2 In claim 1, the input / output interface further includes a sampling circuit that generates sampling values ​​by sampling using the sampling light clock signals corresponding to the last m toggling edges of the light clock signal that toggles the light training pattern included in the light training data n times, and generates result values ​​of the light training using the sampling values, wherein n is greater than m. Claim 3 An input / output interface according to paragraph 2, wherein when the light training data or data processing unit is W-bit, W is a natural number greater than 2, and n is a rational number less than W and greater than (W-1). Claim 4 In paragraph 2, the sampling circuit is an input / output interface that feeds back result values ​​of the light training to the memory controller through the plurality of second data input / output pins while the light clock signal is not toggling. Claim 5 delete Claim 6 In paragraph 2, the input / output interface comprises: a frequency divider that divides the frequency of the light clock signal according to a frequency division ratio and generates the sampling light clock signals, each having a frequency divided according to the frequency division ratio and having different phases; samplers that generate the sampling values ​​by sampling the light training pattern in response to each of the sampling light clock signals; internal samplers that generate internal sampling values ​​by sampling each of the sampling values ​​using one of the sampling light clock signals; a first detection signal generator that generates a first detection signal indicating whether some of the internal sampling values ​​match first reference values; a second detection signal generator that generates a second detection signal indicating whether all of the internal sampling values ​​match second reference values; and a logical OR gate that feeds back the logical OR result of the first detection signal and the second detection signal to the memory controller through one of the plurality of second data input / output pins. An input / output interface comprising a driver that feeds back the second detection signal to the memory controller through another of the plurality of second data input / output pins. Claim 7 A memory device comprising: a first data input / output pin for receiving light training data for light training; a second data input / output pin; a third data input / output pin; a light clock signal pin for receiving a light clock signal; and an input / output interface for transmitting each of the result values ​​of the light training performed using the light clock signal and the light training data to the second data input / output pin and the third data input / output pin, respectively; wherein the input / output interface generates sampling values ​​by sampling the light training data using sampling light clock signals associated with the light clock signal, generates a first detection signal indicating whether the light training data was received before the scheduled time and a second detection signal indicating whether the light training data was received at the scheduled time using the sampling values, transmits the logical OR result of the first detection signal and the second detection signal to the second data input / output pin, and transmits the second detection signal to the third data input / output pin. Claim 8 delete Claim 9 In claim 7, the input / output interface generates the sampling values ​​by sampling a portion of the light training data using the sampling light clock signals corresponding to the last m toggling edges of the light clock signal that toggles n times, and the n is a memory device larger than m. Claim 10 In claim 7, the input / output interface is a memory device that transmits the logical OR result to the second data input / output pin and transmits the second detection signal to the third data input / output pin while the write clock signal is not toggling. Claim 11 In claim 7, the input / output interface comprises a memory device including a frequency divider that divides the frequency of the light clock signal according to a frequency division ratio and generates the sampling light clock signals having different phases, each having a frequency divided according to the frequency division ratio. Claim 12 In claim 11, the input / output interface further comprises: samplers that generate the sampling values ​​by sampling a portion of the light training data in response to each of the sampling light clock signals; internal samplers that generate internal sampling values ​​by sampling each of the sampling values ​​using one of the sampling light clock signals; a first detection signal generator that generates the first detection signal indicating whether some of the internal sampling values ​​match the first reference values; a second detection signal generator that generates the second detection signal indicating whether all of the internal sampling values ​​match the second reference values; a logical OR gate that transmits the logical OR result of the first detection signal and the second detection signal to the second data input / output pin; and a driver that transmits the second detection signal to the third data input / output pin. Claim 13 In claim 12, the memory device further comprises: a first mode register set storing first data indicating entry into a light training mode for light training; a first selection circuit transmitting the logical OR result to the second data input / output pin according to a first selection signal generated by the first data stored in the first mode register set; a second mode register set storing second data indicating entry into the light training mode; and a second selection circuit transmitting the second detection signal to the third data input / output pin according to a second selection signal generated by the second data stored in the second mode register set. Claim 14 In claim 7, the memory device is a memory device that is an LPDDR SDRAM (Low-Power Double Data Rate Synchronous Dynamic Random-access Memory). Claim 15 The memory device; and a memory controller that transmits a light clock signal and light training data for light training to the memory device, wherein the memory device comprises: a first data input / output pin for receiving the light training data; a second data input / output pin; a third data input / output pin; and a light clock signal pin for receiving the light clock signal. A memory system comprising an input / output interface that feeds back result values ​​of the light training performed using the light clock signal and the light training data to the memory controller through the second data input / output pin and the third data input / output pin, wherein the input / output interface generates sampling values ​​by sampling the light training data using sampling light clock signals associated with the light clock signal, generates a first detection signal indicating whether the light training data was received earlier than the scheduled time and a second detection signal indicating whether the light training data was received at the scheduled time using the sampling values, feeds back the logical OR result of the first detection signal and the second detection signal to the memory controller through the second data input / output pin, and feeds back the second detection signal to the memory controller through the third data input / output pin. Claim 16 delete Claim 17 In paragraph 15, the memory controller generates the light clock signal that toggles n times and transmits it to the light clock signal pin, and the input / output interface generates the sampling values ​​by sampling a portion of the light training data using the sampling light clock signals corresponding to the last m toggling edges of the light clock signal that toggles n times, and the memory system where n is greater than m. Claim 18 In claim 15, the above input / output interface feeds back the logical OR result to the memory controller through the second data input / output pin while the write clock signal is not toggling, and feeds back the second detection signal to the memory controller through the third data input / output pin. Claim 19 In claim 18, the memory controller comprises: a delay controller that receives the logical OR result and the second detection signal, interprets the logical OR result and the second detection signal, and generates a delay control signal according to the interpretation result; and a memory system that adjusts the transmission timing of the light training data according to the delay control signal and transmits the light training data with adjusted transmission timing back to the first data input / output pin. Claim 20 In claim 15, the input / output interface comprises: a frequency divider that divides the frequency of the light clock signal according to a frequency division ratio and generates the sampling light clock signals, each having a different phase and a frequency divided according to the frequency division ratio; samplers that generate the sampling values ​​by sampling a portion of the light training data in response to each of the sampling light clock signals; internal samplers that generate internal sampling values ​​by sampling each of the sampling values ​​using one of the sampling light clock signals; a first detection signal generator that generates the first detection signal indicating whether some of the internal sampling values ​​match the first reference values; a second detection signal generator that generates the second detection signal indicating whether all of the internal sampling values ​​match the second reference values; a logical OR gate that transmits the logical OR result of the first detection signal and the second detection signal to the second data input / output pin; and a driver that transmits the second detection signal to the third data input / output pin.

Images