Spatially variable wafer bias power system

Abstract

A plasma deposition system comprises a wafer platform, a first electrode, a second electrode, a first high-voltage pulser, and a second high-voltage pulser. In some embodiments, the second electrode may be positioned in close proximity to the wafer platform. In some embodiments, the second electrode may have a disk shape having a central opening; a central axis, an opening diameter, and an outer diameter. In some embodiments, the first electrode may be positioned in close proximity to the wafer platform and within the central opening of the second electrode. In some embodiments, the first electrode may have a disk shape, a central axis, and an outer diameter. In some embodiments, the first high-voltage pulser may be electrically coupled to the first electrode. In some embodiments, the second high-voltage pulser may be electrically coupled to the second electrode.

Description

Technology Field

[0001] This application claims priority to U.S. preliminary patent application No. 62 / 711,464, filed on July 27, 2018, under the title “Nanosecond pulser system,” which is incorporated by reference in its entirety.

[0002] This application claims priority to U.S. preliminary patent application No. 62 / 711,334 filed on July 27, 2018, titled “Nanosecond pulser thermal management,” which is incorporated by reference in its entirety.

[0003] This application claims priority to U.S. preliminary patent application No. 62 / 711,457, filed on July 27, 2018, titled “Pulse generation of a nanosecond pulser,” which is incorporated by reference in its entirety.

[0004] This application claims priority to U.S. preliminary patent application No. 62 / 711,347, filed on July 27, 2018, under the title “Nanosecond pulser ADC system,” which is incorporated by reference in its entirety.

[0005] This application claims priority to U.S. Preliminary Patent Application No. 62 / 711,467 “Edge Ring Power System” filed on July 27, 2018, which is incorporated by reference in its entirety.

[0006] This application claims priority to U.S. preliminary patent application No. 62 / 711,406, filed on July 27, 2018, under the title “Nanosecond pulser bias compensation,” which is incorporated by reference in its entirety.

[0007] This application claims priority to U.S. preliminary patent application No. 62 / 711,468, filed on July 27, 2018, under the title “Nanosecond pulser control module,” which is incorporated by reference in its entirety.

[0008] This application claims priority to U.S. preliminary patent application No. 62 / 711,523 filed on August 10, 2018, titled “Plasma sheath control for RF plasma reactor,” which is incorporated by reference in its entirety.

[0009] This application claims priority to U.S. preliminary patent application No. 62 / 789,523 filed on January 1, 2019, titled “Efficient nanosecond pulser with source and sink functions for plasma control applications,” the entirety of which is incorporated by reference.

[0010] This application claims priority to U.S. preliminary patent application No. 62 / 789,526 filed on January 1, 2019, titled “Efficient energy recovery of nanosecond pulse circuits,” the entirety of which is incorporated by reference.

[0011] This application claims priority to U.S. non-preliminary patent application No. 16 / 523,840 filed on July 26, 2019, titled “Nanosecond pulser bias compensation”, which is incorporated by reference in its entirety. Background Technology

[0012] Generating high-voltage pulses with fast rise and / or fall times is a difficult task. For example, to achieve fast rise and / or fall times (e.g., less than approximately 50ns) for high-voltage pulses (e.g., greater than about 5kV), the slope of the pulse rise and / or fall must be very steep (e.g., 10 11(Exceeding V / s). Such steep rise and / or fall times are very difficult to generate, especially in circuits driving loads with low capacitance. These pulses can be difficult to generate using standard electrical components, particularly in a compact manner; and / or as pulses with variable pulse width, voltage, and repetition rate; and / or within applications with capacitive loads, such as plasma.

[0013] Furthermore, wafer yield can determine the success of the process. Often, chips located at the edges of the wafer may become unusable due to various defects that can occur at the edges. These defects increase waste and reduce wafer yield.

[0014] Some embodiments of the present invention include a power system having a plasma load that may include a first high-voltage pulser, a second high-voltage pulser, a chamber, a first electrode, and a second electrode. In some embodiments, the first high-voltage pulser may output a first plurality of pulses having a first voltage greater than about 1 kV, a first pulse width less than about 1 μs, and a first pulse repetition frequency greater than about 20 kHz. In some embodiments, the second high-voltage pulser may output a second plurality of pulses having a second voltage greater than about 1 kV, a second pulse width less than about 1 μs, and a second pulse supplementary frequency greater than about 20 kHz. In some embodiments, the first electrode may be disposed within the chamber and electrically coupled to the first high-voltage pulser, and the second electrode may be disposed within the chamber adjacent to the first electrode and electrically coupled to the second high-voltage pulser.

[0015] In some embodiments, the chamber includes one or both of a wafer and a plasma capacitively coupled with the first electrode and the second electrode with a capacitance between 10 pF and 1 μF.

[0016] In some embodiments, the electric field at both ends of the surface of the wafer may be uniform to 25%, 20%, 15%, 10%, 5%, or 2% or less using a first nanosecond pulser and a second nanosecond pulser.

[0017] In some embodiments, the coupling capacitance between the first electrode and the corresponding portion of the wafer is greater than 100 pF; and the capacitance between the second electrode and the corresponding portion of the wafer is greater than 100 pF.

[0018] In some embodiments, the chamber includes a plasma of ions accelerated onto a wafer.

[0019] In some embodiments, the first high voltage pulser generates an electrode voltage on the first electrode greater than about 1 kV, and the second high voltage pulser generates an electrode voltage on the second electrode greater than about 1 kV. In some embodiments, the ratio of the first voltage to the second voltage is less than 2 to 1 or vice versa.

[0020] In some embodiments, one or both of the first electrode and the second electrode are axially symmetric.

[0021] In some embodiments, the first electrode has a first planar surface and the second electrode has a second planar surface so that the second planar surface is 25% of the total sum of the first planar surface and the second planar surface.

[0022] In some embodiments, both the first high-voltage pulser and the second high-voltage pulser include a resistive output terminal. In some embodiments, both the first high-voltage pulser and the second high-voltage pulser include an energy recovery circuit.

[0023] In some embodiments, the parameters of the first plurality of pulses are controlled independently of the parameters of the second plurality of pulses. The first pulse repetition frequency and the second pulse repetition frequency are in phase with each other.

[0024] In some embodiments, the coupling capacitance between the first electrode and the second electrode is less than about 10 nF.

[0025] In some embodiments, the first electrode comprises a disc shape, a central axis, and an outer diameter. In some embodiments, the second electrode comprises a disc shape having a central hole—the first electrode is disposed within the central hole—a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter.

[0026] Some embodiments of the present invention include a spatially variable wafer bias system that may include a wafer platform, a first electrode, a second electrode, a first high-voltage pulser, and a second high-voltage pulser. In some embodiments, the first electrode includes a disk shape, a central axis, and an outer diameter. In some embodiments, the second electrode includes a disk shape having a central hole—the first electrode is disposed within the central hole—a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter. In some embodiments, the first high-voltage pulser is electrically coupled to the first electrode, and the first high-voltage pulser can generate a pulse greater than 5 kV at a pulse repetition rate greater than 10 kHz. In some embodiments, the second high-voltage pulser is electrically coupled to the second electrode, and the second high-voltage pulser can generate a pulse greater than 5 kV at a pulse repetition rate greater than 10 kHz.

[0027] In some embodiments, the second high-voltage pulser provides a pulse having an amplitude that is part of the amplitude of the pulse provided by the first high-voltage pulser. In some embodiments, the second high-voltage pulser provides a pulse having a pulse repetition frequency that is part of the pulse repetition frequency of the pulse provided by the first high-voltage pulser.

[0028] In some embodiments, the spatially variable wafer bias system may further include a first resistive output terminal coupled to the first high-voltage pulser and the first electrode; and a second resistive output terminal coupled to the second high-voltage pulser and the second electrode. In some embodiments, the spatially variable wafer bias system may further include a bias compensation circuit coupled to the first high-voltage pulser and the first electrode.

[0029] In some embodiments, the space-variable wafer bias system may further include a ring of insulating material disposed between the first electrode and the second electrode. In some embodiments, the wafer platform comprises a dielectric material or a ceramic material. In some embodiments, the wafer platform has an outer diameter substantially similar to the outer diameter of the second electrode.

[0030] Some embodiments include a method comprising the step of pulsing a first high-voltage pulse coupled to a first electrode in a plasma chamber, wherein the first high-voltage pulse is pulsed with a first voltage greater than about 1 kV, a first pulse repetition frequency greater than about 20 kHz, and a first pulse width; and the step of pulsing a second high-voltage pulse coupled to a second electrode in the plasma chamber, wherein the second high-voltage pulse is pulsed with a second voltage greater than about 1 kV, a second pulse repetition frequency greater than about 20 kHz, and a second pulse width. In some embodiments, the first electrode and the second electrode are placed below a wafer. The method may also include the step of measuring a parameter corresponding to a physical phenomenon occurring within the plasma chamber; and the step of adjusting at least one of the second voltage, the second pulse repetition frequency, and the second pulse width based on the measured parameter.

[0031] In some embodiments, the voltage or current generated within the plasma chamber corresponds to the uniformity of the electric field across the surface of the wafer.

[0032] In some embodiments, the voltage or current generated within the plasma chamber corresponds to the uniformity of the ion current across the surface of the wafer.

[0033] In some embodiments, the parameter is the current flowing through the resistance of the resistive output terminal or the resistance of the energy recovery circuit.

[0034] Some embodiments of the present invention include a spatially variable wafer bias system. For example, the wafer bias system comprises: a disk-shaped wafer platform; a first electrode having a disk shape positioned and aligned in proximity to the wafer platform; a second electrode having a disk shape and a central opening aligned in proximity to the wafer platform such that the first electrode is positioned within a central opening; a first high-voltage pulser electrically coupled to the first electrode; and a second high-voltage pulser electrically coupled to the second electrode.

[0035] In some embodiments, the second high-voltage pulser provides a pulse having an amplitude that is a part of the amplitude of the pulse provided by the first high-voltage pulser. For example, the part may include 50%, 75%, 100%, 125%, 150%, 200%, etc.

[0036] In some embodiments, the system further includes a first resistive output terminal coupled to the first high-voltage pulser and the first electrode.

[0037] In some embodiments, the system further includes a second resistive output terminal coupled to the second high-voltage pulser and the second electrode.

[0038] In some embodiments, the system further includes a bias capacitor coupled to the first high-voltage pulser and the first electrode.

[0039] In some embodiments, the system further includes a bias capacitor coupled to the first high-voltage pulser and the second electrode.

[0040] In some embodiments, the first high-voltage pulser comprises one or more nanosecond pulsers. In some embodiments, the second high-voltage pulser comprises one or more nanosecond pulsers.

[0041] Some embodiments include a plasma deposition system comprising a wafer platform, a first electrode, a second electrode, a first high-voltage pulser, and a second high-voltage pulser. In some embodiments, the second electrode may be positioned below the wafer platform. In some embodiments, the second electrode may include a disk shape having a central opening, a central axis, an opening diameter, and an outer diameter. In some embodiments, the first electrode may be positioned below the wafer platform and within the central opening of the second electrode. In some embodiments, the first electrode may include a disk shape, a central axis, and an outer diameter. In some embodiments, the first high-voltage pulser may be electrically coupled to the first electrode. In some embodiments, the first high-voltage pulser may generate a pulse greater than 5 kV with a pulse repetition rate greater than 10 kHz. In some embodiments, the second high-voltage pulser may be electrically coupled to the second electrode. In some embodiments, the second high-voltage pulser can generate a pulse greater than 5 kV with a pulse repetition rate greater than 10 kHz.

[0042] Some embodiments include a wafer platform having a first platform region and a second platform region; a first electrode disposed below the first platform region of the wafer platform; a second electrode disposed below the second platform region of the wafer platform; a first high-voltage pulser electrically coupled to the first electrode - the first high-voltage pulser generates a pulse greater than 2 kV with a pulse repetition rate greater than 10 kHz -; and a second high-voltage pulser electrically coupled to the second electrode - the second high-voltage pulser generates a pulse greater than 2 kV with a pulse repetition rate greater than 10 kHz - comprising a plasma deposition system including the following.

[0043] In some embodiments, the second high-voltage pulser provides a pulse having an amplitude that is part of the amplitude of the pulse provided by the first high-voltage pulser.

[0044] In some embodiments, the second high-voltage pulser provides a pulse having a pulse repetition frequency that is part of the pulse repetition frequency of the pulse provided by the first high-voltage pulser.

[0045] In some embodiments, the first high-voltage pulser or the second high-voltage pulser comprises one or more nanosecond pulsers.

[0046] In some embodiments, the first high-voltage pulser or the second high-voltage pulser includes one or more high-voltage switches.

[0047] Some embodiments include a system comprising a wafer platform; a plurality of electrodes disposed below the wafer platform; and a plurality of high-voltage pulsers electrically coupled to each of the plurality of electrodes, wherein each of the plurality of high-voltage pulsers generates a pulse greater than 5 kV with a pulse repetition rate greater than 10 kHz. In some embodiments, each of the plurality of electrodes is separated from each other by an insulator. In some embodiments, each of the plurality of high-voltage pulsers generates a pulse having one or both of different voltages or pulse repetition rates.

[0048] These exemplary embodiments are mentioned not to limit or restrict the disclosure, but to provide examples to aid understanding. Additional embodiments are discussed in the detailed description, and further description is provided. The benefits provided by one or more of the various embodiments may be further understood by reviewing this specification or by practicing one or more of the presented embodiments. Brief explanation of the drawing

[0049] These and other features, aspects, and advantages of the present disclosure are better understood when reading the following detailed description with reference to the accompanying drawings: FIG. 1 is a circuit diagram illustrating a nanosecond pulser according to some embodiments. Figure 2 is an example diagram illustrating a waveform generated by a nanosecond pulser. FIG. 3 is another example illustrating a nanosecond pulser according to some embodiments. FIGS. 4a and 4b are block diagrams illustrating a space-variable wafer bias power system according to some embodiments. FIG. 5 is a block diagram illustrating a space-variable wafer bias power system according to some embodiments. FIG. 6 is a schematic diagram illustrating a space-variable wafer bias system according to some embodiments. FIG. 7 is a schematic diagram illustrating a space-variable wafer bias system according to some embodiments. FIG. 8 is a schematic diagram illustrating a space-variable wafer bias system according to some embodiments. FIG. 9 illustrates an exemplary computational system for performing a function that facilitates the implementation of the embodiments described in this specification. Specific details for implementing the invention

[0050] A system and method for generating different high-voltage pulses on different electrodes are disclosed. For example, each of a plurality of pulse generators (e.g., nanosecond pulsers, RF generators, or HV switches) may be electrically coupled to each of the plurality of electrodes. The plurality of pulse generators may generate different voltages, ion energies, or electric fields on the electrodes. This may be done for various reasons, for example, to compensate for plasma chamber defects, wafer discontinuities, or to reduce wafer edge defects. In one example, a plurality of pulse generator systems may be used to generate different electric field profiles at the edge of the wafer rather than in the middle of the wafer.

[0051] FIG. 1 is a circuit diagram of a nanosecond pulser system (100) according to some embodiments. The nanosecond pulser system (100) may be implemented within a high-voltage nanosecond pulser system. The nanosecond pulser system (100) may be generalized into five stages (these stages may be divided into other stages or generalized into fewer stages and / or may include or not include the components shown in the drawing). The nanosecond pulser system (100) includes a pulser and transformer stage (101), a resistive output stage (102), a lead stage (103), a DC bias compensation circuit (104), and a load stage (106).

[0052] In some embodiments, the nanosecond pulser system (100) can generate pulses from a power source having a voltage greater than 2 kV, a rise time less than about 20 ns, and a frequency greater than about 10 kHz.

[0053] In some embodiments, the pulser and transformer stage (101) can generate multiple high-voltage pulses having high frequency and fast rise and fall times. In all illustrated circuits, the high-voltage pulse may include a nanosecond pulse.

[0054] In some embodiments, the pulser and transformer stage (101) may include one or more solid-state switches (S1) (e.g., solid-state switches such as IGBT, MOSFET, SiC MOSFET, SiC junction transistor, FET, SiC switch, GaN switch, photoconductive switch, etc.), one or more snubber resistors (R3), one or more snubber diodes (D4), one or more snubber capacitors (C5), and / or one or more freewheeling diodes (D2). One or more switches and / or circuits may be arranged in parallel or in series.

[0055] In some embodiments, the load terminal (106) may represent an effective circuit for a plasma deposition system, a plasma etching system, or a plasma sputtering system. Capacitance (C2) may represent the capacitance of a dielectric material on which a wafer may be placed, or capacitance (C2) may represent the capacitance between an electrode separated by a dielectric material and a wafer. Capacitance (C3) may represent the sheath capacitance of the plasma on the wafer. Capacitance (C9) may represent the capacitance within the plasma between the chamber wall and the upper surface of the wafer. Current sources (I2) and current sources (I1) may represent ion currents through the plasma sheath.

[0056] In some embodiments, the resistive output terminal (102) may include one or more inductive elements represented by an inductor (L1) and / or an inductor (L5). For example, the inductor (L5) may represent the parasitic inductance of the leads at the resistive output terminal (102). The inductor (L1) may be configured to minimize the power flowing directly from the pulser and transformer terminal (101) to the resistor (R1).

[0057] In some embodiments, the resistor (R1) can dissipate charge from the load terminal (106) over a rapid time scale, for example (e.g., a time scale of 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The resistance of the resistor (R1) is such that the pulse across the load terminal (106) has a rapid falling time (t f It can be low to ensure having ).

[0058] In some embodiments, the resistor (R1) may include a plurality of resistors arranged in series and / or parallel. The capacitor (C11) may represent the stray capacitance of the resistor (R1) including the capacitance of the series and / or parallel resistors. For example, the stray capacitance of the capacitor (C11) may be 5nF, 2nF, 1nF, 500pF, 250pF, 100pF, 50pF, 10pF, less than 1pF, etc. For example, the stray capacitance of the capacitor (C11) may be smaller than the load capacitance, such as being smaller than the capacitance of C2, C3 and / or C9.

[0059] In some embodiments, a plurality of pulser and transformer terminals (101) may be arranged in parallel and coupled to a resistive output terminal (102) across an inductor (L1) and / or a resistor (R1). Each of the plurality of pulser and transformer terminals (101) may also include a diode (D1) and / or a diode (D6).

[0060] In some embodiments, capacitor (C8) may represent the stray capacitance of the blocking diode (D1). In some embodiments, capacitor (C4) may represent the stray capacitance of the diode (D6).

[0061] In some embodiments, the DC bias compensation circuit (104) may include a DC voltage source (V1) that can be used to bias the output voltage positively or negatively. In some embodiments, a capacitor (C12) isolates / separates the DC bias voltage from the resistive output terminal and other circuit elements. Potential movement from one part of the circuit to another is possible. In some applications, this potential movement is used to hold the wafer in place. A resistor (R2) can protect / isolate the DC bias power supply from the high-voltage pulse generated output at the pulser and transformer terminal (101).

[0062] In this example, the DC bias compensation circuit (104) is a passive bias compensation circuit and may include a bias compensation diode (D1) and a bias compensation capacitor (C15). The bias compensation diode (C15) may be arranged in series with the offset supply voltage (V1). The bias compensation capacitor (C15) may be placed on either or both of the offset supply voltage (V1) and the resistor (R2). The bias compensation capacitor (C15) may have a capacitance of less than 100 nH to 100 μF, such as, for example, about 100 μF, 50 μF, 25 μF, 10 μF, 2 μ, 500 nH, 200 nH, etc.

[0063] In some embodiments, the bias capacitor (C12) may enable a voltage offset between the output of the pulser and transformer terminal (101) (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124). During operation, the electrode may be at a DC voltage of -2 kV, for example, during a burst, while the output of the nanosecond pulser alternates between +6 kV during the pulse and 0 kV between pulses.

[0064] The bias capacitor (C12) may have, for example, 100nF, 10nF, 1nF, 100μF, 10μF, 1μF, etc. The resistor (R2) may have a high resistance, for example, about 1 kOhm, 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, 100 MOhm, etc.

[0065] In some embodiments, the bias compensation capacitor (C15) and the bias compensation diode (D1) enable a voltage offset between the output of the pulser and transformer terminal (101) (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124), which is set when each burst starts, so that the required equilibrium state can be reached. For example, during a course of multiple pulses (e.g., about 5 to 100 pulses), charge is transferred from the bias capacitor (C12) to the bias compensation capacitor (C15) when each burst starts, so that the correct voltage can be set in the circuit.

[0066] In some embodiments, the DC bias compensation circuit (104) may include one or more high voltage switches disposed across the bias compensation diode (D1) and coupled with the power supply (V1). In some embodiments, the high voltage switch may include a plurality of switches arranged in series to collectively open and close the high voltage.

[0067] A high-voltage switch can be connected in series with one or both of an inductor and a resistor. The inductor can limit peak current through the high-voltage switch. For example, the inductor can have an inductance of less than about 100 μH, such as about 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, etc. For example, the resistor can transfer power loss to the resistive output terminal (102). The resistance of the resistor can have a resistance of about 1,000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, less than 10 ohms, etc.

[0068] In some embodiments, the high voltage switch may include a snubber circuit.

[0069] In some embodiments, the high voltage switch may include a plurality of switches arranged in series to collectively open and close the high voltage. For example, the high voltage switch may include any switch described in U.S. Patent Application No. 16 / 178,565 filed November 1, 2018, titled “High voltage switch having isolated power,” which is incorporated herein in its entirety for all purposes.

[0070] In some embodiments, the high voltage switch may be opened when the pulser and transformer terminal (101) is pulsing and closed when the pulser and transformer terminal (101) is not pulsing. For example, when the high voltage switch is closed, the current may be short-circuited across the bias compensation diode (C15). Short-circuiting this current allows the bias between the wafer and the chuck to be less than 2 kV, which may be within an acceptable tolerance.

[0071] In some embodiments, the pulser and transformer stage (101) has a high pulse voltage (e.g., voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), a high pulse repetition frequency (e.g., frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), a fast rise time (e.g., rise time of about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, less than 1,000 ns, etc.), a fast fall time (e.g., fall time of about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, less than 1,000 ns, etc.) and / or a short pulse width (e.g., about 1,000 ns, 500 ns, 250 ns, 100 ns, It is possible to generate a pulse having a pulse width of less than 20 ns.

[0072] FIG. 2 illustrates an exemplary waveform generated by a nanosecond pulser system (100). In this exemplary waveform, the pulse waveform (205) may represent the voltage provided by the pulser and transformer terminal (101). As illustrated, the pulse waveform (205) generates a pulse having the following amounts: high voltage (e.g., greater than about 4 kV as indicated in the waveform), a fast rise time (e.g., less than about 200 ns as indicated in the waveform), a fast fall time (e.g., less than about 200 ns as indicated in the waveform), and a short pulse width (e.g., less than about 300 ns as indicated in the waveform). The waveform (210) may represent the voltage on the wafer surface or the voltage across the capacitor (C3) as indicated in the circuit in FIG. 1 by a point between capacitors (C2) and capacitor (C3). The pulse waveform (215) represents the current flowing into the plasma from the pulser and transformer terminal (101). The nanosecond pulser system (100) may or may not include one or both of the diodes (D1 or D2).

[0073] During the transient state (e.g., during an initial number of pulses not shown in the drawing), high voltage pulses at the pulser and transformer terminal (101) charge capacitor (C2). Because the capacitance of capacitor (C2) is large and / or larger than the capacitance of capacitor (C3) and / or capacitor (C1) or the pulse width of the pulse is short, capacitor (C2) can receive multiple pulses from the high voltage pulser to fully charge. When capacitor (C2) is charged, the circuit reaches a steady state as shown by the waveform in FIG. 2.

[0074] When the switch (S1) is open in the normal state, the capacitor (C2) is charged and slowly dissipates through the resistive output terminal (110), as illustrated by the slightly rising slope of the waveform (210). While the capacitor (C2) is charged and the switch (S1) is open, the voltage on the wafer surface (the point between the capacitor (C2) and the capacitor (C3)) is negative. This negative voltage may be the negative value of the voltage of the pulse provided by the pulser and transformer terminal (101). In the case of the example waveform shown in FIG. 2, the voltage of each pulse is about 4 kV; and the normal state voltage of the wafer is about -4 kV. This results in a negative potential across the plasma (e.g., capacitor (C3)) which accelerates positive ions from the plasma to the wafer surface. While the switch (S1) is open, the charge of the capacitor (C2) slowly dissipates through the resistive output terminal.

[0075] When the switch (S1) is closed, the voltage across the capacitor (C2) can be flipped as the capacitor (C2) is charged (the pulse from the pulser is high as shown in waveform (205)). Also, the voltage at a point between capacitor (C2) and capacitor (C3) (e.g., wafer surface) changes to about 0 as the capacitor (C2) is charged as shown in waveform (210). Thus, the pulse from the high-voltage pulser generates a plasma potential (e.g., plasma potential) that rises from a negative high voltage to 0 and returns to a negative high voltage at a high frequency with a fast rise time, a fast fall time, and / or a short pulse width.

[0076] In some embodiments, the operation of the device represented by the resistive output terminal, i.e., the resistive output terminal (102), can rapidly discharge the stray capacitance (C1) and cause the voltage at the point between capacitors (C2) and (C3) to rapidly return to a stable negative value of about -4 kV, as illustrated by the waveform (210). The resistive output terminal can maximize the time the ions are accelerated to the wafer by ensuring that the voltage at the point between capacitors (C2) and (C3) exists for about % of the time. In some embodiments, the components included within the resistive output terminal may be specifically selected to optimize the time the ions are accelerated to the wafer and to maintain the voltage nearly constant during this time. Thus, for example, a short pulse with a fast rise time and a fast fall time may be useful, so there may be a long period of significantly uniform negative potential. Various other waveforms may be generated by the nanosecond pulser system (100).

[0077] FIG. 3 is a circuit diagram of a nanosecond pulser system (300) having a pulser and a transformer terminal (101) and an energy recovery circuit (305) according to some embodiments. For example, the energy recovery circuit may replace the resistive output terminal (102) shown in FIG. 1. In this example, the energy recovery circuit (305) may be located on or electrically coupled to the secondary side of the transformer (T1). For example, the energy recovery circuit (305) may include a diode (180) (e.g., a clover diode) at both ends of the secondary side of the transformer (T1). For example, the energy recovery circuit (305) may include a diode (310) and an inductor (315) (arranged in series), thereby allowing current to flow from the secondary side of the transformer (T1) to charge the power supply (C7). The diode (310) and inductor (315) may be electrically connected to the secondary side of the transformer (T1) and the power supply (C7). In some embodiments, the energy recovery circuit (165) may include a diode (175) and / or an inductor (170) electrically coupled to the secondary side of the transformer (T1). The inductor (170) may represent a stray inductance and / or include the stray inductance of the transformer (T1).

[0078] When the nanosecond pulser is turned on, current can charge the load terminal (106) (e.g., charge capacitor (C3), capacitor (C2), or capacitor (C9)). For example, if the secondary side voltage of the transformer (T1) rises above the charging voltage of the power supply (C7), some current can flow through the inductor (315). When the nanosecond pulser is turned off, current can be allowed to flow from the capacitor in the load terminal (106) through the inductor (315) until the voltage across the inductor (315) becomes zero, thereby charging the power supply (C7). The diode (330) can prevent the capacitor in the load terminal (106) from ringing into the inductance of the load terminal (106) or the bias compensation circuit (104).

[0079] The diode (310) can, for example, prevent charge from flowing from the power supply (C7) to the capacitor in the load terminal (106).

[0080] The value of the inductor (315) can be selected to control the current fall time. In some embodiments, the inductor (155) may have an inductance value between 1 μH and 500 μH.

[0081] In some embodiments, the energy recovery circuit (305) may include an energy recovery switch that can be used to control the flow of current through the inductor (315). For example, the energy recovery switch may be placed in series with the inductor (315). In some embodiments, the energy recovery switch may be closed when the switch (S1) is open and / or when no more pulses are generated to allow current to flow back from the load terminal (106) to the high voltage load (C7).

[0082] In some embodiments, the energy recovery switch may include a plurality of switches arranged in series to collectively switch high voltage. For example, the energy recovery switch may include the switch described in U.S. Patent Application No. 16 / 178,565, filed November 1, 2018, under the heading “High voltage switch using isolated power,” which is incorporated herein by reference in its entirety for all purposes.

[0083] In some embodiments, the nanosecond pulser system (300) can generate a waveform similar to that shown in FIG. 2.

[0084] FIG. 4a is a cross-sectional side view block diagram, and FIG. 4b is a planar block diagram of a spatially variable wafer bias power system (400) according to some embodiments. The cross-sectional side view shown in FIG. 4a follows line A shown in FIG. 4b. The spatially variable wafer bias power system (400) includes two electrodes, namely a first electrode (415) and a second electrode (420). A wafer (405) may be placed on a wafer platform (410) above both the first electrode (415) and the second electrode (420). The wafer platform (410) may include a dielectric material, for example, ceramic. The first electrode (415) may be in the shape of a disc having a diameter smaller than the diameter of either or both of the wafer platform (410) or the wafer (405). The second electrode (420) may have a donut shape having an opening diameter slightly larger than the diameter of the first electrode (415) and an outer diameter substantially similar to the diameter of either or both of the wafer platform (410) or the wafer (405). The first electrode (415) may be placed within the opening of the second electrode (420).

[0085] In some embodiments, the gap between the first electrode (415) and the second electrode (420) may be about 0.1 mm, 1.0 mm, less than 5.0 mm, etc. In some embodiments, the space between the first electrode (415) and the second electrode (420) may be filled with air, vacuum, insulating gas, solid dielectric material, or other insulating material.

[0086] In some embodiments, the thickness of the first electrode (415) and the second electrode (420) may be substantially the same. In some embodiments, the first electrode (415) and the second electrode (420) may have different thicknesses.

[0087] In some embodiments, the second electrode (420) may have an area of ​​5% to 50% of the wafer platform area.

[0088] In some embodiments, the first electrode (415) and the second electrode (420) may comprise the same material or different materials.

[0089] In some embodiments, the first high voltage pulser (425) may be connected to the first electrode (415), and the second high voltage pulser (430) may be connected to the second electrode (420). For example, the first high voltage pulser (425) and the second high voltage pulser (430) may include the pulser and transformer terminal (101) of the nanosecond pulser system (100).

[0090] In some embodiments, the first high-voltage pulser (425) and the second high-voltage pulser (430) may provide different pulses. For example, the peak voltage provided by the second high-voltage pulser (430) to the second electrode (420) may be different from the peak voltage provided by the first high-voltage pulser (425) to the first electrode (415). As another example, the pulse repetition frequency provided by the second high-voltage pulser (430) to the second electrode (420) may be different from the pulse repetition frequency provided by the first high-voltage pulser (425) to the first electrode (415). As another example, the ion current provided by the second high-voltage pulser (430) to the second electrode (420) may be different from the ion current provided by the first high-voltage pulser (425) to the first electrode (415).

[0091] In some embodiments, the first high-voltage pulser (425) and the second high-voltage pulser may provide substantially the same pulse. For example, the peak voltage provided by the second high-voltage pulser (430) to the second electrode (420) may be substantially the same as the peak voltage provided by the first high-voltage pulser (425) to the first electrode (415). In another example, the pulse repetition frequency provided by the second high-voltage pulser (430) to the second electrode (420) may be substantially the same as the pulse repetition frequency provided by the first high-voltage pulser (425) to the first electrode (415). In another example, the ion current provided by the second high-voltage pulser (430) to the second electrode (420) may be substantially the same as the ion current provided by the first high-voltage pulser (425) to the first electrode (415).

[0092] The first high-voltage pulser (425) may include any or all components of the nanosecond pulser system (100). The first high-voltage pulser (425) may include any or all components of the nanosecond pulser system (300). In some embodiments, the first high-voltage pulser (425) may include any switch described in U.S. Patent Application Serial No. 16 / 178,565 filed November 1, 2018, titled “High-voltage switch having isolated power,” which is incorporated herein by reference in its entirety for all purposes. In some embodiments, the first high-voltage pulser (425) may include an RF generator.

[0093] The second high voltage pulser (430) may include any or all components of the nanosecond pulser system (100). The second high voltage pulser (430) may include any or all components of the nanosecond pulser system (300). In some embodiments, the second high voltage pulser (430) may include any switch described in U.S. Patent Application Serial No. 16 / 178,565 filed November 1, 2018, titled “High voltage switch having isolated power,” which is incorporated herein by reference in its entirety for all purposes. In some embodiments, the second high voltage pulser (430) may include an RF generator.

[0094] In some embodiments, the first high voltage pulser (425) and the second high voltage pulser (430) provide separately controlled pulse bias voltages or separate pulse repetition frequencies or pulses with different phases so that the voltage pulse applied to the edge of the wafer by the second electrode (420) is distinguished from the voltage applied to the center of the wafer by the first electrode (415). The separate voltages can, for example, create different electric field profiles at the wafer edge compared to the center, thereby making the electric field or bias voltage at both ends of the wafer (405) uniform. This can, for example, optimize the wafer yield. In some embodiments, the second high voltage pulser (430) may operate at a lower voltage than the first high voltage pulser (425), for example, such that the second high voltage pulser (430) may operate at 5%, 10%, 15%, 20%, 25%, 30%, etc. of the voltage of the first high voltage pulser (425).

[0095] In some embodiments, the pulse provided by the first high voltage pulser (425) can be controlled relatively independently of the second high voltage pulser (430).

[0096] In some embodiments, the space-variable wafer bias power system can generate a uniform electric field (e.g., a difference of about 5%, 10%, 15%, or less than 20%) or a uniform voltage across the wafer platform (410) or wafer (405).

[0097] In some embodiments, the space-variable wafer bias power system may generate a non-uniform electric field or non-uniform voltage across the wafer platform (410) or wafer (405).

[0098] In some embodiments, the first high voltage pulser (425) and the second high voltage pulser (430) may be capacitively coupled with a capacitance between about 1 pF and 100 nF.

[0099] In some embodiments, the first high-voltage pulser (425) and the second high-voltage pulser (430) may be connected. For example, the first high-voltage pulser (425) and the second high-voltage pulser (430) may comprise a single nanosecond pulser having a voltage divider (e.g., resistive, inductive, or capacitive) that generates different voltages for the first electrode (415) and the second electrode (420). As another example, a single pulser on the primary side of the transformer may be coupled with multiple loads (and energy recovery circuits, resistive output terminals, or bias compensation circuits) coupled with different secondary windings on the secondary side of the transformer (T2). The different secondary windings may have different numbers of windings to generate different voltages.

[0100] Although two electrodes are shown in FIG. 4a, in some embodiments, any number of electrodes may be used with any number of nanosecond pulsers. In some embodiments, the first electrode (415) or the second electrode (420) may include any geometric region under the wafer platform (410) having any geometric shape. Similarly, additional electrodes and nanosecond pulsers may be included, and the additional electrode may be any shape and position relative to the other electrode and the wafer platform.

[0101] In some embodiments, the leads from the first high-voltage pulser (425) to the first electrode (415) and the leads from the second high-voltage pulser (430) to the second electrode (420) may be grouped or bundled together. Due to this bundling, for example, the total stray capacitance to ground of the bundled leads may be less than when each lead is executed individually. For example, this bundling may also save power consumption. In some embodiments, the leads may be arranged in a coaxial configuration, a twin-lead configuration, or a twisted pair. In some embodiments, the stray capacitance from the output to ground may be less than about 100 pF, or less than about 1 nF or 10 nF. In some embodiments, the stray inductance at the output may be less than about 100 nH, 1 μH, 10 μH, etc. In some embodiments, the capacitive coupling between each output may be about 100 pF, 1 nF, less than 10 nF, etc.

[0102] FIG. 5 is a block diagram of a spatially variable wafer bias power system (500) according to some embodiments. The spatially variable wafer bias power system (500) may include a first high voltage pulser (425) and a second high voltage pulser (430).

[0103] The interconnect board (505) may be electrically connected to the first high-voltage pulser (425) and the second high-voltage pulser (430) or additional high-voltage pulsers. In some embodiments, the interconnect board (505) may provide a high DC voltage to each of the first high-voltage pulser (425) or the second high-voltage pulser (430). In some embodiments, the interconnect board (505) may provide a trigger signal to the first high-voltage pulser (425) or the second high-voltage pulser (430). In some embodiments, the interconnect board (505) may provide a low-voltage pulse to the first high-voltage pulser (425) or the second high-voltage pulser (430).

[0104] In some embodiments, the interconnect board (505) may include a controller or processor comprising one or more components of the computing system (900). In some embodiments, one or more sensors may be included to measure characteristics of the plasma chamber, such as, for example, the electric field on the wafer surface, the uniformity of the electric field, the voltage of the first electrode (415), the voltage of the second electrode (420), one or more resistive output terminals, or the voltage across the resistors in one or more energy recovery circuits. Based on the measurements of the sensors, the voltage, pulse width, or pulse repetition frequency of the first high-voltage pulser (425) and the second high-voltage pulser (430) may be adjusted.

[0105] For example, if the voltage of the second electrode (420) is measured and determined to be lower than the voltage of the first electrode (415), an electric field non-uniformity (e.g., a difference of about 5%, 10%, 15%, or less than 20%) may occur on the wafer surface. The controller may adjust the pulse width of the control pulse transmitted to the second high voltage pulser (430), which can increase the voltage generated by the second high voltage pulser (430) (e.g., by increasing the capacitive charging time), and thus increase the electric field of the second electrode. This process may be repeated until the electric field at both ends of the wafer surface is uniform (e.g., 10%, 15%, 20%, 25%, etc.).

[0106] As another example, the voltage across the first resistive output terminal and the second resistive output terminal may be measured. This voltage may correspond to the ion current flowing in the chamber. This current may be affected by the electrode voltage. If the ion current for the first electrode and the ion current for the second electrode are uneven or inconsistent (e.g., a difference of more than 10%, 20%, or 30%), the controller may adjust the pulse width of the control pulse transmitted to the first high voltage pulser (425) or the second high voltage pulser (430), which may increase the voltage generated by the nanosecond pulser (e.g., by increasing the capacitive charging time) and thus increase the electric field of the corresponding electrode.

[0107] In some embodiments, pulses from the first high-voltage pulser (425) and the second high-voltage pulser (430) may pass through the energy recovery circuit (525) and the plasma chamber (535) via a chamber interface board or a bias compensation circuit (510). For example, the energy recovery circuit (525) may include a resistive output terminal (102) of the nanosecond pulser system (100). As another example, the energy recovery circuit (525) may include an energy recovery circuit (305). As another example, the energy recovery circuit (525) may not be required. As another example, the energy recovery circuit (525) may be coupled with one or both of the first high-voltage pulser (425) or the second high-voltage pulser (430). In some embodiments, the plasma chamber (535) may include a plasma chamber, an etching chamber, a deposition chamber, etc. In some embodiments, the effective circuit of the plasma chamber (535) may include a load terminal (106).

[0108] Two high-voltage pulsers are shown, but any number can be used. For example, multiple electrode rings can be combined with multiple high-voltage pulsers.

[0109] In some embodiments, the first high voltage pulser (425) may generate a pulse different from the pulse generated by the second high voltage pulser (430). For example, the first high voltage pulser (425) may provide a pulse of at least 2 kV pulse output. In some embodiments, the second high voltage pulser (430) may provide a pulse of at least 2 kV pulse of the same or different pulse output as the pulse provided by the first high voltage pulser (425).

[0110] As another example, the first high-voltage pulser (425) can generate a pulse having a first pulse repetition frequency, and the second high-voltage pulser (430) can generate a pulse having a second pulse repetition frequency. The first pulse repetition frequency and the second pulse repetition frequency may be the same or different. The first pulse repetition frequency and the second pulse repetition frequency may be in the same phase or different phase from each other.

[0111] As another example, the first high-voltage pulser (425) may generate a first plurality of bursts having a first burst repetition frequency, and the second high-voltage pulser (430) may generate a second plurality of bursts having a second burst repetition frequency. Each burst may include a plurality of pulses. The first burst repetition frequency and the second burst repetition frequency may be the same or different. The first burst repetition frequency and the second burst repetition frequency may be in the same phase or different phase from each other.

[0112] In some embodiments, the first high voltage pulser (425) and the second high voltage pulser (430) may be water-cooled or dielectric-cooled.

[0113] FIG. 6 is a schematic diagram of a spatially variable wafer bias system (600) according to some embodiments. The spatially variable wafer bias system (600) may include a first high-voltage pulser (425) and a second high-voltage pulser (430) coupled with a plasma chamber (535).

[0114] In this example, the first high-voltage pulser (425) includes a first resistive output terminal (610) and a first bias capacitor (615). In some embodiments, for example as shown in the nanosecond pulser system (300), the first resistive output terminal (610) may not be used and an energy recovery circuit may be used.

[0115] In this example, the second high-voltage pulser (430) includes a second resistive output terminal (620) and a second bias capacitor (625). In some embodiments, for example as illustrated in the nanosecond pulser system (300), the second resistive output terminal (620) may not be used and an energy recovery circuit may be used.

[0116] A first electrode (415) and a second electrode (420) are disposed in a plasma chamber (535). In this example, the first electrode (415) is disc-shaped and is disposed within the central opening of the second electrode (420). A first high-voltage pulser (425) is electrically coupled to the first electrode (415), and a second high-voltage pulser (430) is electrically coupled to the second electrode (420). In some embodiments, a floating coupling capacitance (630) may exist between the first high-voltage pulser (425) and the second high-voltage pulser (430). For example, the floating coupling capacitance (630) may be about 100 pF, about 1 nF, less than about 10 nF, etc.

[0117] FIG. 7 is a schematic diagram illustrating a space-variable wafer bias system (700) according to some embodiments. In this example, the space-variable wafer bias system (700) utilizes a plurality of insulated secondary windings to provide different voltages to two different wafer space regions. The space-variable wafer bias system (700) includes a single high-voltage pulser (705). The single high-voltage pulser (705) may include the pulser and transformer terminal (101) shown in FIG. 1 or FIG. 3. In this example, two separate sets of secondary windings may be wound around transformer T1. The first secondary winding (710) may be electrically coupled to a first resistive output terminal (610) and a first bias capacitor (615) forming a first electrode channel. The second secondary winding (715) may be electrically coupled to the second bias capacitor (625) forming the second resistive output terminal (620) and the second electrode channel. In some embodiments, a floating coupling capacitance (630) may exist between the first electrode channel and the second electrode channel. The floating coupling capacitance (630) may be, for example, about 100 pF, about 1 nF, less than about 10 nF, etc.

[0118] In some embodiments, a first energy recovery circuit (e.g., energy recovery circuit (305)) may be used instead of the first resistive output terminal (610), and a second energy recovery circuit (e.g., energy recovery circuit (305)) may be used instead of the second resistive output terminal (620). The first energy recovery circuit and the second energy recovery circuit may be arranged in parallel. The voltage on the first electrode (415) and the second voltage on the second electrode (420) may depend on the number of turns of the first secondary winding and the second secondary winding.

[0119] FIG. 8 is a schematic diagram illustrating a spatially variable wafer bias system (800) according to some embodiments. In this example, the spatially variable wafer bias system (800) uses a voltage divider to provide different voltages to two different wafer spatial regions. The spatially variable wafer bias system (800) includes a single high voltage pulser (805) and a voltage divider (810). The voltage divider (810) may include a plurality of resistors and capacitors. The values ​​of the resistors and capacitors may be selected to provide a voltage ratio of the voltage of the pulse provided to the first electrode channel providing the pulse to the first electrode (415) and the voltage of the pulse provided to the second electrode channel providing the pulse to the second electrode (420).

[0120] The first electrode channel may include a first resistive output terminal (610) and a first bias capacitor (615). The second electrode channel may include a second resistive output terminal (620) and a second bias capacitor (625).

[0121] In some embodiments, the floating coupled capacitance (630) may exist between the first electrode channel and the second electrode channel. For example, the floating coupled capacitance (630) may be about 100 pF, about 1 nF, less than about 10 nF, etc.

[0122] In some embodiments, a first energy recovery circuit (e.g., energy recovery circuit (305)) may be used instead of the first resistive output terminal (610), and a second energy recovery circuit (e.g., energy recovery circuit (305)) may be used instead of the second resistive output terminal (620). The first energy recovery circuit and the second energy recovery circuit may be arranged in parallel.

[0123] Unless otherwise specified, the term “substantially” means within 5% or 10% of the stated value or within the manufacturing tolerance. Unless otherwise specified, the term “about” means within 5% or 10% of the stated value or within the manufacturing tolerance.

[0124] The computational system (900) illustrated in FIG. 9 may be used to perform any embodiment of the present invention. As another example, the computational system (900) may be used to perform any computation, identification, and / or decision described herein. The computational system (900) includes hardware elements that may be electrically coupled (or appropriately communicated) via a bus (905). The hardware elements may include one or more processors (910) including, without limitation, one or more general-purpose processors and / or one or more special-purpose processors (such as digital signal processing chips, graphics acceleration chips, etc.); one or more input devices (915) including, without limitation, a mouse, keyboard, etc.; and one or more output devices (920) including, without limitation, a display device, printer, etc.

[0125] The computing system (900) may further include (and / or communicate with) one or more storage devices (925), which may include, without limitation, local and / or network-accessible storage and / or, without limitation, programmable, flash-updatable and / or similar solid-state storage devices such as disk drives, drive arrays, optical storage devices, random access memory (“RAM”) and / or read-only memory (“ROM”). The computing system (900) may also include, without limitation, a communication subsystem (930), which may include a modem, a network card (wireless or wired), an infrared communication device, a wireless communication device and / or a chipset (e.g., a Bluetooth device, an 802.6 device, a Wi-Fi device, a WiMAX device, a cellular communication facility, etc.). The communication subsystem (930) may be capable of exchanging data with a network (e.g., a network described below) and / or any other device described herein. In many embodiments, the computing system (900) may further include a working memory (935) that may include a RAM or ROM device as described above.

[0126] The computing system (900) may also include software elements depicted as being located within the current working memory (935), including code such as an operating system (940) and / or one or more other application programs (945) that may be designed to implement the method of the present invention and / or constitute the system of the present invention as described herein. For example, one or more procedures described in relation to the method discussed above may be implemented as code and / or instructions executable by a computer (and / or a processor within the computer). A set of these instructions and / or code may be stored in a computer-readable storage medium such as the storage device (925) described above.

[0127] In some cases, the storage medium may be integrated within the computing system (900) or may communicate with the computing system (900). In other embodiments, the storage medium may be detachable from the computing system (900) (e.g., removable media such as a compact disk, etc.) or provided as an installation package, so that the storage medium may be used to program a general-purpose computer with instructions / code stored therein. These instructions may take the form of executable code that can be executed by the computing system (900) and / or take the form of source and / or installable code, which takes the form of executable code when compiled and / or installed on the computing system (900) (e.g., using various commonly available compilers, installers, compression / decompression utilities, etc.).

[0128] Numerous specific details have been described herein to provide a thorough understanding of the subject matter claimed. However, those skilled in the art will understand that the subject matter claimed may be practiced without these specific details. In other examples, methods, apparatuses, or systems known to those skilled in the art have not been described in detail so as not to obscure the subject matter claimed.

[0129] Some parts are provided in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within the memory of a computing system, such as computer memory. These algorithmic descriptions or representations are examples of techniques used by ordinary technicians of data processing technology to convey the nature of the work to those skilled in the art. An algorithm is a coherent sequence of operations or similar processes leading to a desired result. In this context, the operation or process involves the physical manipulation of physical quantities. Generally, but not necessarily, these physical quantities may take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, or manipulated. It has proven convenient, primarily for general use, to refer to signals as bits, data, values, elements, symbols, characters, terms, numbers, numerical values, etc. However, it must be understood that these and similar terms are merely convenient labels and must be associated with the appropriate physical quantities. Unless otherwise specifically stated, descriptions throughout this specification using terms such as “processing,” “computing,” “calculation,” “decision,” and “identification” refer to the operation or process of a computing device, such as one or more computers or similar electronic computing devices or devices, which manipulates or converts data represented as physical, electronic, or magnetic quantities within memory, registers, or other information storage devices, transmission devices, or display devices of a computing platform.

[0130] The system or system described herein is not limited to a specific hardware architecture or configuration. A computing device may include any suitable arrangement of components that provide a coordinated result for one or more inputs. A suitable computing device includes a general-purpose microprocessor-based computer system that accesses stored software to program or configure a computing system from a general-purpose computing device to a specialized computing device that implements one or more embodiments of the subject matter. Any suitable programming, scripting, or other type of language or combination of languages ​​may be used to implement the instructions contained herein in the software used to program or configure the computing device.

[0131] Embodiments of the method disclosed herein may be performed in the operation of such computing devices. The order of the blocks presented in the above examples may be changed. For example, blocks may be rearranged, combined, and / or divided into sub-blocks. Specific blocks or processes may be performed in parallel.

[0132] In this specification, the terms “adapted” or “configured” are used in an open and inclusive manner, not excluding devices adapted or configured to perform additional operations or steps. Furthermore, the use of “based” is used in an open and inclusive manner in that a process, step, calculation, or other operation “based” on one or more mentioned conditions or values ​​may actually be based on additional conditions or values ​​beyond those mentioned. The headings, lists, and numbering included in this specification are for convenience of description only and are not limiting.

[0133] Although the gist of the invention has been described in detail with respect to specific embodiments thereof, those skilled in the art will understand that modifications, variations, and equivalents to such embodiments can be easily obtained by understanding the foregoing. Accordingly, it should be understood that the present disclosure is presented for illustrative purposes rather than for limitation, and does not exclude such modifications, changes, and / or additions to the subject matter as will be apparent to those skilled in the art.

Claims

Claim 1 A power system having a plasma load, comprising: a first high-voltage pulser outputting a first plurality of pulses having a first voltage greater than 1 kV, a first pulse width less than 1 μs, and a first pulse repetition frequency greater than 20 kHz; a second high-voltage pulser outputting a second plurality of pulses having a second voltage greater than 1 kV, a second pulse width less than 1 μs, and a second pulse supplementary frequency greater than 20 kHz; a chamber; a first electrode disposed within the chamber and electrically coupled to the first high-voltage pulser; and a second electrode disposed within the chamber adjacent to the first electrode and electrically coupled to the second high-voltage pulser. Claim 2 A system according to claim 1, wherein the chamber comprises one or both of a wafer and a plasma capacitively coupled with the first electrode and the second electrode with a capacitance between 10 pF and 1 μF. Claim 3 A system according to claim 1, wherein the electric field at both ends of the surface of a wafer placed within the chamber is uniform within 25%. Claim 4 A system according to claim 1, wherein the coupling capacitance between the first electrode and the corresponding portion of the wafer disposed within the chamber is greater than 100 pF; and the capacitance between the second electrode and the corresponding portion of the wafer is greater than 100 pF. Claim 5 A system according to claim 1, wherein the chamber comprises a plasma of ions accelerated onto a wafer disposed within the chamber. Claim 6 A system according to claim 1, wherein the first high-voltage pulser generates an electrode voltage on a first electrode greater than 1 kV, and the second high-voltage pulser generates an electrode voltage on a second electrode greater than 1 kV. Claim 7 A system according to claim 1, wherein the ratio of the first voltage to the second voltage is less than 2 to 1 or vice versa. Claim 8 A system according to claim 1, wherein one or both of the first electrode and the second electrode are axially symmetric. Claim 9 A system according to claim 1, wherein the first electrode has a first planar surface and the second electrode has a second planar surface such that the second planar surface is 25% of the total sum of the first planar surface and the second planar surface. Claim 10 A system according to claim 1, wherein both the first high-voltage pulser and the second high-voltage pulser comprise a resistive output terminal. Claim 11 A system according to claim 1, wherein both the first high-voltage pulser and the second high-voltage pulser include an energy recovery circuit. Claim 12 A system according to claim 1, wherein the parameters of the first plurality of pulses are controlled independently of the parameters of the second plurality of pulses. Claim 13 A system according to claim 1, wherein the first pulse repetition frequency and the second pulse repetition frequency are in phase with each other. Claim 14 A system according to claim 1, wherein the coupling capacitance between the first electrode and the second electrode is less than 10 nF. Claim 15 A system according to claim 1, wherein the first electrode comprises: a disk shape, a central axis, and an outer diameter, and the second electrode comprises: a disk shape having a central hole - the first electrode is disposed within the central hole - a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter. Claim 16 A system comprising: a wafer platform; a first electrode having a disk shape, a central axis, and an outer diameter; a disk shape having a central hole - said first electrode disposed within the central hole -, a second electrode having a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter; a first high-voltage pulser electrically coupled to the first electrode - said first high-voltage pulser generates a pulse greater than 5 kV at a pulse repetition frequency greater than 10 kHz -; and a second high-voltage pulser electrically coupled to the second electrode - said second high-voltage pulser generates a pulse greater than 5 kV at a pulse repetition frequency greater than 10 kHz -. Claim 17 In claim 16, the wafer platform is a system having an outer diameter substantially similar to the outer diameter of the second electrode. Claim 18 In claim 16, the system wherein the second high-voltage pulser provides a pulse having an amplitude that is a part of the amplitude of the pulse provided by the first high-voltage pulser. Claim 19 In claim 16, the system wherein the second high-voltage pulser provides a pulse having a pulse repetition frequency that is part of the pulse repetition frequency of the pulse provided by the first high-voltage pulser. Claim 20 A system according to claim 16, further comprising: a first resistive output terminal coupled to the first high-voltage pulser and the first electrode; and a second resistive output terminal coupled to the second high-voltage pulser and the second electrode. Claim 21 A system according to claim 16, further comprising a bias compensation circuit coupled to the first high-voltage pulser and the first electrode. Claim 22 A system according to claim 16, further comprising a ring of insulating material disposed between the first electrode and the second electrode. Claim 23 In claim 16, the wafer platform comprises a dielectric material or a ceramic material, in a system. Claim 24 A method comprising: a step of pulsing a first high-voltage pulse coupled to a first electrode in a plasma chamber, wherein the first high-voltage pulse is pulsed with a first voltage greater than 1 kV, a first pulse repetition frequency greater than 20 kHz, and a first pulse width; a step of pulsing a second high-voltage pulse coupled to a second electrode in the plasma chamber, wherein the second high-voltage pulse is pulsed with a second voltage greater than 1 kV, a second pulse repetition frequency greater than 20 kHz, and a second pulse width, and wherein the first electrode and the second electrode are disposed below a wafer; a step of measuring a parameter corresponding to a physical phenomenon occurring within the plasma chamber; and a step of adjusting at least one of the second voltage, the second pulse repetition frequency, and the second pulse width based on the measured parameter. Claim 25 In claim 24, the physical phenomenon occurring within the plasma chamber corresponds to the uniformity of the electric field across the surface of the wafer. Claim 26 In claim 24, the physical phenomenon occurring within the plasma chamber corresponds to the uniformity of the ion current across the surface of the wafer. Claim 27 In claim 24, the method wherein the parameter is the current flowing through the resistor of the first high-voltage pulser.

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