Image sensor

Abstract

An image sensor is provided. The image sensor comprises: a substrate including a first surface and a second surface opposite to each other; a pixel separation unit penetrating the substrate and separating into a plurality of pixels, having a planar grid shape, wherein the pixels each form first to third pixel groups arranged in n columns and m rows, and n and m are each independently natural numbers greater than or equal to 2; a light-blocking grid disposed on the first surface and overlapping with the pixel separation unit; and a light-controlling unit disposed on the first surface and overlapping with the pixel separation unit at the center of each of the first to third pixel groups, wherein the light-blocking grid has a first width in a first direction, and the light-controlling unit has a second width in the first direction that is greater than the first width.

Description

Technology Field

[0001] The present invention relates to an image sensor. Background Technology

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor can be classified into a Charge Coupled Device (CCD) type and a Complementary Metal Oxide Semiconductor (CMOS) type. The CMOS type image sensor is abbreviated as a CIS (CMOS image sensor). The CIS comprises a plurality of pixels arranged in a two-dimensional manner. Each of the pixels includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide an image sensor capable of realizing clear image quality.

[0004] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] An image sensor according to embodiments of the present invention for achieving the above objective comprises: a substrate including a first surface and a second surface opposite to each other; a pixel separation unit penetrating the substrate and separating into a plurality of pixels, having a planar grid shape, wherein the pixels each form first to third pixel groups arranged in n columns and m rows, and n and m are each independently natural numbers greater than or equal to 2; a light-blocking grid disposed on the first surface and overlapping with the pixel separation unit; and a light regulator disposed on the first surface and overlapping with the pixel separation unit at the center of each of the first to third pixel groups, wherein the light-blocking grid has a first width in a first direction, and the light regulator has a second width in the first direction that is greater than the first width.

[0006] An image sensor according to one embodiment of the present invention comprises: a substrate including a first surface and a second surface opposite to each other; a pixel separation unit penetrating the substrate and separating into a plurality of pixels, having a planar grid shape, wherein the pixels each constitute first to third pixel groups arranged in n columns and m rows, and n and m are each independently natural numbers greater than or equal to 2, and the pixel separation unit includes a polysilicon pattern and an insulating film surrounding the same; a transmission gate disposed on the second surface; a floating diffusion region adjacent to the second surface and disposed next to the transmission gate; a light-blocking grid disposed on the first surface and overlapping with the pixel separation unit; a light controller disposed on the first surface and overlapping with the pixel separation unit at the center of each of the first to third pixel groups; and a color filter disposed between the light controller and the light-blocking grid. Micro lenses are disposed on the color filter, the light-blocking grid, and the light controller, each corresponding to the first to third pixel groups, wherein the light-blocking grid has a first width in a first direction, the light controller has a second width in the first direction that is greater than the first width, and the top of the light controller is located at a distance of 1 / 3 to 2 / 3 of the radius of curvature of the micro lens from the top of the micro lens.

[0007] An image sensor according to another aspect of the present invention comprises: a substrate including a first surface and a second surface opposite to each other; a pixel separation part penetrating the substrate and separating into a plurality of pixels, having a planar grid shape, wherein the pixels each constitute first to third pixel groups arranged in n columns and m rows, and n and m are each independently natural numbers greater than or equal to 2; and a light-blocking grid disposed on the first surface and overlapping with the pixel separation part. and includes a light controller disposed on the first plane and overlapping with the pixel separation part at the center of each of the first to third pixel groups, wherein the light-blocking grid has a first width in a first direction and the light controller has a second width in the first direction that is greater than the first width, the light-blocking grid has a first light-blocking pattern and a first low-refractive pattern stacked in sequence, the light controller has a second light-blocking pattern and a second low-refractive pattern stacked in sequence, the first light-blocking pattern and the second light-blocking pattern include the same metal, and the first low-refractive pattern and the second low-refractive pattern include the same dielectric material. Effects of the invention

[0008] The image sensor according to the present invention includes a light controller capable of controlling the path of light, thereby preventing light from being incident on a polysilicon pattern included within a pixel separation unit located at the center of a pixel group. This improves quantum efficiency, enabling the realization of sharp image quality in the image sensor. Additionally, it can provide excellent autofocus capabilities. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram illustrating an image sensor according to embodiments of the present invention. FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to embodiments of the present invention. FIG. 3a is a plan view of an image sensor according to embodiments of the present invention. FIG. 3b is a plan view of a pixel group of an image sensor according to embodiments of the present invention. FIG. 4a is a cross-sectional view of FIG. 3a taken along line A-A' according to embodiments of the present invention. Figure 4b shows the path of light from the image sensor of Figure 4a. FIGS. 5A and FIGS. 5B are cross-sectional views sequentially illustrating the manufacturing process of an image sensor having the cross-section of FIG. 4A. FIGS. 6a to 6d show partial plan views of an image sensor according to embodiments of the present invention. FIGS. 7A and FIGS. 7B show plan views of an image sensor according to embodiments of the present invention. FIGS. 8a to 8e are cross-sectional views of FIG. 3a taken along line A-A' according to embodiments of the present invention. FIG. 9 is a cross-sectional view of an image sensor according to embodiments of the present invention. FIG. 10 is a cross-sectional view of FIG. 3a taken along line A-A' according to embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0012] FIG. 1 is a block diagram illustrating an image sensor according to embodiments of the present invention.

[0013] Referring to FIG. 1, the image sensor may include an active pixel sensor array (1001), a row decoder (1002), a row driver (1003), a column decoder (1004), a timing generator (1005), a correlated double sampler (CDS; 1006), an analog to digital converter (ADC; 1007), and an input / output buffer (I / O buffer; 1008).

[0014] The active pixel sensor array (1001) includes a plurality of unit pixels arranged in two dimensions and can convert an optical signal into an electrical signal. The active pixel sensor array (1001) can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver (1003). Additionally, the converted electrical signal can be provided to a correlation double sampler (1006).

[0015] The row driver (1003) can provide a plurality of driving signals to the active pixel sensor array (1001) to drive a plurality of unit pixels according to the result decoded by the row decoder (1002). If the unit pixels are arranged in a matrix form, driving signals can be provided for each row.

[0016] The timing generator (1005) can provide timing signals and control signals to the row decoder (1002) and the column decoder (1004).

[0017] A correlated dual sampler (CDS; 1006) can receive, hold, and sample an electrical signal generated from an active pixel sensor array (1001). The correlated dual sampler (1006) can double-sample a specific noise level and a signal level by an electrical signal to output a difference level corresponding to the difference between the noise level and the signal level.

[0018] An analog-to-digital converter (ADC; 1007) can convert an analog signal corresponding to the difference level output from a correlated double sampler (1006) into a digital signal and output it.

[0019] The input / output buffer (1008) latches a digital signal, and the latched signal can sequentially output the digital signal to an image signal processing unit (not shown in the drawing) according to the decoding result in the column decoder (1004).

[0020] FIG. 2 is a circuit diagram of an active pixel sensor array of an image sensor according to embodiments of the present invention.

[0021] Referring to FIGS. 1 and 2, the sensor array (1001) includes a plurality of pixels (PX), and the pixels (PX) may be arranged in a matrix form. Each pixel (PX) may include a transfer transistor (TX) and logic transistors (RX, SX, DX). The logic transistors may include a reset transistor (RX), a select transistor (SX), and a source follower transistor (DX). The transfer transistor (TX) may include a transfer gate (TG). Each pixel (PX) may further include a photoelectric conversion element (PD) and a floating diffusion region (FD).

[0022] A photoelectric conversion device (PD) can generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion device (PD) may include a photodiode, a phototransistor, a photogate, a pinned photodiode, and combinations thereof. A transfer transistor (TX) can transfer the charge generated in the photoelectric conversion device (PD) to a floating diffusion region (FD). The floating diffusion region (FD) can receive the charge generated in the photoelectric conversion device (PD) and store it cumulatively. A source follower transistor (DX) can be controlled according to the amount of photocharges accumulated in the floating diffusion region (FD).

[0023] The reset transistor (RX) can periodically reset the charges accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) is connected to the floating diffusion region (FD), and the source electrode can be connected to the power supply voltage (VDD). When the reset transistor (RX) is turned on, the power supply voltage (VDD) connected to the source electrode of the reset transistor (RX) can be applied to the floating diffusion region (FD). Therefore, when the reset transistor (RX) is turned on, the charges accumulated in the floating diffusion region (FD) are discharged, and the floating diffusion region (FD) can be reset.

[0024] The source follower transistor (DX) can function as a source follower buffer amplifier. The source follower transistor (DX) can amplify the potential change in the floating diffusion region (FD) and output it to the output line (Vout).

[0025] The select transistor (SX) can select pixels (PX) to be read row by row. When the select transistor (SX) is turned on, the power supply voltage (VDD) can be applied to the drain electrode of the source follower transistor (DX).

[0027] FIG. 3a is a plan view of an image sensor according to embodiments of the present invention. FIG. 3b is a plan view of a pixel group of an image sensor according to embodiments of the present invention. FIG. 4a is a cross-sectional view of FIG. 3a cut along the line A-A' according to embodiments of the present invention. FIG. 4b shows the path of light in the image sensor of FIG. 4a.

[0028] Referring to FIGS. 3a, 3b, and 4a, the image sensor (500) according to the present example may include a semiconductor substrate (1). The semiconductor substrate (1) may be a silicon single-crystal wafer or a silicon epitaxial layer. The semiconductor substrate (1) may be doped with an impurity of a first conductivity type. The first conductivity type may be, for example, a P-type, and the impurity may be boron. The semiconductor substrate (1) may include a first surface (1a) and a second surface (1b) facing each other.

[0029] A shallow device isolation portion (2) may be disposed adjacent to a first surface (1a) of a semiconductor substrate (1). The shallow device isolation portion (2) may define active regions for transistors disposed on the first surface (1a). The shallow device isolation portion (2) may be formed by a Shallow Trench Isolation (STI) process. The shallow device isolation portion (2) may have a single film or multiple film structure of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0030] A pixel separation unit (DTI) is disposed on the semiconductor substrate (1) to separate pixels (PX) from each other. The pixel separation unit (DTI) may be disposed within a deep trench (7). The deep trench (7) may be formed from the first surface (1a) toward the second surface (1b). The deep trench (7) may be formed penetrating the shallow component separation unit (2) and the semiconductor substrate (1). The width of the deep trench (7) may become narrower from the first surface (1a) toward the second surface (1b).

[0031] The pixel separation unit (DTI) may include an impurity-doped polysilicon pattern (51), a side insulating film (55) surrounding the sidewalls thereof, and a buried insulating pattern (4). Since the polysilicon pattern (51) has a thermal expansion coefficient nearly equal to that of the semiconductor substrate (1) made of a silicon single crystal, it can reduce physical stress caused by the difference in thermal expansion coefficients of the materials. Additionally, the polysilicon pattern (51) can serve as a common bias line. A negative voltage may be applied to the polysilicon pattern (51). This can improve dark current characteristics by trapping holes that may exist on the surface of the deep trench (7). The side insulating film (55) and the buried insulating pattern (4) may each independently have a single-film or multi-film structure of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0032] A transfer transistor (TX), as described with reference to FIG. 2, may be disposed on the first surface (1a) at each pixel (PX). Additionally, at least one of logic transistors (RX, SX, DX) may be disposed at each pixel (PX). The logic transistors (RX, SX, DX) may be shared among adjacent pixels (PX). The transfer transistor (TX) may include a transfer gate (TG), a gate insulating film (GO), and a floating diffusion region (FD) disposed next to it.

[0033] The transmission gate (TG) may have a vertical type shape in which a portion is inserted into the substrate (1). Alternatively, the transmission gate (TG) may have a planar type shape. The gate insulating film (GO) may include, for example, at least one of silicon oxide, silicon nitride, and a high dielectric film. The high dielectric film may include an insulating material having a dielectric constant higher than that of silicon oxide. The transmission gate (TG) may include a conductive film. The floating diffusion region (FD) may be doped with an impurity of a second conductivity type opposite to the first conductivity type. Although the floating diffusion region (FD) is shown in FIG. 4a as being placed in each pixel (PX), the floating diffusion region (FD) may be shared among adjacent pixels (PX). In this case, the floating diffusion region (FD) may be located between adjacent pixels (PX) or at the center of a pixel group (GP1~GP3).

[0034] A ground region (GR) may be disposed within the substrate (1) adjacent to the first surface (1a) at each pixel (PX). The ground region (GR) may be doped with an impurity of the first conductivity type doped in the substrate (1), and may be doped at a higher concentration than the concentration of the impurity doped in the substrate (1).

[0035] In each pixel (PX), a photoelectric conversion unit (PD) may be disposed within the substrate (1). The photoelectric conversion unit (PD) may be a region doped with an impurity of a second conductivity type opposite to the first conductivity type. For example, the photoelectric conversion unit (PD) may be doped with N-type arsenic or phosphorus. The photoelectric conversion unit (PD) may form a photodiode by forming a PN junction with the surrounding semiconductor substrate (1).

[0036] The first surface (1a) of the semiconductor substrate (1) may be covered with an interlayer insulating film (IL). The interlayer insulating film (IL) may include a single film or multiple film structure among at least one silicon oxide film, silicon oxynitride film, silicon nitride film, and porous insulating film. Multilayer wiring (5) may be disposed within the interlayer insulating film (IL).

[0037] The pixels (PX) can be arranged two-dimensionally along a first direction (X) and a second direction (Y) as in FIG. 3a. Four pixels (PX) in a 2x2 array that are adjacent to each other and consist of two columns and two rows can form a pixel group (GP1~GP3). Each pixel group (GP1~GP3) can be covered by a corresponding color filter (CF1~CF3) and a micro lens (ML). That is, a first pixel group (GP1) containing four pixels (PX) consisting of two columns and two rows can be covered by one first color filter (CF1) and one micro lens (ML). A second pixel group (GP2) containing four pixels (PX) consisting of two columns and two rows can be covered by one second color filter (CF2) and one micro lens (ML). A third pixel group (GP3) comprising four pixels (PX) arranged in two columns and two rows may be covered by one third color filter (CF3) and one micro lens (ML). The lower portions of the micro lenses (ML) may be connected to each other. The color filters (CF1 to CF3) may each have one of green, red, and blue. For example, the first color filter (CF1) may be red, the second color filter (CF2) may be blue, and the third color filter (CF3) may be green.

[0038] The image sensor (500) can perform an autofocus function by detecting light entering through a micro lens (ML) placed over a pixel group (GP1~GP3) at four pixels (PX). In addition, since the four pixels (PX) constituting the pixel group (GP1~GP3) are separated by a pixel separation unit (DTI), blooming between adjacent pixels (PX) can be prevented. This enables excellent autofocus performance and the realization of clear image quality. The image sensor (500) may be an autofocus image sensor. In this example, four pixels (PX) in a 2x2 array constitute a pixel group (GP1~GP3), but the present invention is not limited thereto. That is, pixels (PX) in an nxm array may form a pixel group (GP1~GP3), where n and m may each independently be natural numbers greater than or equal to 2.

[0039] A fixed charge film (15) may be interposed between the color filters (CF1~CF3) and the second surface (1b). The fixed charge film (15) may be in contact with the second surface (1b). The fixed charge film (15) may have a negative fixed charge. The fixed charge film (15) may be made of a metal oxide or metal fluoride comprising at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanide. For example, the fixed charge film (15) may be a hafnium oxide film or an aluminum oxide film. At this time, hole accumulation may occur around the fixed charge film (15). This can effectively reduce the occurrence of dark current and white spots.

[0040] Although not illustrated, an anti-reflective film, a planarization film, etc. may be additionally disposed between the color filters (CF1~CF3) and the fixed charge film (15). The anti-reflective film (46) may include, for example, silicon oxide or silicon nitride. The planarization film may include silicon oxide.

[0041] A light-blocking grid (WG) may be placed on the fixed charge film (15). The light-blocking grid (WG) may overlap with the pixel separation unit (DTI) located between the pixel groups (GP1 to GP3). A light regulator (LS) may be placed on the fixed charge film (15) at the center of each pixel group (GP1 to GP3) and overlap with the pixel separation unit (DTI). The light regulator (LS) may be spaced apart from the light-blocking grid (WG).

[0042] The light regulator (LS) may overlap with the center of the microlens (ML) placed thereon. For example, the center of the light regulator (LS) may overlap with the center of the microlens (ML) placed thereon. The light regulator (LS) may be covered by the corresponding color filters (CF1 to CF3). The light-blocking grid (WG) may be covered by adjacent color filters (CF1 to CF3).

[0043] The light-blocking grid (WG) may include a first light-blocking pattern (17a) and a first low-refractive index pattern (25a) stacked in sequence. The light controller (LS) may include a second light-blocking pattern (17b) and a second low-refractive index pattern (25b) stacked in sequence. The first light-blocking pattern (17a) and the second light-blocking pattern (17b) may include the same thickness and the same metal. For example, the first light-blocking pattern (17a) and the second light-blocking pattern (17b) may include titanium or tungsten. The first low-refractive index pattern (25a) and the second low-refractive index pattern (25b) may include the same dielectric material. The first low-refractive index pattern (25a) and the second low-refractive index pattern (25b) may have a refractive index smaller than the refractive index of the color filters (CF1~CF3). Preferably, the first low-refractive index pattern (25a) and the second low-refractive index pattern (25b) have a refractive index of 1.3 or less. Thus, as shown in FIG. 4bc, incident light (L1, L2) is refracted by the light regulator (LS) and incident on the photoelectric conversion unit (PD) of the corresponding pixel (PX).

[0044] As shown in FIG. 4a, the light-blocking grid (WG) may have a first width (WT1). The light controller (LS) may have a second width (WT2) that is wider than the first width (WT1). For example, the second width (WT2) may be 2 to 4 times the first width (WT1). The light controller (LS) may have a cross shape in planar form as shown in FIG. 3a and 3b. The second width (WT2) of the light controller (LS) may be wider than the width of the pixel separation unit (DTI). The light controller (LS) may completely cover the pixel separation unit (DTI) located at the center of each of the pixel groups (GP1 to GP3). The light controller (LS) may have a (rectangular) cross-section.

[0045] As shown in FIG. 4a, the upper surface of the light-blocking grid (WG) may have a first level (LV1). The upper surface of the light regulator (LS) may have a second level (LV2). In this example, the second level (LV2) may be equal to the first level (LV1). The upper surface of the light regulator (LS) may be located at or near the focal length of the microlens (ML). Preferably, the distance (DS2) from the top of the microlens (ML) to the upper surface of the light regulator (LS) may be located at 1 / 3 to 2 / 3 of the radius of curvature (DS1) of the microlens (ML). Thus, as shown in FIG. 4b, light (L1, L2) incident through the microlens (ML) is scattered by the light regulator (LS) and incident on the photoelectric converter (PD). This prevents light (L1, L2) from being incident on the polysilicon pattern (51) located within the pixel separation unit (DTI) below the light controller (LS). Since polysilicon has the property of absorbing light, light loss occurs when light is incident on the polysilicon pattern (51), and this can reduce the quantum efficiency (incident photon signal electron conversion efficiency). In the present invention, the quantum efficiency can be improved by the light controller (LS). This increases the amount of light in the image sensor and improves light sensitivity, thereby enabling the realization of clear image quality. Additionally, excellent autofocus capabilities can be provided.

[0047] FIGS. 5A and FIGS. 5B are cross-sectional views sequentially illustrating the manufacturing process of an image sensor having the cross-section of FIG. 4A.

[0048] Referring to FIG. 5a, a substrate (1) having a first surface (1a) and a second surface (1b) opposite each other is prepared. Through a conventional process, a shallow device isolation section (2) and a pixel isolation section (DTI) are formed on the substrate (1) to define pixels (PX). The pixel isolation section (DTI) may be formed to include an impurity-doped polysilicon pattern (51), a side insulating film (55) surrounding the sidewalls thereof, and a buried insulating pattern (4). The side insulating film (55) may be formed to cover the bottom surface of a deep trench (7). The side insulating film (55) may be formed to be spaced apart from the second surface (1b). A photoelectric conversion section (PD) is formed within the substrate (1) at each pixel (PX). A transmission gate (TG), a gate insulating film (GO), a floating diffusion region (FD) and a ground region (GR) are formed on the first surface (1a). Multilayer wiring (5) and an interlayer insulating film (IL) are formed on the first surface (1a). The substrate (1) is flipped so that the second surface (1b) faces upward.

[0049] Referring to FIG. 5b, a back grinding process is performed on the second surface (1b) of the substrate (1) to remove a portion of the substrate (1) and a portion of the side insulating film (55) to expose the polysilicon pattern (51) of the pixel separation unit (DTI). A fixed charge film (15) is formed on the second surface (1b) of the substrate (1). Then, a light-blocking film and a low-refractive film are sequentially stacked on the fixed charge film (15), and then the low-refractive film and the light-blocking film are sequentially etched to form a light-blocking grid (WG) and a light controller (LS), and the fixed charge film (15) is exposed. The light-blocking grid (WG) may include a first light-blocking pattern (17a) and a first low-refractive pattern (25a) that are sequentially stacked. The light regulator (LS) may include a second light-blocking pattern (17b) and a second low-refractive index pattern (25b) stacked in sequence. The light regulator (LS) may be formed to overlap with a pixel separation part (DTI) at the center of each pixel group (GP1 to GP3). The light regulator (LS) may be formed to have a cross shape in planar form as in FIG. 3a.

[0050] In the present invention, a light regulator (LS) can be formed simultaneously when forming a light-blocking grid (WG). This eliminates the need for a separate process to form the light regulator (LS), thereby simplifying the process.

[0051] Subsequently, with reference to FIGS. 3a and FIGS. 4a, color filters (CF1 to CF3) are formed on the fixed charge film (15). One of the color filters (CF1 to CF3) is formed to cover a corresponding pixel group (GP1 to GP3). The color filters (CF1 to CF3) can cover a light-blocking grid (WG) and a light controller (LS). A microlens (ML) is formed on each of the color filters (CF1 to CF3).

[0052] FIGS. 6a to 6d show partial plan views of an image sensor according to embodiments of the present invention.

[0053] Referring to FIG. 6a, the light controller (LS) according to the present example may have a circular shape in planar form. The light controller (LS) may be spaced apart from the light-blocking grid (WG), and a pixel separation unit (DTI) may be exposed between them.

[0054] Alternatively, referring to FIG. 6b, the light regulator (LS) may have a cross shape in planar form. The light regulator (LS) may be connected to the light-blocking grid (WG) by a grid protrusion (WGP). The grid protrusion (WGP) overlaps with the pixel separation unit (DTI). In this case, the pixel separation unit (DTI) is not exposed between the light regulator (LS) and the light-blocking grid (WG). The light regulator (LS), the grid protrusion (WGP), and the light-blocking grid (WG) may be formed as a single unit, and there may be no boundary area between them.

[0055] Alternatively, referring to FIG. 6c, the light regulator (LS) may have a cross shape in planar form. The light regulator (LS) may have an empty space (CV) inside. The empty space (CV) may overlap with the center of a pixel group (GP1 to GP3). The light regulator (LS) may be spaced apart from the light-blocking grid (WG), and a pixel separation part (DTI) may be exposed between them.

[0056] Alternatively, referring to FIG. 6d, the light regulator (LS) may have a planar rectangular, pyramidal, or rhombus shape. The light regulator (LS) may be spaced apart from the light-blocking grid (WG), and a pixel separation unit (DTI) may be exposed between them.

[0058] FIGS. 7A and FIGS. 7B show plan views of an image sensor according to embodiments of the present invention.

[0059] Referring to FIG. 7a, the image sensor (501) according to the present example may include various types of light controllers (LS1 to LS4). Each of the light controllers (LS1 to LS4) is spaced apart from the light-blocking grid (WG). For example, a cross-shaped first light controller (LS1) disclosed in FIG. 3b may be placed at the center of the first pixel group (GP1) located at the rearmost and first from the left in FIG. 7a. A circular second light controller (LS2) disclosed in FIG. 6a may be placed at the center of the third pixel group (GP3) located at the rearmost and second from the left in FIG. 7a. A rhombus-shaped third light controller (LS3) disclosed in FIG. 6d may be placed at the center of the first pixel group (GP1) located at the rearmost and third from the left in FIG. 7a. In FIG. 7a, a cross-shaped fourth light modulator (LS4) having an internal empty space (CV) as disclosed in FIG. 6c may be placed at the center of the third pixel group (GP3), which is located at the very back and fourth from the left. The positions of the light modulators (LS1 to LS4) may vary for each column or each row.

[0060] Referring to FIG. 7a, the image sensor (502) according to the present example may have light controllers (LS) connected to a light-blocking grid (WG) by grid protrusions (WGP). The image sensor (502) of FIG. 7a has a form in which a plurality of pixel groups (GP1~GP3) disclosed in FIG. 6b are provided and arranged two-dimensionally.

[0062] FIGS. 8a to 8e are cross-sectional views of FIG. 3a taken along line A-A' according to embodiments of the present invention.

[0063] Referring to FIG. 8a, in the image sensor (503) according to the present example, the upper surface of the light-blocking grid (WG) may have a first level (LV1). The upper surface of the light controller (LS) may have a second level (LV2). In the present example, the second level (LV2) may be different from the first level (LV1). The second level (LV2) may be higher than the first level (LV1). Other configurations may be as described with reference to FIG. 4a.

[0064] Referring to FIG. 8b, in the image sensor (504) according to the present example, the light controller (LS) may have an inclined side wall. The light controller (LS) may have a triangular cross-section. Other configurations may be as described with reference to FIG. 8a.

[0065] Referring to FIG. 8c, in the image sensor (505) according to the present example, the light controller (LS) may have a void space (CV). The void space (CV) may also be referred to as an air gap region. The void space (CV) may expose the upper surface of the second light-blocking pattern (17b). The second low-refractive index pattern (25b) may define the top and side surfaces of the void space (CV). Other configurations may be as described with reference to FIG. 4a. FIG. 8c may correspond to a cross-section of FIG. 6c.

[0066] Referring to FIG. 8d, in the image sensor (506) according to the present example, the light controller (LS), the light-blocking grid (WG), and the fixed charge film (15) may be conformally covered with a gas permeable film (GSPL). The gas permeable film (GSPL) may be formed from at least one material selected from the group comprising silicon dioxide (SiO2), silicon hydrogen carbonate oxide (SiOCH), and silicon nitride carbonate (SiCN). The gas permeable film (GSPL) may have a thickness of 0.001 to 5 nm. In this case, the first and second low-refractive patterns (25a, 25b) constituting the light controller (LS) and the light-blocking grid (WG), respectively, may be air gap regions. The image sensor (506) of FIG. 8c can form the first and second low-refractive patterns (25a, 25b) in the step of FIG. 5b with a material that can be decomposed by heat or light (e.g., ultraviolet light), and then conformally form a gas permeable film (GSPL) on the first and second low-refractive patterns (25a, 25b), and then apply heat or irradiate light to the first and second low-refractive patterns (25a, 25b). As a result, the first and second low-refractive patterns (25a, 25b) are decomposed into small molecular weight gases, and these gases can escape through the gas permeable film (GSPL). As a result, the first and second low-refractive patterns (25a, 25b) can be transformed into air gap regions.

[0067] Referring to FIG. 8e, in the image sensor (507) according to the present example, a pixel separation unit (DTI) may be disposed within a deep trench (7). The deep trench (7) may be formed from a second surface (1b) toward a first surface (1a). The width of the deep trench (7) may become narrower from the second surface (1b) toward the first surface (1a). The pixel separation unit (DTI) may include a fixed charge film (9) that conformally covers the sidewall of the deep trench (7) and a buried insulating film (11) that fills the deep trench (7). The fixed charge film (9) may have a negative fixed charge. The fixed charge film (9) may be made of a metal oxide or metal fluoride comprising at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanide. For example, the fixed charge film (9) may be a hafnium oxide film or an aluminum oxide film. In this case, hole accumulation may occur around the fixed charge film (9). This can effectively reduce the occurrence of dark current and white spots. Alternatively, the buried insulating film (11) may be formed as an insulating film with good step coverage characteristics, for example, a silicon oxide film. Although not illustrated, the deep device isolation portion (13) may have a grid shape in a planar view. The fixed charge film (9) may extend onto the second surface (1b) and come into contact with the second surface (1b). The above-mentioned buried insulating film (11) can also be extended onto the above-mentioned second surface (1b).

[0068] A device isolation region (3) may be disposed within the semiconductor substrate (1) and interposed between a pixel isolation unit (DTI) and a shallow device isolation unit (2). The device isolation region (3) may be doped with an impurity of a first conductivity type. The concentration of the impurity of the first conductivity type doped in the device isolation region (3) may be higher than the concentration of the impurity of the first conductivity type doped in the semiconductor substrate (1).

[0069] An auxiliary insulating film (16) may be disposed on the above-mentioned embedded insulating film (11). The auxiliary insulating film (16) may include an anti-reflective film and / or a flattening film. The auxiliary insulating film (16) may include a silicon nitride film and / or an organic insulating film. Other configurations may be as described with reference to FIG. 4a.

[0071] FIG. 9 is a cross-sectional view of an image sensor according to embodiments of the present invention.

[0072] Referring to FIG. 9, the image sensor (508) according to the present example may have a structure in which a first sub-chip (CH1) and a second sub-chip (CH2) are bonded. The first sub-chip (CH1) may preferably perform an image sensing function. The second sub-chip (CH2) may preferably include circuits for driving the first sub-chip (CH1) or storing electrical signals generated from the first sub-chip (CH1).

[0073] The second sub-chip (CH2) may include a second substrate (100), a plurality of transistors (TR) disposed on the second substrate (100), a second interlayer insulating film (110) covering the second substrate (100), and second wiring (112) disposed within the second interlayer insulating film (110). The second interlayer insulating film (110) may have a single film or multiple film structure among at least one silicon oxide film, silicon nitride film, silicon oxynitride film, and porous insulating film. The first sub-chip (CH1) and the second sub-chip (CH2) are bonded. This allows the first interlayer insulating film (IL) and the second interlayer insulating film (110) to come into contact.

[0074] The first sub-chip (CH1) includes a first substrate (1) comprising a pad area (PAD), a connection area (CNR), an optical black area (OB), and a pixel array area (APS). The pixel array area (APS) may include a plurality of pixels (PX). A pixel separation unit (DTI) may be disposed on the first substrate (1) in the pixel array area (APS) to separate the pixels (PX). A shallow element separation unit (STI) may be disposed adjacent to a first surface (1a) on the first substrate (1). The pixel separation unit (DTI) may penetrate the shallow element separation unit (STI). A photoelectric conversion unit (PD) may be disposed within the first substrate (1) at each of the pixels (PX). A transmission gate (TG) may be disposed on the first surface (1a) of the first substrate (1) at each pixel (PX). A floating diffusion region (FD) may be disposed within the first substrate (1) on one side of the transmission gate (TG). The first surface (1a) may be covered with first interlayer insulating films (IL). Wiring (5) and contacts (CT1) may be disposed within the first interlayer insulating films (IL).

[0075] Light may not be incident into the substrate (1) in the optical black region (OB). The pixel separation unit (DTI) may extend to the optical black region (OB) to separate the first black pixel (PXO1) and the second black pixel (PXO2). A photoelectric conversion unit (PD) may be disposed within the first substrate (1) in the first black pixel (PXO1). In the second black pixel (PXO2), there is no photoelectric conversion unit (PD) within the first substrate (1). A transmission gate (TG) and a floating diffusion region (FD) may be disposed in both the first black pixel (PXO1) and the second black pixel (PXO2). The first black pixel (PXO1) may detect the amount of charge that may be generated from the photoelectric conversion unit (PD) where light is blocked, and provide a first reference charge amount. The first reference charge amount can be a relative reference value when calculating the charge amount generated from the unit pixels (IP). The second black pixel (PXO2) can provide a second reference charge amount by detecting the charge amount that may be generated in the absence of a photoelectric converter (PD). The second reference charge amount can be used as information to remove process noise.

[0076] The first fixed charge film (24), the second fixed charge film (42), the first protective film (44), and the second protective film (56) may also extend onto the second surface (1b) on the optical black region (OB), the connection region (CNR), and the pad region (PAD).

[0077] In the above connection area (CNR), the connection contact (BCA) can penetrate the first protective film (44), the second fixed charge film (44), and a portion of the first substrate (1) to come into contact with the polysilicon pattern (51p) of the pixel separation unit (DTI). The connection contact (BCA) may be located within the first trench (46). The connection contact (BCA) may include a first diffusion prevention pattern (17d) conformally covering the inner sidewall and bottom surface of the first trench (46), a first metal pattern (52) on the first diffusion prevention pattern (17d), and a second metal pattern (54) filling the first trench (46).

[0078] A portion of the first diffusion prevention pattern (17d) may extend onto the first protective film (44) on the optical black region (OB) to provide a first optical black pattern (17c). A portion of the first metal pattern (52) may extend onto the first optical black pattern (17c) on the optical black region (OB) to provide a second optical black pattern (52a). The second optical black pattern (52a) and the connection contact (BCA) may be covered by a second protective film (56). A third optical black pattern (CFB) may be located on the protective film (56) in the optical black region (OB) and the connection region (CNR).

[0079] A first via (V1) may be placed next to the connection contact (BCA) in the connection area (CNR). The first via (V1) may also be named a back bias stack via. The first via (V1) may penetrate the first protective film (44), the second fixed charge film (44), the first fixed charge film (24), the first substrate (1), the first interlayer insulating films (IL), and a portion of the second interlayer insulating film (110) to simultaneously come into contact with some of the first wirings (5) and some of the second wirings (112).

[0080] The first via (V1) may be placed inside the first via hole (H1). The first via (V1) may include a first diffusion prevention pattern (17d) and a first via pattern (52b) on the first diffusion prevention pattern (17d). The first via pattern (52b) may be connected to the first metal pattern (52). The connection contact (BCA) may be connected to some of the first wires (5) and some of the second wires (112) through the first via (V1).

[0081] The first diffusion prevention pattern (17d) and the first via pattern (52b) can each conformally cover the inner wall of the first via hole (H1). The first diffusion prevention pattern (17d) and the first via pattern (52b) may not completely fill the first via hole (H1). The first low-refractive index residue film (50b) can fill the first via hole (H1). A color filter residue film (CFR) may be placed on the first low-refractive index residue film (50b).

[0082] An external connection pad (62) and a second via (V2) connected to each other may be disposed in the pad area (PAD). The external connection pad (62) may penetrate the first protective film (44), the second fixed charge film (44), the first fixed charge film (24), and a portion of the first substrate (1). The external connection pad (62) may be disposed in the fourth trench (60). The external connection pad (62) may include the third diffusion prevention pattern (17e) and the first pad pattern (52c) that conformally cover the inner wall and bottom surface of the fourth trench (60) in sequence, and the second pad pattern (54a) that fills the fourth trench (60).

[0083] The second via (V2) may penetrate the first protective film (44), the second fixed charge film (44), the first fixed charge film (24), the first substrate (1), the first interlayer insulating films (IL), and a portion of the second interlayer insulating film (110) to come into contact with some of the second wirings (112). The external connection pad (62) may be connected to some of the second wirings (112) through the second via (V2). The second via (V2) may be placed inside the second via hole (H2). The second via (V2) may include a fourth diffusion prevention pattern (17f) and a second via pattern (52d) that conformally cover the inner wall and bottom surface of the second via hole (H2) in sequence. The fourth diffusion prevention pattern (17f) and the second via pattern (52d) do not completely fill the second via hole (H2). The second low-refractive index residue film (50c) can fill the second via hole (H2). A color filter residue film (CFR) may be placed on the second low-refractive index residue film (50c).

[0084] The first and second light-blocking patterns (17a, 17b), the first diffusion-prevention pattern (17d), the first optical black pattern (17c), and the diffusion-prevention patterns (17d–17f) may have the same thickness and the same material (e.g., titanium). The first metal pattern (52), the second optical black pattern (52a), the first via pattern (52b), the first pad pattern (52c), and the second via pattern (52d) may have the same thickness and the same material (e.g., tungsten). The second metal pattern (54) and the second pad pattern (54a) may have the same material (e.g., aluminum).

[0085] The first and second low-refractive index patterns (25a, 25b), the first low-refractive index residue film (50b), and the second low-refractive index residue film (50c) may have the same material as each other. The color filter residue film (CFR) may have the same color and material as one of the color filters (CF1, CF2).

[0086] The first light-blocking pattern (17a) and the first low-refractive index pattern (25a) can form a light-blocking grid (WG). The second light-blocking pattern (17b) and the second low-refractive index pattern (25b) can form a light regulator (LS).

[0087] The second protective layer (56) may extend to the pad area (PAD) and may have an opening that exposes the second pad pattern (54a). A micro-lens array layer (MLL) comprising a plurality of micro-lenses (ML) may extend to the optical black area (OB), the connection area (CNR), and the pad area (PAD). The micro-lens array layer (MLL) may have an opening (35) that exposes the second pad pattern (54a) in the pad area (PAD). Other structures may be the same or similar as described with reference to FIGS. 3a and FIGS. 4a.

[0089] FIG. 10 is a cross-sectional view of FIG. 3a taken along line A-A' according to embodiments of the present invention.

[0090] Referring to FIG. 10, in the image sensor (509) according to the present example, a through electrode (57) may be disposed within a semiconductor substrate (1). The through electrode (57) may be insulated from a polysilicon pattern (51) of a deep device isolation section. The through electrode (57) is surrounded by a first via insulating film (59). A via embedded insulating pattern (4a) is disposed between the through electrode (57) and the interlayer insulating film (IL). The through electrode (57), the first via insulating film (59), and the via embedded insulating pattern (4a) may be disposed within a through electrode hole (7h) disposed within the semiconductor substrate (1). A transmission gate electrode (TG) may be disposed on a first surface (1a) of the semiconductor substrate (1). A first floating diffusion region (FD1) may be disposed within the semiconductor substrate (1) adjacent to the transmission gate electrode (TG). A second floating diffusion region (FD2) separated from the first floating diffusion region (FD1) by a shallow device separation portion (2) may be disposed within the semiconductor substrate (1). A first photoelectric conversion portion (PD1) may be disposed within the semiconductor substrate (1) in unit pixel regions (UP). The first photoelectric conversion portion (PD1) may be a region doped with impurities of the second conductivity type.

[0091] A fixed charge film (15) may be disposed on the second surface (1b) of the semiconductor substrate (1). Color filters (CF1, CF2) may be disposed on the fixed charge film (15). A light-blocking grid (WG) may be disposed on the fixed charge film (15) between the color filters (CF1, CF2). A light controller (LS) may be disposed on the fixed charge film (15) at the center of the pixel group (GP1~GP3).

[0092] A first insulating film (30) may be disposed on the color filters (CF1, CF2). The first insulating film (30) may be a silicon oxide film or a silicon nitride film. Pixel electrodes (32) may be disposed on the first insulating film (30) for each pixel (PX). A second insulating film (144) may be interposed between the pixel electrodes (32). The second insulating film (144) may be a silicon oxide film or a silicon nitride film. A second photoelectric converter (PD2) may be disposed on the pixel electrodes (32). A common electrode (34) may be disposed on the second photoelectric converter (PD2). A passivation film (36) may be disposed on the common electrode (34). A microlens (ML) may be disposed on the passivation film (36).

[0093] The pixel electrode (32) and the common electrode (34) may include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO (Zinc Oxide), and / or an organic transparent conductive material. The second photoelectric conversion unit (PD2) may be, for example, an organic photoelectric conversion layer. The second photoelectric conversion unit (PD2) may include a p-type organic semiconductor material and an n-type organic semiconductor material, and the p-type organic semiconductor material and the n-type organic semiconductor material may form a pn junction. Alternatively, the second photoelectric conversion unit (PD2) may include a quantum dot or a chalcogenide.

[0094] The pixel electrode (32) may be electrically connected to the through electrode (57) by a via plug (140). The via plug (140) may include impurity-doped polysilicon, a metal nitride film such as titanium nitride, a metal material such as tungsten, titanium, copper, or a transparent conductive material such as ITO. The via plug (140) may pass through the light-shielding grid (WG) and the fixed charge film (15) to come into contact with the through electrode (57). The sidewall of the via plug (140) is covered with a second via insulating film (142). The through electrode (57) may be electrically connected to the second floating diffusion region (FD2) by a contact (CT1) and wiring (5). Other configurations may be the same or similar as described with reference to FIGS. 3a and FIGS. 4a.

[0096] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The embodiments of FIGS. 3a through 10 may be combined with one another.

Claims

Claim 1 A substrate comprising a first surface and a second surface opposite to each other; a pixel separation unit penetrating the substrate and separating into a plurality of pixels, having a planar grid shape, wherein the pixels each constitute first to third pixel groups arranged in n columns and m rows, and n and m are each independently natural numbers greater than or equal to 2; a light-blocking grid disposed on the first surface and overlapping with the pixel separation unit; and a light regulator disposed on the first surface and overlapping with the pixel separation unit at the center of each of the first to third pixel groups. An image sensor comprising micro-lenses disposed on the light-blocking grid and the light-controller and corresponding to each of the first to third pixel groups, wherein the light-blocking grid has a first width in a first direction, the light-controller has a second width in the first direction that is greater than the first width, the second width being 2 to 4 times the first width, the top of the light-controller is located at a distance of 1 / 3 to 2 / 3 of the radius of curvature of the micro-lens from the top of the micro-lens, and the light-controller is vertically superimposed with at least 4 of the pixels. Claim 2 delete Claim 3 In claim 1, the light controller is an image sensor having a planar cross, square, or circular shape. Claim 4 In claim 1, the light controller is an image sensor having a triangular or square cross-section. Claim 5 In claim 1, the light regulator is an image sensor having a cavity inside. Claim 6 An image sensor according to claim 1, wherein the light-blocking grid has a first light-blocking pattern and a first low-refractive pattern stacked in sequence, the light-blocking controller has a second light-blocking pattern and a second low-refractive pattern stacked in sequence, the first light-blocking pattern and the second light-blocking pattern include the same metal, and the first low-refractive pattern and the second low-refractive pattern include the same dielectric material. Claim 7 In claim 1, the upper part of the light regulator is an image sensor higher than the upper part of the light-blocking grid. Claim 8 An image sensor according to claim 1, further comprising a gas permeable film covering the light controller, wherein the light controller includes an air gap region. Claim 9 A substrate comprising a first surface and a second surface opposite to each other; a pixel separation unit penetrating the substrate and separating into a plurality of pixels, having a planar grid shape, wherein the pixels each constitute first to third pixel groups arranged in n columns and m rows, and n and m are each independently natural numbers greater than or equal to 2, and the pixel separation unit includes a polysilicon pattern and an insulating film surrounding the same; a transmission gate disposed on the second surface; a floating diffusion region adjacent to the second surface and disposed next to the transmission gate; a light-blocking grid disposed on the first surface and overlapping with the pixel separation unit; An image sensor comprising: a light controller positioned on a first plane and overlapping with the pixel separation part at the center of each of the first to third pixel groups; a color filter positioned between the light controller and the light-blocking grid; and micro-lenses positioned on the color filter, the light-blocking grid, and the light controller, each corresponding to the first to third pixel groups, wherein the light-blocking grid has a first width in a first direction, the light controller has a second width in the first direction that is greater than the first width, the second width being 2 to 4 times the first width, the top of the light controller is located at a distance of 1 / 3 to 2 / 3 of the radius of curvature of the micro-lens from the top of the micro-lens, and the light controller is vertically overlapping with at least four of the pixels. Claim 10 A substrate comprising a first surface and a second surface opposite to each other; a pixel separation unit penetrating the substrate and separating into a plurality of pixels, having a planar grid shape, wherein the pixels each constitute first to third pixel groups arranged in n columns and m rows, and n and m are each independently natural numbers greater than or equal to 2; a light-blocking grid disposed on the first surface and overlapping with the pixel separation unit; and a light regulator disposed on the first surface and overlapping with the pixel separation unit at the center of each of the first to third pixel groups. The image sensor comprises micro-lenses disposed on the light-blocking grid and the light-controller, each corresponding to the first to third pixel groups, wherein the light-blocking grid has a first width in a first direction, the light-controller has a second width in the first direction that is greater than the first width, the light-blocking grid has a first light-blocking pattern and a first low-refractive pattern stacked in sequence, the light-controller has a second light-blocking pattern and a second low-refractive pattern stacked in sequence, the first light-blocking pattern and the second light-blocking pattern contain the same metal, the first low-refractive pattern and the second low-refractive pattern contain the same dielectric material, the second width is 2 to 4 times the first width, the top of the light-controller is located at a distance of 1 / 3 to 2 / 3 of the radius of curvature of the micro-lens from the top of the micro-lens, and the light-controller is vertically superimposed with at least 4 pixels.

Images