Semiconductor devices having air gaps

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By integrating air gaps within the spacer structure of semiconductor devices, parasitic capacitance is minimized, improving the reliability and electrical performance of these devices as they become more integrated and miniaturized.

KR102997455B1Active Publication Date: 2026-07-29SAMSUNG ELECTRONICS CO LTD

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Patent Information

Authority / Receiving Office: KR · KR
Patent Type: Patents
Current Assignee / Owner: SAMSUNG ELECTRONICS CO LTD
Filing Date: 2021-04-22
Publication Date: 2026-07-29

AI Technical Summary

Technical Problem

The challenge of reducing parasitic capacitance between bit line structures and buried contacts in semiconductor devices without compromising device reliability is a key issue as semiconductor devices become increasingly integrated and miniaturized.

Method used

Incorporating an air gap within the spacer structure between bit line structures and buried contacts, specifically through the use of buried spacers and air gaps that expose the sides of these components, thereby reducing direct contact and minimizing parasitic capacitance.

Benefits of technology

This design effectively reduces parasitic capacitance, enhancing the reliability and electrical performance of semiconductor devices by maximizing the horizontal distance between bit line structures and buried contacts.

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Abstract

A substrate comprising a semiconductor active region; a gate electrode disposed within the substrate and extending in a first horizontal direction; a bit line structure extending across the gate electrode and intersecting the first horizontal direction in a second horizontal direction, wherein the bit line structure comprises a direct contact disposed within a contact recess of the substrate; a buried contact disposed on the substrate and connected to the active region; and a spacer structure disposed between the bit line structure and the buried contact. The spacer structure comprises a buried spacer disposed on the side of the direct contact and an air gap on the buried spacer. The air gap exposes the side of the bit line structure.

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Description

Technology Field

[0001] The technical concept of the present disclosure is to a semiconductor device having an air gap. Background Technology

[0002] In response to the demand for high integration and miniaturization of semiconductor devices, the size of these devices is also becoming finer. Consequently, high integration density is required for semiconductor memory devices used in electronic devices, leading to a reduction in design rules for their configurations. Technology is required to reduce device size without compromising reliability. The problem to be solved

[0003] The objective according to embodiments of the technical concept of the present disclosure is to provide a semiconductor device comprising a spacer structure having an air gap. means of solving the problem

[0004] A semiconductor device according to embodiments of the present disclosure may include: a substrate comprising an active region; a gate electrode disposed within the substrate and extending in a first horizontal direction; a bit line structure extending across the gate electrode and intersecting the first horizontal direction, wherein the bit line structure includes a direct contact disposed within a contact recess of the substrate; a buried contact disposed on the substrate and connected to the active region; and a spacer structure disposed between the bit line structure and the buried contact. The spacer structure may include a buried spacer disposed on the side of the direct contact and an air gap on the buried spacer. The air gap may expose the side of the bit line structure.

[0005] A semiconductor device according to embodiments of the present disclosure may include: a substrate including an active region; a gate electrode disposed within the substrate and extending in a first horizontal direction; a first bit line structure and a second bit line structure extending in a second horizontal direction that crosses the gate electrode and intersects the first horizontal direction, wherein the first bit line structure includes a direct contact disposed within a contact recess of the substrate; a buried contact connected to the active region and disposed between the first bit line structure and the second bit line structure; a landing pad on the buried contact; a first spacer structure disposed between the first bit line structure and the buried contact, wherein the first spacer structure includes a buried spacer disposed on the side of the direct contact and a first air gap on the buried spacer; and a second spacer structure disposed between the second bit line structure and the buried contact. The second spacer structure may include a second air gap on the substrate. The first air gap may expose at least one side of the first bit line structure and the buried contact.

[0006] A semiconductor device according to embodiments of the present disclosure comprises: a substrate including an active region; a gate electrode disposed within the substrate and extending in a first horizontal direction; a first bit line structure and a second bit line structure extending in a second horizontal direction that crosses the gate electrode and intersects the first horizontal direction, wherein the first bit line structure includes a direct contact disposed within a contact recess of the substrate; a buried contact connected to the active region and disposed between the first bit line structure and the second bit line structure; a landing pad on the buried contact; an insulating structure in contact with the landing pad and the first bit line structure; a first spacer structure disposed between the first bit line structure and the buried contact, wherein the first spacer structure includes a buried spacer disposed on the side of the direct contact and a first air gap on the buried spacer; A second spacer structure disposed between the second bit line structure and the buried contact, the second spacer structure includes a second air gap on the substrate; and may include a capacitor structure on the landing pad. The first air gap exposes the insulating structure, the first bit line structure, and the buried contact, and the second air gap may expose the side of the second bit line structure. Effects of the invention

[0007] According to embodiments of the present disclosure, the spacer structure includes an air gap, so that parasitic capacitance between the bit line structure and the buried contact can be reduced. Brief explanation of the drawing

[0008] FIG. 1 is a layout of a semiconductor device according to an embodiment of the present disclosure. Figure 2 is a vertical cross-sectional view along lines II' and II-II' of the semiconductor device shown in Figure 1. Figure 3 is a partial enlarged view of the semiconductor device shown in Figure 2. FIGS. 4 to 28 are plan views and vertical cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIGS. 29 to 31 are vertical cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIGS. 32 to 35 are vertical cross-sectional views of semiconductor devices according to embodiments of the present disclosure. Specific details for implementing the invention

[0009] FIG. 1 is a layout of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a vertical cross-sectional view along lines II' and II-II' of the semiconductor device shown in FIG. 1. FIG. 3 is a partial enlarged view of the semiconductor device shown in FIG. 2.

[0010] Referring to FIGS. 1 to 3, the semiconductor device (100) may include a substrate (102), a gate electrode (WL), a bit line structure (BLS), a spacer structure (SP), a buried contact (BC), a landing pad (LP), an insulating structure (174), a lower electrode (180), a capacitor dielectric layer (182), and an upper electrode (184).

[0011] The substrate (102) may include a semiconductor material. For example, the substrate (102) may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or an SOI (silicon on insulator) substrate.

[0012] The substrate (102) may include an active region (AR) and a device isolation layer (104). The device isolation layer (104) may be an insulating layer extending downward from the upper surface of the substrate (102) and may define the active regions (AR). For example, the active regions (AR) may correspond to a portion of the upper surface of the substrate (102) surrounded by the device isolation layer (104). In a plan view, the active regions (AR) may have a bar shape having a minor axis and a major axis and may be spaced apart from each other.

[0013] In the plan view, the gate electrodes (WL) extend in the x-direction and may be spaced apart from each other in the y-direction. In this specification, the x-direction and the y-direction may be referred to as the first horizontal direction and the second horizontal direction, respectively. Additionally, the gate electrodes (WL) may cross an active region (AR). For example, two gate electrodes (WL) may intersect within one active region (AR). In the cross-sectional view, the gate electrodes (WL) may be embedded within the substrate (102), for example, the gate electrodes (WL) may be placed inside a trench formed within the substrate (102). The semiconductor device (100) may further include a gate dielectric layer (107) and a gate capping layer (108) placed inside the trench. The gate dielectric layer (107) may be formed conformally to the inner wall of the trench. The gate electrode (WL) may be disposed at the bottom of the trench, and the gate capping layer (108) may be disposed on the gate electrode (WL). The upper surface of the gate capping layer (108) may be co-planar with the upper surface of the device isolation layer (104) and the region isolation layer.

[0014] The semiconductor device (100) may further include a buffer layer (110) covering the upper surface of the device isolation layer (104) and the gate capping layer (108). The buffer layer (110) may include silicon nitride.

[0015] In the plan view, the bit line structures (BLS) extend in the y-direction and may be spaced apart from each other in the x-direction. The bit line structures (BLS) may include a bit line (BL), a first capping layer (130), an insulating liner (132), and a second capping layer (134) that are sequentially stacked on the buffer layer (110).

[0016] The bit line (BL) may include a first conductive layer (120), a second conductive layer (122), and a third conductive layer (124) that are sequentially stacked on the buffer layer (110). The first conductive layer (120) may include a direct contact (DC) that penetrates the buffer layer (110) and contacts an active region (AR). For example, the direct contact (DC) may be placed inside a contact recess (R) formed on the upper surface of the substrate (102). In a plan view, the direct contact (DC) may be placed in the center of the active region (AR). The direct contact (DC) may be a part of the first conductive layer (120). The direct contact (DC) may electrically connect the active region (AR) to the bit line structure (BLS). The first conductive layer (120) may include polysilicon, and the second conductive layer (122) and the third conductive layer (124) may each include TiN, TiSiN, W, tungsten silicide, or a combination thereof.

[0017] The first capping layer (130), the insulating liner (132), and the second capping layer (134) may be sequentially stacked on the bit line (BL). For example, the first capping layer (130) may be in contact with the third conductive layer (124). The first capping layer (130), the insulating liner (132), and the second capping layer (134) may extend in the y-direction on the bit line (BL). The first capping layer (130), the insulating liner (132), and the second capping layer (134) may comprise silicon nitride. In one embodiment, the first capping layer (130), the insulating liner (132), and the second capping layer (134) may be formed integrally. The first capping layer (130), the insulating liner (132), and the second capping layer (134) may be collectively referred to as the capping layer.

[0018] Spacer structures (SP) can be placed on each side of the bit lines (BL) and can be extended in the y-direction. Additionally, the spacer structures (SP) can be extended into the contact recess (R) of the substrate (102) in a portion that overlaps perpendicularly with the direct contact (DC) and can cover the side of the direct contact (DC).

[0019] The spacer structure (SP) may include an inner spacer (140), a buried spacer (141), an upper spacer (146), and an air gap (AG). The inner spacer (140) may be in contact with the side of the bit line structure (BLS) and may include an inner lower spacer (140L) and an inner upper spacer (140U). For example, the inner lower spacer (140L) may be positioned along the inner wall of the contact recess (R) and the side of the direct contact (DC). The inner lower spacer (140L) may not completely cover the side of the direct contact (DC), and the side of the direct contact (DC) may be partially exposed. The inner upper spacer (140U) may cover the upper side of the bit line structure (BLS). For example, the inner upper spacer (140U) may partially cover the sides of the first capping layer (130), the insulating liner (132), and the second capping layer (134). The inner upper spacer (140U) may extend in the y-direction.

[0020] The buried spacer (141) may be placed inside the contact recess (R). For example, the buried spacer (141) may be formed on the inner lower spacer (140L) and may fill the contact recess (R). The upper surface of the buried spacer (141) may be co-surfaced with the upper surface of the inner lower spacer (140L). The buried spacer (141) may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0021] The upper spacer (146) may be positioned on the upper side of the bit line structure (BLS). For example, the upper spacer (146) may cover the upper and side surfaces of the inner upper spacer (140U) and may be in contact with the second capping layer (134). The upper spacer (146) may comprise silicon nitride. In some embodiments, the inner upper spacer (140U) and / or the upper spacer (146) may be omitted.

[0022] The air gap (AG) may extend in the y-direction from the side of the bit line structure (BLS) and may include a lower air gap (AG1) and an upper air gap (AG2). In the longitudinal section, the air gap (AG) may have a concave portion, and the lower part of the concave portion may be referred to as the lower air gap (AG1), and the upper part of the concave portion as the upper air gap (AG2). The lower air gap (AG1) may expose the buried contact (BC) and the bit line structure (BLS). For example, the lower air gap (AG1) may be defined by a buried spacer (141), an inner lower spacer (140L), a bit line structure (BLS), a landing pad (LP), and a silicide pattern (BCU). A portion of the buried contact (BC) and direct contact (DC) covered by the inner lower spacer (140L) may not be exposed to the lower air gap (AG1). The lower air gap (AG1) may be formed by completely removing the spacer material between the bit line structure (BLS), the landing pad (LP), and the buried contact (BC). There may be no interposed material between the bit line structure (BLS), the landing pad (LP), and the buried contact (BC). For example, at the first vertical level (L1) between the upper surface of the buried spacer (141) and the buried contact (BC), the horizontal distance between the buried contact (BC) and the bit line structure (BLS) may be equal to the horizontal width (W1) of the lower air gap (AG1). Additionally, at the second vertical level (L2) between the lower surface of the landing pad (LP) and the upper air gap (AG2), the horizontal distance between the landing pad (LP) and the bit line structure (BLS) may be equal to the horizontal width (W2) of the lower air gap (AG1). Since there is no interposed material between the bit line structure (BLS) and the buried contact (BC), the horizontal width of the lower air gap (AG1) can be maximized, and the parasitic capacitance between the buried contact (BC) and the bit line structure (BLS) can be reduced.

[0023] The upper air gap (AG2) may communicate with the lower air gap (AG1) and may be defined by a landing pad (LP), an insulating structure (174), and a bit line structure (BLS). For example, the upper air gap (AG2) may be provided between the lower air gap (AG1) and the insulating structure (174). Between the upper air gap (AG2) and the lower air gap (AG1), a portion of the landing pad (LP) may protrude horizontally toward the bit line structure (BLS).

[0024] A buried contact (BC) may be positioned between bit line structures (BLS). The upper surface of the buried contact (BC) may be located at a lower level than the upper surface of the bit line structure (BLS), and the buried contact (BC) may extend into the interior of the substrate (102). For example, the lower surface of the buried contact (BC) may be located at a lower level than the upper surface of the substrate (102) and may be in contact with an active region (AR). The semiconductor device (100) may further include fence insulating layers (not shown) that are alternately positioned with the buried contact (BC) along the y-direction in the plan view. The fence insulating layers may overlap with the gate electrodes (WL). The semiconductor device (100) may further include a silicide pattern (BCU) in contact with a landing pad (LP) on the buried contact (BC). A silicide pattern (BCU) can be formed by silicideizing the upper surface of a buried contact (BC). In one embodiment, the silicide pattern (BCU) may be omitted. The buried contact (BC) may include polysilicon, and the silicide pattern (BCU) may include metal silicide.

[0025] A landing pad (LP) may be placed on a buried contact (BC) and may be in contact with a silicide pattern (BCU). For example, the lower surface of the landing pad (LP) may be located at a lower level than the upper surface of the second capping layer (134) and may correspond to the buried contact (BC). The upper surface of the landing pad (LP) may be located at a higher level than the second capping layer (134). The landing pad (LP) may be electrically connected to an active region (AR) through the buried contact (BC). The landing pad (LP) may include a barrier pattern (150) and a conductive pattern (152) on the barrier pattern (150). The barrier pattern (150) may be conformally placed on bit line structures (BLS) and buried contacts (BC), and the conductive pattern (152) may cover the barrier pattern (150).

[0026] Insulating structures (174) may be placed between landing pads (LP) and may electrically insulate the landing pads (LP) from each other. The upper surface of the insulating structures (174) may be in a co-surface with the upper surface of the landing pad (LP). The insulating structures (174) may extend downward from the upper surface of the landing pad (LP) and come into contact with the bit line structure (BLS). The insulating structures (174) may include a lower insulating layer (170) and an upper insulating layer (172) on the lower insulating layer (170). The lower insulating layer (170) may be conformally placed along the lower surface and sides of the insulating structures (174) and may come into contact with the bit line structure (BLS). Additionally, the lower insulating layer (170) may define the upper limit of the upper air gap (AG2). The upper insulating layer (172) may fill the inner wall of the lower insulating layer (170). In one embodiment, the lower insulating layer (170) and the upper insulating layer (172) may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0027] The semiconductor device (100) may further include an insulating pattern (156) disposed between an insulating structure (174) and a landing pad (LP). The insulating pattern (156) may include silicon nitride. In one embodiment, the insulating pattern (156) may be omitted.

[0028] A capacitor structure of a semiconductor device (100) may be placed on a landing pad (LP). The capacitor structure may consist of a lower electrode (180), a capacitor dielectric layer (182), and an upper electrode (184). Each lower electrode (180) may be placed to be in contact with a corresponding landing pad (LP), and the capacitor dielectric layer (182) may be placed conformally along an insulating structure (174) and the lower electrode (180). The upper electrode (184) may be placed on the capacitor dielectric layer (182).

[0029] FIGS. 4 to 28 are plan views and vertical cross-sectional views illustrated in process order to explain a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIGS. 4, 6, 8, 10, 12, 14, 16, 18, and 20 are plan views, and FIGS. 5, 7, 9, 11, 13, 15, 17, 19, and 21 are vertical cross-sectional views along lines II' and II-II' of FIGS. 4, 6, 8, 10, 12, 14, 16, 18, and 20, respectively. FIGS. 22 to 28 are enlarged views of parts of the cross-sectional view along line I-I'.

[0030] Referring to FIGS. 4 and 5, a device isolation layer (104) and a region isolation layer may be formed on a substrate (102). The device isolation layer (104) may be formed by forming a trench on the upper surface of the substrate (102) and filling the trench with an insulating material. The device isolation layer (104) may define active regions (AR). For example, the active regions (AR) may correspond to a portion of the upper surface of the substrate (102) surrounded by the device isolation layer (104). In a plan view, the active regions (AR) may have a bar shape having a minor axis and a major axis and may be spaced apart from each other. The device isolation layer (104) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The device isolation layer (104) may be composed of a single layer or multiple layers.

[0031] Gate electrodes (WL) can be formed to cross active regions (AR) within the cell region. For example, gate electrodes (WL) can be formed by forming trenches extending in the x-direction on the upper surface of the substrate (102), forming a gate dielectric layer (107) covering the inner wall of the trench, forming a conductive material on the lower side of the trench, and forming a gate capping layer (108) on the upper side of the trench. The gate electrodes (WL) can be spaced apart from each other in the y-direction. The upper surface of the gate capping layer (108) can be co-planar with the upper surfaces of the substrate (102), the device isolation layer (104), and the region isolation layer.

[0032] The gate electrodes (WL) may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. The gate dielectric layer (107) may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric material, or a combination thereof. The gate capping layer (108) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0033] In one embodiment, after forming the gate electrodes (WL), source and drain regions may be formed by implanting impurity ions into the portions of the active region (AR) of the substrate (102) on both sides of each gate electrode (WL). In another embodiment, an impurity ion implantation process to form the source and drain regions may be performed before the gate electrodes (WL) are formed.

[0034] The buffer layer (110) may be formed to cover the device isolation layer (104), active regions (AR), and gate capping layer (108). The buffer layer (110) may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric material, or a combination thereof.

[0035] Referring to FIGS. 6 and 7, a contact recess (R) may be formed on the upper surface of the substrate (102). Forming the contact recess (R) may be performed by an anisotropic etching process. The device isolation layer (104) and the buffer layer (110) may be etched, and the upper surface of the active region (AR) may be exposed by the contact recess (R). In the top view, the contact recess (R) may be formed in the central part of the active region (AR), for example, in the source region of the active region (AR).

[0036] Referring to FIGS. 8 and 9, a first conductive layer (120), a second conductive layer (122), a third conductive layer (124), a first capping layer (130), an insulating liner (132), and a second capping layer (134) may be formed. The first conductive layer (120) may fill the contact recess (R) and cover the buffer layer (110). The first conductive layer (120) may be formed by depositing a conductive material on the contact recess (R) and the buffer layer (110) and performing a planarization process. The portion of the first conductive layer (120) that fills the contact recess (R) may be referred to as a direct contact (DC). For example, the direct contact (DC) may be embedded within the substrate (102) and may be in contact with the device isolation layer (104) and the active region (AR). The first conductive layer (120) may include polysilicon.

[0037] A second conductive layer (122), a third conductive layer (124), a first capping layer (130), an insulating liner (132), and a second capping layer (134) may be sequentially laminated on a first conductive layer (120). The first conductive layer (120), the second conductive layer (122), and the third conductive layer (124) may constitute a bit line material layer (BLp). In this specification, the first capping layer (130), the insulating liner (132), and the second capping layer (134) may be collectively referred to as a capping layer. The second conductive layer (122) and the third conductive layer (124) may each include TiN, TiSiN, W, tungsten silicide, or a combination thereof. The first capping layer (130), the insulating liner (132), and the second capping layer (134) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0038] Referring to FIGS. 10 and 11, a first conductive layer (120), a second conductive layer (122), a third conductive layer (124), a first capping layer (130), an insulating liner (132), and a second capping layer (134) may be etched. The etching process may be an anisotropic etching process. During the etching process, a direct contact (DC) may be partially etched, and a side of the etched direct contact (DC) may be exposed. The etched first conductive layer (120), the second conductive layer (122), and the third conductive layer (124) may form a bit line (BL). In the plan view, the bit lines (BL) may have a bar shape extending in the y-direction. Additionally, the first capping layer (130), the insulating liner (132), and the second capping layer (134) may extend in the y-direction on the bit line (BL). The bit line (BL), the first capping layer (130), the insulating liner (132), and the second capping layer (134) can form a bit line structure (BLS).

[0039] Referring to FIGS. 12 and 13, an inner spacer (140) and a buried spacer (141) may be formed on the side of a bit line structure (BLS). The inner spacer (140) and the buried spacer (141) may be formed by conformally depositing an inner spacer material layer on the result of FIG. 11, depositing a buried spacer material layer on the inner spacer (140) material layer, and performing an anisotropic etching process so that the upper surface of the buffer layer (110) is exposed. The inner spacer (140) may be conformally formed along the side of the bit line structure (BLS) and the inner wall of the contact recess (R). The buried spacer (141) may be formed inside the contact recess (R). For example, a buried spacer (141) may be formed on an inner spacer (140) and may fill a contact recess (R). The upper surface of the buried spacer (141) may be co-planar with the upper surface of the buffer layer (110). The inner spacer (140) may extend in the y-direction along the bit line structure (BLS), and each buried spacer (141) may be placed inside the contact recesses (R).

[0040] Subsequently, a sacrificial spacer (142) and an outer spacer (144) may be formed. The sacrificial spacer (142) and the outer spacer (144) may be formed by sequentially stacking a spacer material layer on the inner spacer (140) and then performing an anisotropic etching process so that the upper surface of the buffer layer (110) is exposed. For example, the sacrificial spacer (142) may be formed on the side of the inner spacer (140), and the lower surface of the sacrificial spacer (142) may be in contact with the upper surface of the buried spacer (141). The outer spacer (144) may be formed on the side of the sacrificial spacer (142), and the lower surface of the outer spacer (144) may be in contact with the buried spacer (141). The sacrifice spacer (142) and the outer spacer (144) can be extended in the y-direction along the bit line structure (BLS).

[0041] The sacrificial spacer (142) may include a material having an etching selectivity with respect to the inner spacer (140) and the buried spacer (141). In one embodiment, the sacrificial spacer (142) may include silicon oxide, and the inner spacer (140) and the buried spacer (141) may include silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, at least one of the inner spacer (140) and the buried spacer (141) may include SiC, SiOC, SiOCN, or a combination thereof. The buried spacer (141) may include a material having an etching selectivity with respect to the sacrificial spacer (142). The buried spacer (141) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0042] Referring to FIGS. 14 and 15, preliminary contact layers (BCp) may be formed between bit line structures (BLS). Before the preliminary contact layers (BCp) are formed, sacrificial layers (160) and fence insulating layers (not shown) may be formed. For example, the preliminary contact layers (BCp) may be formed by filling a sacrificial layer (160) extending in the y-direction between bit line structures (BLS), forming fence insulating layers at the portion where the sacrificial layer (160) intersects the gate line, removing the sacrificial layer (160), and filling a conductive layer. Forming the preliminary contact layers (BCp) may further include partially etching the conductive layer by an etch-back process. For example, the upper surface of the preliminary contact layers (BCp) may be located at a lower level than the upper surface of the bit line structures (BLS). Preliminary contact layers (BCp) and fence insulation layers may be alternately arranged along the y-direction between bit line structures (BLS). Preliminary contact layers (BCp) may extend into the interior of the substrate (102). For example, the preliminary contact layers (BCp) may penetrate the buffer layer (110) and the inner spacer (140) on the inner wall of the contact recess (R) and may come into contact with the active region (AR). In one embodiment, the preliminary contact layer (BCp) may comprise polysilicon.

[0043] Referring to FIGS. 16 and 17, the sacrificial spacer (142) and the outer spacer (144) may be partially etched to form the sacrificial spacer (143) and the outer spacer (145). For example, the upper portion of the sacrificial spacer (142) and the outer spacer (144) that is not covered by the pre-contact layer (BCp) may be etched so that the height of the sacrificial spacer (142) and the outer spacer (144) may be reduced. The etching process may include an anisotropic etching process or an isotropic etching process. The upper side of the inner spacer (140) may be exposed by the etching process. The upper surface of the sacrificial spacer (143) and the outer spacer (145) may be located at a higher level than the upper surface of the pre-contact layer (BCp). However, it is not limited thereto, and in one embodiment, the upper surface of the sacrificial spacer (143) and the outer spacer (145) may co-face with the upper surface of the pre-contact layer (BCp). Additionally, the upper surface of the second capping layer (134) may be partially etched by the etching process. For example, the upper surface of the second capping layer (134) may be rounded.

[0044] Referring to FIGS. 18 and 19, an upper spacer (146) may be formed on the side of the inner spacer (140). The upper spacer (146) may be formed by conformally depositing an insulating material on the result of FIG. 17 and then performing an anisotropic etching process so that the second capping layer (134) and the pre-contact layer (BCp) are exposed. The upper spacer (146) may cover the upper part of the inner spacer (140) that is not covered by the sacrificial spacer (143). Additionally, the lower surface of the upper spacer (146) may be in contact with the upper surface of the sacrificial spacer (143). In the plan view, the upper spacer (146) may have a ring shape or a frame shape surrounding the buried contact (BC). The horizontal width of the upper spacer (146) may be smaller than the sum of the upper widths of the sacrificial spacer (143) and the outer spacer (145). That is, the distance between adjacent upper spacers (146) may be greater than the distance between adjacent outer spacers (145). Accordingly, the landing pad (LP) described below may be formed wider. The upper spacer (146) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the upper spacer (146) may include silicon nitride.

[0045] After the upper spacer (146) is formed, the upper part of the pre-contact layer (BCp) may be partially etched to form a buried contact (BC). The upper surface of the buried contact (BC) may be located at a lower level than the upper surfaces of the sacrificial spacer (143) and the outer spacer (145). The side of the outer spacer (145) may be partially exposed.

[0046] FIG. 21 is a vertical cross-sectional view of FIG. 20, and FIG. 22 is a partial enlarged view of FIG. 20.

[0047] Referring to FIGS. 20 to 22, a barrier pattern (150) and a conductive pattern (152) may be formed. The barrier pattern (150) and the conductive pattern (152) may form a landing pad (LP). Forming the barrier pattern (150) and the conductive pattern (152) may include conformally depositing a barrier material on the result of FIG. 19, forming a conductive material on the barrier material, and etching the barrier material and the conductive material to form a pad recess (154).

[0048] The barrier pattern (150) may include metal silicides such as cobalt silicide, nickel silicide, and manganese silicide. The conductive pattern (152) may include polysilicon, metal, metal silicide, conductive metal nitride, or a combination thereof. In one embodiment, the conductive pattern (152) may include tungsten.

[0049] Forming the pad recess (154) may include forming a hard mask (M) on a conductive material, etching the conductive material by an etching process in which the hard mask (M) is used as an etching mask, depositing an insulating material on the etched portion of the conductive material, and then performing an additional etching process to etch the bottom of the insulating material. The insulating material that is not removed may remain on the sidewall of the pad recess (154) to form an insulating pattern (156). In one embodiment, the insulating pattern (156) may be omitted. The insulating pattern (156) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In one embodiment, the insulating pattern (156) may include silicon nitride.

[0050] The pad recess (154) may partially expose the bit line structure (BLS) and spacers. For example, the inner spacer (140) and the sacrificial spacer (143) may be exposed. In one embodiment, the outer spacer (145) may also be exposed. Additionally, a portion of the second capping layer (134) may be exposed by the pad recess (154). In this specification, a portion of the inner spacer (140) located inside the pad recess (154) may be referred to as the inner lower spacer (140L). That is, the inner lower spacer (140L) may cover the side of the buried spacer (141). A portion of the inner spacer (140) located above the buried spacer (141) may be referred to as the inner upper spacer (140U).

[0051] In one embodiment, a silicide pattern (BCU) may be formed on a buried contact (BC) before forming the barrier material and the conductive material. The silicide pattern (BCU) may be formed by forming a metal layer on the buried contact (BC) and reacting the metal layer with the buried contact (BC) through a heat treatment process. The silicide patterns (BCU) may be placed on the buried contacts (BC) and may come into contact with the barrier patterns (150).

[0052] The silicide pattern (BCU) may include, for example, titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or molybdenum silicide. In one embodiment, the process of forming the silicide pattern (BCU) may be omitted.

[0053] Referring to FIG. 23, the sacrificial spacer (143) can be removed by an isotropic etching process. For example, the sacrificial spacer (143) can be selectively removed by providing an etching etchant having an etching selectivity for the inner spacer (140) and the outer spacer (145) in the pad recess (154). When the sacrificial spacer (143) is removed, a lower air gap (AG1) can be formed in the space surrounded by the buried spacer (141), the inner spacer (140), and the outer spacer (145). The first upper spacer (146) and the outer spacer (145) can be exposed by the lower air gap (AG1). Although not shown in the drawing, a sacrificial spacer (143) located to the right of the bit line structure (BLS) in the cross-sectional view may also be exposed by the pad recess (154) and removed by the etching process to form a lower air gap (AG1).

[0054] Referring to FIG. 24, the inner upper spacer (140U) and the outer spacer (145) exposed by the lower air gap (AG1) can be removed. In one embodiment, the inner spacer (140) and the outer spacer (145) may comprise SiC, SiOC, SiOCN, or a combination thereof and can be removed by an ashing process. For example, the inner upper spacer (140U) and the outer spacer (145) exposed by the lower air gap (AG1) can be oxidized by a plasma ashing process. Subsequently, the oxidized inner upper spacer (140U) and the outer spacer (145) can be optionally removed by a dry etching process or an isotropic etching process. The inner upper spacer (140U) and the outer spacer (145) may be removed to expand the lower air gap (AG1), and the lower air gap (AG1) may be defined as a space enclosed by the bit line structure (BLS), the buried spacer (141), the buried contact (BC), the silicide pattern (BCU), and the landing pad (LP). In the cross-sectional view, the inner upper spacer (140U) and the upper spacer (146) are shown as remaining unremoved on the opposite side of the pad recess (154) relative to the bit line structure (BLS), but are not limited thereto. In one embodiment, the inner upper spacer (140U) may be completely removed by an ashing process. Alternatively, if the upper spacer (146) comprises SiC, SiOC, SiOCN, or a combination thereof, the upper spacer (146) may also be removed by an ashing process.

[0055] As illustrated in FIG. 24, by removing the inner spacer (140) and the outer spacer (145), the lower air gap (AG1) can be expanded so that the distance between the bit line structure (BLS) and the buried contact (BC) can be increased. Thus, the parasitic capacitance between the bit line structure (BLS) and the buried contact (BC) can be reduced, and the reliability and electrical characteristics of the device can be further improved.

[0056] Referring to FIG. 25, a sacrificial layer (160) may be formed to fill the pad recess (154) and the lower air gap (AG1). The sacrificial layer (160) may be in contact with the bit line structure (BLS), the buried spacer (141), the buried contact (BC), the landing pad (LP), and the insulation pattern (156). The sacrificial layer (160) may comprise a polymer or a pyrolytic material. In one embodiment, the sacrificial layer (160) may comprise amorphous silicon.

[0057] Referring to FIG. 26, the upper portion of the sacrificial layer (160) may be partially etched. For example, the upper portion of the sacrificial layer (160) may be removed by an etch-back process. The side of the pad recess (154) and the insulation pattern (156) may be exposed by the etching process. The upper surface of the etched sacrificial layer (160) may be located at a lower level than the upper surface of the landing pad (LP) and the bit line structure (BLS). The etched sacrificial layer (160) may be filled in the lower air gap (AG1) and the lower portion of the pad recess (154).

[0058] Referring to FIG. 27, a lower insulating layer (170) may be deposited on the inner wall of a pad recess (154). The lower insulating layer (170) may be formed conformally along the inner wall of the pad recess (154) and may be in contact with an insulating pattern (156) and a sacrificial layer (160). The lower insulating layer (170) may be formed by a Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD) process, and the deposition process may be performed at a low temperature such that the sacrificial layer (160) does not decompose. The lower insulating layer (170) formed by the low-temperature deposition process may be a porous thin film. The lower insulating layer (170) may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0059] Referring to FIG. 28, the sacrificial layer (160) may be removed to form a lower air gap (AG1) and an upper air gap (AG2). In one embodiment, the sacrificial layer (160) may be removed by a pyrolysis process and discharged through a lower insulating layer (170), which is a porous thin film. The lower air gap (AG1) and the upper air gap (AG2) may constitute an air gap (AG). The lower air gap (AG1) may be defined as a space surrounded by a bit line structure (BLS), a buried spacer (141), a buried contact (BC), and a landing pad (LP). The upper air gap (AG2) may be defined as a space surrounded by a landing pad (LP), a lower insulating layer (170), and a bit line structure (BLS). The upper air gap (AG2) may be located on the lower air gap (AG1) and may communicate with the lower air gap (AG1).

[0060] Referring again to FIGS. 1 to 3, an upper insulating layer (172) that fills the pad recess (154) may be formed on the lower insulating layer (170). The upper surface of the upper insulating layer (172) may form a co-surface with the upper surface of the landing pad (LP). The lower insulating layer (170) and the upper insulating layer (172) may form an insulating structure (174). The upper insulating layer (172) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0061] Subsequently, a semiconductor device (100) can be formed by forming a lower electrode (180), a capacitor dielectric layer (182), an upper electrode (184), and an upper insulating layer (172). The lower electrode (180) may be positioned to correspond to a landing pad (LP). For example, the lower electrode (180) may be in contact with the upper surface of the landing pad (LP) and may be electrically connected to a drain region through the landing pad (LP) and a buried contact (BC). In one embodiment, the lower electrode (180) may have a pillar shape, but is not limited thereto. In another embodiment, the lower electrode (180) may have a cylinder shape or a hybrid shape of a pillar shape and a cylinder shape.

[0062] The capacitor dielectric layer (182) can be conformally formed along the surfaces of the landing pad (LP), the insulating structure (174), and the lower electrode (180). The upper electrode (184) can be formed on the capacitor dielectric layer (182). The lower electrode (180), the capacitor dielectric layer (182), and the upper electrode (184) can constitute a capacitor structure of the semiconductor device (100).

[0063] The lower electrode (180) may include a metal such as Ti, W, Ni, Co, or a metal nitride such as TiN, TiSiN, TiAlN, TaN, TaSiN, WN, etc. In one embodiment, the lower electrode (180) may include TiN. The capacitor dielectric layer (182) may include a metal oxide such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2, a dielectric material with a perovskite structure such as SrTiO3 (STO), BaTiO3, PZT, PLZT, or a combination thereof. The upper electrode (184) may include a metal such as Ti, W, Ni, Co, or a metal nitride such as TiN, TiSiN, TiAlN, TaN, TaSiN, WN, etc.

[0064] FIGS. 29 to 31 are vertical cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0065] In one embodiment, an ashing process may be performed before the removal process of the sacrificial spacer (143) described with reference to FIG. 23 is performed. FIG. 29 illustrates an inner spacer (140) and an outer spacer (145) on which this method has been performed. The upper portions of the inner spacer (140) and the outer spacer (145) may be oxidized by the ashing process. For example, an inner oxide layer (140a) and an outer oxide layer (145a) may be formed, respectively, on the inner upper spacer (140U) and the outer spacer (145) exposed to the pad recess (154).

[0066] Referring to FIG. 30, oxides can be selectively removed by an isotropic etching process. The inner oxide layer (140a) and the outer oxide layer (145a) can be removed, and the upper part of the sacrificial spacer (143) can be partially etched. By the etching process, a lower air gap (AG1) can be formed in the space surrounded by the inner upper spacer (140U), the sacrificial spacer (143), the outer spacer (145), the bit line structure (BLS), and the landing pad (LP).

[0067] Referring to FIG. 31, the sacrificial spacer (143) can be selectively removed by an isotropic etching process. As shown in FIG. 29 and FIG. 30, the inner spacer (140) and the outer spacer (145) are oxidized to form an oxide layer, and then the oxide layer is removed to form a lower air gap (AG1), thereby expanding the space into which the etching etchant flows during the etching process of the sacrificial spacer (143), thereby reducing the difficulty of the etching process. Subsequently, the remaining inner upper spacer (140U) and the outer spacer (145) can be removed by an ashing process.

[0068] FIGS. 32 to 35 are vertical cross-sectional views of semiconductor devices according to embodiments of the present disclosure.

[0069] Referring to FIG. 32, a spacer structure (SP) of a semiconductor device (200) may include an outer spacer (245) provided between a buried contact (BC) and a bit line structure (BLS). The outer spacer (245) may constitute the spacer structure (SP). In one embodiment, the outer spacer (245) may not be removed by the ashing process described with reference to FIG. 24. For example, the outer spacer (245) may include silicon nitride. A lower air gap (AG1) may be provided between the outer spacer (245) and the bit line structure (BLS). That is, the lower air gap (AG1) may be defined by the outer spacer (245), the buried spacer (141), and the bit line structure (BLS). The buried contact (BC) and landing pad (LP), which are partially covered by the outer spacer (245), may not be exposed to the lower air gap (AG1). At any vertical level between the buried spacer (141) and the upper air gap (AG2), the horizontal distance between the outer spacer (245) and the bit line structure (BLS) may be equal to the horizontal width of the lower air gap (AG1).

[0070] Referring to FIG. 33, a spacer structure (SP) of a semiconductor device (300) may include an inner spacer (340) provided between a buried contact (BC) and a bit line structure (BLS). The inner spacer (340) may include an inner lower spacer (340L) disposed along the inner wall of the contact recess (R) and the side of the direct contact (DC), and an inner upper spacer (340U) disposed on the inner lower spacer (340L) and covering the side of the bit line structure (BLS). In one embodiment, the inner spacer (340) may not be removed by the ashing process described with reference to FIG. 24. For example, the inner spacer (340) may include silicon nitride. A lower air gap (AG1) may be provided between the buried contact (BC) and the inner spacer (340). That is, the lower air gap (AG1) can be defined by a buried contact (BC), a buried spacer (141), and an inner spacer (340). The bit line structure (BLS) is covered by the inner spacer (340) so that it may not be exposed to the lower air gap (AG1). At any vertical level between the buried spacer (141) and the upper air gap (AG2), the horizontal distance between the buried contact (BC) and the inner spacer (340) may be equal to the horizontal width of the lower air gap (AG1).

[0071] Referring to FIG. 34, the spacer structure (SP) of the semiconductor device (400) may include an inner lower spacer (440L) positioned along the inner wall of the contact recess (R) and the side of the direct contact (DC). The buried contact (BC) and the bit line structure (BLS) may be exposed to the lower air gap (AG1). In one embodiment, the upper surface of the inner lower spacer (440L) may be located at a lower level than the upper surface of the buried spacer (141). Additionally, the upper surface of the inner lower spacer (440L) may be concave.

[0072] Referring to FIG. 35, the spacer structure (SP) of the semiconductor device (500) may include an inner upper spacer (540U) that is positioned on an inner lower spacer (140L) and partially covers the side of the bit line structure (BLS). The buried contact (BC) and the bit line structure (BLS) may be exposed to the lower air gap (AG1). In one embodiment, the upper surface of the inner upper spacer (540U) may be located at a higher level than the upper surface of the buried spacer (141). Additionally, the upper surface of the inner upper spacer (540U) may be concave. Although the upper surface of the inner upper spacer (540U) is depicted as being located at a lower level than the upper surface of the direct contact (DC), it is not limited thereto.

[0073] Although embodiments according to the present disclosure have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. The embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0074] 100 : Semiconductor device 102 : Substrate 104: Device isolation layer 107: Gate dielectric layer 108: Gate capping layer 110: Buffer layer 140: Inner spacer 140L: Inner lower spacer 140U: Inner upper spacer 141: Embedded spacer 143: Sacrifice Spacer 145: Outer Spacer 146: Upper spacer 150: Barrier pattern 152: Challenge pattern 154: Pad recess 156 : Insulation pattern 174 : Insulation structure 180: Lower electrode 182: Capacitor dielectric layer 184 : Upper electrode DC : Direct contact BLS: Bit line structure SP: Spacer structure AG : Air gap AG1 : Lower air gap AG2: Upper air gap BC: Buried contact LP: Landing pad

Claims

Claim 1 A substrate including an active region; a gate electrode disposed within the substrate and extending in a first horizontal direction; a bit line structure extending in a second horizontal direction that crosses the gate electrode and intersects the first horizontal direction, wherein the bit line structure includes a direct contact disposed within a contact recess of the substrate; and a buried contact disposed on the substrate and connected to the active region. A semiconductor device comprising a spacer structure disposed between the bit line structure and the buried contact, wherein the spacer structure comprises an inner lower spacer in contact with the inner wall of the contact recess and the side of the bit line structure, a buried spacer disposed on the inner lower spacer, and an air gap on the buried spacer, wherein the air gap exposes the side of the bit line structure, the upper surface of the inner lower spacer, and the upper surface of the buried spacer, wherein the lower portion of the direct contact contacts the inner lower spacer, and the upper portion of the direct contact is exposed by the air gap. Claim 2 In claim 1, the air gap is a semiconductor device that further exposes the buried contact. Claim 3 In paragraph 2, a semiconductor device in which, at the first vertical level, the horizontal distance between the buried contact and the bit line structure is equal to the horizontal width of the air gap. Claim 4 A semiconductor device according to claim 1, further comprising a landing pad on the buried contact, wherein the air gap further exposes the landing pad. Claim 5 In claim 1, the spacer structure further includes an outer spacer in contact with the buried contact, and the air gap is provided between the outer spacer and the bit line structure. Claim 6 delete Claim 7 A substrate including an active region; a gate electrode disposed within the substrate and extending in a first horizontal direction; a first bit line structure and a second bit line structure extending in a second horizontal direction that crosses the gate electrode and intersects the first horizontal direction, wherein the first bit line structure includes a direct contact disposed within a contact recess of the substrate; a buried contact connected to the active region and disposed between the first bit line structure and the second bit line structure; a landing pad on the buried contact; a first spacer structure disposed between the first bit line structure and the buried contact, wherein the first spacer structure includes an inner lower spacer in contact with the inner wall of the contact recess and the side of the first bit line structure, a buried spacer disposed on the inner lower spacer, and a first air gap on the buried spacer; A semiconductor device comprising a second spacer structure disposed between the second bit line structure and the buried contact, wherein the second spacer structure comprises a second air gap on the substrate, and the first air gap exposes at least one side of the first bit line structure and the buried contact, the upper surface of the inner lower spacer and the upper surface of the buried spacer, wherein the lower portion of the direct contact contacts the inner lower spacer and the upper portion of the direct contact contact is exposed by the first air gap. Claim 8 A semiconductor device according to claim 7, further comprising an insulating structure in contact with the landing pad and the first bit line structure. Claim 9 In claim 8, the first air gap comprises a first lower air gap and a first upper air gap on the first lower air gap, wherein the first lower air gap is defined by the buried contact, the buried spacer, the landing pad, and the first bit line structure, and the first upper air gap is defined by the landing pad, the insulating structure, and the first bit line structure. Claim 10 In claim 7, the first air gap and the second air gap are semiconductor devices that expose both sides of the buried contact.