Semiconductor devices

Abstract

One embodiment of the present invention provides a semiconductor device comprising: a fin-shaped active region protruding from a substrate and extending in a first direction; a plurality of channel layers spaced apart from each other in a direction perpendicular to the upper surface of the substrate on the fin-shaped active region; a gate structure extending across the fin-shaped active region in a second direction intersecting the first direction and surrounding each of the plurality of channel layers; fence spacers extending in the perpendicular direction, each disposed on both sides of the gate structure located in the second direction of the fin-shaped active region; and source / drain regions each disposed between the fence spacers on the fin-shaped active region on both sides of the gate structure, connected to each of the plurality of channel layers, and having a void on each of the two sides facing the fence spacers.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the demand for integration density of semiconductor devices is also increasing. To meet the demand for high integration of semiconductor devices, the development of semiconductor devices equipped with channels having a three-dimensional structure is actively underway. The problem to be solved

[0005] One of the technical problems that the present invention aims to solve is to provide a highly integrated semiconductor device. means of solving the problem

[0007] One embodiment of the present invention provides a semiconductor device comprising: a fin-shaped active region protruding from a substrate and extending in a first direction; a plurality of channel layers spaced apart from each other in a direction perpendicular to the upper surface of the substrate on the fin-shaped active region; a gate structure extending across the fin-shaped active region in a second direction intersecting the first direction and surrounding each of the plurality of channel layers; fence spacers extending in the perpendicular direction, each disposed on both sides of the gate structure located in the second direction of the fin-shaped active region; and source / drain regions each disposed between the fence spacers on the fin-shaped active region on both sides of the gate structure, connected to each of the plurality of channel layers, and having a void on each of the two sides facing the fence spacers.

[0009] One embodiment of the present invention comprises: a pin-shaped active region protruding on a substrate and extending in a first direction; a plurality of channel layers spaced apart from each other on the pin-shaped active region in a direction perpendicular to the upper surface of the substrate; a gate structure extending across the pin-shaped active region in a second direction intersecting the first direction and surrounding each of the plurality of channel layers; and a source / drain region comprising a first epitaxial layer disposed along the first direction on the sides of each of the plurality of channel layers in the upper surface area of ​​the pin-shaped active region on both sides of the gate structure, and a second epitaxial layer disposed on the first epitaxial layer and having a composition different from that of the first epitaxial layer. The semiconductor device comprises fence spacers that are respectively disposed on both sides of the fin-shaped active region located in the second direction on both sides of the gate structure and extend to both sides of the source / drain region, wherein in the cross-section in the first direction, the source / drain region has a left-right asymmetric shape with an aspect ratio of 2.5 or more, and each of the fence spacers has an upper level of 30% or more of the height of the source / drain region.

[0011] One embodiment of the present invention comprises: a pin-shaped active region protruding on a substrate and extending in a first direction; a plurality of channel layers spaced apart from each other on the pin-shaped active region in a direction perpendicular to the upper surface of the substrate; a gate structure extending across the pin-shaped active region in a second direction intersecting the first direction and surrounding each of the plurality of channel layers; and a source / drain region comprising a first epitaxial layer disposed along the first direction on the sides of each of the plurality of channel layers in the upper surface area of ​​the pin-shaped active region on both sides of the gate structure, and a second epitaxial layer disposed on the first epitaxial layer and having a composition different from that of the first epitaxial layer. The semiconductor device comprises fence spacers that are respectively disposed on both sides of the fin-shaped active region located in the second direction on both sides of the gate structure and extend to both sides of the source / drain region, wherein the source / drain region has a concave void on each of the two sides facing the fence spacers, and the two sides of the source / drain region facing the fence spacers are provided by the second epitaxial layer. Effects of the invention

[0013] The semiconductor device according to the present embodiment can control the width of the source / drain region by introducing relatively high fence spacers. In addition, the two sides facing the fence spacers in the source / drain region may have concave voids.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention. Figure 2 is a cross-sectional view of the semiconductor device of Figure 1 taken by cutting along the line I-I'. FIGS. 3a and 3b are cross-sectional views of the semiconductor device of FIG. 1 taken by cutting along the lines II1-II1' and II2-II2'. Figures 4a and 4b are enlarged views of the "A" portion of Figure 2 and the "B" portion of Figure 3b, respectively. FIGS. 5 to 8 are perspective views illustrating a part of the process (forming a fin structure and a dummy gate) of a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 9 to 16 are cross-sectional views illustrating a part of a method for manufacturing a semiconductor device according to one embodiment of the present invention (formation of source / drain and gate structures). FIGS. 17a and FIGS. 17b are cross-sectional views showing a semiconductor device according to one embodiment of the present invention. FIGS. 18 and FIGS. 19 are cross-sectional views showing a semiconductor device according to various embodiments of the present invention. Specific details for implementing the invention

[0017] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0019] FIG. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention, FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 taken along the line I-I', and FIG. 3a and FIG. 3b are cross-sectional views of the semiconductor device of FIG. 1 taken along the lines II1-II1' and II2-II2'.

[0021] Referring to FIGS. 1 and 2, a semiconductor device (100) according to the present embodiment comprises a substrate (101), a pin-shaped active region (105) protruding on the substrate (101) and extending in a first direction (e.g., X direction), a channel structure (140) disposed on the pin-shaped active region (105), and a gate structure (160) extending in a second direction (e.g., Y direction) intersecting the pin-shaped active region (105). The channel structure (140) may include a plurality of channel layers (141, 142, 143) disposed spaced apart in a direction perpendicular to the upper surface of the substrate (100) (e.g., Z direction) on the pin-shaped active region (105).

[0022] Additionally, the semiconductor device (100) may further include source / drain regions (150) disposed on both sides of the gate structure (160) and in contact with a plurality of channel layers (141, 142, 143, 144), and contact plugs (180) connected to the source / drain regions (150).

[0023] In this embodiment, the fin-shaped active region (105) extends in a first direction (e.g., X direction) and has a protruding fin structure. For example, the substrate (101) may be a semiconductor substrate such as a silicon substrate or a germanium substrate, or a silicon-on-insulator (SOI) substrate. A device isolation layer (110) may define the fin-shaped active region (105). As illustrated in FIGS. 3a and 3b, the device isolation layer (110) may be placed on the substrate (101) to cover the side of the fin-shaped active region (105) of the substrate (101). The device isolation layer (110) may include, for example, an oxide film, a nitride film, or a combination thereof. In some embodiments, the device isolation layer (110) may include a deep trench isolation (DTI) region (not shown) formed deeper than the STI to define an active region in which a fin structure is formed, in addition to a shallow trench isolation (STI) region that defines a fin-shaped active region (105).

[0024] The device isolation layer (110) may be formed so that the upper region of the pin-shaped active region (105) is exposed. In some embodiments, the device isolation layer (110) may have a curved upper surface having a higher level as it is adjacent to the pin-shaped active region (105).

[0025] Referring to FIG. 2, the upper region of the pin-shaped active region (105) may protrude from the upper surface of the device isolation film (110). The pin-shaped active region (105) may include a part of the substrate (101) or an epitaxial growth from the substrate (101). However, a part of the pin-shaped active region (105) on the substrate (101) located on both sides of the gate structures (160) may be exposed (or recessed), and source / drain regions (150) may be formed in the exposed region. Details of the source / drain regions (150) employed in this embodiment will be described later.

[0026] The gate structure (160) may include a gate electrode (165) that extends in a second direction (e.g., Y direction) as shown in FIG. 2 and surrounds a plurality of channel layers (141, 142, 143, 144), a gate dielectric layer (162) disposed between the gate electrode (165) and the plurality of channel layers (141, 142, 143, 144), gate spacers (164) disposed on the sides of the gate electrode (165), and a gate capping layer (166) disposed on the gate electrode (165).

[0027] As such, the semiconductor device (100) according to the present embodiment may be a gate-all-around type field-effect transistor (e.g., P-MOS transistor) comprising channel structures (140), source / drain regions (150), and gate structures (160).

[0029] Specifically, the channel structure (140) may include first to fourth channel layers (141, 142, 143, 144) spaced apart from each other in a third direction (e.g., Z direction) perpendicular to the upper surface of the substrate (101) on the pin-shaped active region (105). Both sides of the first to fourth channel layers (141, 142, 143, 144) along the first direction (X direction) may come into contact with the source / drain region (150).

[0030] The first to fourth channel layers (141, 142, 143, 144) may have a width equal to or similar to that of the pin-shaped active region (105) in the second direction (e.g., Y direction) and may have a width equal to or similar to that of the gate structure (160) in the first direction (e.g., X direction). This is not limited thereto, and in some embodiments, the widths of the first to fourth channel layers (141, 142, 143, 144) may vary slightly. For example, the width of the first channel layer (141) may be greater than the width of the second channel layer (142). Additionally, in some embodiments, when viewed from the first direction (X direction), the width of the first to fourth channel layers (141, 142, 143, 144) may be smaller than the width of the gate structure (160) so that the sides of the first to fourth channel layers (141, 142, 143, 144) are located at the bottom of the gate structure (160).

[0031] The first to fourth channel layers (141, 142, 143, 144) may include a semiconductor material capable of providing a channel region. For example, the first to fourth channel layers (141, 142, 143, 144) may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The first to fourth channel layers (141, 142, 143, 144) may be made of, for example, the same material as the substrate (101). In this embodiment, the channel layers (141, 142, 143, 144) are exemplified as four, but their number and shape may be varied (see FIG. 17a and FIG. 17b).

[0032] As the number of channel layers (141, 142, 143, 144) increases, the aspect ratio of the source / drain region may increase. In this embodiment, by introducing four channel layers (141, 142, 143, 144), the aspect ratio of the source / drain region (150) may be relatively large. In a cross-section in the first direction (e.g., X direction) (see FIG. 2 and FIG. 4a), the aspect ratio (b1 / a1) of the source / drain region (150) may be 2.5 or greater, and in some embodiments, may be 2.8 or greater (e.g., 3). Referring to FIG. 4a, the horizontal length (a1) is defined as the spacing between adjacent fourth channel layers (144), and the vertical length (b1) may be defined as the depth of the recess (see 'RC' in FIG. 9) for the source / drain region (150).

[0034] Referring to FIGS. 3a and 4b, the semiconductor device (100) may further include fence spacers (174) that are respectively positioned on both sides of the gate structure (160) in the second direction (e.g., Y direction) of the fin-shaped active region (105) and extend in the third direction (e.g., Z direction). Source / drain regions (150) may be positioned between the fence spacers (174) and connected to both sides of the channel layers (140).

[0035] The fence spacers (140) may have sufficient height to guide growth along a second direction (e.g., Y direction) of the source / drain region (150). Referring to FIG. 4b, the fence spacers (174) may be formed to have an upper level of at least 30% of the height (b1) of the source / drain region (150). As in the present embodiment, the fence spacers (174) may have an upper level of at least 50% of the height (b1) of the source / drain region (150). For example, the height (h) of the fence spacers (174) may be 30 nm or more.

[0036] In the process of forming the source / drain region (150) (see FIGS. 12 to 14), since the inflow of gas is not smooth due to the fence spacers (174), the side regions of the source / drain region (150) adjacent to each of the fence spacers (174) may not be completely filled. As a result, as shown in FIGS. 3a and 4b, the source / drain region (150) may have concave voids (V1, V2) formed on each of the sides facing the fence spacers (174).

[0037] During the filling process of the intermediate penetration region (TV in FIG. 13), referred to as a "pinch-off void," dislocation defects may be observed at points (P1, P2) where epitaxial portions growing from different directions merge. The voids (V1, V2) located on each of the two opposing sides may be located at different levels. The voids (V1, V2) located on both sides may have different shapes and / or sizes. As illustrated in FIG. 3a and FIG. 4b, the source / drain region (150) may have a left-right asymmetrical shape.

[0038] In this embodiment, the width of the source / drain area (150) in the second direction (e.g., Y direction) may be defined by the spacing of the fence spacers (174), but is not limited thereto, and in another embodiment (see FIG. 19), the upper area of ​​the source / drain area (150) may have a width greater than the spacing of the fence spacers (174).

[0040] Referring to FIG. 2 and FIG. 3a, the source / drain region (150) employed in the present embodiment may include a first epitaxial layer (150A) disposed continuously on the upper surface region of the pin-shaped active region (105) on both sides of the gate structure (160) and on the sides of each of the channel layers (141, 142, 143, 144), and a second epitaxial layer (150B) disposed on the first epitaxial layer (150A). From a process perspective (see FIG. 12), the first epitaxial layer (150A) may be formed on the bottom surface and sides of the recess according to the first direction (e.g., X direction), and the second epitaxial layer (150B) may be disposed on the first epitaxial layer (150A) to fill the remaining space of the recess and may provide a region connected to a contact plug (180).

[0042] The first epitaxial layer (150A) may have a bottom region (150A1) located on the upper surface of the fin-shaped active region (105) and a sidewall region (150A2) extending continuously along the sides of the first to fourth channel layers (141, 142, 143, 144) from the bottom region (150A1) in a first direction (e.g., X direction). In some embodiments, the thickness of the bottom region (150A1) may be slightly greater than the thickness of the sidewall region (150A2). The second epitaxial layer (150B) may have a somewhat convex shape, but is not limited thereto.

[0043] In the source / drain region (150), both sides located in the first direction (e.g., X direction) are provided by the first epitaxial layer (150A) (see FIG. 3a), and both sides located in the second direction (e.g., Y direction), i.e., sides where voids (V1, V2) are formed, may be provided by the second epitaxial layer (150B) (see FIG. 3b).

[0044] As previously explained, the aspect ratio (b1 / a1) of the source / drain region (150) may be 2.5 or greater, and in some embodiments may be 2.8 or greater (e.g., 3). The aspect ratio of the recess after the first epitaxial layer (150A) is formed, i.e., the aspect ratio (b2 / a2) of the second epitaxial layer (150B), may be 2.0 or greater, and in some embodiments may be 2.3 or greater (e.g., 2.5).

[0046] In this embodiment, the first epitaxial layer (150A) and the second epitaxial layer (150B) may have different compositions. For example, the first and second epitaxial layers (150A, 150B) may include at least one of silicon (Si), silicon germanium (SiGe), and silicon carbide (SiC) and may have different impurity concentrations. For example, in the case of a P-MOSFET, the P-type impurity may include at least one of B, Al, Ga, and In.

[0047] In some embodiments (e.g., P-MOSFET), the first epitaxial layer (150A) may comprise silicon germanium (SiGe) containing Ge in a first composition ratio, and the second epitaxial layer (150B) may comprise silicon germanium containing Ge in a second composition ratio greater than the first composition ratio. For example, the Ge composition ratio of the SiGe in the first epitaxial layer (150A) may be 15% or less, furthermore 10% or less, and the Ge composition ratio of the SiGe in the second epitaxial layer (150B) may be 20% or more.

[0049] As previously described, the gate structure (160) may include a gate dielectric layer (162), a gate electrode (165), gate spacers (164), and a gate capping layer (166).

[0050] The gate dielectric layer (162) may be disposed between the fin-shaped active region (105) and the gate electrode (165) and between the channel structure (140) and the gate electrode (165), as shown in FIG. 2. The gate dielectric layer (162) may be formed to surround the channel layers (141, 142, 143, 144) in a second direction (e.g., Y direction) and may extend from the upper surface of the fin-shaped active region (105) to the upper surface of the device isolation film (110) (see FIG. 3B). As shown in FIG. 2, the gate dielectric layer (162) may extend between the gate electrode (165) and the gate spacers (164). For example, the gate dielectric layer (162) may comprise an oxide, a nitride, or a high-dielectric (high-k) material. The above high dielectric constant material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The above high dielectric constant material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi2). x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It may be at least one of ), and praseodymium oxide (Pr2O3).

[0051] A gate electrode (165) may be disposed extending above the channel structure (140) and filling between a plurality of channel layers (141, 142, 143, 144) above the fin-shaped active region (105). The gate electrode (165) may be spaced apart from the plurality of channel layers (141, 142, 143, 144) by a gate dielectric layer (162). The gate electrode (165) may include a conductive material and may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. In some embodiments, the gate electrode (165) may be composed of two or more layers. In some embodiments, the gate electrode (165) is positioned across adjacent transistors, and the gate electrode (165) may be separated by a separate separator located between adjacent transistors.

[0053] Gate spacers (164) may be placed on both sides of the gate electrode (165). The gate spacers (164) may insulate the source / drain regions (150) from the gate electrodes (165). In some embodiments, the gate spacers (164) may be made of a multilayer structure. For example, the gate spacers (164) may include oxides, nitrides, and oxynitrides, and in particular may include low dielectric constant films. The fence spacers (174) employed in this embodiment may include the same material as the gate spacers (164). A gate capping layer (166) may be placed on top of the gate electrode (165), and the bottom and sides may be surrounded by the gate electrode (165) and the gate spacers (164), respectively.

[0054] In this embodiment, the semiconductor device (100) may further include internal spacers (130) disposed on both sides of the gate electrode (165) between the channel layers (141, 142, 143, 144), as shown in FIG. 2. Below the third channel layer (143), the gate electrode (165) may be electrically isolated from the source / drain regions (150) by the internal spacers (130). The internal spacers (130) may have a convex curved surface on the side in contact with the gate electrode (165) toward the gate electrode (165), but are not limited thereto. For example, the internal spacers (130) may include oxides, nitrides, and oxynitrides. In particular, the internal spacers (130) may be made of a low dielectric constant film.

[0055] The contact plug (180) can be connected to the source / drain region (150) by penetrating the interlayer insulating film (190) and can apply an electrical signal to the source / drain region (150). The contact plug (180) can be placed on the source / drain region (150) as shown in FIGS. 1 and 2. In some embodiments, the contact plug (180) may be placed to have a longer length along the second direction (Y direction) than the source / drain region (150). The contact plug (180) may have a structure in which the width of the lower portion is narrower than the width of the upper portion, but is not limited thereto. The contact plug (180) may extend from the top, for example, below the fourth channel layer (144). The contact plug (180) may be recessed, for example, to a height corresponding to the upper surface of the third channel layer (143). For example, the contact plug (180) may include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo).

[0056] The interlayer insulating film (190) covers the source / drain regions (150) and gate structures (160) and may be positioned to cover the device isolation film (110) in an unillustrated region. For example, the interlayer insulating film (190) may comprise at least one of an oxide, a nitride, and an oxynitride, and may comprise a low dielectric constant material.

[0059] Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described in detail with reference to FIGS. 5 to 16.

[0060] FIGS. 5 to 8 are perspective views illustrating the formation of a fin structure and a dummy gate in a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 9 to 16 are cross-sectional views illustrating the process of forming a source / drain region and a gate structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0062] First, referring to FIG. 5, a semiconductor stack (ST) is formed on a substrate (101) in which first semiconductor layers (111) and second semiconductor layers (112) are alternately stacked.

[0063] The first semiconductor layers (111) can be removed in a subsequent process and used as a sacrificial layer, and the second semiconductor layers (112) can be used as a channel layer. The first semiconductor layers (111) and the second semiconductor layers (112) may include a semiconductor material comprising at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different semiconductor materials. The first semiconductor layers (111) may be made of a material having etch selectivity with respect to the second semiconductor layers (112). The second semiconductor layers (112) may include impurities but are not limited thereto. In some embodiments, the first semiconductor layers (111) may include silicon germanium (SiGe), and the second semiconductor layers (112) may include silicon (Si). The first semiconductor layers (111) and the second semiconductor layers (112) can be formed by performing an epitaxial growth process on the substrate (101). Each of the first semiconductor layers (111) and the second semiconductor layers (112) may have a thickness in the range of about 1 Å to 100 nm.

[0065] Next, referring to FIG. 6, an active structure can be formed by removing a portion of the semiconductor stack (ST) and the substrate (101) using a first mask pattern (M1) extended in a first direction (e.g., X direction).

[0066] The active structure may include a pin-shaped active region (105) and a pin structure (FS). The pin-shaped active region includes a structure protruding from the upper surface of the substrate (101) by removing a portion of the substrate (101), and the pin structure (FS) may include first semiconductor patterns (111) and second semiconductor patterns (112) that are alternately stacked on the pin-shaped active region (105). The pin-shaped active region (105) and the pin structure (FS) may be formed in a line shape extending in one direction, for example, in the first direction (X direction).

[0067] In the area where a portion of the substrate (101) has been removed, an insulating material is embedded, and then an etch-back is performed so that a portion of the pin-shaped active region (105) protrudes, thereby forming a device isolation film (110). That is, the upper surface of the device isolation film (110) can be etch-backed lower than the upper surface of the pin-shaped active region (105).

[0069] Next, referring to FIG. 7, sacrificial gate structures (170) can be formed to intersect a portion of the active structure, and gate spacers (164) and fence spacers (174) can be formed on both sides of the sacrificial gate structures (170) and on both sides of the active structure, respectively.

[0070] The sacrificial gate structures (170) may be sacrificial structures formed in a region where a gate dielectric layer (162) and a gate electrode (165) are disposed on top of the channel structures (140) shown in FIG. 2 through a subsequent process. The sacrificial gate structures (170) may have a line shape extending in a second direction (e.g., Y direction) intersecting the active structures and may be arranged spaced apart from each other in a first direction (X direction). After forming first and second sacrificial gate layers (172, 175) that are sequentially stacked on a substrate (101) (particularly, a device isolation layer (110)) on which the active structures are formed, the stack may be patterned using a second mask pattern (M2) to form the sacrificial gate structures (170) as shown in FIG. 7.

[0071] The first and second sacrificial gate layers (172, 175) may each be an insulating layer and a conductive layer, but are not limited thereto, and the first and second sacrificial gate layers (172, 175) may be formed as a single layer. In some embodiments, the first sacrificial gate layer (172) may comprise silicon oxide, and the second sacrificial gate layer (175) may comprise polysilicon. The second mask pattern (M2) may comprise silicon oxide and / or silicon nitride.

[0072] Next, after conformally forming a spacer material layer on the sacrificial gate structure and the active structure, anisotropic etching can be applied to form gate spacers (164) on both sides of the sacrificial gate structures (170), and fence spacers (174) can be formed on both sides of the active structure, namely the fin-shaped active region (105) and the fin structure (FS). The sides on which the gate spacers (164) are formed may be facing sides located in the first direction (e.g., X direction) of the sacrificial gate structures (170), and the sides on which the fence spacers (174) are formed may be facing sides located in the second direction (e.g., Y direction) of the active structure. Additionally, the gate spacers (164) and the fence spacers (174) may be made of the same material. The spacer material layer, i.e., the gate spacers (164) and fence spacers (174), may be made of a low dielectric constant material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0074] FIGS. 9 to 16 are cross-sectional views illustrating the process of forming internal spacers, source / drain regions, and gate structures as other parts of the manufacturing method of a semiconductor device according to one embodiment of the present invention.

[0075] Referring to FIG. 9, channel structures (140) can be formed by removing the sacrificial layers (120) and channel layers (141, 142, 143, 144) between the sacrificial gate structures (170) to form a recess (RC).

[0076] Here, the sacrificial layers (120) correspond to the first semiconductor pattern (111) shown in FIG. 8, and the channel layers (141, 142, 143, 144) may correspond to the second semiconductor pattern (112) shown in FIG. 8. The exposed sacrificial layers (120) and channel layers (141, 142, 143) can be removed using the second mask pattern (M2) and gate spacers (164) as a mask. Through this process, the length of the channel layers (141, 142, 143) along the first direction (e.g., X direction) can be determined. At the bottom of the sacrificial gate structures (170), the sacrificial layers (120) and channel structures (140) may be partially removed from the sides so that both sides along the first direction (e.g., X direction) are located at the bottom of the sacrificial gate structures (170) and gate spacers (164). Additionally, after this process, fence spacers (174) located on both sides of the active structure may remain. In the process of removing the exposed portions of the sacrificial layers (120) and channel layers (141, 142, 143), a portion of the fence spacers (174) (indicated by a dotted line) may be lost, thereby determining the height of the final fence spacers (174). In the cross-section in the first direction (e.g., X direction), the aspect ratio of the recess (RC) formed in this process may be 2.5 or greater, and in some embodiments, 2.8 or greater.

[0078] Next, referring to FIG. 10, a portion of the exposed sacrificial layers (120) is removed through both sides exposed in a first direction (e.g., X direction), and then, referring to FIG. 11, internal spacers (130) can be formed in the area where the sacrificial layers (120) have been removed.

[0079] The sacrificial layers (120) can be selectively etched with respect to the channel structures (140) by, for example, a wet etching process and removed to a predetermined depth from the side along the first direction (X direction). The sacrificial layers (120) may have inwardly concave sides (RL) by such side etching. However, the shape of the sides of the sacrificial layers (120) is not limited to that shown.

[0080] Internal spacers (130) can be formed by burying an insulating material in the area where the sacrificial layers (120) have been removed and removing the insulating material deposited on the outside of the channel structures (140). The internal spacers (130) can be formed of the same material as the gate spacers (164), but are not limited thereto. For example, the internal spacers (130) may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0082] Next, referring to FIG. 12, a first epitaxial layer (150A) can be formed to form source / drain regions in recesses (RC) located on both sides of the sacrifice gate structures (170).

[0083] The first epitaxial layer (150A) can be formed from silicon germanium (SiGe) by an SEG process. The first compositional ratio of germanium (Ge) in the first epitaxial layer (150A) may be 5% to 15%. It can be grown from the upper surface region of the pin-shaped active region (105), which is the bottom surface of the recess region (RC), and from the sides of the channel layers (141, 142, 143, 144). For example, the first epitaxial layer (150A) may be grown from the upper surface region of the pin-shaped active region (105). <100> It grows in the plane direction, and from the sides of the channel layers (141, 142, 143, 144) <110> It can be grown in a planar direction. In some embodiments, by adjusting the growth process conditions, portions formed from the sides of adjacent channel layers (141, 142, 143, 144) are merged together so that the first epitaxial layer (150A) can be grown continuously along the sidewall of the recess (RC). These growth conditions can be obtained, for example, by adjusting the growth pressure, growth temperature, and / or gas flow rate.

[0085] Referring to FIGS. 13 and 14, the process of forming a second epitaxial layer (150B) on a first epitaxial layer (150A) is illustrated.

[0086] First, referring to FIG. 13, a second epitaxial layer (150B') having an intermediate penetration region (TV) can be formed in the first epitaxial layer (150A).

[0087] The second epitaxial layer (150B') can be grown from the first epitaxial layer (150A) using an SEG process. The second epitaxial layer (150B') may contain silicon germanium containing Ge in a second compositional ratio greater than the first compositional ratio of the first epitaxial layer (150A). For example, the Ge compositional ratio of the SiGe that is the second epitaxial layer (150B') may be 20% or more. The second epitaxial layer (150B') is formed around the inlet of the recess (RC) before the reaction gas reaches the bottom surface of the recess (RC). <110> The area that reacts first in the plane direction may increase. Meanwhile, near the bottom surface of the recess (RC) <100> Growth in the planar direction may occur at a slow rate due to increased stress caused by the relatively narrow area. As a result, as shown in FIG. 11, around the entrance of the recess (RC) <110> A second epitaxial (150B) grown in the plane direction may be merged to form an intermediate penetration region (TV) which is a pinch-off void. This intermediate penetration region (TV) may have a structure open to the side facing the fence spacers (174). As in this embodiment, when the aspect ratio of the recess (RC) is large, the merging to form the intermediate penetration region (TV) may be performed more quickly.

[0089] Next, referring to FIG. 14, a second epitaxial layer (150B) can be formed within a first epitaxial layer (150A) through a continuous epitaxial growth process to form a desired source / drain region (150).

[0090] Through this process, the intermediate penetration region (TV) is filled, but because the lateral supply of reaction gas is not smooth due to the fence spacers (174), concave voids (V1, V2) that are not completely filled may be formed on each of the two sides of the source / drain region (150). In this incomplete filling process, epitaxial portions are merged from different directions, so dislocation defect points (P1, P2) may be observed within each void (V1, V2).

[0091] The source / drain region (150) formed in this embodiment may have a left-right asymmetrical shape. Specifically, the voids (V1, V2) located on both sides facing each of the fence spacers (174) may be located at different levels and may have different shapes and / or sizes. The second epitaxial layer (150B) may have a relatively flat or somewhat convex upper surface.

[0093] Next, referring to FIG. 15, an interlayer insulating film (190) can be formed, and the sacrificial layers (120) and sacrificial gate structures (170) can be removed to form upper gap regions (UR) and lower gap regions (LR).

[0094] The interlayer insulating film (190) can be formed by forming an insulating film covering the sacrificial gate structures (170) and source / drain regions (150) and performing a planarization process. The sacrificial layers (120) and the sacrificial gate structures (170) can be selectively removed with respect to the gate spacers (164), the interlayer insulating film (190), and the channel structures (140). First, upper gap regions (UR) can be formed by removing the sacrificial gate structures (170) together with the second mask pattern (M2), and then lower gap regions (LR) can be formed by removing the sacrificial layers (120) exposed through the upper gap regions (UR). For example, if the sacrificial layers (120) comprise silicon germanium (SiGe) and the channel structure (140) comprises silicon (Si), the sacrificial layers (120) can be selectively removed by performing a wet etching process using peracetic acid as an etchant. During this removal process, the source / drain regions (150) can be protected by an interlayer insulating film (190) and internal spacer layers (130).

[0096] Next, referring to FIG. 16, gate structures (160) can be formed within the upper gap regions (UR) and lower gap regions (LR).

[0097] Gate dielectric layers (162) can be formed to conformally cover the inner surfaces of the upper gap regions (UR) and lower gap regions (LR). Gate electrodes (165) can be formed to completely fill the upper gap regions (UR) and lower gap regions (LR), and then removed from the upper gap regions (UR) to a predetermined depth from the top. A gate capping layer (166) can be formed in the area where the gate electrodes (165) have been removed from the upper gap regions (UR). Through these processes, gate structures (160) comprising the gate dielectric layer (162), gate electrodes (165), gate spacers (164), and gate capping layer (166) can be formed.

[0099] Next, a semiconductor device (100) illustrated in FIGS. 2 to 3b can be manufactured by forming a contact plug (180) that penetrates the interlayer insulating film (190) and is connected to the source / drain region (150). A contact hole connected to the source / drain region (150) can be formed to penetrate the interlayer insulating film (190), and a contact plug (180) can be formed by embedding a conductive material within the contact hole. The lower surface of the contact hole may be recessed into the source / drain regions (150) or may have a curvature along the upper surface of the source / drain regions (150).

[0102] FIGS. 17a and FIGS. 17b are cross-sectional views illustrating a semiconductor device according to an embodiment of the present invention. The cross-sections of FIGS. 17a and FIGS. 17b can each be understood as regions corresponding to the cross-sections of FIGS. 4a and FIGS. 4b.

[0104] Referring to FIGS. 17a and 17b, the semiconductor device (100A) according to the present embodiment can be understood as similar to the semiconductor device (100) illustrated in FIGS. 1 to 4, except that the channel structure (140) includes three channel layers (141, 142, 143) and the source / drain regions include a first epitaxial layer (150A), a second epitaxial layer (150B), and a third epitaxial layer (150C). Additionally, unless specifically stated otherwise, the components of the present embodiment can be understood by referring to the description of identical or similar components of the semiconductor device (100) illustrated in FIGS. 1 to 4.

[0105] The channel structure (140) employed in this embodiment may include three channel layers (141, 142, 143). When the number of channel layers is small, a relatively low aspect ratio may be achieved, but because the fence spacers (174) are relatively high during the growth process of the source / drain region (150), the supply of reaction gas in the lateral direction is not smooth, so the previously described intermediate penetration region ("TV") in FIG. 13 may not be fully filled. As a result, the source / drain region (150) employed in this embodiment may have voids (V1, V2) formed on each of the two sides facing the fence spacers (174A).

[0106] The source / drain region (150) employed in this embodiment may include a first epitaxial layer (150A) disposed along the first direction on the sides of the plurality of channel layers (141, 142, 143) on the upper surface of the fin-shaped active region (105), a second epitaxial layer (150B) disposed on the first epitaxial layer (150A) and having a composition different from that of the first epitaxial layer (150A), and a third epitaxial layer (150C) disposed on the second epitaxial layer (150B) and having a composition different from that of the second epitaxial layer (150B) or a different impurity concentration.

[0107] For example, the first epitaxial layer (150A) may comprise silicon or silicon germanium having a relatively low composition ratio of germanium, and the second epitaxial layer (150B) may comprise silicon germanium having a relatively high composition ratio of germanium. Additionally, the third epitaxial layer (150C) may comprise silicon germanium having a relatively higher composition ratio of germanium or silicon germanium having other impurity concentrations. In this embodiment, the third epitaxial layer (150C) provides a region connected to the contact plug (170), and voids (V1, V2) may be formed on each side of the third epitaxial layer (150C).

[0109] FIGS. 18 and 19 are cross-sectional views illustrating semiconductor devices according to various embodiments of the present invention.

[0110] Referring to FIG. 18, the semiconductor device (100B) according to the present embodiment can be understood as similar to the semiconductor device (100) shown in FIG. 1 to 4, except that the fence spacers (174A) have a relatively large height and the location and arrangement of the voids (V1, V2) in the source / drain region (150) are different. Additionally, unless specifically stated otherwise, the components of the present embodiment can be understood by referring to the description of identical or similar components of the semiconductor device (100) shown in FIG. 1 to 4.

[0111] The fence spacers (174A) employed in this embodiment may have a height greater than that of the fence spacers (174) introduced in the preceding embodiment. The position and arrangement of the voids (V1, V2) can be varied by the relatively high fence spacers (174A). As shown in FIG. 18, in this embodiment, the voids (V1, V2) are positioned at a relatively low location on the side of the source / drain region (150), and in the cross-section along the second direction (e.g., Y direction), the shape of the source / drain region (150) may have an asymmetric structure different from that of the preceding embodiment.

[0113] Referring to FIG. 19, the semiconductor device (100C) according to the present embodiment can be understood as similar to the semiconductor device (100) shown in FIG. 1 to 3, except that the fence spacers (174B) have a relatively low height and the upper region of the source / drain area (150) has a width greater than the spacing of the fence spacers (174B). Additionally, unless specifically stated otherwise, the components of the present embodiment can be understood by referring to the description of identical or similar components of the semiconductor device (100) shown in FIG. 1 to 3.

[0114] The fence spacers (174B) employed in this embodiment may have a height smaller than that of the fence spacers (174) introduced in the preceding embodiment. The cross-sectional shape of the source / drain region (150), as well as the location and arrangement of the voids (V1, V2), may be altered by the relatively lower fence spacers (174A). In the cross-section according to the second direction (e.g., Y direction), the shape of the source / drain region (150) employed in this embodiment has an asymmetric structure different from that of the preceding embodiments. For example, as shown in FIG. 19, voids (V1, V2) may be formed at different locations on the sides facing the fence spacers (174B). Additionally, the width of the lower region of the source / drain region (150) in the second direction (e.g., Y direction) is defined by the spacing of the fence spacers (174), but unlike the previous embodiment, the upper region of the source / drain region (150) may have a width greater than the spacing of the fence spacers (174).

[0116] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0118] 101: Substrate 105: Pin-shaped active region 110: Device isolation layer 111: Sacrificial layer 112: Semiconductor layer 130: Internal spacer layer 140: Channel structure 141, 142, 143, 144: Channel layer 150: Source / Drain Region 150A: First Epitaxial Layer 150B: Second epitaxial layer V1, V2: Void 160: Gate structure 162: Gate dielectric layer 164: Gate spacer 165: Gate electrode 166: Gate capping layer 170: Sacrifice gate structure 174: Fence Spacer 180: Contact Plug 190: Interlayer insulation film

Claims

Claim 1 A semiconductor device comprising: a fin-shaped active region protruding from a substrate and extending in a first direction; a plurality of channel layers spaced apart from each other in a direction perpendicular to the upper surface of the substrate on the fin-shaped active region; a gate structure extending across the fin-shaped active region in a second direction intersecting the first direction and surrounding each of the plurality of channel layers; fence spacers extending in the vertical direction, each positioned to contact each of the two sides of the gate structure located in the second direction of the fin-shaped active region; and a source / drain region each positioned between the fence spacers on the fin-shaped active region on both sides of the gate structure and connected to each of the plurality of channel layers; wherein the source / drain region comprises a first portion positioned higher than the fence spacers in the vertical direction and a second portion having a void that contacts each of the two sides facing the fence spacers. Claim 2 A semiconductor device according to claim 1, wherein each of the fence spacers has an upper level of at least 30% of the height of the source / drain region. Claim 3 In claim 1, each of the fence spacers is a semiconductor device having a height of 30 nm or more. Claim 4 A semiconductor device according to claim 1, wherein the gate structure further comprises gate spacers located on both sides extended along the second direction, and the fence spacers comprise the same material as the material of the gate spacers. Claim 5 A semiconductor device according to claim 1, wherein in the cross-section in the first direction, the aspect ratio of the source / drain region is 2.5 or greater. Claim 6 A semiconductor device according to claim 1, further comprising internal spacer layers disposed on each of the two sides of the gate structure along the first direction below the lower surface of each of the plurality of channel layers. Claim 7 A fin-shaped active region protruding from a substrate and extending in a first direction; a plurality of channel layers spaced apart from each other and disposed on the fin-shaped active region in a direction perpendicular to the upper surface of the substrate; a gate structure extending across the fin-shaped active region in a second direction intersecting the first direction and surrounding each of the plurality of channel layers; and a source / drain region comprising a first epitaxial layer disposed along the first direction on the sides of each of the plurality of channel layers in the upper surface region of the fin-shaped active region on both sides of the gate structure, and a second epitaxial layer disposed on the first epitaxial layer and having a composition different from that of the first epitaxial layer. A semiconductor device comprising: fence spacers arranged to be in contact with each of the two sides of the fin-shaped active region located in the second direction on both sides of the gate structure, and each extending to each of the two sides of the source / drain region; wherein the source / drain region comprises a first portion arranged higher than the fence spacers in the vertical direction and a second portion arranged between the fence spacers, the cross-section in the second direction having a left-right asymmetric shape, and in the cross-section in the first direction, the aspect ratio of the cross-section of the source / drain region is 2.5 or greater, and each of the fence spacers has an upper level of 30% or more of the height of the source / drain region. Claim 8 In claim 7, the source / drain region has a concave void on each of the two sides facing the fence spacers, and the two sides of the source / drain region facing the fence spacers are provided by the second epitaxial layer. Claim 9 In claim 8, the concave voids located on each of the two sides facing the fence spacers are semiconductor devices located at different levels. Claim 10 A semiconductor device according to claim 7, wherein in the cross-section in the first direction, the aspect ratio of the second epitaxial layer is 2 or more.

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