Semiconductor package, and method of manufacturing the same

Abstract

One embodiment of the present invention comprises a first semiconductor chip including a first substrate, a first pad disposed on the first substrate, and a first insulating layer surrounding the first pad on the first substrate; A semiconductor package is provided that includes a second semiconductor chip disposed on the first semiconductor chip, comprising a second substrate, a second pad disposed below the second substrate and in contact with the first pad, and a second insulating layer that surrounds the second pad below the second substrate and in contact with the first insulating layer, wherein the first insulating layer has a first recess spaced apart from the first pad in a first direction, and the second insulating layer has a second recess spaced apart from the second pad in the first direction and overlapping with at least a portion of the first recess in a second direction perpendicular to the first direction to provide an air gap together with the first recess, and a first bonding surface in which the first insulating layer and the second insulating layer contact at one side of the air gap adjacent to the first pad and the second pad, and a second bonding surface in which the first insulating layer and the second insulating layer contact at the other side of the air gap opposite to the one side.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. Background Technology

[0003] As the demand for high capacity, thinness, and miniaturization of electronic products increases, various types of semiconductor packages are being developed. Recently, direct bonding technology, which joins semiconductor chips without adhesive films (e.g., NCF) or connection bumps (e.g., solder balls), is being developed as a method to integrate more components (e.g., semiconductor chips) into the package structure. The problem to be solved

[0005] One of the problems that the present invention aims to solve is to provide a semiconductor package with improved reliability and a method for manufacturing the semiconductor package. means of solving the problem

[0007] As a means of solving the above-mentioned problem, one embodiment of the present invention comprises a first semiconductor chip including a first substrate, a first pad disposed on the first substrate, and a first insulating layer surrounding the first pad on the first substrate; A semiconductor package is provided that includes a second semiconductor chip disposed on the first semiconductor chip, comprising a second substrate, a second pad disposed below the second substrate and in contact with the first pad, and a second insulating layer that surrounds the second pad below the second substrate and in contact with the first insulating layer, wherein the first insulating layer has a first recess spaced apart from the first pad in a first direction, and the second insulating layer has a second recess spaced apart from the second pad in the first direction and overlapping with at least a portion of the first recess in a second direction perpendicular to the first direction to provide an air gap together with the first recess, and a first bonding surface in which the first insulating layer and the second insulating layer contact at one side of the air gap adjacent to the first pad and the second pad, and a second bonding surface in which the first insulating layer and the second insulating layer contact at the other side of the air gap opposite to the one side.

[0009] Additionally, a first semiconductor chip comprising a first substrate, a plurality of first pads disposed on the first substrate, and a first insulating layer surrounding the plurality of first pads on the first substrate; A semiconductor package is provided that includes a second semiconductor chip disposed on the first semiconductor chip, comprising a second substrate, a plurality of second pads disposed below the second substrate, and a second insulating layer surrounding the plurality of second pads below the second substrate, wherein the first and second semiconductor chips are electrically connected by at least one pair of first and second bonding pad structures in which the plurality of first pads and the plurality of second pads come into contact, and has a first gap surrounding the first bonding pad structure and a second gap surrounding the second bonding pad structure, and has first bonding surfaces in which at least a portion of the first insulating layer and the second insulating layer come into contact between the first bonding pad structure and the first gap and between the second bonding pad structure and the second gap, and a second bonding surface in which at least a portion of the first insulating layer and the second insulating layer come into contact between the first gap and the second gap.

[0011] Additionally, the semiconductor package comprises: a first semiconductor chip including a first substrate, a first pad disposed on the first substrate, and a first insulating layer having a first recess surrounding the first pad; and a second semiconductor chip disposed on the first semiconductor chip, comprising a second substrate, a second pad disposed below the second substrate and in contact with the first pad, and a second insulating layer having a second recess surrounding the second pad and in contact with the first insulating layer, wherein the entire side of each of the first pad and the second pad is covered by the first and second insulating layers.

[0013] Additionally, the present invention provides a method for manufacturing a semiconductor package comprising the steps of: preparing a semiconductor wafer including a preliminary substrate, a circuit layer disposed on the front surface of the preliminary substrate, and a preliminary insulating layer disposed on the circuit layer; etching at least a portion of the preliminary insulating layer to form a front insulating layer including an etching groove; forming a preliminary barrier layer and a preliminary conductive layer on the front insulating layer and the etching groove; polishing the preliminary barrier layer and the preliminary conductive layer to form a front pad including a barrier layer and a conductive layer - performed by a polishing process using a first slurry -; and polishing the front insulating layer to form a recess spaced apart from the front pad by a predetermined distance - performed by a polishing process using a second slurry -.

[0015] Additionally, the present invention provides a method for manufacturing a semiconductor package comprising the steps of: preparing a semiconductor wafer including a preliminary substrate and a plurality of through electrodes arranged within the preliminary substrate; removing a portion of the preliminary substrate to form a substrate having a rear surface on which the plurality of through electrodes protrude; forming a preliminary protective layer and a preliminary buffer film covering the plurality of through electrodes on the rear surface of the substrate; flattening the preliminary protective layer and the preliminary buffer film to form a flat surface on which the plurality of through electrodes are exposed; forming a preliminary insulating layer on the flat surface; etching at least a portion of the preliminary insulating layer to form a rear insulating layer including an etching groove; forming a preliminary barrier layer and a preliminary conductive layer on the rear insulating layer and the etching groove; polishing the preliminary barrier layer and the preliminary conductive layer to form a rear pad including a barrier layer and a conductive layer - performed by a polishing process using a first slurry -; and polishing the rear insulating layer to form a recess spaced apart from the rear pad by a predetermined distance - performed by a polishing process using a second slurry -.

[0017] Additionally, the present invention provides a method for manufacturing a semiconductor package comprising the steps of: preparing a semiconductor wafer including a plurality of rear pads and a rear insulating layer surrounding the plurality of rear pads, wherein the rear insulating layer includes first recesses spaced apart from the plurality of rear pads; preparing a plurality of second semiconductor chips including a plurality of front pads and a front insulating layer surrounding the plurality of front pads, wherein the front insulating layer includes second recesses spaced apart from the plurality of front pads; arranging the plurality of second semiconductor chips on the semiconductor wafer such that a gap is formed between the first and second recesses, wherein the plurality of rear pads are in contact with the plurality of front pads, and the rear insulating layer is in contact with the front insulating layer in the remaining portion excluding the gap; and performing a thermal compression process to combine the rear insulating layer and the front insulating layer joined together, and to combine the plurality of rear pads and the plurality of front pads joined together. Effects of the invention

[0019] According to embodiments of the present invention, by introducing a gap spaced apart from the bonding pad structure, a stack of semiconductor chips having a bonding interface of excellent quality can be realized, and a semiconductor package with improved reliability and a method for manufacturing the semiconductor package can be provided. Brief explanation of the drawing

[0021] FIG. 1a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, FIG. 1b is a partial enlarged view illustrating region 'A' of FIG. 1a, FIG. 1c is a partial enlarged view illustrating region 'B' of FIG. 1a, and FIG. 1d and FIG. 1e are plan views illustrating a cross-sectional view along line II' of FIG. 1c. FIG. 2 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention. FIG. 3 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention. FIG. 4 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention. FIG. 5 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention. FIG. 6 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention. FIG. 7 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention. FIG. 8 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 9a is a plan view illustrating a semiconductor package according to one embodiment of the present invention, and FIG. 9b is a cross-sectional view illustrating a cross-section along the line II-II' of FIG. 9a. FIG. 10a is a plan view illustrating a semiconductor package according to one embodiment of the present invention, and FIG. 10b is a cross-sectional view illustrating a cross-section along the line III-III' of FIG. 10a. FIGS. 11a to 11h are cross-sectional views illustrating a manufacturing process for forming a recess on the back surface of a semiconductor chip. FIGS. 12a to 12d are cross-sectional views illustrating a manufacturing process for forming a recess on the front surface of a semiconductor chip. FIG. 13 is a cross-sectional view illustrating the manufacturing process of the semiconductor package of FIG. 1a. Specific details for implementing the invention

[0022] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0024] FIG. 1a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, FIG. 1b is a partial enlarged view illustrating region 'A' of FIG. 1a, FIG. 1c is a partial enlarged view illustrating region 'B' of FIG. 1a, and FIG. 1d and 1e are plan views illustrating a cross-sectional view along line II' of FIG. 1c.

[0026] Referring to FIG. 1a, a semiconductor package (10) of one embodiment may include a plurality of semiconductor chips stacked in a vertical direction (Z-axis direction), for example, a first semiconductor chip (100) and a second semiconductor chip (200). The first semiconductor chip (100) and the second semiconductor chip (200) may be directly bonded and coupled (for example, referred to as hybrid bonding, direct bonding, etc.) between the upper surface of the first semiconductor chip (100) and the lower surface of the second semiconductor chip (200) without connecting members such as metal bumps. A first insulating layer (151) and first upper pads (152) providing the upper surface of the first semiconductor chip (100) may be bonded and coupled with a second insulating layer (231) and second lower pads (232) providing the lower surface of the second semiconductor chip (200), respectively. The first semiconductor chip (100) can be electrically connected to the second semiconductor chip (200) by bonding pad structures (BP) in which the first upper pads (152) and the second lower pads (232) are bonded.

[0027] The present invention can trap gases generated during the thermal compression process and prevent interfacial delamination or void formation by forming air gaps (AG) surrounding bonding pad structures (BP) between the first insulating layer (151) and the second insulating layer (231). Additionally, the air gaps (AG) are spaced apart from the bonding pad structures (BP) by a predetermined distance, thereby forming a bonding interface (or 'bonding surface') between the first insulating layer (151) and the second insulating layer (231) between the bonding pad structures (BP) and the air gaps (AG), which can improve the bonding quality of the first upper pads (152) and the second lower pads (232).

[0028] For example, at least a portion of the first insulating layer (151) may be located between the side of the first upper pad (152) and the first recess (151R), and at least a portion of the second insulating layer (231) may be located between the side of the second lower pad (232) and the second recess (231R), wherein the at least portion of the first insulating layer (151) may be in contact with the at least portion of the second insulating layer. Thus, the entire side of each of the first upper pad (152) and the second lower pad (232) may be covered by the first and second insulating layers (151, 231) and may not be exposed through the first and second recesses (151R, 231R). Here, the "first insulating layer" and the "second insulating layer" may be referred to as the "first upper insulating layer" or the "first rear insulating layer" and the "second lower insulating layer" or the "second front insulating layer," respectively, in order to distinguish the locations of the components within the first semiconductor chip (100) or the second semiconductor chip (200). Additionally, the "first upper pad" and the "second lower pad" may be referred to as the "first pad" or the "first rear pad" and the "second pad" or the "second front pad," respectively.

[0029] Hereinafter, the components of the first semiconductor chip (100) and the second semiconductor chip (200) will be described in detail with reference to FIG. 1b to 1e together with FIG. 1a.

[0031] The first semiconductor chip (100) may include a first substrate (110), a first circuit layer (120), a first through electrode (140), a first insulating layer (151), and a first upper pad (152). The first semiconductor chip (100) may have a flat upper surface provided by the upper surface of the first insulating layer (151) and the upper surface of the first upper pads (152). For example, the upper surface of the first insulating layer (151) excluding the first recess (151R) and the upper surface of the first upper pads (152) exposed from the first insulating layer (151) may be substantially coplanar.

[0033] The first substrate (110) may be a semiconductor wafer substrate having a front surface (FR) and a back surface (BA) facing each other. For example, the first substrate (110) may be a semiconductor wafer comprising a semiconductor element such as silicon or germanium, or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The front surface (FR) may be an active surface having an impurity-doped active region, and the back surface (BA) may be an inactive surface located opposite to the front surface (FR). An insulating protective layer (113) that electrically insulates the first upper pad (152) and the first substrate (110) may be disposed on the back surface (BA) of the first substrate (110). For example, the insulating protective layer (113) may include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film (114), such as a polishing stop layer or a barrier, may be disposed on the upper surface of the insulating protective layer (113). For example, the buffer film (114) may include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0035] The first circuit layer (120) is disposed on the front surface (FR) of the first substrate (110) and may include a first wiring structure (not shown) connected to an active area and a first interlayer insulating layer (not shown) surrounding it. Below the first circuit layer (120), a first lower pad (132) electrically connected to the wiring structure (not shown) may be disposed. The first lower pad (132) may be a pad structure electrically connected to the wiring structure (not shown). Below the first lower pad (132), a connection bump (136) may be disposed. The connection bump (136) may be a conductive bump structure including, for example, a solder ball or a copper (Cu) post. The first circuit layer (120) may have the same or similar structure as the second circuit layer (220) shown in FIG. 1b and 1c, etc. Accordingly, the first wiring structure (not shown) and the first interlayer insulation layer (not shown) can be understood to have similar characteristics to the second wiring structure (225) and the second interlayer insulation layer (221) of the second circuit layer (220) described later. Additionally, by referring to the modified example of FIG. 7, the structure of the first wiring structure ('125' in FIG. 7) and the first interlayer insulation layer ('121' in FIG. 7) of the first circuit layer (120) can be easily understood.

[0037] The first through electrode (140) can penetrate the first substrate (110) and the insulating protective layer (113) to electrically connect the first upper pad (152) and the first lower pad (132). The first through electrode (140) may include a via plug (145) and a side barrier layer (141) surrounding the side of the via plug (145). The via plug (145) may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu) and may be formed by a plating process, a PVD process, or a CVD process. The side barrier layer (141) may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) and may be formed by a plating process, a PVD process, or a CVD process. A side insulating film (not shown) comprising an insulating material such as silicon oxide, silicon nitride, silicon oxynitride (e.g., HARP (High Aspect Ratio Process) oxide) may be formed between the side barrier layer (141) and the first substrate (110).

[0039] The first insulating layer (151) may be disposed on the back surface (BA) of the first substrate (110). The first insulating layer (151) may include an insulating material that can be bonded and coupled with the second insulating layer (231) below the second semiconductor chip (200). For example, the first insulating layer (151) may include silicon oxide (SiO) or silicon carbonitride (SiCN). That is, at least a portion of the first insulating layer (151) may be bonded with the second insulating layer (131) to form bonding surfaces (BS1, BS2) that bond and combine the first semiconductor chip (100) and the second semiconductor chip (200). Additionally, the first insulating layer (151) is formed to surround a plurality of first upper pads (152) arranged on its upper surface, and may have a plurality of first recesses (151R) surrounding the plurality of first upper pads (152) at a predetermined distance apart from them. The plurality of first recesses (151R) may be vertically aligned with a plurality of second recesses (231R) of the second semiconductor chip (200) to form a void (AG) surrounding the bonding pad structure (BP). Here, the first insulating layer (151) may be referred to as the first upper insulating layer (151).

[0041] The first upper pad (152) is disposed on the back surface (BA) of the first substrate (110) and may include a first barrier layer (153) and a first conductive layer (155). At least a portion of the first upper pad (152) may be bonded to the second lower pad (232) of the second semiconductor chip (200) to form a bonding pad structure (BP) and a bonding surface ('BS3' in FIG. 13) that physically and electrically bond the first semiconductor chip (100) and the second semiconductor chip (200). The first barrier layer (153) may be formed to extend conformally between the first conductive layer (155) and the first insulating layer (151) to surround the outer edge of the first conductive layer (155). The first conductive layer (155) and the first barrier layer (153) may include a conductive material. For example, the first conductive layer (155) may include at least one of copper (Cu), nickel (Ni), gold (Au), and silver (Ag), and the first barrier layer (153) may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0043] A second semiconductor chip (200) is disposed on a first semiconductor chip (100) and may include a second substrate (210), a second circuit layer (220), a second insulating layer (231), and a second lower pad (232). The second semiconductor chip (200) may have a flat bottom surface provided by the bottom surface of the second insulating layer (231) and the bottom surface of the second lower pads (232). For example, the bottom surface of the second insulating layer (231) excluding the second recess (231R) and the bottom surface of the second lower pads (232) exposed from the second insulating layer (231) may be substantially in the same plane. Since the first semiconductor chip (100) and the second semiconductor chip (200) may have substantially the same or similar structure, identical or similar components are indicated by identical or similar reference numerals, and a repeated description of identical components is omitted below. For example, the second substrate (210) can be understood to have substantially the same features as the first substrate (110) described above.

[0045] The second circuit layer (220) is disposed on the front or active surface of the second substrate (210) and may include a second wiring structure (225) connected to the active area and a second interlayer insulating layer (221) surrounding it.

[0046] The second interlayer insulating layer (221) may include FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma) oxide, PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD) oxide, or a combination thereof. At least a portion of the second interlayer insulating layer (221) surrounding the second wiring structure (225) may be composed of a low dielectric layer. The second interlayer insulating layer (221) may be formed using a chemical vapor deposition (CVD), a flowable-CVD process, or a spin coating process.

[0047] The second wiring structure (225) may be formed as a multilayer structure including wiring patterns and vias made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film (not shown) comprising titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the wiring pattern or / and vias and the second interlayer insulating layer (221). Individual components (215) constituting an integrated circuit may be disposed on the front surface of the second substrate (210). In this case, the second wiring structure (225) may be electrically connected to the individual components (215) by an interconnection portion (213) (e.g., a contact plug). The individual devices (215) may include various active and / or passive devices such as FETs like planar FET or FinFET, memory devices such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, RRAM, logic devices such as AND, OR, NOT, system LSI, CIS, MEMS.

[0049] The second insulating layer (231) may be disposed below the second substrate (210) or the second circuit layer (220). The second insulating layer (231) may include an insulating material that can be bonded and coupled with the first insulating layer (151) of the first semiconductor chip (200). For example, the second insulating layer (231) may include silicon oxide (SiO) or silicon carbonitride (SiCN). That is, at least a portion of the second insulating layer (231) may be bonded with the first insulating layer (151) to form bonding surfaces (BS1, BS2) that bond and combine the first semiconductor chip (100) and the second semiconductor chip (200). Additionally, the second insulating layer (231) is formed to surround a plurality of second lower pads (232) arranged on its lower surface, and may have a plurality of second recesses (231R) surrounding the plurality of second lower pads (232) at a predetermined distance apart from them. The plurality of second recesses (231R) may be vertically aligned with a plurality of first recesses (151R) of the first semiconductor chip (100) to form a void (AG) surrounding the bonding pad structure (BP). Here, the second insulating layer (231) may be referred to as the second lower insulating layer (151).

[0051] The second lower pad (232) is positioned below the second substrate (210) and may include a second barrier layer (233) and a second conductive layer (235). At least a portion of the second lower pad (232) may be bonded to the first upper pad (152) of the first semiconductor chip (100) to form a bonding pad structure (BP) and a bonding surface ('BS3' in FIG. 13) that physically and electrically bond the first semiconductor chip (100) and the second semiconductor chip (200). The second barrier layer (233) and the second conductive layer (235) may be made of the same or similar structure and material as the first barrier layer (153) and the first conductive layer (155) described above.

[0053] As described above, the first recess (151R) of the first insulating layer (151) and the second recess (231R) of the second insulating layer (231) can provide a void (AG) surrounding the bonding pad structure (BP). By being spaced apart from the bonding pad structure (BP) by a predetermined distance, the quality of the bonding interface between the first semiconductor chip (100) and the second semiconductor chip (200) can be improved, and the reliability of the semiconductor package (10) can be enhanced. Below, the bonding surfaces (BS1, BS2) formed around the bonding pad structure (BP) and the void (AG) will be described in more detail.

[0055] As illustrated in FIG. 1b, the semiconductor package (10) of the present embodiment may include at least one pair of adjacent first bonding pad structures (BP1) and second bonding pad structures (BP2) among a plurality of bonding pad structures (BP) that electrically connect a first semiconductor chip (100) and a second semiconductor chip (200).

[0056] At least one pair of first bonding pad structures (BP1) and second bonding pad structures (BP2) may be conductive structures in which a plurality of first upper pads (152) and a plurality of second lower pads (232) are bonded and combined. At this time, between at least one pair of first bonding pad structures (BP1) and second bonding pad structures (BP2), a first void (AG1) adjacent to the first bonding pad structure (BP1), a second void (AG2) adjacent to the second bonding pad structure (BP2), first bonding surfaces (BS1) located between the first bonding pad structure (BP1) and the first void (AG1) and between the second bonding pad structure (BP2) and the second void (AG2), and a second bonding surface (BS1) located between the first void (AG1) and the second void (AG2) may be formed.

[0057] The first void (AG1) may be configured to surround the first bonding pad structure (BP1) at a predetermined distance from the first bonding pad structure (BP1). The second void (AG2) may be configured to surround the second bonding pad structure (BP2) at a predetermined distance from the second bonding pad structure (BP2). The first bonding surfaces (BS1) may be the bonding interfaces of the first upper insulating layer (231) and the second lower insulating layer (231) bonded between the first bonding pad structure (BP1) and the first void (AG1), and between the second bonding pad structure (BP2) and the second void (AG2). The second bonding surface (BS2) may be the bonding interfaces of the first upper insulating layer (231) and the second lower insulating layer (231) bonded between the first void (AG1) and the second void (AG2).

[0058] The first void (AG1) and the second void (AG2) can trap gases generated during the bonding process of the first semiconductor chip (100) and the second semiconductor chip (200), and prevent interfacial delamination or the occurrence of voids. The width (W1) of the first void (AG1) and the width (W2) of the second void may each be about 25% or less of the gap (D) (hereinafter referred to as 'pad gap') between the first bonding pad structure (BP1) and the second bonding pad structure (BP2), for example, in the range of about 5% to about 25%, about 10% to about 25%, or about 15% to about 25%. If the width (W1) of the first void (AG1) and the width (W2) of the second void are less than about 5% of the pad gap (D), the gas trapping effect may be negligible. If the width (W1) of the first gap (AG1) and the width (W2) of the second gap exceed about 25% of the pad gap (D), sufficient bonding force may not be secured between the first upper insulating layer (231) and the second lower insulating layer (231). The bonding force between the first upper insulating layer (231) and the second lower insulating layer (231) can be secured by the second bonding surface (BS2). For example, the second bonding surface (BS2) may have a length (L2) that is equal to or greater than the sum of the width (W1) of the first gap (AG1) and the width (W2) of the second gap (AG2). On the other hand, the first bonding surfaces (BS1) are intended to support and secure the first upper pad (152) and the second lower pad (232) and ensure the reliability of their bonding during the bonding process (e.g., a heat pressing process), so they may be formed with a length (L1) that is relatively smaller than that of the second bonding surface (BS2). For example, the first bonding surfaces (BS1) may have a length (L1) that is smaller than the width (W1) of the first gap and the width (W2) of the second gap. Here, the length (L1) of the first bonding surface (BS) may refer to the width ('w' in FIG. 1d) of the bonding interface between the first upper insulating layer (151) and the second lower insulating layer (231) between the bonding pad structure (BP) and the gap (AG).

[0059] For example, when the pad gap (D) is about 2 μm, the widths (W1, W2) of the first and second gaps (AG1, AG2) are each in the range of about 0.1 μm to about 0.5 μm, the length (L2) of the second bonding surface (BS2) is in the range of about 1 μm to about 1.8 μm, and the length (L1) of the first bonding surfaces (BS1) is in the range of about 0.1 nm to about 100 nm. Here, since the length (L1) of the first bonding surfaces (BS1) is very small compared to the widths (W1, W2) of the first and second gaps (AG1, AG2) and the length (L2) of the second bonding surface (BS2), the widths (W1, W2) of the first and second gaps (AG1, AG2) were calculated without considering the length (L1) of the first bonding surfaces (BS1) within the pad gap (D). That is, the length (L1) of the first bonding surfaces (BS1) can be varied in various ways considering the size of the first upper pad (152) or the second lower pad (132), process margin, etc., and is not limited to the numerical range described above.

[0061] As illustrated in FIG. 1c, the void (AG) surrounding the bonding pad structure (BP) can be formed by a first recess (151R) and a second recess (231R). For example, the first upper insulating layer (151) may have a first recess (151R) spaced apart from the first upper pad (152) in a first direction (X-axis or Y-axis direction), and the second lower insulating layer (231) may have a second recess (231R) spaced apart from the second lower pad (232) in a first direction (X-axis or Y-axis direction) and overlapping with the first recess (151R) in a second direction (Z-axis direction) to provide a single void (AG) together with the first recess (151R).

[0062] A first bonding surface (BS1) may be formed on one side of a void (AG) adjacent to the first upper pad (132) and the second lower pad (232), and a second bonding surface (BS2) may be formed on the other side of the void (AG) opposite to the said side. That is, the first upper insulating layer (151) and the second lower insulating layer (231) may be bonded between the bonding pad structure (BP) and the void (AG) to form the first bonding surface (BS1), and bonded on the outside of the void (AG) to form the second bonding surface (BS2).

[0063] The shapes of the first recess (151R), the second recess (231R), and the void (AG) are not particularly limited and may have various shapes depending on the manufacturing process. For example, the first recess (151R) may include a curved surface recessed from a first upper surface of the first upper insulating layer (151) facing the second semiconductor chip (200) toward a first lower surface opposite to the first upper surface, and the second recess (231R) may include a curved surface recessed from a second lower surface of the second lower insulating layer (231) facing the first semiconductor chip (100) toward a second upper surface opposite to the second lower surface.

[0064] The first recess (151R) and the second recess (231R) (or void (AG)) may have a predetermined separation distance (d) from the first upper pad (152) or the second lower pad (232). As described with reference to FIG. 1b, the separation distance (d) is intended to ensure the reliability of the bonding between the first upper pad (152) and the second lower pad (232), so it may be formed in various ranges depending on the size of the first upper pad (152) and the second lower pad (232). For example, the above separation distance (d) may be in the range of about 0.1 nm to about 500 nm, about 0.1 nm to about 400 nm, about 0.1 nm to about 300 nm, about 0.1 nm to about 200 nm, about 0.1 nm to about 100 nm, about 1 nm to about 100 nm, about 10 nm to about 100 nm, etc. The above separation distance (d) can be understood as substantially the same as the length (L1) of the first bonding surface (BS) described with reference to FIG. 1b. However, depending on the embodiment, the above separation distance (d) and the length (L1) of the first bonding surface (BS) may be different (the embodiment of FIG. 2).

[0066] The first recess (151R) and the second recess (231R) may each be formed to surround the first upper pad (152) and the second lower pad (232), respectively, on a plane (e.g., an XY plane).

[0067] For example, as illustrated in FIG. 1d, the void (AG) (or the first and second recesses (151R, 231R)) may be formed to surround at least part or all of the bonding pad structure (BP) (or the first upper pad (152) and the second lower pad (232)) in a planar plane. Additionally, the first bonding surface (BS1) may be formed to surround at least part or all of the bonding pad structure (BP) (or the first upper pad (152) and the second lower pad (232)) with a predetermined width (w) in a planar plane. Here, the width (w) of the first bonding surface (BS1) can be understood to have a range similar to the spacing distance (d) in FIG. 1c. Depending on the embodiment, the width (w) of the first bonding surface (BS1) may not be constant as illustrated in FIG. 1d (see FIG. 1e).

[0068] For example, as illustrated in FIG. 1e, the first bonding surface (BS1') may be formed to have a first width (w1) and a second width (w2) of different sizes. For example, the first width (w1) and the second width (w2) may be formed in a range of about 0.1 nm to about 500 nm, about 0.1 nm to about 400 nm, about 0.1 nm to about 300 nm, about 0.1 nm to about 200 nm, about 0.1 nm to about 100 nm, about 1 nm to about 100 nm, about 10 nm to about 100 nm, etc. The first width (w1) and the second width (w2) are not limited to the numerical ranges described above and may be varied in various ways depending on the size (width, volume, etc.) of the first upper pad (152) or the second lower pad (232).

[0070] FIG. 2 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention.

[0072] Referring to FIG. 2, in a modified example semiconductor package (10a), the length (La) of the first bonding surface (BS1) may differ from the separation distances (d1, d2) of the first recess (151R) and the second recess (231R), respectively. For example, the first recess (152R) and the first upper pad (152) may be separated by a first distance (d1), the second recess (231R) and the second lower pad (232) may be separated by a second distance (d2), and the first bonding surface (BS1) may have a length (La) smaller than the first and second distances (d1, d2). The length (La) of the first bonding surface (BS1) may refer to the length of the bonding interface between the first upper insulating layer (151) and the second lower insulating layer (231) within the first and second distances (d1, d2). For example, the difference in length (La) of the first bonding surface (BS1) and the spacing distances (d1, d2) of the first recess (151R) and the second recess (231R) may be caused by a mismatch between the first upper pad (152) and the second lower pad (232). However, the present variation is not limited to the mismatch form shown in the drawing. For example, the present variation may also appear when there is a difference in size between the first upper pad (152) and the second lower pad (232), for example, when the horizontal (X-axis direction) width of the first upper pad (152) is greater than the horizontal (X-axis direction) width of the second lower pad (232).

[0074] FIG. 3 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention.

[0076] Referring to FIG. 3, the semiconductor package (10b) of the modified example may have a heterojunction structure in which different materials are bonded at the bonding interface of the first upper insulating layer (151) and the second lower insulating layer (231). For example, the second lower insulating layer (231) may include a lower insulating film (231b) in direct contact with the first upper insulating layer (151), and an upper insulating film (231a) disposed on the lower insulating film (231b). To improve the bonding strength between the first upper insulating layer (151) and the second lower insulating layer (231), the lower insulating film (231b) may include an insulating material different from that of the first upper insulating layer (151). For example, the first upper insulating layer (151) may include silicon oxide (SiO), and the lower insulating film (231b) of the second lower insulating layer (231) may include silicon carbonitride (SiCN). In this case, the second recess (231R) may have a depth (dp) equal to or smaller than the thickness (t) of the lower insulating film (231b). For example, the thickness (t) of the lower insulating film (231b) may be in the range of about 0.1 μm to about 2 μm.

[0078] FIG. 4 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention.

[0080] Referring to FIG. 4, a semiconductor package (10b) of a modified example may include a first upper insulating layer (151) and / or a second lower insulating layer (231) composed of a plurality of insulating films. For example, the second lower insulating layer (231) may include a lower insulating film (231b) in direct contact with the first upper insulating layer (151), and an upper insulating film (231a) disposed on the lower insulating film (231b), and the lower insulating film (231b) may be composed of a first lower insulating film (231b1) and a second lower insulating film (231b2). The second lower insulating film (231b2) may include an insulating material different from that of the first upper insulating layer (151). For example, the first upper insulating layer (151) may include silicon oxide (SiO), and the second lower insulating film (231b2) may include silicon carbonitride (SiCN). Additionally, the first lower insulating film (231b1) may contain the same or different material as the second lower insulating film (231b2). For example, the first lower insulating film (231b1) may contain silicon oxide (SiO) or silicon carbonitride (SiCN). In the case of this variation, the second recess (231R) may have a depth (dp) equal to or smaller than the thickness (t1) of the second lower insulating film (231b2) located at the bottom. That is, the second recess (231R) is formed within the thickness (t1) of the second lower insulating film (231b2) that forms a bonding interface with the first upper insulating layer (151), thereby ensuring interface reliability between the first lower insulating film (231b1) and the second lower insulating film (231b2). The lower insulating film (231b) may be composed of a greater number of insulating films than shown in the drawing. In addition, depending on the variation example, the first upper insulating layer (151) may also be composed of a plurality of insulating films.

[0082] FIG. 5 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention.

[0084] Referring to FIG. 5, a semiconductor package (10d) of a modified example may include grooves (g1, g2) formed within a bonding pad structure (BP). For example, a first upper pad (152) may include a first conductive layer (155) and a first barrier layer (153) surrounding the side of the first conductive layer (155), and a second lower pad (232) may include a second conductive layer (235) in contact with at least a portion of the first conductive layer (155) and a second barrier layer (233) surrounding the side of the second conductive layer (235), wherein the first conductive layer (155) may have a first groove (g1) that exposes at least a portion of the first barrier layer (153), and the second conductive layer (235) may have a second groove (g2) that exposes at least a portion of the second barrier layer (233). That is, at least a portion of the inner walls of the first barrier layer (153) and the second barrier layer (233) may be exposed from the first conductive layer (155) and the second conductive layer (235) by the first groove (g1) and the second groove (g2). On the other hand, the outer walls of the first barrier layer (153) and the second barrier layer (233) may be covered by the first upper insulating layer (151) and the second lower insulating layer (231) and may not be exposed to the void (AG). The first groove (g1) and the second groove (g2) secure an expansion space for the first conductive layer (155) and the second conductive layer (235) during the bonding and joining process of the first upper pad (152) and the second lower pad (232), thereby allowing the first upper pad (152) and the second lower pad (232), which are fixed by the first bonding surface (BS1), to be joined more stably.

[0086] FIG. 6 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention.

[0088] Referring to FIG. 6, a semiconductor package (10e) of a modified example may include a first recess (151R) and a second recess (231R) formed by a photolithography process and an etching process. For example, the first recess (151R) may include a first flat surface recessed from a first upper surface of a first upper insulating layer (151) facing the second semiconductor chip (200) toward the opposite first lower surface (S1), and the second recess (231R) may include a second flat surface recessed from a second lower surface of a second lower insulating layer (231) facing the first semiconductor chip (100) toward the opposite second upper surface (S2). In the case of this modified example, the spacing between the first recess (151R) and the second recess (231R) and the length of the first bonding surface (BS1) can be easily adjusted compared to forming the first recess (151R) and the second recess (231R) using a flattening process (e.g., a CMP process).

[0090] FIG. 7 is a partial enlarged view illustrating a modified example of a semiconductor package according to one embodiment of the present invention.

[0092] Referring to FIG. 7, in a modified example semiconductor package (10f), a second semiconductor chip (200) can be stacked on a first circuit layer (120) of a first semiconductor chip (100). That is, the first semiconductor chip (100) and the second semiconductor chip (200) can be arranged so that a first front surface (FR1) and a second front surface (FR2) face each other. A first circuit layer (120), a first front surface insulating layer (131), and a first front surface pad (132) can be disposed on the first front surface (FR1) of the first semiconductor chip (100), and a second circuit layer (220), a second front surface insulating layer (231), and a second front surface pad (232) can be disposed on the second front surface (FR2) of the second semiconductor chip (200). The first circuit layer (120) may include a first wiring structure (125) electrically connected to individual elements (115) through an interconnection portion (113) and a first interlayer insulating layer (121) surrounding the first wiring structure (125). Since the first circuit layer (120) has substantially the same features as the second circuit layer (220) described above, a redundant description is omitted.

[0093] In this modified example, the first front insulating layer (131) may have a first recess (131R) that provides a gap (AG) together with a second recess (231R). The first recess (131R) may be spaced apart from the first front pad (132) by a predetermined distance, and a first bonding surface (BS1) may be formed between the first recess (131R) and the first front pad (132). Here, the first insulating layer (151) (or the first upper insulating layer) and the first upper pad (152) are disposed on opposite sides of the first front insulating layer (131) and the first front pad (132), and it can be understood that the first insulating layer (151) does not include a recess. In addition, the second front insulating layer (231) and the second front pad (232) can be understood as being identical to the second lower insulating layer (231) and the second lower pad (232) described above. That is, this modified example may have the same or similar features as described with reference to FIGS. 1a to 6, except that the first semiconductor chip (100) of FIG. 1a is inverted vertically and bonded to the second semiconductor chip (200).

[0095] FIG. 8 is a cross-sectional view illustrating a semiconductor package (10A) according to one embodiment of the present invention.

[0097] Referring to FIG. 8, the semiconductor package (10A) of one embodiment has the same or similar features as described with reference to FIG. 1a to 7, except that it includes a plurality of second semiconductor chips (200A, 200B, 200C, 200D) and a molding member (90) stacked vertically (Z-axis direction) on the first semiconductor chip (100). Therefore, redundant descriptions are omitted.

[0098] A bonding interface may be formed between a plurality of second semiconductor chips (200A, 200B, 200C, 200D) in which a second rear insulating layer (251) and a second front insulating layer (231), and a second rear pad (252) and a second front pad (232) are bonded. The plurality of second semiconductor chips (200A, 200B, 200C, 200D) may be electrically connected to each other by an upper bonding pad structure (BPb) in which the second rear pad (252) and the second front pad (232) are bonded and combined. Among the plurality of second semiconductor chips (200A, 200B, 200C, 200D), the lowest second semiconductor chip (200A) can be electrically connected to the first semiconductor chip (100) by a lower bonding pad structure (BPa) in which the second front pad (232) is bonded and coupled with the first rear pad (152) of the first semiconductor chip (100). Additionally, voids (AG) surrounding the lower bonding pad structure (BPa) and the upper bonding pad structure (BPb) may be formed. The voids (AG) may be formed at a predetermined distance from the lower bonding pad structure (BPa) or the upper bonding pad structure (BPb).

[0099] A plurality of second semiconductor chips (200A, 200B, 200C, 200D) may have the same or similar structure as the second semiconductor chip (200) described with reference to FIGS. 1a through 7, except that they further include a second through electrode (240) for forming an mutual electrical connection path. However, the second semiconductor chip (200D) placed at the top may not have the second through electrode (240) and may have a relatively large thickness. According to the embodiment, more or fewer semiconductor chips than shown in the drawings may be stacked on the first semiconductor chip (100). For example, three or fewer or five or more semiconductor chips may be stacked on the first semiconductor chip (100).

[0100] For example, the first semiconductor chip (100) may be a buffer chip or a control chip comprising a plurality of logic elements and / or memory elements. The first semiconductor chip (100) may transmit signals from a plurality of second semiconductor chips (200A, 200B, 200C, 200D) stacked on top thereof to the outside, and may also transmit signals and power from the outside to the plurality of second semiconductor chips (200A, 200B, 200C, 200D). The plurality of second semiconductor chips (200A, 200B, 200C, 200D) may be memory chips comprising volatile memory elements such as DRAM or SRAM, or non-volatile memory elements such as PRAM, MRAM, FeRAM, or RRAM. In this case, the semiconductor package (10A) of the present embodiment may be used for High Bandwidth Memory (HBM) products or Electro Data Processing (EDP) products, etc.

[0101] The molding member (160) is disposed on the first semiconductor chip (100) and can seal at least a portion of each of the plurality of second semiconductor chips (200A, 200B, 200C, 200D). The molding member (160) may be formed to expose the upper surface of the second semiconductor chip (200D) disposed at the top. However, according to an embodiment, the molding member (160) may be formed to cover the upper surface of the second semiconductor chip (200D) at the top. The molding member (160) may include, for example, EMC (Epoxy Mold Compound), but the material of the molding member (160) is not particularly limited.

[0103] FIG. 9a is a plan view illustrating a semiconductor package (10B) according to one embodiment of the present invention, and FIG. 9b is a cross-sectional view illustrating a cross-section along the line II-II' of FIG. 9a.

[0105] Referring to FIGS. 9a and 9b, a semiconductor package (10B) of one embodiment may include a package substrate (600), an interposer substrate (700), and at least one package structure (PS). Additionally, the semiconductor package (10B) may further include a logic chip (or processor chip) (800) disposed adjacent to the package structure (PS) on the interposer substrate (700). The package structure (PS) is illustrated in the form of the semiconductor package (10A) shown in FIG. 8, but is not limited thereto, and may have the same or similar features as the semiconductor packages (10, 10a, 10b, 10c, 10d, 10e, 10f) described with reference to FIGS. 1a through 7.

[0107] The package substrate (600) is a support substrate on which an interposer substrate (700), a logic chip (800), and a package structure (PS) are mounted, and may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, etc. The package substrate (600) may include a lower pad (612) disposed on the lower surface of the body, an upper pad (611) disposed on the upper surface of the body, and a wiring circuit (613) that electrically connects the lower pad (612) and the upper pad (611). The body of the package substrate (600) may include different materials depending on the type of substrate. For example, if the package substrate (600) is a printed circuit board, it may be in the form of a body copper foil laminate or a form in which a wiring layer is additionally laminated on one or both sides of the copper foil laminate. The lower pad and the upper pads (612, 611) and the wiring circuit (613) may form an electrical path connecting the lower surface and the upper surface of the package substrate (600). An external connection bump (620) connected to a lower pad (612) may be disposed on the lower surface of the package substrate (600). The external connection bump (620) may include, for example, a solder ball.

[0109] The interposer substrate (700) may include a substrate (701), a lower protective layer (703), a lower pad (705), an interconnect structure (710), a conductive bump (720), and a through-via (730). A package structure (PS) and a processor chip (800) may be laminated on a package substrate (600) via the interposer substrate (700). The interposer substrate (700) may electrically connect the package structure (PS) and the processor chip (800) to each other.

[0110] The substrate (701) may be formed from, for example, any one of silicon, organic, plastic, and glass substrates. If the substrate (701) is a silicon substrate, the interposer substrate (700) may be referred to as a silicon interposer. If the substrate (701) is an organic substrate, as shown in the drawing, the interposer substrate (700) may be referred to as a panel interposer.

[0111] A lower protective layer (703) is disposed on the lower surface of the substrate (701), and a lower pad (705) can be disposed on the lower protective layer (703). The lower pad (705) can be connected to a through-via (730). A package structure (PS) and a processor chip (800) can be electrically connected to a package substrate (600) through conductive bumps (720) disposed on the lower pad (705).

[0112] An interconnect structure (710) is disposed on the upper surface of a substrate (701) and may include an interlayer insulating layer (711) and a single-layer or multi-layer wiring structure (712). If the interconnect structure (710) is composed of a multi-layer wiring structure, wiring patterns of different layers may be connected to each other through contact vias. An upper pad (704) connected to the wiring structure (712) may be disposed on the interconnect structure (710). A package structure (PS) and a processor chip (800) may be connected to the upper pad (704) through a connection bump (139).

[0113] The through-via (730) may extend from the upper surface of the substrate (701) to the lower surface and penetrate the substrate (701). For example, the through-via (730) may extend into the interior of the interconnect structure (710) and be electrically connected to the wiring of the interconnect structure (710). If the substrate (701) is silicon, the through-via (730) may be referred to as a TSV. According to an embodiment, the interposer substrate (700) may contain only the interconnect structure and may not contain the through-via.

[0114] The interposer substrate (700) may be used for the purpose of converting or transmitting input electrical signals between the package substrate (600) and the package structure (PS) or processor chip (800). Accordingly, the interposer substrate (700) may not include components such as active or passive components. According to an embodiment, the interconnect structure (710) may be placed on the lower part of the substrate (701).

[0115] The conductive bump (720) is placed on the lower surface of the interposer substrate (700) and can be electrically connected to the wiring of the interconnection structure (710). The interposer substrate (700) can be mounted on the package substrate (600) through the conductive bump (720). For example, some of the lower pads (705) used for power or ground are integrated and connected together to the conductive bump (720), so that the number of lower pads (705) may be greater than the number of conductive bumps (720).

[0117] The logic chip or processor chip (800) may include, for example, a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc. Depending on the type of integrated circuits included inside the chip (800), the semiconductor package (10B) may be referred to as a server-oriented semiconductor package or a mobile-oriented semiconductor package, etc. According to the embodiment, the logic chip (800) and / or package structure (PS) mounted on the interposer substrate (700) may be provided in a number greater or less than that shown in the drawing.

[0119] FIG. 10a is a plan view illustrating a semiconductor package (10C) according to one embodiment of the present invention, and FIG. 10b is a cross-sectional view illustrating a cross-section along the line III-III' of FIG. 10a.

[0121] Referring to FIGS. 10a and 10b, a semiconductor package (10C) of one embodiment may include a plurality of second semiconductor chips (200a, 200b, 200c) horizontally arranged on a first semiconductor chip (100). In this embodiment, the plurality of second semiconductor chips (200a, 200b, 200c) (hereinafter referred to as 'chiplets') may include chiplets constituting a Multi-Chip Module (MCM). For example, first to third chiplets (200a, 200b, 200c) may be mounted on the first semiconductor chip (100). According to the embodiment, the first to third chiplets (200a, 200b, 200c) may be electrically connected to each other through a wiring circuit (125) of the first semiconductor chip (100). Between the first semiconductor chip (100) and the first to third chiplets (200a, 200b, 200c), a bonding pad structure (BP) and voids (AG) described with reference to FIGS. 1a through 7 may be formed. The voids (AG) are spaced apart from the bonding pad structure (BP) by a predetermined distance, thereby improving the bonding quality of the first upper pads (152) and the second lower pads (232).

[0123] The first semiconductor chip (100) may include an active interposer that performs the function of an I / O chip. For example, the first semiconductor chip (100) may include an I / O element, a DC / DC converter, a sensor, a test circuit, etc., internally. Since the first semiconductor chip (100) may include elements similar to the interposer substrate (700) shown in FIG. 9b, a redundant description is omitted. In the drawings, the first semiconductor chip (100) is shown in the form of a silicon interposer substrate, but the substrate applicable to this embodiment is not limited thereto. The first semiconductor chip (100) may be mounted on a package substrate (600).

[0125] A plurality of chiplets (200a, 200b, 200c) may include a CPU, GPU, FPGA, etc. The plurality of chiplets (200a, 200b, 200c) may be composed of different chips. For example, the first chiplet (200a) may be a GPU chip, the second chiplet (200b) may be a CPU chip, and the third chiplet (200c) may be an FPGA chip. However, depending on the embodiment, the plurality of chiplets (200a, 200b, 200c) may be composed of chips of the same type. For example, the first to third chiplets (200a, 200b, 200c) may all include GPU chips. The number of chiplets disposed on the first semiconductor chip (100) is not specifically limited, and for example, two or fewer or four or more chiplets may be mounted on the first semiconductor chip (100). Here, chiplets or chiplet technology may refer to semiconductor chips manufactured by distinguishing according to the size and function of the device or manufacturing technology of such semiconductor chips.

[0127] FIGS. 11a to 11h are cross-sectional views illustrating a manufacturing process for forming a recess on the back surface of a semiconductor chip. FIGS. 11a to 11h illustrate a part of the manufacturing process of the first semiconductor chip (100) illustrated in FIG. 1a in the order of process steps.

[0129] Referring to FIG. 11a, a first semiconductor wafer (WF1) can be prepared comprising a first pre-substrate (110p) and a plurality of through electrodes (140) arranged within the first pre-substrate (110p).

[0130] A first semiconductor wafer (WF1) may be temporarily supported on a first carrier substrate (C1) by a bonding material layer (RL), such as glue. The first semiconductor wafer (WF1) may include components for a plurality of semiconductor chips (or 'first semiconductor chips'). Specifically, it may include a first circuit layer (120) formed on an active surface of a first pre-substrate (110p), and a plurality of through electrodes (140) connected to a wiring structure of the first circuit layer (120). The plurality of through electrodes (140) may be formed before or during the formation of the first circuit layer (120), but may be formed so as not to completely penetrate the first pre-substrate (110p). Additionally, a connection bump (136) embedded in the bonding material layer (RL) may be disposed on the lower part of the first semiconductor wafer (WF1).

[0132] Referring to FIG. 11b, a first substrate (110) can be formed by removing a portion of the first pre-substrate (110p) to form a first substrate (110) having a rear surface (110BS) with a plurality of through electrodes (140) protruding therefrom.

[0133] A first substrate (110) having a desired thickness can be formed by applying a polishing process to the upper surface (inactive surface) of the first pre-substrate (110p). The polishing process can be performed by a grinding process such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof. For example, the first pre-substrate (110p) can be reduced to a certain thickness by performing a grinding process, and the through electrodes (140) can be sufficiently exposed by applying an etch-back under appropriate conditions.

[0135] Referring to FIG. 11c, a preliminary protective layer (113p) and a preliminary buffer film (114p) can be formed to cover the top (140T) of a plurality of through electrodes (140) protruding onto the back surface (110BS) of the first substrate (110). The preliminary protective layer (113p) may be silicon oxide, and the preliminary buffer film (114p) may be silicon nitride or silicon oxynitride. The preliminary protective layer (113p) and the preliminary buffer film (114p) may be formed using a PVD process or a CVD process. Subsequently, the preliminary protective layer (113p) and the preliminary buffer film (114p) may be flattened (e.g., ground) so that the through electrodes (140) are exposed. By the flattening process, the preliminary protective layer (113p) and the preliminary buffer film (114p) may be removed up to a predetermined line (GL). In addition, a portion of the top (140T) of the penetrating electrodes (140) can also be removed.

[0137] Referring to FIG. 11d, the first semiconductor wafer (WF1) may have a flat surface (FS) in which a protective layer (113), a buffer film (114), and a plurality of through electrodes (140) are exposed. As described above, since the top (140T) of the through electrodes (140) is partially removed by the flat surface (FS), a portion of the via plug (145) may be exposed through the flat surface (FS).

[0139] Referring to FIG. 11e, a back insulating layer (151) including a first etching groove (ER1) can be formed on a flat surface ('FS' in FIG. 12d) of a first semiconductor wafer (WF1).

[0140] The first etching groove (ER1) can be formed by etching at least a portion of the pre-insulating layer formed on the protective layer (113) and the buffer film (114). The pre-insulating layer may comprise, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN) and may be formed using a PVD or CVD process. The first etching groove (ER1) may be formed using an etching process such as reactive-ion etching (RIE) using a photoresist (not shown), for example.

[0142] Referring to FIG. 11f, a first preliminary barrier layer (153p) and a first preliminary conductive layer (155p) can be formed on the surface of the rear insulating layer (151) and inside the first etching groove (ER1).

[0143] The first pre-barrier layer (153p) can be conformally formed along the surface of the back insulating layer (151). The first pre-conductive layer (155p) is formed on the first pre-barrier layer (153p) and can fill the interior of the first etching groove (ER1). The first pre-barrier layer (153p) and the first pre-conductive layer (155p) can be formed using a plating process, a PVD process, or a CVD process. For example, the first pre-barrier layer (153p) may include titanium (Ti) or titanium nitride (TiN), and the first pre-conductive layer (155p) may include copper (Cu). A seed layer (not shown) containing the same material as the first pre-conductive layer (155p) may be formed between the first pre-barrier layer (153p) and the first pre-conductive layer (155p).

[0145] Referring to FIG. 11g, a rear pad (152) including a first barrier layer (153) and a first conductive layer (155) can be formed by polishing the first preliminary barrier layer (153p) and the first preliminary conductive layer (155p).

[0146] A portion of the first pre-barrier layer (153p) and the first pre-conductive layer (155p) may be removed by a polishing process, and a back pad (152) comprising the first barrier layer (153) and the first conductive layer (155) may be formed. The polishing process may be performed, for example, using a CMP process with a first slurry. The first slurry may have a polishing selectivity ratio for the first pre-barrier layer (153p), the first pre-conductive layer (155p), and the back insulating layer (151). For example, a third recess (152R) may be formed on the upper surface of the back pad (152), which is recessed compared to the upper surface (151S) of the back insulating layer (151) flattened by the polishing process. The third recess (152R) may provide an expansion space for the first conductive layer (155) during the subsequent bonding process of the back pad (152).

[0148] Referring to FIG. 11h, the rear insulating layer (151) can be polished to form a first recess (151R) spaced apart from the rear pad (152) by a predetermined distance.

[0149] The polishing process can be performed, for example, using a CMP process with a second slurry. The second slurry may have a polishing selectivity ratio for the first barrier layer (153), the first conductive layer (155), and the back insulating layer (151). For example, the polishing rate of the back insulating layer (151) with respect to the second slurry may be greater than the polishing rate of the first barrier layer (153) and the first conductive layer (155). Accordingly, a first recess (151R) recessed toward the bottom of the back insulating layer (151) may be formed on the upper surface (151S) of the back insulating layer (151).

[0151] FIGS. 12a to 12d are cross-sectional views illustrating a manufacturing process for forming a recess on the front surface of a semiconductor chip. FIGS. 12a to 12d illustrate a part of the manufacturing process of the second semiconductor chip (200) illustrated in FIG. 1a in the order of process steps.

[0153] Referring to FIG. 12a, a front insulating layer (231) including a second etching groove (ER2) can be formed on a second semiconductor wafer (WF2).

[0154] The second semiconductor wafer (WF2) may include a second pre-substrate (210p), a second circuit layer (220) disposed on the front surface of the second pre-substrate (210p), and a front insulating layer (231) disposed on the second circuit layer (220). The second semiconductor wafer (WF2) may be supported and temporarily bonded to a second carrier substrate (C2). The second etching groove (ER2) may be formed by etching at least a portion of the pre-insulating layer formed on the second circuit layer (220). The pre-insulating layer may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN) and may be formed using a PVD or CVD process. The second etching groove (ER2) may be formed using an etching process such as reactive-ion etching (RIE) using a photoresist (not shown), for example.

[0156] Referring to FIG. 12b, a second preliminary barrier layer (233p) and a second preliminary conductive layer (235p) can be formed on the surface of the front insulating layer (231) and inside the second etching groove (ER2).

[0157] The second pre-barrier layer (233p) can be conformally formed along the surface of the front insulating layer (231). The second pre-conductive layer (235p) is formed on the second pre-barrier layer (233p) and can fill the interior of the second etching groove (ER2). The second pre-barrier layer (233p) and the second pre-conductive layer (235p) can be formed using a plating process, a PVD process, or a CVD process. For example, the second pre-barrier layer (233p) may include titanium (Ti) or titanium nitride (TiN), and the second pre-conductive layer (235p) may include copper (Cu). A seed layer (not shown) containing the same material as the second pre-conductive layer (235p) may be formed between the second pre-barrier layer (233p) and the second pre-conductive layer (235p).

[0159] Referring to FIG. 12c, a front pad (232) including a second barrier layer (233) and a second conductive layer (235) can be formed by polishing the second preliminary barrier layer (233p) and the second preliminary conductive layer (235p).

[0160] A portion of the second preliminary conductive layer (235p) and the second preliminary barrier layer (233p) may be removed by a polishing process, and a front pad (232) comprising the second conductive layer (235) and the second barrier layer (233) may be formed. The polishing process may be performed, for example, using a CMP process with a first slurry. The first slurry may have a polishing selectivity ratio for the second preliminary barrier layer (233p), the second preliminary conductive layer (235p), and the front insulating layer (231). For example, the polishing rate of the front insulating layer (231) with respect to the first slurry may be lower than the polishing rate of the second preliminary barrier layer (233p) and the second preliminary conductive layer (235p). For example, a fourth recess (232R) may be formed on the upper surface of the front pad (232) that is recessed compared to the upper surface (231S) of the front insulating layer (231) that has been flattened by a polishing process. The fourth recess (232R) may provide an expanded space for the second conductive layer (235) during the subsequent bonding process of the front pad (232).

[0162] Referring to FIG. 12d, the front insulating layer (231) can be polished to form a second recess (231R) spaced apart from the front pad (232) by a predetermined distance.

[0163] The polishing process can be performed, for example, using a CMP process with a second slurry. The second slurry may have a polishing selectivity ratio for the second barrier layer (233), the second conductive layer (235), and the front insulating layer (231). For example, the polishing rate of the front insulating layer (231) with respect to the second slurry may be greater than the polishing rate of the second barrier layer (233) and the second conductive layer (235). For example, a second recess (231R) recessed toward the bottom of the front insulating layer (231) may be formed on the upper surface (231S) of the front insulating layer (231). Subsequently, the back surface of the second pre-substrate (210p) may be ground to form a plurality of semiconductor chips (200) (or 'second semiconductor chips') having a desired thickness.

[0165] FIG. 13 is a cross-sectional view illustrating the manufacturing process of the semiconductor package (10) of FIG. 1a.

[0167] Referring to FIG. 13, first, a semiconductor wafer (WF) provided for the first semiconductor chips (100) can be prepared. The semiconductor wafer (WF) can be formed through the manufacturing process of FIG. 11a to 11h. The semiconductor wafer (WF) may include a plurality of back pads (152) and a back insulating layer (151) surrounding the plurality of back pads (152). The back insulating layer (151) may include first recesses (151R) spaced apart from the plurality of back pads (152). The semiconductor wafer (WF) may be supported on a temporary carrier (CW) by a bonding material layer (RL).

[0168] Next, a plurality of second semiconductor chips (200) may be prepared. The plurality of second semiconductor chips (200) may be formed through the manufacturing process of FIGS. 12a to 12d. The plurality of second semiconductor chips (200) may include a plurality of front pads (232) and a front insulating layer (231) surrounding the plurality of front pads (232). The front insulating layer (231) may include second recesses (231R) spaced apart from the plurality of front pads (232). The semiconductor wafer (WF) and the plurality of second semiconductor chips (200) are not provided sequentially, but may each be formed through an independent manufacturing process.

[0169] Next, a plurality of second semiconductor chips (200) can be placed on a semiconductor wafer (WF). The plurality of second semiconductor chips (200) can be placed on the first semiconductor chips (100) of the semiconductor wafer (WF), for example, using a pick-and-place device. The plurality of second semiconductor chips (200) can be aligned with the first semiconductor chips (100) such that a gap (AG) is formed between the first recess (151R) and the second recess (231R). Accordingly, a plurality of rear pads (232) can be in contact with a plurality of front pads (152), and a rear insulating layer (151) can be in contact with the front insulating layer (231) in the remaining portion excluding the gap (AG).

[0170] Next, a thermal compression process can be performed to combine the rear insulating layer (151) and the front insulating layer (231) that are bonded together, and to combine the plurality of rear pads (152) and the plurality of front pads (232) that are bonded together. The thermal compression process can be performed so that the rear insulating layer (151) and the front insulating layer (231) are first bonded, and then the plurality of rear pads (152) and the plurality of front pads (232) are bonded. For example, the thermal compression process can be performed so that the rear insulating layer (151) and the front insulating layer (231) are bonded in a thermal atmosphere in the range of about 100°C to about 200°C, and the plurality of rear pads (152) and the plurality of front pads (232) are bonded in a thermal atmosphere in the range of about 200°C to about 300°C. However, the temperature of the thermal atmosphere is not limited to the range described above (about 100°C to about 300°C) and can vary. During the thermal compression process, the third recess (152R) of the plurality of rear pads (152) and the fourth recess (232R) of the plurality of front pads (232) may expand to form a third bonding surface (BS3) between the plurality of rear pads (152) and the plurality of front pads (232). According to the present invention, since the first bonding surface (BS1) is formed before the third bonding surface (BS3) is formed, the bonding area or expansion area of ​​the rear pad (152) and the front pad (232) may be limited by the rear insulating layer (151) and the front insulating layer (231). Therefore, the quality of the bonding interface (third bonding surface (BS3)) of the rear pad (152) and the front pad (232) can be improved, and the reliability of the bonding pad structure (BP) can be ensured.

[0172] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

Claims

Claim 1 A first semiconductor chip comprising a first substrate, a first pad disposed on the first substrate, and a first insulating layer surrounding the first pad on the first substrate; A semiconductor package comprising a second semiconductor chip disposed on the first semiconductor chip, the second substrate, a second pad disposed below the second substrate and in contact with the first pad, and a second insulating layer that surrounds the second pad below the second substrate and in contact with the first insulating layer, wherein the first insulating layer has a first recess spaced apart from the first pad in a first direction, and the second insulating layer has a second recess spaced apart from the second pad in the first direction and overlaps with at least a portion of the first recess in a second direction perpendicular to the first direction to provide an air gap together with the first recess, a first bonding surface in which the first insulating layer and the second insulating layer contact at one side of the air gap adjacent to the first pad and the second pad, and a second bonding surface in which the first insulating layer and the second insulating layer contact at the other side of the air gap opposite to the one side. Claim 2 A semiconductor package according to claim 1, wherein the first recess and the first pad are spaced apart by a first distance, the second recess and the second pad are spaced apart by a second distance, and the first bonding surface has a length in the first direction that is equal to or smaller than the first and second distances. Claim 3 A semiconductor package according to claim 2, wherein the first and second distances are in the range of 0.1 nm to 500 nm. Claim 4 In claim 1, the first and second recesses each surround the first pad and the second pad on a plane, respectively, in a semiconductor package. Claim 5 In claim 4, the first and second recesses each surround the entirety of the first pad and the second pad, respectively, in a semiconductor package. Claim 6 A semiconductor package according to claim 1, wherein the first recess includes a curved surface recessed from a first upper surface of the first insulating layer facing the second semiconductor chip toward a first lower surface opposite to the first upper surface, and the second recess includes a curved surface recessed from a second lower surface of the second insulating layer facing the first semiconductor chip toward a second upper surface opposite to the second lower surface. Claim 7 A semiconductor package according to claim 1, wherein the first recess includes a first flat surface recessed from a first upper surface of the first insulating layer facing the second semiconductor chip toward a first lower surface opposite to the first upper surface, and the second recess includes a second flat surface recessed from a second lower surface of the second insulating layer facing the first semiconductor chip toward a second upper surface opposite to the second lower surface. Claim 8 A semiconductor package according to claim 1, wherein the second insulating layer comprises a lower insulating film in direct contact with the first insulating layer and an upper insulating film disposed on the lower insulating film, and the lower insulating film comprises an insulating material different from that of the first insulating layer. Claim 9 A semiconductor package according to claim 8, wherein the first insulating layer comprises silicon oxide (SiO), and the lower insulating film of the second insulating layer comprises silicon carbonitride (SiCN). Claim 10 In claim 8, the second recess is a semiconductor package having a depth equal to or smaller than the thickness of the lower insulating film. Claim 11 A semiconductor package according to claim 1, wherein the first pad comprises a first conductive layer and a first barrier layer surrounding the side of the first conductive layer, and the second pad comprises a second conductive layer in contact with at least a portion of the first conductive layer and a second barrier layer surrounding the side of the second conductive layer. Claim 12 A semiconductor package according to claim 11, wherein the first conductive layer has a first groove that exposes at least a portion of the first barrier layer, and the second conductive layer has a second groove that exposes at least a portion of the second barrier layer. Claim 13 A semiconductor package according to claim 1, wherein the first semiconductor chip further comprises a first circuit layer disposed below the first substrate, a lower pad disposed below the first circuit layer, and a first through electrode that penetrates the first substrate and electrically connects the first pad and the lower pad. Claim 14 A first semiconductor chip comprising a first substrate, a plurality of first pads disposed on the first substrate, and a first insulating layer surrounding the plurality of first pads on the first substrate; A semiconductor package comprising a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip comprising a second substrate, a plurality of second pads disposed below the second substrate, and a second insulating layer surrounding the plurality of second pads below the second substrate, wherein the first and second semiconductor chips are electrically connected by at least one pair of first and second bonding pad structures in which the plurality of first pads and the plurality of second pads come into contact, and having a first gap surrounding the first bonding pad structure and a second gap surrounding the second bonding pad structure, and having first bonding surfaces in which at least a portion of the first insulating layer and the second insulating layer come into contact between the first bonding pad structure and the first gap and between the second bonding pad structure and the second gap, and a second bonding surface in which at least a portion of the first insulating layer and the second insulating layer come into contact between the first gap and the second gap. Claim 15 In claim 14, the first bonding surfaces have a length smaller than the width of each of the first and second gaps in a semiconductor package. Claim 16 A semiconductor package according to claim 15, wherein the width of each of the first and second gaps is in the range of 5% to 25% of the gap between the first bonding pad structure and the second bonding pad structure. Claim 17 In claim 14, the second bonding surface is a semiconductor package having a length equal to or greater than the sum of the widths of each of the first and second gaps. Claim 18 A semiconductor package comprising: a first substrate, a first pad disposed on the first substrate, and a first insulating layer having a first recess surrounding the first pad; and a second semiconductor chip disposed on the first semiconductor chip, comprising a second substrate, a second pad disposed below the second substrate and in contact with the first pad, and a second insulating layer having a second recess surrounding the second pad and in contact with the first insulating layer, wherein the entire sides of each of the first pad and the second pad are covered by the first and second insulating layers, the first recess is spaced apart from the entire side of the first pad in a first direction and a second direction opposite to each other, and the second recess is spaced apart from the entire side of the second pad in the first direction and the second direction. Claim 19 A semiconductor package according to claim 18, wherein a first portion of the first insulating layer is located between the entire side of the first pad and the first recess, and a second portion of the second insulating layer is located between the entire side of the second pad and the second recess. Claim 20 In claim 19, the first portion of the first insulating layer is in contact with the second portion of the second insulating layer in a semiconductor package.

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