Semiconductor device and method of fabricating the same

Abstract

One embodiment of the present invention comprises: a first active pin extending in a first direction and having a plurality of first pin-shaped patterns aligned with a first separation region; a second active pin extending in the first direction and having a plurality of second pin-shaped patterns aligned with a second separation region, wherein the first and second separation regions are arranged so as not to overlap in a second direction intersecting the first direction, and the first trench region between the first and second active pins has a first depth; a third active pin extending in the first direction and positioned adjacent to the first active pin, wherein the second trench region between the first and third active pins has a second depth greater than the first depth; a fourth active pin extending in the first direction and positioned adjacent to the second active pin, wherein the third trench region between the second and fourth active pins has a third depth greater than the first depth; A semiconductor device comprising: at least one first gate line extending in the second direction and arranged to intersect the first and second active pins and the third active pin; and at least one second gate line extending in the second direction and arranged to intersect the first and second active pins and the fourth active pin; wherein the plurality of first pin-shaped patterns and the plurality of second pin-shaped patterns are merged by the first trench region, and the second and third trench regions are each connected to the first and second separation regions, and the bottoms of the first and second separation regions each have a level substantially the same as the bottom level of the second and third trench regions.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing. Background Technology

[0002] As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a fin-shaped silicon body is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale, and current control capability can be improved without increasing the gate length of the multi-gate transistor.

[0004] As the spacing between pins is narrowed to reduce cell area, an etching process using multiple masks is required for the pin cutting process, which has led to process complexity and problems in reducing cell area. The problem to be solved

[0005] One of the technical problems that the present invention aims to solve is to provide a highly integrated semiconductor device.

[0006] One of the technical problems that the present invention aims to solve is to provide a method for manufacturing a highly integrated semiconductor device. means of solving the problem

[0007] One embodiment of the present invention comprises: a first active pin extending in a first direction and having a plurality of first pin-shaped patterns aligned with a first separation region; a second active pin extending in the first direction and having a plurality of second pin-shaped patterns aligned with a second separation region, wherein the first and second separation regions are arranged so as not to overlap in a second direction intersecting the first direction, and the first trench region between the first and second active pins has a first depth; a third active pin extending in the first direction and positioned adjacent to the first active pin, wherein the second trench region between the first and third active pins has a second depth greater than the first depth; a fourth active pin extending in the first direction and positioned adjacent to the second active pin, wherein the third trench region between the second and fourth active pins has a third depth greater than the first depth; A semiconductor device comprising: at least one first gate line extending in the second direction and arranged to intersect the first and second active pins and the third active pin; and at least one second gate line extending in the second direction and arranged to intersect the first and second active pins and the fourth active pin; wherein the plurality of first pin-shaped patterns and the plurality of second pin-shaped patterns are merged by the first trench region, and the second and third trench regions are each connected to the first and second separation regions, and the bottoms of the first and second separation regions each have a level substantially the same as the bottom level of the second and third trench regions.

[0009] One embodiment of the present invention comprises: a first active pin extending in a first direction and having first and second pin-shaped patterns separated by a separation region; a second active pin extending in the first direction and having a central region that overlaps with the separation region in a second direction intersecting the first direction and first and second end regions that overlap with the first and second pin-shaped patterns, respectively, in the second direction - a first trench region defining the opposing sides of the first and second active pins has a first depth -; a third active pin extending in the first direction and having one side facing the other side of the first active pin - a second trench region defining the other side of the first active pin and one side of the third active pin has a second depth greater than the first depth -; and a first gate line extending in the second direction and arranged to intersect the first pin-shaped pattern of the first active pin and the first part of the second active pin. The semiconductor device comprises: a second gate line extending in the second direction and arranged to intersect a second pin-shaped pattern of the first active pin and a second portion of the second active pin; wherein the first and second pin-shaped patterns of the first active pin are combined with the second active pin by the first trench region, the second trench region is connected to the separation region, and the bottom of the separation region has a level substantially the same as the level of the bottom of the second trench region.

[0011] One embodiment of the present invention comprises: a first active pin extending in a first direction and having a plurality of first pin-shaped patterns separated from one another by a first separation region; a second active pin extending in the first direction and having a plurality of second pin-shaped patterns separated from one another by a second separation region - wherein the first and second separation regions are each arranged to overlap with the central region of each of the plurality of second and first pin-shaped patterns in a second direction intersecting the first direction, and the plurality of first and second pin-shaped patterns are each arranged to overlap with two adjacent pin-shaped patterns among the plurality of second and first pin-shaped patterns in the second direction -; a third active pin extending in the first direction and positioned adjacent to the first active pin; a fourth active pin extending in the first direction and positioned adjacent to the second active pin; a first trench region positioned between the first and second active pins and having a first depth smaller than the depth of the separation region; and a second trench region positioned between the first and third active pins and having a second depth larger than the first depth. A semiconductor device is provided comprising: a third trench region disposed between the second and fourth active pins and having a third depth greater than the first depth; first gate lines extending in the second direction and disposed to intersect the third active pin and the overlapping portions of the plurality of first and second pin-shaped patterns; and second gate lines extending in the second direction and disposed to intersect the fourth active pin and the overlapping portions of the plurality of first and second pin-shaped patterns.

[0013] One embodiment of the present invention provides a method for manufacturing a semiconductor device comprising: forming a plurality of line patterns each extended parallel to a first direction on a semiconductor substrate, wherein the plurality of line patterns include adjacent first and second line patterns and a third line pattern located on one side of the first line pattern; forming a hard mask covering the plurality of line patterns on the semiconductor substrate; performing a lithography process using a photomask on the hard mask to form a photoresist pattern; forming a mask pattern from the hard mask using the photoresist pattern, wherein the mask pattern has a first portion covering the first and second line patterns, a second portion covering the third line pattern, a first opening located between the first portion and the second portion, and a second opening extending from the first opening to open a portion of the first line pattern to separate the first line pattern; and etching the semiconductor substrate using the mask pattern to form a plurality of active pins extended in the first direction. Effects of the invention

[0015] According to the present embodiment, a cell with a complex structure (e.g., ultra-high density SRAM) can be implemented through a simple process (e.g., a single EUV process) by using an active pin formation process with a mask having a notch region. In particular, by designing the mask using the H-CR (Hexagonal-Corner Rounding) OPC (Optical proximity Correction) method, distortion is minimized and a vertical component is introduced into the internal line of the notch, thereby resolving the problem of gate line alignment errors despite the inevitable errors of the EUV process.

[0017] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0019] FIG. 1 is a layout diagram of a semiconductor device according to one embodiment of the present invention. FIGS. 2a and FIGS. 2b are cross-sectional views of the semiconductor device shown in FIG. 1, taken by cutting along I1-I1' and I2-I2', respectively. FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 1, taken by cutting along II-II'. Figures 4a and 4b are layout diagrams of an SRAM cell of a semiconductor device shown in Figure 1, respectively. Figure 5 is a circuit diagram of the SRAM cell shown in Figure 4b. FIG. 6 is a cross-sectional view of the SRAM cell shown in FIG. 2a, cut along A-A', BB', and C-C'. Figure 7 is a cross-sectional view of the SRAM cell shown in Figure 2a, cut along D-D'. FIGS. 8 and FIGS. 9 are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIGS. 10a to 17a are plan views of major processes for explaining a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 10b to 12b are cross-sectional views obtained by cutting the planes of FIGS. 10a to 12a along I-I', respectively. FIGS. 13b to 17b are cross-sectional views obtained by cutting the planes of FIGS. 13a to 17a along I1-I1', respectively, and FIGS. 13c to 17c are cross-sectional views obtained by cutting the planes of FIGS. 13a to 17a along I2-I2', respectively. FIG. 18 is a plan view showing the photomask applied to the process of FIG. 12a and FIG. 12b. FIGS. 19a and FIGS. 19b are magnified partial views of a part ("C1") of FIG. 18 and are schematic plan views to explain the optical proximity correction process for designing a notch area. FIG. 20a is a cross-sectional view taken by cutting the plane of FIG. 15a along II-II', and FIG. 20b is a magnified view showing a part of FIG. 15a ("C2"). Specific details for implementing the invention

[0020] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0022] FIG. 1 is a layout diagram of a semiconductor device according to one embodiment of the present invention, FIG. 2a and FIG. 2b are cross-sectional views of the semiconductor device shown in FIG. 1 taken by cutting along I1-I1' and I2-I2', respectively, and FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken by cutting along II-II'.

[0024] Referring to FIGS. 1 to 3, a semiconductor device (100) according to the present embodiment includes a substrate (101), a plurality of active pins (105) protruding on the substrate (101) and extending in a first direction (e.g., D1), and a gate line (160) extending in a second direction (e.g., D2) intersecting the plurality of active pins (105).

[0025] The semiconductor device (100) may have first to fourth active pins (105A, 105B, 105C, 105D) in mirror symmetry in the left and right regions of the semiconductor device. For example, the first to fourth active pins (105A, 105B, 105C, 105D) may have a structure protruding in a third direction (e.g., D3) perpendicular to the upper surface of the substrate (101), as shown in FIG. 2a and FIG. 2b. For example, the substrate (101) may be a semiconductor substrate such as a silicon substrate or a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0026] The device isolation layer (110) may define the first to fourth active pins (105A, 105B, 105C, 105D). As illustrated in FIGS. 2a and 2b, the device isolation layer (110) may be disposed on the substrate (101) to cover the sides of the first to fourth active pins (105A, 105B, 105C, 105D) of the substrate (101). The device isolation layer (110) may comprise, for example, an oxide film, a nitride film, or a combination thereof. In some embodiments, the device isolation layer (110) may be a shallow trench isolation (STI) region defining the first to fourth active pins (105A, 105B, 105C, 105D).

[0027] The semiconductor device (100) according to the present embodiment forms the first to fourth active pins (105A, 105B, 105C, 105D) by a single mask process (e.g., EUV process), so it may not include a deep trench isolation (DTI) region deeper than the STI region. The device isolation film (110) may be formed so that the upper region of the first to fourth active pins (105A, 105B, 105C, 105D) is exposed. In some embodiments, the device isolation film (110) may have a curved upper surface having a higher level as it is adjacent to the first to fourth active pins (105A, 105B, 105C, 105D).

[0028] Referring to FIGS. 1, 2a, and 2b, the first and second active pins (105A, 105B) may be positioned adjacent to each other and extend in a first direction (e.g., D1). The adjacent first and second active pins (105A, 105B) may be positioned between the third and fourth active pins (105C, 105D). That is, the third active pin (105C) and the fourth active pin (105D) may be positioned adjacent to the first active pin (105A) and the second active pin (105B), respectively. The spacing between the first and second active pins (105A, 105B) may be smaller than the spacing between the first and third active pins (105A, 105C) and / or the spacing between the second and fourth active pins (105B, 105D). The spacing of the first and third active pins (105A, 105C) may be substantially the same as the spacing of the second and fourth active pins (105B, 105D).

[0029] Each active pin (105A, 105B, 105C, 105D) can be configured with one or more FinFETs. In this embodiment, each active pin (105A, 105B, 105C, 105D) can be configured with FinFETs that constitute an SRAM (see FIG. 4b). As such, the semiconductor device (100) illustrated in FIG. 1 may be an array of six SRAM cells in which SRAM unit cells labeled "A" are arranged in a 2×3 configuration.

[0030] In this embodiment, the substrate (101) has a first conductivity type (e.g., p-type) active region and may include a first conductivity type (e.g., n-type) well (W) that is different from the second conductivity type. The first and second active pins (105A, 105B) are of the second conductivity type (e.g., n-type) for forming a first conductivity type (e.g., p-type) transistor, and the third and fourth active pins (105C, 105D) may be of the first conductivity type (e.g., p-type) for forming a second conductivity type (e.g., n-type) transistor.

[0032] Referring to FIG. 1 and FIG. 2b, the first active pin (105A) may have a plurality (e.g., two) first pin-shaped patterns (105A1, 105A2) aligned with a first separation region (SP1) (also called the "first notch region"), and the second active pin (105B) may have a plurality (e.g., two) second pin-shaped patterns (105B1, 105B2) aligned with a second separation region (SP2) (also called the "second notch region"). The plurality of first and second pin-shaped patterns (105A1, 105A2 and 105B1, 105B2) may each be aligned on the same line.

[0033] A first trench region (T1) having a first depth (P1) is formed between the first and second active pins (105A, 105B). The first trench region (T1) may define the facing sides of the first and second active pins (105A, 105B). A second and third trench region (T2, T3) may be formed between the first and third active pins (105A, 105C) and between the second and fourth active pins (105B, 105D), respectively. The second trench region (T2) defines the facing sides of the first and third active pins (105A, 105C), and the third trench region (T3) may define the facing sides of the second and fourth active pins (105B, 105D). The second depth (P2) of the second trench area (T2) and the third depth (P3) of the third trench area (T3) may be greater than the first depth (P1).

[0034] As illustrated in FIG. 2b, the first and second active pins (105A, 105B) can be merged by a first trench region (T1). Specifically, the lower region of a plurality of first pin-shaped patterns (105A1) and the lower region of a plurality of second pin-shaped patterns (105A2) can be merged together by a first trench region (T1) of relatively low depth.

[0035] The first and second separation regions (SP1, SP2) may each be structures extending into a notch region to separate the first and second active pins (105A, 105B) from the second and third trench regions (T2, T3). The first and second separation regions (SP1, SP2) may form a depth greater than the first depth (P1) of the first trench region (T1). As illustrated in FIG. 2a, the bottom of the first separation region (SP1) may have a level (La2) substantially the same as the bottom level (La1) of the second trench region (T2). Similarly, the bottom of the second separation region (SP2) may have a level substantially the same as the bottom level of the third trench region (T3).

[0036] In this embodiment, the first trench region (T1) may have a portion (TE) that extends along the first direction (e.g., D1) into the first and second separation regions (SP1, SP2). Referring to FIGS. 2a and FIGS. 3, the extended portion (TE) may have a level (Lb) higher than the bottom level (La2) of the first and second separation regions and the bottom level (La1) of the second and third trench regions (T2, T3). The upper surface level (Lb) of the extended portion (TE) may have a level substantially equal to or slightly lower than the bottom level of the first trench region (T1).

[0038] Referring to FIG. 1, from a planar perspective, the first and second separation regions (SP1, SP2) may be arranged so as not to overlap in the second direction (e.g., D2). In this embodiment, a plurality of first pin-shaped patterns (105A1, 105A2) may each have a central region that overlaps with the second separation region (SP2) in the second direction (e.g., D2) and two end regions that overlap with two adjacent second pin-shaped patterns (105B1, 105B2) in the second direction (e.g., D2). Similarly, a plurality of second pin-shaped patterns (105B1, 105B2) may have a central region that overlaps with the first separation region (SP1) in the second direction (e.g., D2) and end regions on both sides that overlap with two adjacent first pin-shaped patterns (105A1, 105A2) in the second direction (e.g., D2). Although not limited thereto, in the present embodiment, a plurality of first and second pin-shaped active patterns (105A1, 105A2, 105B1, 105B2) may each have the same length. Additionally, the length of the portion overlapped in the second direction (e.g., D2) may be designed to be greater than the width of the first and second separation regions (SP1, SP2) in the first direction (e.g., D1).

[0040] The semiconductor device (100) according to the present embodiment may include a plurality of gate lines (GL1, GL2, GL3, GL4) that extend in the second direction (e.g., D2) and are arranged to intersect with at least one of the active pins (105).

[0041] Referring to FIG. 3, the gate lines (GL1, GL2, GL3, GL4) may include a gate dielectric layer (162), a gate electrode (165), gate spacers (164), and a gate capping layer (166).

[0042] The gate dielectric layer (162) may be disposed between the active pin (105) and the gate electrode (165) and between the channel structure (140) and the gate electrode (165), as shown in FIGS. 3 and 7. The gate dielectric layer (162) may be formed to surround the channel layers (141, 142, 143, 144) in a second direction (e.g., D2) and may extend from the upper surface of the pin-shaped active region (105) to the upper surface of the device isolation film (110) (see FIG. 7). As shown in FIG. 3, the gate dielectric layer (162) may extend between the gate electrode (165) and the gate spacers (164). For example, the gate dielectric layer (162) may comprise an oxide, a nitride, or a high-dielectric (high-k) material. The above high dielectric constant material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The above high dielectric constant material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi2). x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It may be at least one of ), and praseodymium oxide (Pr2O3).

[0043] The gate electrode (165) may comprise a conductive material and may comprise a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. In some embodiments, the gate electrode (165) may be composed of two or more layers. In some embodiments, the gate electrode (165) is positioned across adjacent transistors and may be separated by a separate separator ("GP") in FIG. 7 located between adjacent transistors.

[0044] Gate spacers (164) may be placed on both sides of the gate electrode (165). In some embodiments, the gate spacers (164) may be made of a multilayer structure. For example, the gate spacers (164) may include oxides, nitrides, and oxynitrides, and in particular may include low dielectric constant films.

[0045] The gate capping layer (166) may be placed on top of the gate electrode (165), and the bottom and sides may be surrounded by the gate electrode (165) and the gate spacer layers (164), respectively. For example, the gate capping layer (166) may include oxide, nitride, and oxynitride.

[0046] Referring to FIG. 3, as indicated by "B", one side of each of the second and third gate lines can be aligned so as to nearly coincide with the cross-section of the first and second pin-shaped patterns provided by the first separation region. This alignment can be achieved by minimizing distortion occurring during the EUV process by designing the notch region of the mask (i.e., the region corresponding to the separation region) using the OPC method and H-CR (Hexagonal-Corner Rounding) OPC (Optical Proximity Correction). (See FIG. 18, FIG. 19a and FIG. 19b)

[0048] As illustrated in FIG. 3. On both sides of the gate lines (GS), the active pins (105) are partially recessed, and source / drain regions (150) can be placed on the recessed active pins (105).

[0049] Source / drain regions (150) may be placed on recessed regions of active pins (105) on both sides of the gate lines (GL1, GL2, GL3, GL4). In this embodiment, the source / drain region (150) may form a recess in a portion of the active pin (105) and selective epitaxial growth (SEG) may be performed on the recess to have a top surface at a higher level than the top surface of the active pin (105). The source / drain regions (150) may be provided as a source region or a drain region of a FinFET. The top surface of the source / drain regions (150) may be located at the same or similar height level as the bottom surface of the gate lines (GL1, GL2, GL3, GL4) in the cross-section shown in FIG. 3. In other embodiments, the relative heights of the source / drain regions (150) and the gate lines (GL1, GL2, GL3, GL4) can be varied.

[0050] The source / drain regions (150) may be made of an epitaxial layer containing impurities, for example, the active pins (105) may contain impurities diffused from the source / drain regions (120) in the region in contact with the source / drain regions (150).

[0051] According to FIGS. 2a and 2b, the cross-sections may include first and second source / drain regions (150P, 150N) having different shapes. In this embodiment, the first source / drain region (150P) associated with the first and second active pins (105A, 105B) may include a silicon-germanium (SiGe) epitaxial. As illustrated in FIGS. 2a and 2b, the cross-section of the first source / drain region (150A) may have a somewhat angular polygon, i.e., a pentagonal shape. In some embodiments, the silicon-germanium (SiGe) epitaxial may improve electrical characteristics by generating compressive stress in the first and second active pins (105A, 105B), which are silicon (Si). In this embodiment, p-type impurities may be doped in-situ into the first source / drain region (150P) or doped by a separate ion implantation process. For example, the p-type impurities may be boron (B), indium (In), and / or gallium (Ga). Since the spacing between the first and second active pins (105A, 105B) is relatively close, the first source / drain regions (150A) grown from the first and second active pins (105A, 105B) may have a structure that is combined with each other.

[0052] Additionally, the second source / drain regions (150N) associated with the third and fourth active pins (105C, 105D) may include a silicon (Si) epitaxial layer. The cross-section of the second source / drain region (150N) may have a smooth hexagonal shape. The second source / drain regions (150N) may be doped with n-type impurities in a manner similar to the doping method of the first source / drains (150P). For example, the n-type impurities may be phosphorus (P), nitrogen (N), arsenic (As), and / or antimony (Sb).

[0054] The interlayer insulating layer (190) may be positioned to cover the source / drain regions (150) and gate lines (GL1, GL2, GL3, GL4). The interlayer insulating layer (190) may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low dielectric. Contacts (195A, 195B in FIG. 4b) may penetrate the interlayer insulating layer (190) to be connected to the first and second source / drain regions (150P, 150N) or penetrate the gate capping layer (166) to be connected to the gate electrode (165), and may apply electrical signals to the first and second source / drain regions (150P, 150N) and the gate electrode (165). The contacts (195A, 195B) may be positioned to recess source / drain regions (150P, 150N) to a predetermined depth, but are not limited thereto, the contacts (195A, 195B) may include a conductive barrier and a contact plug. For example, the contact plug may include a metallic material such as tungsten (W), aluminum (Al), copper (Cu), or a semiconductor material such as doped polysilicon.

[0056] In this way, each active pin (105A, 105B, 105C, 105D) can be combined with gate lines (GL1, GL2, GL3, GL4) and source / drain (150) to form a FinFET. As previously described, such FinFETs can be provided as transistors constituting an SRAM.

[0057] Hereinafter, with reference to FIGS. 4a, 4b, and FIG. 5, an SRAM cell of a semiconductor device according to the present embodiment will be described in detail.

[0058] FIG. 4a shows the layout of the active pin and gate line of the SRAM cell corresponding to the "A" region of the semiconductor device (100) of FIG. 1.

[0059] Referring to FIG. 4a, the first and second pin-shaped patterns (105A1, 105B2) may have overlapping portions in a second direction (e.g., D2). The first and second separation regions (SP1, SP2) may be positioned at the ends of the other side of the first and second pin-shaped patterns (105A1, 105B2) respectively so as not to partially overlap. The length of the overlapping portions in the second direction (e.g., D2) may be greater than the width of the first and second separation regions (SP1, SP2) in the first direction (e.g., D1).

[0060] The first gate line (GL1) may be positioned to extend in a second direction (e.g., D2) and intersect the third active pin (105C) and the overlapping portions. Similarly, the second gate line (GL2) may be positioned to intersect the fourth active pin (105D) and the overlapping portions, respectively. Additionally, the third gate line (GL3) may be positioned to extend in the second direction (e.g., D2) and intersect the fourth active pin (105D). The fourth gate line (GL4) may be positioned to extend in the second direction (e.g., D2) and intersect the third active pin (105C). The third and fourth gate lines (GL3, GL4) may be located on the same line as the first and second gate lines ((GL1, GL2)), respectively. In some embodiments, the first and second gate lines (GL1, GL2) and the third and fourth gate lines (GL3, GL4) can be understood as structures obtained by forming the same gate line (or dummy gate line) and then separating it into a gate separation part ("GP") in FIG. 7.

[0062] As shown in FIG. 4b, a desired SRAM cell can be constructed by forming contacts (190, 195) and metal lines (M1, M2, M3, M4) based on the layout of active pins and gate lines shown in FIG. 4a.

[0063] Referring to FIG. 4b and FIG. 5, the SRAM cell employed in the present embodiment may include a pair of inverters (INV1, INV2) connected in parallel between a power node (Vcc) and a ground node (Vss), and a first pass transistor (PS1) and a second pass transistor (PS2) connected to the output nodes of each inverter (INV1, INV2). The first pass transistor (PS1) and the second pass transistor (PS2) may each be connected to a bit line (BL) and a complementary bit line (BL / ). The gates of the first pass transistor (PS1) and the second pass transistor (PS2) may be connected to a word line (WL).

[0064] The first inverter (INV1) includes a first pull-up transistor (PU1) and a first pull-down transistor (PD1) connected in series, and the second inverter (INV2) includes a second pull-up transistor (PU2) and a second pull-down transistor (PD2) connected in series. The first pull-up transistor (PU1) and the second pull-up transistor (PU2) are PMOS transistors, and the first pull-down transistor (PD1) and the second pull-down transistor (PD2) may be NMOS transistors.

[0065] In addition, the first inverter (INV1) and the second inverter (INV2) form a latch circuit, so that the input node of the first inverter (INV1) is connected to the output node of the second inverter (INV2), and the input node of the second inverter (INV2) is connected to the output node of the first inverter (INV1).

[0066] Here, referring to FIG. 4b, the first pull-up transistor (PU1) is defined by the area where the first gate line (GL1) and the first pin-shaped pattern (105A1) intersect and the surrounding area, the first pull-down transistor (PD1) is defined by the area where the first gate line (GL1) and the third active pin (105C) intersect and the surrounding area, and the first pass transistor (PS1) is defined by the area where the fourth gate line (GL4) and the third active pin (105C) intersect and the surrounding area. Similarly, the second pull-up transistor (PU2) is defined by the area where the second gate line (GL2) and the second pin-shaped pattern (105B1) intersect and the surrounding area, the second pull-down transistor (PD2) is defined by the area where the second gate line (GL2) and the fourth active pin (105D) intersect and the surrounding area, and the second pass transistor (PS2) is defined by the area where the third gate line (GL3) and the fourth active pin (105D) intersect and the surrounding area.

[0067] Although not clearly illustrated in FIG. 4b, source / drains (150 in FIG. 6) may be formed on both sides of the area where the first to fourth gate lines (GL1, GL2, GL3, GL4) and the active pin (including the first and second pin-shaped patterns) intersect. A contact (195A) may be formed on this source / drain (150). In addition to the contact (195A), a shared contact (195B) may be formed. A shared contact (195B) may simultaneously connect the first pin-shaped pattern (105A1) and the second gate line (GL2), and may be connected to the third active pin (105C) by the first metal line (M1). Similarly, another shared contact (195B) can simultaneously connect the second pin-shaped pattern (105B1) and the first gate line (GL1), and can be connected to the fourth active pin (105D) by the second metal line (M2). Thus, the SRAM circuit structure illustrated in FIG. 5 can be implemented. In this embodiment, the first and second pull-up transistors (PU1, PU2) may each be p-type MOSFETs, and the first and second pull-down transistors (PD1, PD2) and the first and second pass transistors (PS1, PS2) may each be n-type MOSFETs.

[0069] FIG. 6 is a cross-sectional view of the SRAM cell shown in FIG. 2a, cut along A-A', BB', and C-C', and FIG. 7 is a cross-sectional view of the SRAM cell shown in FIG. 2a, cut along D-D'.

[0070] Referring to FIG. 6, the cross-sections cut along A-A', BB', and C-C' represent the cross-sections of the first pull-up transistor (PU1), the first pull-down transistor (PD1), and the first pass transistor (PS1), respectively.

[0071] As previously explained, the first and second pull-up transistors (PU1, PU2) may be p-type MOSFETs, and the first and second pull-down transistors (PD1, PD2) and the first and second pass transistors (PS1, PS2) may be n-type MOSFETs.

[0072] In the substrate (101), the first and second active pins (105A, 105B) may be n-type, and the third and fourth active pins (105C, 105D) may be p-type. The first source / drain region (150P) of the first and second active pins (105A, 105B) constituting the first pull-up transistor (PU1) may be formed by regrowth of a SiGe epitaxial layer having a relatively large lattice constant. The Ge content may vary depending on the growth direction in the selectively epitaxially grown SiGe layer. As previously described, the first source / drain region (150P) may have a pentagonal cross-section (see FIG. 2a and FIG. 2b).

[0073] The source / drain regions (150N) of the first and second pull-down transistors (PD1, PD2) and the first and second pass transistors (PS1, PS2) can be formed by regrowing Si or SiC epitaxial material with a relatively small lattice constant. As previously described, the second source / drain region (150N) may have a hexagonal or polygonal cross-section with gentle angles (see FIG. 2a and FIG. 2b).

[0074] Although not shown, cross-sections of the second pull-up transistor (PU2), the second pull-down transistor (PD1), and the first pass transistor (PS2) can also be understood to have a structure similar to the cross-sections shown in FIG. 6.

[0075] Referring to FIG. 7, second and fourth gate lines (GL2, GL4) located on the same line are illustrated. The gate lines may be formed along the surfaces of the first to fourth active pins and the upper surface of the device isolation film. As previously described, the second and fourth gate lines (GL2, GL4) may be a structure obtained by forming identical gate lines (or dummy gate lines) and then separating them into gate isolation sections (GP).

[0077] The semiconductor device (100) according to the present embodiment can be applied to transistors of various structures. As an example, the semiconductor device (100A) illustrated in FIGS. 8 and 9 has a transistor (i.e., MBCFET®) structure having a nanosheet. FIGS. 8 and 9 are cross-sectional views of a semiconductor device according to one embodiment of the present invention, respectively, and can be understood as cross-sections corresponding to FIGS. 6 and 7.

[0079] Referring to FIGS. 8 and FIGS. 9, the semiconductor device (100A) according to the present embodiment can be understood as similar to the semiconductor device (100) shown in FIGS. 1 to 7, except that the active pattern in each transistor region is a single structure and the active structure for the transistor is configured to include a plurality of nanosheets. Additionally, unless specifically stated otherwise, the components of the present embodiment can be understood by referring to the description of identical or similar components of the semiconductor device (100) shown in FIGS. 1 to 7.

[0081] Referring to FIGS. 8 and FIGS. 9, the semiconductor device (100) according to the present embodiment includes an active pin (105) for each transistor. Similar to the preceding embodiment, the active pin (105) may have a structure that protrudes in a third direction (e.g., D3) from the upper surface of the substrate (101) and extends along the first direction (e.g., D1).

[0082] A semiconductor device (100A) according to the present embodiment may further include a plurality of nanosheet-shaped channel layers (140) spaced perpendicularly apart from each other on active pins (105) (105A, 105B, 105C, 105D in FIG. 9) and internal spacer layers (130) spaced parallel to a gate electrode layer (165) between the plurality of channel layers (140). The semiconductor device (100A) may include transistors of a gate-all-around type structure in which the gate electrode (165) is spaced between the active pin (105) and the lowest channel layers (140) and between the plurality of channel layers (140). For example, each transistor of the semiconductor device (100A) may be composed of channel layers (140), source / drain regions (150P, 150N), and a gate electrode (165).

[0084] Multiple channel layers (140) may be arranged in two or more such that they are spaced apart from each other in a third direction (e.g., D3) on the active pin (105). The channel layers (140) may be spaced apart from the upper surfaces of the active pin (105) while being connected to the source / drain regions (150). The channel layers (140) may have a width equal to or similar to that of the active pin (105) in the second direction (e.g., D2) and may have a width equal to or similar to that of the gate lines (GL1, GL2, G4) in the first direction (e.g., D1). However, as in the present embodiment, when an internal spacer (130) is used, the channel layers (140) may have a width that is reduced compared to the width of the sides below the gate lines (GL).

[0085] A plurality of channel layers (140) may be made of a semiconductor material and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel layers (140) may be made of, for example, the same material as the substrate (101) (particularly, the active region). The number and shape of the channel layers (140) forming a single channel structure may vary in the embodiments.

[0086] Internal spacers (130) may be disposed on both sides of the gate electrode layer (165) in the first direction between a plurality of channel layers (140). The gate electrode (165) may be electrically separated from the source / drain regions (150P, 150N) by the internal spacers (130). The internal spacers (130) may have a flat side facing the gate electrode (165) or a convexly rounded cross-section facing the gate electrode (165) (see FIG. 8). The internal spacers (130) may be made of oxide, nitride, and oxynitride, and in particular may be made of a low dielectric constant film.

[0088] As such, the semiconductor device according to the present embodiment can be applied to transistors of various structures, and in addition to the embodiments described above, it can be implemented as a semiconductor device including a vertical FET (VFET) having an active region extending vertically on the upper surface of a substrate (101) and a gate structure surrounding it, or as a semiconductor device including a negative capacitance FET (NCFET) using a gate insulating film having ferroelectric properties.

[0090] FIGS. 10a to 17a are plan views of major processes for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 10b to 12b are cross-sectional views obtained by cutting the planes of FIGS. 10a to 12a along I-I', FIGS. 13b to 17b are cross-sectional views obtained by cutting the planes of FIGS. 13a to 17a along I1-I1', FIGS. 13c to 17c are cross-sectional views obtained by cutting the planes of FIGS. 13a to 17a along I2-I2'.

[0092] First, referring to FIG. 10a and FIG. 10b, a plurality of line patterns (LP) can be formed on a substrate (101) that are extended parallel to each of the first directions (e.g., D1).

[0093] A plurality of line patterns (LP) include two groups of line patterns arranged in a second direction (e.g., D2), and each group of line patterns (LP) may include a pair of first line patterns (LP1), a pair of second line patterns (LP2) located on one side of the first line patterns (LP1), and a pair of third line patterns (LP3) located on the other side of the first line patterns (LP2).

[0094] The plurality of line patterns (LP) employed in this embodiment may include a plurality of spacers (SP) extended in a first direction (e.g., D1) and a mask pattern (MP) corresponding to the plurality of spacers (SP). In one embodiment, a first hard mask (HM1, indicated by a dotted line) is formed on the substrate (101), a self-aligning patterning process is performed on the first hard mask (HM1) to form a plurality of spacers (SP) extended in the first direction (e.g., D1), and the first hard mask (HM1) is patterned using the plurality of spacers (SP) to form line patterns (LP) composed of a mask pattern (MP) and spacers (SP).

[0095] Multiple line patterns (LP) can be formed in various forms under conditions permitted in the self-aligning patterning process. For example, multiple spacers have the same width and can be varied in the spacing between the multiple spacers.

[0096] In this embodiment, the spacing (d1) of a pair of first line patterns (LP1) may be substantially the same as the spacing (d1) of a pair of second and fourth line patterns, respectively. The spacing (d2) of adjacent first and second line patterns is the same as the spacing (d2) of adjacent first and third line patterns, but may be different from the spacing (d1) of the first line patterns and the spacing (d3) of two groups of adjacent line patterns.

[0098] Next, referring to FIGS. 11a and FIGS. 11b, a second hard mask (HM2) is formed to cover a plurality of line patterns (LP) on the substrate (101), and a photoresist layer (PR) is applied on the second hard mask (HM2).

[0099] In some embodiments, the photoresist film may be made of a resist material for extreme ultraviolet (EUV) (e.g., 135 nm). In other embodiments, the photoresist film may be made of a resist for an F2 excimer laser (157 nm), a resist for an ArF excimer laser (193 nm), or a resist for a KrF excimer laser (248 nm). The photoresist film may be made of a positive photoresist or a negative photoresist. In some embodiments, to form a photoresist film made of the positive photoresist, a photoresist composition comprising a photosensitive polymer having an acid-labile group, a potential acid, and a solvent may be spin-coated onto the second hard mask (HM2).

[0101] Next, referring to FIGS. 12a and FIGS. 12b, a photomask (PM) for patterning a photoresist layer (PR) is placed.

[0102] FIG. 13 illustrates a photomask employed in the present process. Referring to FIG. 12a and FIG. 13, the photomask (PM) employed in the present embodiment may include a first serif portion (SF1) and a pair of second serif portions (SF2a, SF2b) located on both sides of the first serif portion (SF1). The first serif portion (SF1) has an area covering a pair of first line patterns (LP1) and may have first and second cut patterns (CT1, CT2) at both corners. In the present embodiment, the second serif portions (SF2a, SF2b) may be formed to cover one second line pattern (LP2) and one third line pattern (LP3) respectively adjacent to the pair of first line patterns (LP1).

[0103] The first and second cut patterns (CT1, CT2) can define first and second notch regions (NA1, NA2) for first and second separation regions (SP1, SP2 in FIG. 1). In this embodiment, by designing a photomask (PM) using the H-CR (Hexagonal-Corner Rounding) OPC (Optical proximity Correction) method to minimize distortion, the internal lines of the first and second notch regions (NA1, NA2) can introduce a vertical component ("SL") in FIG. 20, thereby resolving the problem of gate line alignment errors caused by inevitable errors in the EUV process (e.g., changes in the D2 direction of the active pin position).

[0104] The EUV corner rounding optimization method using H-CR OPC employed in this embodiment can be explained with reference to FIG. 19a and FIG. 19b.

[0105] Referring to FIG. 19a, to design a desired rectangular notch area in a virtual mask pattern (SF1'), the vertices of the notch area are divided into an inner vertex group (①+②+③) and an outer vertex group (⑤+⑥). For each group, a correction radius (Ri,Ro) is calculated as a correction movement value, and corner rounding is applied to implement it in the actual mask pattern (SF1) as shown in FIG. 19b. Subsequently, the remaining vertices ④ and ⑦ can also have their radii optimized in a similar manner to the preceding process to satisfy the Total Edge Placement Error, and the corner rounding can be further optimized.

[0106] Referring to FIG. 19b, the notch region (NA1) may have two outer corners (RC1) that are convexly rounded with a first radius (Ro) and two inner corners (RC2) that are concavely rounded with a second radius (Ri). Additionally, the notch region (NA1) may have a convexly rounded portion (RC3) between the two inner corners (RC2).

[0107] In this way, by using a photomask (PM) having optically approximated cut patterns (CT1, CT2) according to the present embodiment, a notch area (i.e., cut pattern (CT1, CT2)) indicated by a dotted line can be formed.

[0108] Next, referring to FIGS. 13a to 13c, a photoresist pattern (PR') can be formed by performing a lithography process using a photomask (PM) on the second hard mask (HM2).

[0109] The photoresist pattern (PR') includes a first pattern (PM1) obtained from a first serif portion (SF1) and a pair of second patterns (PM2a, PM2b) obtained from a pair of second serif patterns (SF2a, SF2b). The cut pattern (CT1, CT2) formed on the first pattern (PM1) can sufficiently secure the vertical component of the side defining the cross-section of the active pin. In this way, by minimizing the slope of the side of the cross-section by the cut pattern (CT1, CT2) along the second direction (e.g., D2), it is possible to effectively prevent defects (e.g., untuck and ghost fin) in which the end of the active pin is not accurately aligned with the gate line during gate line formation due to inevitable errors in which the position of the active pin changes in the second direction (e.g., D2) during the EUV process for the active pin.

[0110] As illustrated in FIG. 12a, the width of the first serif portion (SF1) and the second serif portion (SF2a, SF2b) in the second direction (D2) is designed to be somewhat larger than the width of the line patterns (LP), so that the photoresist pattern (PR') can also be formed such that a portion of the second hard mask (HM2) remains on both sides of the line patterns (LP).

[0112] Next, referring to FIGS. 14a to 14c, a mask pattern (FP) is formed from the second hard mask (HM2) using the photoresist pattern (PR'), and the photoresist pattern (PR') is removed from the mask pattern (FP).

[0113] In this process, one second line pattern and one third line pattern located in the open area of ​​the photoresist pattern (PR') are removed, and the portion of the pair of first line patterns exposed by the cut pattern (CT1, CT2) can be removed. First and second separation openings (SP1', SP2') can be formed. The pair of first line patterns (LP1a, LP1b) can each be separated into multiple (e.g., two) by the first and second separation openings (SP1', SP2').

[0114] The remaining mask pattern (FP) may include a second hard mask portion (HP) surrounding the remaining line pattern (LP1a, LP1b, LP2, LP3). In the present embodiment, the mask pattern (FP) may include a first portion (FP1) comprising a pair of first line patterns (LP1a, LP1b), a second portion (FP2) covering the remaining second line pattern (LP2), and a second portion (FP3) covering the remaining third line pattern (LP3).

[0115] Additionally, the mask pattern (FP) may include a first opening located between the first part (FP1) and the second part (FP2), a second opening located between the first part (FP1) and the third part (FP3), a first separation opening (SP1') extending from the first opening to separate an adjacent first line pattern (LP1a), and a second separation opening (SP2') extending from the second opening to separate an adjacent first line pattern (LP1b).

[0117] Next, referring to FIGS. 15a to 15c, a plurality of active pins (105) extending in the first direction (e.g., D1) are formed by etching the substrate (101) using the mask pattern (MP).

[0118] A plurality of active pins (105) may include first and second active pins (105A, 105B) corresponding to a first part (FP1), a third active pin (105C) corresponding to a second part (FP2), and a fourth active pin (105D) corresponding to a third part (FP3).

[0119] The first active pin (105A) has first and second pin-shaped patterns (105A1, 105A2) separated by a first separation region (SP1) corresponding to the first separation opening (SP1'), and similarly, the second active pin (105B) has first and second pin-shaped patterns (105B1, 105B2) separated by a first separation region (SP2) corresponding to the second separation opening (SP2').

[0120] The first trench region (T1) between the first and second active pins (105A, 105B) has a lower depth than other trench regions, namely the second to fourth trench regions (T2, T3, T4). Since the second hard mask material (HP) is present in the first portion (FP1) corresponding between the first and second active pins (105A, 105B), it is less etched compared to other trench regions (T2, T3, T4) that provide a complete opening, and thus has a relatively lower depth. Additionally, the first to fourth active pins (105A, 105B, 105C, 105D) may have a step structure (ST) in which the width of the lower region is greater than the width of the upper region due to the second hard mask portion (HP).

[0121] Additionally, as illustrated in FIG. 15b, the bottom of the first separation area (SP1) may have a level (La2) substantially the same as the bottom level (La1) of the second trench area (T2). Similarly, the bottom of the second separation area (SP2) may have a level substantially the same as the bottom level of the third trench area (T3). In this embodiment, the first trench area (T1) may have a portion (TE) extending along the first direction (e.g., D1) to the first and second separation areas (SP1, SP2).

[0122] FIG. 20a is a cross-sectional view taken by cutting the plane of FIG. 15a along II-II'.

[0123] Referring to FIG. 20a together with FIG. 15a and FIG. 15b, the extended portion (TE) may have a level (Lb) higher than the bottom level (La2) of the first and second separated regions and the bottom level (La1) of the second to fourth trench regions (T2, T3, T4). The upper surface level (Lb) of the extended portion (TE) may have a level substantially the same as or somewhat lower than the bottom level of the first trench region (T1).

[0124] FIG. 20b is a magnified view showing a part ("C2") of FIG. 15a.

[0125] Referring to FIG. 20b, the first pin-shaped patterns (105A1, 105A2) each have a cross-section defined by the first separation region (SP1), and the cross-section of the first pin-shaped patterns (105A1, 105A2) each may have a portion (SL) that is substantially perpendicular to the first direction (e.g., D1) in a planar view. Thus, despite errors in the EUV process for forming active pins, one side of each of the gate lines (GL2, GL3) in FIG. 3 can be aligned to almost coincide with the cross-section of the first pin-shaped patterns (105A1, 105A2) provided by the first separation region (SP1). Similarly, the cross-section of each of the second pin-shaped patterns (105A1, 105A2) defined by the second separation region (SP2) may also have a significant perpendicular component, thereby preventing defects caused by misalignment of the gate lines.

[0126] As shown in FIG. 20b, the first and second separation regions (SP1, SP2) each have outer edges adjacent to the third or fourth active pin and inner edges adjacent to the second active pin, and in a planar view, the outer edges may have a convexly rounded portion (R1) and the inner edges may have a concavely rounded portion (R2) in a planar view.

[0128] Next, referring to FIGS. 16a to 16c, after forming a device isolation film (110) to cover a plurality of active pins (105), a planarization process can be performed to a desired height (PL). Then, referring to FIGS. 17a to 17c, the device isolation film (110) can be etched back to expose a portion of the plurality of active pins (105) from the upper surface of the device isolation film (110) to a desired height.

[0129] Subsequently, by additionally performing a dummy gate formation process, a source / drain formation process, and a gate line formation process, the semiconductor device illustrated in FIGS. 1 to 3 can be manufactured.

[0131] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0133] 101: Substrate 105: Active pin 105A, 105B, 105C, 105D: 1st to 4th active pins 105A1, 105A2: First pin-type pattern 105B1, 105B2: Second pin-type pattern 110: Device isolation film SP: Isolation region TR1, TR2, TR3, TR4: 1st to 4th trench regions TE: Trench extension area 130: Internal spacer layer 140: Channel layer 150: Source / drain region 160: Gate structure 162: Gate dielectric layer 164: Gate spacer 165: Gate electrode 166: Gate capping layer 190: Interlayer insulating film

Claims

Claim 1 A first active pin extending in a first direction and having a plurality of first pin-shaped patterns separated by a first separation region - the plurality of first pin-shaped patterns are aligned in the first direction with the first separation region in between -; a second active pin extending in the first direction and having a plurality of second pin-shaped patterns separated by a second separation region - the plurality of second pin-shaped patterns are aligned in the first direction with the second separation region in between, and the first and second separation regions are arranged so as not to overlap in a second direction intersecting the first direction, and the first trench region between the first and second active pins has a first depth -; a third active pin extending in the first direction and disposed adjacent to the first active pin - the second trench region between the first and third active pins has a second depth greater than the first depth -; A semiconductor device comprising: a fourth active pin extending in the first direction and positioned adjacent to the second active pin, wherein a third trench region between the second and fourth active pins has a third depth greater than the first depth; at least one first gate line extending in the second direction and positioned to intersect the first and second active pins and the third active pin; and at least one second gate line extending in the second direction and positioned to intersect the first and second active pins and the fourth active pin; wherein the plurality of first pin-shaped patterns and the plurality of second pin-shaped patterns are merged by the first trench region, and the second and third trench regions are each connected to the first and second separation regions, and the bottoms of the first and second separation regions each have the same level as the bottom level of the second and third trench regions. Claim 2 A semiconductor device according to claim 1, wherein each of the plurality of first pin-shaped patterns has a first central region that overlaps with the first separation region in the second direction and first and second end regions located on both sides of the first central region, and each of the plurality of second pin-shaped patterns has a second central region that overlaps with the second separation region in the second direction and third and fourth end regions located on both sides of the second central region. Claim 3 A semiconductor device according to paragraph 2, wherein the plurality of first and second pin-shaped patterns are arranged such that the first end region and the fourth end region overlap in the second direction, and the second end region and the third end region overlap in the second direction. Claim 4 A semiconductor device according to claim 3, wherein the at least one first gate line comprises a plurality of first gate lines arranged to intersect the third active pin and the overlapping first and fourth end regions, and the at least one second gate line comprises a plurality of second gate lines arranged to intersect the fourth active pin and the overlapping second and third end regions. Claim 5 A semiconductor device according to paragraph 3, wherein the first and second active pins are of the first conductivity type and the third and fourth active pins are of the second conductivity type. Claim 6 A semiconductor device according to claim 3, comprising a third gate line extending in the second direction, located on the same line as the at least one first gate line, and arranged to intersect the fourth active pin, and a fourth gate line extending in the second direction, located on the same line as the at least one second gate line, and arranged to intersect the third active pin. Claim 7 A semiconductor device according to claim 1, wherein the first and second separation regions each have outer edges adjacent to the third and fourth active pins, and the outer edges have convexly rounded portions in a planar view. Claim 8 A semiconductor device according to claim 1, wherein the first and second pin-shaped patterns each have a cross-section defined by the first and second separation regions, and the cross-sections of the first and second pin-shaped patterns each have a portion perpendicular to the first direction in a planar view. Claim 9 A semiconductor device according to claim 1, wherein the first and second separation regions each have inner edges adjacent to the second and first active pins, and the inner edges have concavely rounded portions in a planar view. Claim 10 A semiconductor device according to claim 1, wherein the first trench region defines the opposing sides of the plurality of first and second pin-shaped patterns and has a portion extending to the first and second separation regions along the first direction. Claim 11 A semiconductor device according to claim 10, wherein the extended portion of the first trench region has an upper surface having the same level as the bottom level of the first trench region. Claim 12 A semiconductor device according to claim 1, wherein the spacing between the first and second active pins is smaller than the spacing between the first and third active pins or the spacing between the second and fourth active pins. Claim 13 A semiconductor device according to claim 12, wherein the spacing of the first and third active pins is the same as the spacing of the second and fourth active pins. Claim 14 A first active pin extending in a first direction and having first and second pin-shaped patterns separated by a separation region - said first and second pin-shaped patterns are aligned in the first direction with the separation region in between -; a second active pin extending in the first direction and having a central region that overlaps with the separation region in a second direction intersecting the first direction and first and second end regions that overlap with the first and second pin-shaped patterns, respectively, in the second direction - said first trench region defining the opposing sides of the first and second active pins has a first depth -; a third active pin extending in the first direction and having one side facing the other side of the first active pin - said second trench region defining the other side of the first active pin and one side of the third active pin has a second depth greater than the first depth -; a first gate line extending in the second direction and arranged to intersect the first pin-shaped pattern of the first active pin and the first part of the second active pin; A semiconductor device comprising: a second gate line extending in the second direction and arranged to intersect with a second pin-shaped pattern of the first active pin and a second portion of the second active pin; wherein the first and second pin-shaped patterns of the first active pin are combined with the second active pin by the first trench region, the second trench region is connected to the separation region, and the bottom of the separation region has the same level as the bottom of the second trench region. Claim 15 In claim 14, a semiconductor device in which at least one of the first and second gate lines extends in the second direction so as to intersect with the third active pin. Claim 16 A semiconductor device according to claim 14, wherein the first and second pin-shaped patterns each have a cross-section defined by the separation region, and the cross-sections of the first and second pin-shaped patterns each have a portion perpendicular to the first direction in a planar view. Claim 17 A semiconductor device according to claim 16, wherein the separation region each has an outer edge adjacent to the third active pin and an inner edge adjacent to the second active pin, and in a planar view, the outer edge has a convexly rounded portion and the inner edge has a concavely rounded portion. Claim 18 A semiconductor device according to claim 14, wherein the first trench region has a portion extending along the first direction to the separation region, and the extended portion of the first trench region has an upper surface having the same level as the bottom level of the first trench region. Claim 19 A first active pin extending in a first direction and having a plurality of first pin-shaped patterns separated by a first separation region - the plurality of first pin-shaped patterns are aligned in the first direction with the first separation region in between -; a second active pin extending in the first direction and having a plurality of second pin-shaped patterns separated by a second separation region - the plurality of second pin-shaped patterns are aligned in the first direction with the second separation region in between, and the first and second separation regions are each arranged to overlap with the central region of each of the plurality of second and first pin-shaped patterns in a second direction intersecting the first direction, and the plurality of first and second pin-shaped patterns are each arranged to overlap with two adjacent pin-shaped patterns among the plurality of second and first pin-shaped patterns in the second direction -; a third active pin extending in the first direction and positioned adjacent to the first active pin; A fourth active pin extending in the first direction and positioned adjacent to the second active pin; a first trench region positioned between the first and second active pins and having a first depth smaller than the depth of the separation region; a second trench region positioned between the first and third active pins and having a second depth larger than the first depth; a third trench region positioned between the second and fourth active pins and having a third depth larger than the first depth; first gate lines extending in the second direction and positioned to intersect the third active pin and the overlapping portions of the plurality of first and second pin-shaped patterns; A semiconductor device comprising second gate lines extending in the second direction and arranged to intersect the overlapping portions of the fourth active pin and the plurality of first and second pin-shaped patterns, wherein the second and third trench regions are each connected to the first and second separation regions, and the bottoms of the first and second separation regions each have the same level as the bottom level of the second and third trench regions. Claim 20 A step of forming a plurality of line patterns each extended parallel to a first direction on a semiconductor substrate - the plurality of line patterns include adjacent first and second line patterns and a third line pattern located on one side of the first line pattern -; a step of forming a hard mask covering the plurality of line patterns on the semiconductor substrate; a step of forming a photoresist pattern by performing a lithography process using a photomask on the hard mask; a step of forming a mask pattern from the hard mask using the photoresist pattern - the mask pattern has a first portion covering the first and second line patterns, a second portion covering the third line pattern, a first opening located between the first portion and the second portion, and a second opening extending from the first opening to open a portion of the first line pattern to separate the first line pattern -; A method for manufacturing a semiconductor device comprising: a step of etching the semiconductor substrate using the mask pattern to form a plurality of active pins extending in the first direction; wherein, in the step of forming the plurality of active pins, a trench region defined by the first opening and a separation region defined by the second opening are formed, the trench region is connected to the separation region, and the bottom of the separation region has the same level as the bottom of the trench region.

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