Display apparatus

Abstract

A display device according to an embodiment of the present specification may include a substrate comprising a display area and a non-display area adjacent to the display area; a first semiconductor pattern disposed in the display area of ​​the substrate and comprising a first polysilicon; a first gate electrode overlapping with the first semiconductor pattern with a first gate insulating layer in between; and a first source electrode and a first drain electrode connected to the first semiconductor pattern; a second thin-film transistor comprising a second semiconductor pattern disposed in the display area of ​​the substrate and comprising a first oxide semiconductor; a second gate electrode overlapping with the second semiconductor pattern with a second gate insulating layer and a third gate insulating layer in between; and a second source electrode and a second drain electrode connected to the second semiconductor pattern; and a third thin-film transistor disposed in the non-display area of ​​the substrate and comprising a third semiconductor pattern comprising a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern with a third gate insulating layer in between, and a third source electrode and a third drain electrode connected to the third semiconductor pattern.

Description

Technology Field

[0001] This specification relates to a display device comprising a thin-film transistor. Background Technology

[0002] Generally, electronic devices such as monitors, TVs, laptops, and digital cameras include display devices that display images. For example, a display device may include a Liquid Crystal Display (LCD) containing liquid crystals and an Electroluminescence Display (ELD) containing a light-emitting layer.

[0003] Among display devices, electroluminescent display devices utilize self-luminescent elements that emit light on their own.

[0004] A display device may include a plurality of pixels. Each pixel may emit a specific color. Within each pixel, a driving element may be located to generate a driving current according to a gate signal and a data signal. For example, the driving element may include at least one thin-film transistor.

[0005] Thin film transistors can be classified based on the material constituting the active layer into amorphous silicon thin film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin film transistors in which oxide semiconductor is used as the active layer.

[0006] Since amorphous silicon can be deposited to form an active layer in a short time, amorphous silicon thin-film transistors (a-Si TFTs) have the advantages of short manufacturing process times and low production costs. On the other hand, amorphous silicon thin-film transistors have the disadvantage of limited use in applications such as active matrix organic light-emitting diodes (AMOLEDs) due to their low mobility resulting in poor current driving capability and the occurrence of threshold voltage fluctuations.

[0007] Polycrystalline silicon thin-film transistors (poly-Si TFTs) are fabricated by crystallizing amorphous silicon after it has been deposited. Polycrystalline silicon TFTs possess advantages such as high electron mobility, excellent stability, thin thickness, the ability to achieve high resolution, and high power efficiency. Examples of such polycrystalline silicon TFTs include Low Temperature Poly Silicon (LTPS) thin-film transistors or polysilicon thin-film transistors. However, because the manufacturing process of polycrystalline silicon TFTs requires a crystallization step for amorphous silicon, the number of process steps increases, leading to higher manufacturing costs, and crystallization must occur at high process temperatures. Consequently, there are difficulties in applying polycrystalline silicon TFTs to large-area devices. Furthermore, due to their polycrystalline characteristics, it is challenging to ensure the uniformity of polycrystalline silicon TFTs.

[0008] Oxide semiconductor thin-film transistors (TFTs), which possess high mobility and exhibit significant resistance changes depending on oxygen content, have the advantage of easily achieving desired physical properties. Additionally, manufacturing costs are low because the oxide forming the active layer can be deposited at relatively low temperatures during the fabrication process. Due to the inherent properties of oxides, oxide semiconductors are transparent, making them advantageous for realizing transparent displays. However, oxide semiconductor TFTs have the disadvantage of lower stability and electron mobility compared to polycrystalline silicon thin-film transistors.

[0009] Oxide semiconductor thin-film transistors (TFTs) can be manufactured in a bottom-gate type back-channel etch (BCE) or etch stopper (ES) structure, or in a top-gate type coplanar structure. In the case of a coplanar structure oxide semiconductor thin-film transistor, controlling the conductive region formed by the oxide semiconductor is very important, and the mobility of the TFT can vary depending on the sheet resistance of the conductive region. Therefore, it is necessary to manage the process conditions for forming the conductive region, and it is necessary to minimize the influence of the conductive region on insulating layers placed above or below the oxide semiconductor layer. The problem to be solved

[0010] The present specification, proposed to solve the aforementioned problem, provides a display device comprising a thin-film transistor including a conductive portion formed by doping without patterning of the gate insulating film.

[0011] The present specification provides a display device having different mobilities for a thin-film transistor comprising an oxide semiconductor disposed in a non-display area and a thin-film transistor comprising an oxide semiconductor disposed in a display area.

[0012] The present specification provides a display device in which the mobility of a driving thin-film transistor controlling the current flowing to a light-emitting element disposed in a display area and the mobility of a switching thin-film transistor disposed in a pixel area controlling the on-off of the driving thin-film transistor are different.

[0013] The problems to be solved according to the embodiments of this specification are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0014] A display device according to one embodiment of the present specification may include a substrate comprising a display area and a non-display area adjacent to the display area; a first semiconductor pattern disposed in the display area of ​​the substrate and comprising a first polysilicon; a first gate electrode overlapping with the first semiconductor pattern with a first gate insulating layer in between; and a first source electrode and a first drain electrode connected to the first semiconductor pattern; a second semiconductor pattern disposed in the display area of ​​the substrate and comprising a first oxide semiconductor; a second gate electrode overlapping with the second semiconductor pattern with a second gate insulating layer and a third gate insulating layer in between; and a second source electrode and a second drain electrode connected to the second semiconductor pattern; and a third thin-film transistor disposed in the non-display area of ​​the substrate and comprising a third semiconductor pattern comprising a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern with a third gate insulating layer in between, and a third source electrode and a third drain electrode connected to the third semiconductor pattern.

[0015] A display device according to another embodiment of the present specification may include a substrate comprising a display area and a non-display area adjacent to the display area; a first semiconductor pattern disposed in the display area of ​​the substrate and comprising a first oxide semiconductor; a first gate electrode overlapping with the first semiconductor pattern with a second gate insulating layer and a third gate insulating layer in between; and a first source electrode and a first drain electrode connected to the first semiconductor pattern; a second semiconductor pattern disposed in the display area of ​​the substrate and comprising a second oxide semiconductor; a second gate electrode overlapping with the second semiconductor pattern with a third gate insulating layer in between; and a second source electrode and a second drain electrode connected to the second semiconductor pattern; and a third thin-film transistor disposed in the non-display area of ​​the substrate and comprising a third semiconductor pattern comprising polysilicon, a third gate electrode overlapping with the third semiconductor pattern with a first gate insulating layer in between, and a third source electrode and a third drain electrode connected to the third semiconductor pattern. Effects of the invention

[0016] According to one embodiment of the present specification, a conductive portion of a semiconductor layer can be formed by doping using a photoresistor pattern as a mask without patterning a gate insulating film.

[0017] According to another embodiment of the present specification, a display device including thin-film transistors having different mobility characteristics can be provided by designing the stacking structure of the gate insulating film of a thin-film transistor placed in a display area of ​​the display device and the gate insulating film of a thin-film transistor placed in a non-display area differently. Furthermore, by providing thin-film transistors having different mobility characteristics, high-quality images can be realized in the display device. According to another embodiment of the present specification, the stacking structure of the gate insulating film of a driving thin-film transistor that controls the current flowing to a light-emitting element placed in a display area and the gate insulating film of a switching thin-film transistor placed in a pixel area that controls the on-off of the driving thin-film transistor can be formed differently. Accordingly, the functionality of the display device can be improved by providing thin-film transistors suitable for the characteristics of each thin-film transistor. Brief explanation of the drawing

[0018] FIG. 1 is a cross-sectional view of a display device according to one embodiment of the present specification. FIG. 2 is a cross-sectional view of a display device according to another embodiment of the present specification. FIG. 3 is a cross-sectional view of a display device according to another embodiment of the present specification. FIG. 4 is a cross-sectional view of a display device according to another embodiment of the present specification. Specific details for implementing the invention

[0019] The advantages and features according to this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed herein and may be implemented in various different forms.

[0020] The embodiments of this specification are provided to ensure that the technical concept of this specification is sufficiently conveyed to those skilled in the art; therefore, this specification may be embodied in other forms so as not to be limited to the embodiments described below.

[0021] It should be noted that in assigning reference numbers to the components of each drawing in this specification, identical components are given the same number as much as possible, even if they are shown in different drawings.

[0022] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of this specification are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing embodiments of this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the gist of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0023] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0024] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0025] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0026] The term 'at least one' should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of 'at least one of the first item, the second item, and the third item' is not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0027] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0028] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an interlocking relationship.

[0029] Hereinafter, embodiments of the present specification are described in detail with reference to the attached drawings.

[0030] FIG. 1 is a cross-sectional view of a display device according to one embodiment of the present specification.

[0031] Referring to FIG. 1, the substrate (110) of the display device (100) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be composed of a plurality of pixels. Each pixel may be composed of a first thin-film transistor (310) and a second thin-film transistor (320). The first thin-film transistor (310) may include a polysilicon (Poly-Si) material. Among the polysilicon (Poly-Si) materials, it may include a low-temperature polysilicon (LTPS) material. The second thin-film transistor (320) may include an oxide semiconductor material. The first thin-film transistor (310) containing the polysilicon (Poly-Si) material may be a switching thin-film transistor (Switching TFT) that controls the operation of the second thin-film transistor (320), which is a driving thin-film transistor. Additionally, the second thin-film transistor (320) containing an oxide semiconductor material may be a driving thin-film transistor (DFT) electrically connected to the first electrode (410) to supply current to the light-emitting element (400). However, it is not limited thereto, and the first thin-film transistor (310) containing a polysilicon (Poly-Si) material may be a driving thin-film transistor. Additionally, the second thin-film transistor (320) containing an oxide semiconductor material may be a switching thin-film transistor.

[0032] A non-display area (NDA) may be positioned adjacent to a display area (DA). Additionally, a driving circuit for driving pixels of the display area (DA) may be positioned in the non-display area (NDA). The driving circuit may include a third thin-film transistor (330) and a fourth thin-film transistor (340). Thus, the third thin-film transistor (330) positioned in the non-display area (NDA) may include an oxide semiconductor. Additionally, the fourth thin-film transistor (340) may include polysilicon (Poly-Si).

[0033] The first thin-film transistor (310) placed in the display area (DA) may be composed of a negative-type transistor (n-type TFT) or a positive-type transistor (p-type TFT). Additionally, the second thin-film transistor (320) placed in the display area (DA) may be composed of a negative-type transistor (n-type TFT). Furthermore, the fourth thin-film transistor (340) placed in the non-display area (NDA) may be composed of a negative-type transistor (n-type TFT) or a positive-type transistor (p-type TFT). Additionally, the third thin-film transistor (330) placed in the non-display area (NDA) may be composed of a negative-type transistor (n-type TFT).

[0034] For example, a fourth thin-film transistor (340) comprising polysilicon and placed in a non-display area (NDA) may be configured as a positive-type transistor (p-type TFT). At this time, a first thin-film transistor (310) comprising polysilicon and placed in a display area (DA) may also be configured as a positive-type transistor (p-type TFT). Additionally, a second thin-film transistor (320) comprising an oxide semiconductor and placed in a display area (DA), and a third thin-film transistor (330) comprising an oxide semiconductor and placed in a non-display area (NDA) may be configured as a negative-type transistor (n-type TFT).

[0035] In another example, a fourth thin-film transistor (340) comprising polysilicon and placed in a non-display area (NDA) may be configured as a negative-type transistor (n-type TFT). At this time, a first thin-film transistor (310) comprising polysilicon and placed in a display area (DA) may also be configured as a negative-type transistor (n-type TFT). Additionally, a second thin-film transistor (320) comprising an oxide semiconductor and placed in a display area (DA), and a third thin-film transistor (330) comprising an oxide semiconductor and placed in a non-display area (NDA) may be configured as negative-type transistors (n-type TFTs).

[0036] Referring to FIG. 1, a display device (100) according to one embodiment of the present specification may include a substrate (110), a first buffer layer (111), a first gate insulating layer (112), a first interlayer insulating layer (113), a second buffer layer (114), a second gate insulating layer (115), a third gate insulating layer (116), a second interlayer insulating layer (117), a first protective layer (118), a second protective layer (119), a bank layer (120), a spacer (121), a first storage capacitor (140), a second storage capacitor (150), a first connecting electrode (160), a second connecting electrode (170), an auxiliary electrode (180), a light-emitting element (400), an encapsulation member (500), a first thin-film transistor (310), a second thin-film transistor (320), a third thin-film transistor (330), and a fourth thin-film transistor (340).

[0037] The substrate (110) can support various components of the display device (100). The substrate (110) may be made of glass or a plastic material having flexibility. If the substrate (110) is made of a plastic material, for example, it may be made of polyimide (PI). If the substrate (110) is made of polyimide (PI), the display device manufacturing process may proceed with a support substrate made of glass placed under the substrate (110), and the support substrate may be released after the display device manufacturing process is completed. Additionally, after the support substrate is released, a back plate for supporting the substrate (110) may be placed under the substrate (110).

[0038] When the substrate (110) is made of polyimide (PI), moisture components may penetrate the substrate (110) made of polyimide (PI) and pass through to the first thin-film transistor (310) or light-emitting element (400), thereby degrading the performance of the display device. A display device (100) according to one embodiment of the present specification may be composed of double polyimide (PI) to prevent performance degradation due to moisture penetration. Additionally, by forming an inorganic insulating layer between the two polyimide (PI) layers, moisture components can be blocked from penetrating the lower polyimide (PI) layer, thereby improving the reliability of the display device.

[0039] Additionally, when an inorganic insulating layer is formed between two polyimides (PI), the charge placed on the lower polyimide (PI) may form a back bias and affect the first thin-film transistor (310) or the second thin-film transistor (320). Therefore, it is necessary to form a separate metal layer to block the charge placed on the polyimide (PI). However, a display device according to another embodiment of this specification can improve product reliability by blocking the charge placed on the lower polyimide (PI) by forming an inorganic film between two polyimides (PI). The inorganic insulating layer may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. For example, the inorganic insulating layer may be formed with a silicon dioxide (SiO2) material. In addition, since the process of forming a metal layer to block the charge charged on the polyimide (PI) can be omitted, the process can be simplified and production costs can be reduced.

[0040] The first buffer layer (111) may be formed over the entire surface of the substrate (110). The first buffer layer (111) may consist of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. According to an embodiment of the present specification, the first buffer layer (111) may be formed as a multilayer in which silicon oxide (SiOx) and silicon nitride (SiNx) are alternately formed. For example, the first buffer layer (111) may consist of n+1 layers. Here, n may be an even number including 0, such as 0, 2, 4, 6, or 8. Thus, when n=0, the first buffer layer (111) is formed as a single layer. Also, the first buffer layer (111) may be silicon nitride (SiNx) or silicon oxide (SiOx). When n=2, the first buffer layer (111) may be formed as a triple layer. When the first buffer layer (111) is formed as a triple layer, the upper and lower layers may be silicon oxide (SiOx), and the intermediate layer placed between the upper and lower layers may be silicon nitride (SiNx). And, when n=4, the first buffer layer (111) may be formed as a quintuplet layer.

[0041] In this way, when the first buffer layer (111) is composed of a multilayer formed alternately of silicon oxide (SiOx) and silicon nitride (SiNx), the uppermost layer and the lowermost layer of the first buffer layer (111) may be formed of silicon oxide (SiOx) material. For example, the first buffer layer (111) composed of a plurality of layers may include an upper layer in contact with the first semiconductor pattern (311) of the first thin-film transistor (310) and the fourth semiconductor pattern (341) of the fourth thin-film transistor (340), a lower layer in contact with the substrate (110), and an intermediate layer located between the upper layer and the lower layer. Also, the upper layer and the lower layer may be formed of silicon oxide (SiOx) material. Furthermore, the upper layer of the first buffer layer (111) composed of multiple layers may be formed to be thicker than the thickness of the lower layer and the intermediate layer.

[0042] The first thin-film transistor (310) and the fourth thin-film transistor (340) may be disposed on the first buffer layer (111). The first thin-film transistor (310) disposed in the display area (DA) may include a first semiconductor pattern (311), a first gate electrode (314), a first source electrode (312), and a first drain electrode (313). Without being limited thereto, the first source electrode (312) may be a drain electrode, and the first drain electrode (313) may be a source electrode. The fourth thin-film transistor (340) disposed in the non-display area (NDA) may include a fourth semiconductor pattern (341), a fourth gate electrode (344), a fourth source electrode (342), and a fourth drain electrode (343). Without being limited thereto, the fourth source electrode (342) may be a drain electrode, and the fourth drain electrode (343) may be a source electrode.

[0043] A first semiconductor pattern (311) of a first thin-film transistor (310) and a fourth semiconductor pattern (341) of a fourth thin-film transistor (340) may be disposed on the first buffer layer (111). The first semiconductor pattern (311) may be disposed in a display area (DA), and the fourth semiconductor pattern (341) may be disposed in a non-display area (NDA). The first semiconductor pattern (311) and the fourth semiconductor pattern (341) may include polysilicon (Poly-si). For example, the first semiconductor pattern (311) and the fourth semiconductor pattern (341) may include low-temperature polysilicon (LTPS).

[0044] Polysilicon material has high mobility (100 cm² / Vs or higher), low power consumption, and excellent reliability, so it can be applied to gate drivers and / or multiplexers (MUX) for driving devices that drive thin-film transistors for display devices. Furthermore, it can be applied as a semiconductor pattern of a switching thin-film transistor in a display device according to the embodiments of this specification, but is not limited thereto. For example, it may be applied as a semiconductor pattern of a driving thin-film transistor.

[0045] According to an embodiment of the present specification, the first semiconductor pattern (311) of the first thin-film transistor (310) placed in the display area (DA) can be applied as a semiconductor pattern of a switching thin-film transistor. In addition, the fourth semiconductor pattern (341) of the fourth thin-film transistor (340) in the non-display area (NDA) can be applied as a semiconductor pattern of a thin-film transistor for a gate signal. The thin-film transistor for a gate signal may be a switching thin-film transistor that performs a switching function.

[0046] An amorphous silicon (a-Si) material may be deposited on the first buffer layer (111), and a polysilicon layer may be formed through a crystallization process. Then, the polysilicon layer may be patterned to form a first semiconductor pattern (311) and a fourth semiconductor pattern (341).

[0047] A first semiconductor pattern (311) formed in a display area (DA) may include a first channel area (311C) in which a channel is formed when the first thin-film transistor (310) is driven, and a first source area (311S) and a first drain area (311D) on both sides of the first channel area (311C). The first source area (311S) may be a portion of the first semiconductor pattern (311) connected to a first source electrode (312), and the first drain area (311D) may be a portion of the first semiconductor pattern (311) connected to a first drain electrode (313). The first source area (311S) and the first drain area (311D) may be formed by ion doping (impurity doping) of the first semiconductor pattern (311). The first source region (311S) and the first drain region (311D) can be created by ion doping a polysilicon material, and the first channel region (311C) can be a portion left as an un-ion-doped polysilicon material.

[0048] The fourth semiconductor pattern (341) formed in the non-display area (NDA) may include a fourth channel area (341C) in which a channel is formed when the fourth thin-film transistor (340) is driven, and a fourth source area (341S) and a fourth drain area (341D) on both sides of the fourth channel area (341C). The fourth source area (341S) may be a portion of the fourth semiconductor pattern (341) connected to the fourth source electrode (342), and the fourth drain area (341D) may be a portion of the fourth semiconductor pattern (341) connected to the fourth drain electrode (343). The fourth source area (341S) and the fourth drain area (341D) may be formed by ion doping (impurity doping) of the fourth semiconductor pattern (341). The fourth source region (341S) and the fourth drain region (341D) can be created by ion doping the polysilicon material, and the fourth channel region (341C) can be a portion left as un-ion-doped polysilicon material.

[0049] A first gate insulating layer (112) may be disposed on the first semiconductor pattern (311) of the first thin-film transistor (310) and the fourth semiconductor pattern (341) of the fourth thin-film transistor (340). The first gate insulating layer (112) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0050] A first gate electrode (314) of a first thin-film transistor (310), a fourth gate electrode (344) of a fourth thin-film transistor (340), a first storage lower electrode (141) of a first storage capacitor (140), and a second storage lower electrode (151) of a second storage capacitor (150) may be disposed on a first gate insulating layer (112).

[0051] The first gate electrode (314), the fourth gate electrode (344), the first storage lower electrode (141), and the second storage lower electrode (151) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The first gate electrode (314), the fourth gate electrode (344), the first storage lower electrode (141), and the second storage lower electrode (151) may be formed of the same material.

[0052] The first gate electrode (314) is placed in the display area (DA) and can overlap with the first channel area (311C) of the first semiconductor pattern (311) with the first gate insulating layer (112) in between. The fourth gate electrode (444) is placed in the non-display area (NDA) and can overlap with the fourth channel area (341C) of the fourth semiconductor pattern (341) with the first gate insulating layer (112) in between. Additionally, the first storage lower electrode (141) is placed in the display area (DA), and the second storage lower electrode (151) can be placed in the non-display area (NDA).

[0053] A first interlayer insulating layer (113) may be disposed on a first gate insulating layer (112), a first gate electrode (314), a fourth gate electrode (344), a first storage lower electrode (141), and a second storage lower electrode (151). The first interlayer insulating layer (113) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0054] The first storage upper electrode (142) of the first storage capacitor (140) and the second storage upper electrode (152) of the second storage capacitor (150) may be disposed on the first interlayer insulating layer (113). The first storage upper electrode (142) and the second storage upper electrode (152) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first storage upper electrode (142) may overlap with the first storage lower electrode (141) with the first interlayer insulating layer (113) in between. And, the second storage upper electrode (152) may overlap with the second storage lower electrode (151) with the first interlayer insulating layer (113) in between.

[0055] And, the first storage upper electrode (142) and the second storage upper electrode (152) can be formed of the same material as the first storage lower electrode (141) and the second storage lower electrode (151).

[0056] The first storage lower electrode (141) of the first storage capacitor (140) and the second storage lower electrode (151) of the second storage capacitor (150) may be omitted based on the driving characteristics of the display device and the structure and type of the thin-film transistor. For example, the first storage upper electrode (142) of the first storage capacitor (140) may be arranged to overlap with the first gate electrode (314) of the first thin-film transistor (310). In this case, the first gate electrode (314) may perform the same role as the first storage lower electrode (141). Therefore, the first storage lower electrode (141) may be omitted. The second storage upper electrode (152) of the second storage capacitor (150) may be arranged to overlap with the fourth gate electrode (344) of the fourth thin-film transistor (340). In this case, the fourth gate electrode (344) may perform the same role as the second storage lower electrode (151). Therefore, the second storage lower electrode (151) can be omitted.

[0057] A second buffer layer (114) may be disposed on the first interlayer insulating layer (113), the first storage upper electrode (142), and the second storage upper electrode (152). The second buffer layer (114) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0058] A second semiconductor pattern (321) of a second thin-film transistor (320) may be formed on the second buffer layer (114). The second semiconductor pattern (321) may be placed in a display area (DA) and may be placed to overlap with the first storage capacitor (140). The second semiconductor pattern (321) may be an oxide semiconductor pattern made of an oxide semiconductor. The second thin-film transistor (320) may include a second semiconductor pattern (321), a second gate electrode (324), a second source electrode (322), and a second drain electrode (323). As another example, the second source electrode (322) may be a drain electrode, and the second drain electrode (323) may be a source electrode.

[0059] The second semiconductor pattern (321) may include a second channel region (321C) where a channel is formed when the second thin-film transistor (320) is driven, a second source region (321S) and a second drain region (321D) on both sides of the second channel region (321C). The second source region (321S) may be a part of the second semiconductor pattern (321) connected to the second source electrode (322), and the second drain region (321D) may be a part of the second semiconductor pattern (321) connected to the second drain electrode (323).

[0060] The oxide semiconductor material of the second semiconductor pattern (321) has a larger bandgap compared to the polysilicon material, so electrons cannot cross the bandgap in the off state, and accordingly, the off-current is low. Therefore, a thin-film transistor including an active layer made of an oxide semiconductor may be suitable for a switching thin-film transistor that has a short on time and maintains a long off time, but is not limited thereto. For example, it may be applied as a driving thin-film transistor. Also, since the off-current is small and the size of the auxiliary capacitance can be reduced, it is suitable for a high-resolution display device. Referring to FIG. 1, the second thin-film transistor (320) including the oxide semiconductor may be a driving thin-film transistor that is electrically connected to the first electrode (410) and supplies current to the light-emitting element (400).

[0061] A second gate insulating layer (115) may be formed on the second semiconductor pattern (321) and the second buffer layer (114). The second gate insulating layer (115) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0062] And, a third semiconductor pattern (331) of the third thin-film transistor (330) may be disposed on the second gate insulating layer (115). The third semiconductor pattern (331) may be disposed in a non-display area (NDA) and may be disposed to overlap with the second storage capacitor (150). The third semiconductor pattern (331) may be an oxide semiconductor pattern made of an oxide semiconductor. The third thin-film transistor (330) may include a third semiconductor pattern (331), a third gate electrode (334), a third source electrode (332), and a third drain electrode (333). As another example, the third source electrode (332) may be a drain electrode, and the third drain electrode (333) may be a source electrode.

[0063] The third semiconductor pattern (331) may include a third channel region (331C) where a channel is formed when the third thin-film transistor (330) is driven, a third source region (331S) and a third drain region (331D) on both sides of the third channel region (331C). The third source region (331S) may be a part of the third semiconductor pattern (331) connected to the third source electrode (332), and the third drain region (331D) may be a part of the third semiconductor pattern (331) connected to the third drain electrode (333).

[0064] Since the oxide semiconductor material of the third semiconductor pattern (331) has a larger bandgap compared to the polysilicon material, electrons cannot cross the bandgap in the off state, and accordingly, the off-current is low. Therefore, a thin-film transistor including an active layer made of an oxide semiconductor may be suitable for a switching thin-film transistor that maintains a short on time and a long off time, but is not limited thereto. For example, it may be applied as a driving thin-film transistor. Also, since the off-current is small and the size of the auxiliary capacitance can be reduced, it is suitable for a high-resolution display device. Referring to FIG. 1, the third semiconductor pattern (331) including the oxide semiconductor may be applied as a semiconductor pattern for a thin-film transistor for a gate signal of a display device. The thin-film transistor for a gate signal may be a switching thin-film transistor that performs a switching function.

[0065] The second semiconductor pattern (321) and the third semiconductor pattern (331) may be made of metal oxides. For example, they may be made of various metal oxides such as IGZO (indium-gallium-zinc-oxide). Although the second semiconductor pattern (321) and the third semiconductor pattern (331) have been described as being formed as an IGZO layer among various metal oxides, they are not limited thereto. For example, they may be formed of metal oxides other than IGZO, such as IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), or IGO (indium-gallium-oxide).

[0066] As illustrated in FIG. 1, a third gate insulating layer (116) may be formed on a third semiconductor pattern (331) of a third thin-film transistor (330) disposed in a second gate insulating layer (115) and a non-display area (NDA). The third gate insulating layer (116) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0067] A second gate electrode (324) and a third gate electrode (334) may be formed on the third gate insulating layer (116). The second gate electrode (324) placed in the display area (DA) may overlap with the second channel area (321C) of the second semiconductor pattern (321) with the second gate insulating layer (115) and the third gate insulating layer (116) in between. Additionally, the third gate electrode (334) placed in the non-display area (NDA) may overlap with the third channel area (331C) of the third semiconductor pattern (331) with the third gate insulating layer (116) in between.

[0068] In this way, the gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) placed in the display area (DA) can be formed as a stacked structure of the second gate insulating layer (115) and the third gate insulating layer (116). And, the gate insulating layer stacked between the third gate electrode (334) and the third semiconductor pattern (331) of the third thin-film transistor (330) placed in the non-display area (NDA) can be made of the third gate insulating layer (116).

[0069] Accordingly, the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the second gate electrode (324) may be greater than the thickness of the gate insulating layer located between the third semiconductor pattern (331) and the third gate electrode (334). The thicker the gate insulating layer, the less current leakage can be reduced. Therefore, a thin film transistor including a thick gate insulating layer can be utilized as a driving thin film transistor for controlling the amount of current. Since the switching thin film transistor performs a switching function that controls turn-on or turn-off, current leakage does not pose a significant problem. Therefore, the thickness of the gate insulating layer of the thin film transistor performing the switching function can be formed thinner than the thickness of the gate insulating layer of the thin film transistor used as a driving thin film transistor.

[0070] As such, when the thickness of the gate insulating layer of a thin-film transistor is formed thicker, there is an advantage in that the amount of current leakage is reduced, allowing for effective control of the current amount. However, as the thickness of the gate insulating layer of the thin-film transistor is formed thicker, the mobility decreases, and the characteristics of the switching function may deteriorate. Conversely, when the thickness of the gate insulating layer of the thin-film transistor is formed relatively thinner, there is an advantage in that the mobility increases, thereby improving the characteristics of the switching function. However, as the thickness of the gate insulating layer is formed thinner, the amount of current leakage increases, and the characteristics of the current amount control function may deteriorate. Therefore, in the display device (100) according to the embodiment of the present specification, the thickness of the gate insulating layer can be designed differently depending on the characteristics of the thin-film transistor. Accordingly, thin-film transistors having different mobilities may be included.

[0071] Referring to FIG. 1, the second thin-film transistor (320) used as a driving thin-film transistor may include a gate insulating layer thicker than the third thin-film transistor (330) which performs a switching function as a thin-film transistor for a gate signal. Accordingly, the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the second gate electrode (324) may be greater than the thickness of the gate insulating layer located between the third semiconductor pattern (331) and the third gate electrode (334). For example, as shown in FIG. 1, the gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) may be formed as a stacked structure of the second gate insulating layer (115) and the third gate insulating layer (116). Also, the gate insulating layer stacked between the third gate electrode (334) and the third semiconductor pattern (331) of the third thin-film transistor (330) may be made of the third gate insulating layer (116).

[0072] The second gate electrode (324) and the third gate electrode (334) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. Additionally, the second gate electrode (324) and the third gate electrode (334) may be formed of the same material.

[0073] A second interlayer insulating layer (117) may be formed on the second gate electrode (324), the third gate electrode (334), and the third gate insulating layer (116).

[0074] The second interlayer insulating layer (117) may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx)-based material or a multilayer thereof.

[0075] A contact hole can be formed to expose a first semiconductor pattern (311) of a first thin-film transistor (310) and a fourth semiconductor pattern (341) of a fourth thin-film transistor (340) by etching the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), the second buffer layer (114), the first interlayer insulating layer (113), and the first gate insulating layer (112). For example, a contact hole can be formed to expose a first source region (311S) and a first drain region (311D) of a first semiconductor pattern (311) by etching the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), the second buffer layer (114), the first interlayer insulating layer (113), and the first gate insulating layer (112). And, a contact hole can be formed that exposes the fourth source region (341S) and the fourth drain region (341D) of the fourth semiconductor pattern (341).

[0076] Additionally, the second interlayer insulating layer (117), the third gate insulating layer (116), and the second gate insulating layer (115) can be etched to form a contact hole for exposing the second semiconductor pattern (321) of the second thin-film transistor (320). For example, the second interlayer insulating layer (117), the third gate insulating layer (116), and the second gate insulating layer (115) can be etched to form a contact hole that exposes the second source region (321S) and the second drain region (321D) of the second semiconductor pattern (321).

[0077] Additionally, the second interlayer insulating layer (117) and the third gate insulating layer (116) can be etched to form a contact hole for exposing the third semiconductor pattern (331) of the third thin-film transistor (330). For example, the second interlayer insulating layer (117) and the third gate insulating layer (116) can be etched to form a contact hole that exposes the third source region (331S) and the third drain region (331D) of the third semiconductor pattern (331).

[0078] Additionally, the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), and the second buffer layer (114) can be etched to form a contact hole that exposes the first storage upper electrode (142) and the second storage upper electrode (152).

[0079] On the second interlayer insulating layer (117), a first connecting electrode (160), a second connecting electrode (170), a first source electrode (312) and a first drain electrode (313) of a first thin-film transistor (310), a second source electrode (322) and a second drain electrode (323) of a second thin-film transistor (320), a third source electrode (332) and a third drain electrode (333) of a third thin-film transistor (330), and a fourth source electrode (342) and a fourth drain electrode (343) of a fourth thin-film transistor (340) may be disposed.

[0080] The first source electrode (312) and the first drain electrode (313) of the first thin-film transistor (310) can be connected to the first source region (311S) and the first drain region (311D) of the first semiconductor pattern (311) through contact holes formed in the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), the second buffer layer (114), the first interlayer insulating layer (113), and the first gate insulating layer (112).

[0081] And, the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320) can be connected to the second source region (321S) and the second drain region (321D) of the second semiconductor pattern (321) through contact holes formed in the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), the second buffer layer (114), the first interlayer insulating layer (113), and the first gate insulating layer (112).

[0082] Additionally, the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330) can be connected to the third source region (331S) and the third drain region (331D) of the third semiconductor pattern (331) through contact holes formed in the second interlayer insulating layer (117) and the third gate insulating layer (116).

[0083] Additionally, the fourth source electrode (342) and the fourth drain electrode (343) of the fourth thin-film transistor (340) can be connected to the fourth source region (341S) and the fourth drain region (341D) of the fourth semiconductor pattern (341) through contact holes formed in the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), the second buffer layer (114), the first interlayer insulating layer (113), and the first gate insulating layer (112).

[0084] And, the first connecting electrode (160) placed in the display area (DA) can be connected to the first storage upper electrode (142) of the first storage capacitor (140) through a contact hole formed in the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), and the second buffer layer (114). And, the first connecting electrode (160) can be electrically connected to the second drain electrode (323) of the second thin-film transistor (320). As another example, the first connecting electrode (160) can be connected to the second source electrode (322) of the second thin-film transistor (320). The first connecting electrode (160) can be an integral type connected to the second drain electrode (323) of the second thin-film transistor (320). As another example, the first connecting electrode (160) may be an integral type connected to the second source electrode (322) of the second thin-film transistor (320).

[0085] Additionally, the second connecting electrode (170) placed in the non-display area (NDA) can be connected to the second storage upper electrode (152) of the second storage capacitor (150) through a contact hole formed in the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), and the second buffer layer (114). Furthermore, the second connecting electrode (170) can be electrically connected to the third drain electrode (333) of the third thin-film transistor (330). As another example, the second connecting electrode (170) can be connected to the third source electrode (332) of the third thin-film transistor (330). The second connecting electrode (170) can be an integral type connected to the third drain electrode (333) of the third thin-film transistor (330). As another example, the second connecting electrode (170) may be an integral type connected to the third source electrode (332) of the third thin-film transistor (330).

[0086] The first connecting electrode (160), the second connecting electrode (170), the first source electrode (312) and the first drain electrode (313) of the first thin-film transistor (310), the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320), the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330), and the fourth source electrode (342) and the fourth drain electrode (343) of the fourth thin-film transistor (340) can be formed of the same material and can be arranged on the same layer. For example, as illustrated in FIG. 1, the first connecting electrode (160), the second connecting electrode (170), the first source electrode (312) and the first drain electrode (313) of the first thin-film transistor (310), the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320), the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330), and the fourth source electrode (342) and the fourth drain electrode (343) of the fourth thin-film transistor (340) may be arranged in contact with the upper surface of the second interlayer insulating layer (117). And, they may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), or an alloy thereof.

[0087] A first protective layer (118) may be formed on the first connecting electrode (160), the second connecting electrode (170), the first source electrode (312) and the first drain electrode (313) of the first thin-film transistor (310), the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320), the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330), and the fourth source electrode (342) and the fourth drain electrode (343) of the fourth thin-film transistor (340).

[0088] A contact hole may be formed in the first protective layer (118) to expose the second drain electrode (323) of the second thin-film transistor (320). However, it is not limited thereto, and a contact hole may be formed in the first protective layer (118) to expose the second source electrode (322) of the second thin-film transistor (320). The first protective layer (118) may be an organic material layer. For example, the first protective layer (118) may be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. As another example, the first protective layer (118) may be composed of a single layer of inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) material or a multilayer thereof.

[0089] The auxiliary electrode (180) may be disposed on the first protective layer (118). The auxiliary electrode (180) may be connected to the second drain electrode (323) of the second thin-film transistor (320) through a contact hole of the first protective layer (118). The auxiliary electrode (180) may electrically connect the second thin-film transistor (320) and the first electrode (410). The auxiliary electrode (180) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The auxiliary electrode (180) may be formed of the same material as the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320).

[0090] A second protective layer (119) may be disposed on an auxiliary electrode (180) and a first protective layer (118). As shown in FIG. 1, a contact hole may be formed in the second protective layer (119) to expose the auxiliary electrode (180). The second protective layer (119) may be an organic material layer. For example, the second protective layer (119) may be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0091] A first electrode (410) of a light-emitting element (400) may be disposed on the second protective layer (119). The first electrode (410) may be electrically connected to an auxiliary electrode (180) through a contact hole formed in the second protective layer (119). Thus, the first electrode (410) may be electrically connected to a second thin-film transistor (320) by being connected to an auxiliary electrode (180) through a contact hole formed in the second protective layer (119). The first electrode (410) may be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film may be made of a material with a relatively high work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). In addition, the opaque conductive film may be formed as a single layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the first electrode (410) may have a transparent conductive film, an opaque conductive film, and a transparent conductive film formed sequentially. However, it is not limited thereto, and for example, a transparent conductive film and an opaque conductive film may be formed sequentially.

[0092] Since the display device according to the embodiment of the present specification is a top emission display device, the first electrode (410) may be an anode electrode. In the case where the display device is bottom emission, the first electrode (410) disposed on the second protective layer (119) may be a cathode electrode.

[0093] A bank layer (120) may be disposed on the first electrode (410) and the second protective layer (119). An opening may be formed in the bank layer (120) to expose the first electrode (410). Since the bank layer (120) can define a light-emitting area of ​​the display device, it may also be called a pixel defining film. A spacer (121) may be further disposed on the bank layer (120). And, a light-emitting layer (420) of a light-emitting element (400) may be further disposed on the first electrode (410).

[0094] The light-emitting layer (420) can be formed on the first electrode (410) in the order of a hole layer (HL), a light-emitting material layer (EML), and an electron layer (EL), or in reverse order.

[0095] In addition, the light-emitting layer (420) may have a first light-emitting layer and a second light-emitting layer with a charge generation layer (CGL) in between. In this case, either of the first light-emitting layer and the second light-emitting layer may generate blue light, and the other of the first light-emitting layer and the second light-emitting layer may generate yellow-green light, thereby generating white light through the first light-emitting layer and the second light-emitting layer. The white light generated through the first light-emitting layer and the second light-emitting layer may be incident on a color filter located above the light-emitting layer to create a color image. As another example, a color image may be created by generating color light corresponding to each subpixel in each light-emitting layer without a separate color filter. That is, the light-emitting layer of the red (R) subpixel may generate red light, the light-emitting layer of the green (G) subpixel may generate green light, and the light-emitting layer of the blue (B) subpixel may generate blue light.

[0096] Referring to FIG. 1, a second electrode (430) of a light-emitting element (400) may be further disposed on the light-emitting layer (420). The second electrode (430) may overlap with the first electrode (410) with the light-emitting layer (420) in between. In a display device according to an embodiment of the present specification, the second electrode (430) may be a cathode electrode.

[0097] A sealing member (500) that inhibits moisture penetration may be further disposed on the second electrode (430). The sealing member (500) may include a first sealing layer (510), a second sealing layer (520), and a third sealing layer (530). The second sealing layer (520) may include a material different from the first sealing layer (510) and the third sealing layer (530). For example, the first sealing layer (510) and the third sealing layer (530) may be inorganic insulating films formed of inorganic insulating materials, and the second sealing layer (520) may be an organic insulating film formed of organic insulating materials. The first sealing layer (510) of the sealing member (500) may be disposed on the second electrode (430). And, the second sealing layer (520) may be disposed on the first sealing layer (510). Additionally, the third bag layer (530) can be placed on the second bag layer (520).

[0098] The first sealing layer (510) and the third sealing layer (530) of the sealing member (500) may be formed from an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second sealing layer (520) of the sealing member (500) may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0099] FIG. 2 is a cross-sectional view of a display device according to another embodiment of the present specification.

[0100] Referring to FIG. 2, the substrate (210) of the display device (200) may have a display area (DA) composed of a plurality of pixels. Each pixel may be composed of a first thin-film transistor (350) and a second thin-film transistor (320). The first thin-film transistor (350) and the second thin-film transistor (320) may include an oxide semiconductor material. However, they are not limited thereto, and may additionally include thin-film transistors including a polysilicon (Poly-Si) material as in FIG. 1. FIG. 2 describes the second thin-film transistor (320), which is a switching thin-film transistor, and the first thin-film transistor (350), which is a driving thin-film transistor, among the thin-film transistors made of oxide semiconductors.

[0101] In the substrate (210), a non-display area (NDA) may be disposed adjacent to a display area (DA). Additionally, a driving circuit for driving pixels of the display area (DA) may be disposed in the non-display area (NDA). The driving circuit may include a third thin-film transistor (330). The third thin-film transistor (330) disposed in the non-display area (NDA) may include an oxide semiconductor.

[0102] The first thin-film transistor (350) and the second thin-film transistor (320) placed in the display area (DA) may be configured as negative-type transistors (n-type TFTs). Additionally, the third thin-film transistor (330) placed in the non-display area (NDA) may be configured as a negative-type transistor (n-type TFT).

[0103] Referring to FIG. 2, a display device (200) according to another embodiment of the present specification may include a substrate (210), a buffer layer (211), a first gate insulating layer (212), a second gate insulating layer (213), an interlayer insulating layer (214), a protective layer (215), a bank layer (216), a spacer (217), a first metal pattern (610), a second metal pattern (620), a third metal pattern (630), a light-emitting element (400), an encapsulation member (500), a first thin-film transistor (350), a second thin-film transistor (320), and a third thin-film transistor (330).

[0104] The substrate (210) can support various components of the display device (200). The substrate (210) may be made of glass or a plastic material having flexibility. If the substrate (210) is made of a plastic material, for example, it may be made of polyimide (PI). If the substrate (210) is made of polyimide (PI), moisture components may penetrate the substrate (210) made of polyimide (PI) and permeate to the first thin-film transistor (350), the second thin-film transistor (320), the third thin-film transistor (330), or the light-emitting element (400), thereby degrading the performance of the display device.

[0105] A display device (200) according to an embodiment of the present specification may form a first metal pattern (610), a second metal pattern (620), and a third metal pattern (630) on a substrate (210) to prevent performance degradation due to moisture penetration.

[0106] Additionally, the first metal pattern (610), the second metal pattern (620), and the third metal pattern (630) may serve as a light-blocking mechanism to prevent external light from entering the semiconductor patterns of the first thin-film transistor (350), the second thin-film transistor (320), and the third thin-film transistor (330).

[0107] Accordingly, as illustrated in FIG. 2, the first metal pattern (610) can overlap with the first semiconductor pattern (351) of the first thin-film transistor (350). Also, the second metal pattern (620) can overlap with the second semiconductor pattern (321) of the second thin-film transistor (320). Additionally, the third metal pattern (630) can overlap with the third semiconductor pattern (331) of the third thin-film transistor (330). The first metal pattern (610), the second metal pattern (620), and the third metal pattern (630) may be of the same material and may be formed on the same layer. And, the first metal pattern (610), the second metal pattern (620), and the third metal pattern (630) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or an alloy thereof.

[0108] A buffer layer (211) may be formed on a first metal pattern (610), a second metal pattern (620), and a third metal pattern (630). The buffer layer (211) may consist of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. According to an embodiment of the present specification, the buffer layer (211) may be formed as a multilayer of silicon oxide (SiOx) and silicon nitride (SiNx) formed alternately.

[0109] In this way, when the buffer layer (211) is composed of a multilayer formed alternately of silicon oxide (SiOx) and silicon nitride (SiNx), the uppermost layer and the lowermost layer of the buffer layer (211) may be formed of silicon oxide (SiOx) material.

[0110] The first thin-film transistor (350) can be placed on the buffer layer (211). The first thin-film transistor (350) can be placed in the display area (DA) of the display device (200).

[0111] A first thin-film transistor (350) placed in a display area (DA) may include a first semiconductor pattern (351), a first gate electrode (354), a first source electrode (352), and a first drain electrode (353). Without being limited thereto, the first source electrode (352) may be a drain electrode, and the first drain electrode (353) may be a source electrode.

[0112] Referring to FIG. 2, a first semiconductor pattern (351) of a first thin-film transistor (350) may be formed on a buffer layer (211). The first semiconductor pattern (351) may be placed in a display area (DA) and may be placed to overlap with a first metal pattern (610). The first semiconductor pattern (351) may be an oxide semiconductor pattern made of an oxide semiconductor. The first thin-film transistor (350) may include a first semiconductor pattern (351), a first gate electrode (354), a first source electrode (352), and a first drain electrode (353). In another example, the first source electrode (352) may be a drain electrode, and the first drain electrode (353) may be a source electrode.

[0113] The first semiconductor pattern (351) may include a first channel region (351C) where a channel is formed when the first thin-film transistor (350) is driven, a first source region (351S) and a first drain region (351D) on both sides of the first channel region (351C).

[0114] Referring to FIG. 2, the first thin-film transistor (350) including an oxide semiconductor may be a driving thin-film transistor that supplies current to a light-emitting element (400).

[0115] A first gate insulating layer (212) may be formed on the first semiconductor pattern (351) and the buffer layer (211). The first gate insulating layer (212) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0116] And, a second semiconductor pattern (321) of a second thin-film transistor (320) and a third semiconductor pattern (331) of a third thin-film transistor (330) can be placed on the first gate insulating layer (212).

[0117] The second semiconductor pattern (321) may be placed in the display area (DA) and may be placed to overlap with the second metal pattern (620). The second semiconductor pattern (321) may be an oxide semiconductor pattern made of an oxide semiconductor. The second thin-film transistor (320) may include the second semiconductor pattern (321), a second gate electrode (324), a second source electrode (322), and a second drain electrode (323). As another example, the second source electrode (322) may be the drain electrode, and the second drain electrode (323) may be the source electrode.

[0118] The second semiconductor pattern (351) may include a second channel region (321C) where a channel is formed when the second thin-film transistor (320) is driven, a second source region (321S) and a second drain region (321D) on both sides of the second channel region (321C).

[0119] Referring to FIG. 2, the second thin-film transistor (320) including an oxide semiconductor may be a switching thin-film transistor.

[0120] The third semiconductor pattern (331) of the third thin-film transistor (330) may be placed in a non-display area (NDA) and may be placed to overlap with the third metal pattern (630). The third semiconductor pattern (331) may be an oxide semiconductor pattern made of an oxide semiconductor. The third thin-film transistor (330) may include the third semiconductor pattern (331), the third gate electrode (334), the third source electrode (332), and the third drain electrode (333). As another example, the third source electrode (332) may be the drain electrode, and the third drain electrode (333) may be the source electrode.

[0121] The third semiconductor pattern (331) may include a third channel region (331C) where a channel is formed when the third thin-film transistor (330) is driven, a third source region (331S) and a third drain region (331D) on both sides of the third channel region (331C).

[0122] Referring to FIG. 2, a third thin-film transistor (330) including an oxide semiconductor can be applied as a semiconductor pattern of a thin-film transistor for a gate signal of a display device (200). The thin-film transistor for a gate signal may be a switching thin-film transistor that performs a switching function.

[0123] A second gate insulating layer (213) may be formed on the second semiconductor pattern (321), the third semiconductor pattern (331), and the first gate insulating layer (212). The second gate insulating layer (213) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0124] A first gate electrode (354), a second gate electrode (324), and a third gate electrode (334) may be formed on the second gate insulating layer (213). The first gate electrode (354) placed in the display area (DA) may overlap with the first channel area (351C) of the first semiconductor pattern (351) with the first gate insulating layer (212) and the second gate insulating layer (213) in between. Additionally, the second gate electrode (324) placed in the display area (DA) may overlap with the second channel area (321C) of the second semiconductor pattern (321) with the second gate insulating layer (213) in between. Furthermore, the third gate electrode (334) placed in the non-display area (NDA) may overlap with the third channel area (331C) of the third semiconductor pattern (331) with the second gate insulating layer (213) in between.

[0125] In this way, the gate insulating layer stacked between the first gate electrode (354) and the first semiconductor pattern (351) of the first thin-film transistor (350) placed in the display area (DA) can be formed as a stacked structure of the first gate insulating layer (212) and the second gate insulating layer (213). Additionally, the gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) placed in the display area (DA) can be composed of the second gate insulating layer (213). Furthermore, the gate insulating layer stacked between the third gate electrode (334) and the third semiconductor pattern (331) of the third thin-film transistor (330) placed in the non-display area (NDA) can be composed of the second gate insulating layer (213).

[0126] Accordingly, the thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the third semiconductor pattern (331) and the second gate electrode (324) and the third gate electrode (334). The thicker the gate insulating layer, the less current leakage can be reduced. Therefore, a thin-film transistor including a thick gate insulating layer can be utilized as a driving thin-film transistor for controlling the amount of current. Since the switching thin-film transistor performs a switching function that controls turn-on or turn-off, current leakage does not pose a significant problem. Therefore, the thickness of the gate insulating layer of the thin-film transistor performing the switching function can be formed thinner than the thickness of the gate insulating layer of the thin-film transistor used as a driving thin-film transistor.

[0127] As such, when the thickness of the gate insulating layer of a thin-film transistor is formed thicker, there is an advantage in that the amount of current leakage is reduced, allowing for effective control of the current amount. However, as the thickness of the gate insulating layer of the thin-film transistor is formed thicker, the mobility decreases, and the characteristics of the switching function may deteriorate. Conversely, when the thickness of the gate insulating layer of the thin-film transistor is formed relatively thinner, there is an advantage in that the mobility increases, thereby improving the characteristics of the switching function. However, as the thickness of the gate insulating layer is formed thinner, the amount of current leakage increases, and the characteristics of the current amount control function may deteriorate. Therefore, in the display device (200) according to the embodiment of the present specification, the thickness of the gate insulating layer can be configured differently depending on the characteristics of the thin-film transistor. Accordingly, the display device (200) may include thin-film transistors having different mobilities.

[0128] Referring to FIG. 2, the first thin-film transistor (350) used as a driving thin-film transistor may include a gate insulating layer thicker than the third thin-film transistor (330) which performs a switching function as a gate signal thin-film transistor. Also, among the thin-film transistors placed in the display area (DA), the first thin-film transistor (350) used as a driving thin-film transistor that supplies current to the light-emitting element (400) may include a gate insulating layer thicker than the second thin-film transistor (320) used as a switching thin-film transistor.

[0129] Accordingly, the thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the third semiconductor pattern (331) and the third gate electrode (334). Additionally, the thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the second gate electrode (324). For example, as shown in FIG. 2, the gate insulating layer stacked between the first gate electrode (354) and the first semiconductor pattern (351) of the first thin-film transistor (350) may be formed as a stacked structure of the first gate insulating layer (212) and the second gate insulating layer (213). Additionally, the gate insulating layer stacked between the third gate electrode (334) and the third semiconductor pattern (331) of the third thin-film transistor (330) may be composed of the second gate insulating layer (213). Furthermore, the gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) may also be composed of the second gate insulating layer (213).

[0130] The first gate electrode (354), the second gate electrode (324), and the third gate electrode (334) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. Additionally, the first gate electrode (354), the second gate electrode (324), and the third gate electrode (334) may be formed of the same material and may be placed on the same layer.

[0131] An interlayer insulating layer (214) may be formed on the first gate electrode (354), the second gate electrode (324), the third gate electrode (334), and the second gate insulating layer (213).

[0132] The interlayer insulating layer (214) may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx)-based material or multiple layers thereof.

[0133] A contact hole can be formed to expose a first semiconductor pattern (351) of a first thin-film transistor (350) by etching the interlayer insulating layer (214), the second gate insulating layer (213), and the first gate insulating layer (212).

[0134] And, the interlayer insulating layer (214) and the second gate insulating layer (213) can be etched to form a contact hole for exposing the second semiconductor pattern (321) of the second thin-film transistor (320) and the third semiconductor pattern (331) of the third thin-film transistor (330).

[0135] On the interlayer insulating layer (214), the first source electrode (352) and the first drain electrode (352) of the first thin-film transistor (350), the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330) may be disposed.

[0136] The first source electrode (352) and the first drain electrode (353) of the first thin-film transistor (350) can be connected to the first source region (351S) and the first drain region (351D) of the first semiconductor pattern (351) through contact holes formed in the interlayer insulating layer (214), the second gate insulating layer (213), and the first gate insulating layer (212).

[0137] And, the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320) can be connected to the second source region (321S) and the second drain region (321D) of the second semiconductor pattern (321) through contact holes formed in the interlayer insulating layer (214) and the second gate insulating layer (213).

[0138] Additionally, the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330) can be connected to the third source region (331S) and the third drain region (331D) of the third semiconductor pattern (331) through contact holes formed in the interlayer insulating layer (214) and the second gate insulating layer (213).

[0139] The first source electrode (352) and first drain electrode (353) of the first thin-film transistor (350), the second source electrode (322) and second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (332) and third drain electrode (333) of the third thin-film transistor (330) may be disposed in contact with the upper surface of the interlayer insulating layer (214). Furthermore, they may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0140] A protective layer (215) may be formed on the first source electrode (352) and first drain electrode (353) of the first thin-film transistor (350), the second source electrode (322) and second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (332) and third drain electrode (333) of the third thin-film transistor (330).

[0141] A contact hole may be formed in the protective layer (215) to expose the first drain electrode (353) of the first thin-film transistor (350). However, it is not limited thereto, and a contact hole may be formed in the protective layer (215) to expose the first source electrode (352) of the first thin-film transistor (350). The protective layer (215) may be a single layer or a multilayer made of organic material. For example, the protective layer (215) may be a single layer or a multilayer formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. As another example, the protective layer (215) may be composed of a single layer of inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) material, or a multilayer thereof. Additionally, the protective layer (215) may be a multilayer composed of an inorganic material layer and an organic material layer.

[0142] A first electrode (410) of a light-emitting element (400) may be disposed on a protective layer (215). The first electrode (410) may be electrically connected to a first thin-film transistor (350) through a contact hole formed in the protective layer (215). The first electrode (410) may be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film may be made of a material with a relatively high work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The opaque conductive film may be formed as a single layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or an alloy thereof. For example, the first electrode (410) may have a transparent conductive film, an opaque conductive film, and a transparent conductive film formed sequentially. However, it is not limited to this, and for example, a transparent conductive film and an opaque conductive film may be formed sequentially.

[0143] Since the display device according to the embodiment of the present specification is a top emission display device, the first electrode (410) may be an anode electrode. In the case where the display device is bottom emission, the first electrode (410) disposed on the protective layer (215) may be a cathode electrode.

[0144] A bank layer (216) may be disposed on the first electrode (410) and the protective layer (215). An opening may be formed in the bank layer (216) to expose the first electrode (410). Since the bank layer (216) can define a light-emitting area of ​​the display device, it may also be called a pixel defining film. A spacer (217) may be further disposed on the bank layer (216). And, a light-emitting layer (420) of a light-emitting element (400) may be further disposed on the first electrode (410).

[0145] The light-emitting layer (420) can be formed on the first electrode (410) in the order of a hole layer (HL), a light-emitting material layer (EML), and an electron layer (EL), or in reverse order.

[0146] In addition, the light-emitting layer (420) may have a first light-emitting layer and a second light-emitting layer with a charge generation layer (CGL) in between. In this case, either of the first light-emitting layer and the second light-emitting layer may generate blue light, and the other of the first light-emitting layer and the second light-emitting layer may generate yellow-green light, thereby generating white light through the first light-emitting layer and the second light-emitting layer. The white light generated through the first light-emitting layer and the second light-emitting layer may be incident on a color filter located above the light-emitting layer to create a color image. As another example, a color image may be created by generating color light corresponding to each subpixel in each light-emitting layer without a separate color filter. That is, the light-emitting layer of the red (R) subpixel may generate red light, the light-emitting layer of the green (G) subpixel may generate green light, and the light-emitting layer of the blue (B) subpixel may generate blue light.

[0147] Referring to FIG. 2, a second electrode (430) of a light-emitting element (400) may be further disposed on the light-emitting layer (420). The second electrode (430) may overlap with the first electrode (410) with the light-emitting layer (420) in between. In a display device according to an embodiment of the present specification, the second electrode (430) may be a cathode electrode.

[0148] A sealing member (500) that inhibits moisture penetration may be further disposed on the second electrode (430). The sealing member (500) may include a first sealing layer (510), a second sealing layer (520), and a third sealing layer (530). The second sealing layer (520) may include a material different from the first sealing layer (510) and the third sealing layer (530). For example, the first sealing layer (510) and the third sealing layer (530) may be inorganic insulating films formed of inorganic insulating materials, and the second sealing layer (520) may be an organic insulating film formed of organic insulating materials. The first sealing layer (510) of the sealing member (500) may be disposed on the second electrode (430). And, the second sealing layer (520) may be disposed on the first sealing layer (510). Additionally, the third bag layer (530) can be placed on the second bag layer (520).

[0149] The first sealing layer (510) and the third sealing layer (530) of the sealing member (500) may be formed from an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second sealing layer (520) of the sealing member (500) may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0150] FIG. 3 is a cross-sectional view of a display device according to another embodiment of the present specification.

[0151] Referring to FIG. 3, the substrate (310) of the display device (300) may have a display area (DA) composed of a plurality of pixels. Each pixel may be composed of a first thin-film transistor (350) and a second thin-film transistor (320). The first thin-film transistor (350) and the second thin-film transistor (320) may include an oxide semiconductor material. However, they are not limited thereto, and may additionally include thin-film transistors including a polysilicon (Poly-Si) material as in FIG. 1. FIG. 2 describes the second thin-film transistor (320), which is a switching thin-film transistor, and the first thin-film transistor (350), which is a driving thin-film transistor, among the thin-film transistors made of oxide semiconductors.

[0152] In the substrate (310), a non-display area (NDA) may be disposed adjacent to a display area (DA). Additionally, a driving circuit for driving pixels of the display area (DA) may be disposed in the non-display area (NDA). The driving circuit may include a third thin-film transistor (360). The third thin-film transistor (360) disposed in the non-display area (NDA) may include polysilicon.

[0153] The first thin-film transistor (350) and the second thin-film transistor (320) placed in the display area (DA) may be configured as negative-type transistors (n-type TFTs). Additionally, the third thin-film transistor (360) placed in the non-display area (NDA) may be configured as a negative-type transistor (n-type TFT). As another example, the first thin-film transistor (350) and the second thin-film transistor (320) placed in the display area (DA) may be configured as positive-type transistors (p-type TFTs). Additionally, the third thin-film transistor (360) placed in the non-display area (NDA) may be configured as a negative-type transistor (n-type TFT).

[0154] Referring to FIG. 3, a display device (300) according to another embodiment of the present specification may include a substrate (110), a first buffer layer (111), a first gate insulating layer (112), a first interlayer insulating layer (113), a second buffer layer (114), a second gate insulating layer (115), a third gate insulating layer (116), a second interlayer insulating layer (117), a first protective layer (118), a second protective layer (119), a bank layer (120), a spacer (121), a first metal pattern (611), a second metal pattern (612), an auxiliary electrode (180), a light-emitting element (400), an encapsulation member (500), a first thin-film transistor (350), a second thin-film transistor (320), and a third thin-film transistor (360).

[0155] The substrate (110) can support various components of the display device (300). The substrate (110) may be made of glass or a plastic material having flexibility. If the substrate (110) is made of a plastic material, for example, it may be made of polyimide (PI).

[0156] When the substrate (110) is made of polyimide (PI), moisture components may penetrate the substrate (110) made of polyimide (PI) and pass through to the first thin-film transistor (310) or light-emitting element (400), thereby degrading the performance of the display device. A display device (100) according to one embodiment of the present specification may be composed of double polyimide (PI) to prevent performance degradation due to moisture penetration. Additionally, by forming an inorganic insulating layer between the two polyimide (PI) layers, moisture components can be blocked from penetrating the lower polyimide (PI) layer, thereby improving the reliability of the display device.

[0157] The first buffer layer (111) may be formed over the entire surface of the substrate (110). The first buffer layer (111) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. According to an embodiment of the present specification, the first buffer layer (111) may be formed as a multilayer of silicon oxide (SiOx) and silicon nitride (SiNx) formed alternately. Thus, when the first buffer layer (111) is composed of a multilayer of silicon oxide (SiOx) and silicon nitride (SiNx) formed alternately, the top layer and bottom layer of the first buffer layer (111) may be formed of silicon oxide (SiOx) material.

[0158] A third thin-film transistor (360) placed in a non-display area (NDA) may be placed on a first buffer layer (111). The third thin-film transistor (360) placed in the non-display area (NDA) may include a third semiconductor pattern (361), a third gate electrode (364), a third source electrode (362), and a third drain electrode (363). Without being limited thereto, the third source electrode (362) may be a drain electrode, and the third drain electrode (363) may be a source electrode.

[0159] A third semiconductor pattern (361) of a third thin-film transistor (360) may be disposed on the first buffer layer (111). The third semiconductor pattern (361) may be disposed in a non-display area (NDA). The third semiconductor pattern (361) may include polysilicon (Poly-Si). For example, the third semiconductor pattern (361) may include low-temperature polysilicon (LTPS). According to an embodiment of the present specification, the third semiconductor pattern (361) of the third thin-film transistor (360) in the non-display area (NDA) may be applied as a semiconductor pattern of a thin-film transistor for a gate signal. The thin-film transistor for a gate signal may be a switching thin-film transistor that performs a switching function.

[0160] A third semiconductor pattern (361) formed in a non-display area (NDA) may include a third channel area (361C) in which a channel is formed when the third thin-film transistor (360) is driven, and a third source area (361S) and a third drain area (361D) on both sides of the third channel area (361C).

[0161] A first gate insulating layer (112) may be disposed on a third semiconductor pattern (361) of a third thin-film transistor (360). The first gate insulating layer (112) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0162] A third gate electrode (364) of a third thin-film transistor (360) can be placed on the first gate insulating layer (112).

[0163] The third gate electrode (364) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The third gate electrode (364) may be made of the same material and may be formed on the same layer.

[0164] The third gate electrode (364) is placed in the non-display area (NDA) and can overlap with the third channel area (361C) of the third semiconductor pattern (361) with the first gate insulating layer (112) in between.

[0165] A first interlayer insulating layer (113) may be disposed on the first gate insulating layer (112) and the third gate electrode (364). The first interlayer insulating layer (113) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0166] And, a first metal pattern (611) and a second metal pattern (621) may be placed on the first interlayer insulating layer (113) in the display area (DA). And, the first metal pattern (611) overlaps with the first semiconductor pattern (351) of the first thin-film transistor (350), and the second metal pattern (621) may overlap with the second semiconductor pattern (321) of the second thin-film transistor (320).

[0167] The first metal pattern (611) and the second metal pattern (621) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. The first metal pattern (611) and the second metal pattern (621) may be made of the same material and may be formed on the same layer. The first metal pattern (611) and the second metal pattern (621) may serve as a light-blocking element to prevent external light from passing through the substrate and entering the first semiconductor pattern (351) and the second semiconductor pattern (321).

[0168] A second buffer layer (114) may be disposed on the first interlayer insulating layer (113), the first metal pattern (611), and the second metal pattern (621). The second buffer layer (114) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0169] A first semiconductor pattern (351) of a first thin-film transistor (350) may be formed on the second buffer layer (114). The first semiconductor pattern (351) may be placed in a display area (DA) and may be placed to overlap with a first metal pattern (611). The first semiconductor pattern (351) may be an oxide semiconductor pattern made of an oxide semiconductor. The first thin-film transistor (350) may include a first semiconductor pattern (351), a first gate electrode (354), a first source electrode (352), and a first drain electrode (353). As another example, the first source electrode (352) may be a drain electrode, and the first drain electrode (353) may be a source electrode.

[0170] The first semiconductor pattern (351) may include a first channel region (351C) where a channel is formed when the first thin-film transistor (350) is driven, a first source region (351S) and a first drain region (351D) on both sides of the first channel region (351C).

[0171] Referring to FIG. 3, the first thin-film transistor (350) including an oxide semiconductor may be a driving thin-film transistor that supplies current to a light-emitting element (400).

[0172] A second gate insulating layer (115) may be formed on the first semiconductor pattern (351) and the second buffer layer (114). The second gate insulating layer (115) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0173] And, a second semiconductor pattern (321) of the second thin-film transistor (320) may be disposed on the second gate insulating layer (115). The second semiconductor pattern (321) may be disposed in the display area (DA) and may be disposed to overlap with the second metal pattern (621). The second semiconductor pattern (321) may be an oxide semiconductor pattern made of an oxide semiconductor. The second thin-film transistor (320) may include a second semiconductor pattern (321), a second gate electrode (324), a second source electrode (322), and a second drain electrode (323). As another example, the second source electrode (322) may be a drain electrode, and the second drain electrode (323) may be a source electrode.

[0174] The second semiconductor pattern (351) may include a second channel region (321C) where a channel is formed when the second thin-film transistor (320) is driven, and a second source region (321S) and a second drain region (321D) on both sides of the second channel region (321C). Referring to FIG. 3, the second thin-film transistor (320) including an oxide semiconductor may be a switching thin-film transistor.

[0175] A third gate insulating layer (116) may be formed on the second semiconducting pattern (321) and the second gate insulating layer (115). The third gate insulating layer (116) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0176] A first gate electrode (354) and a second gate electrode (324) may be formed on the third gate insulating layer (116). The first gate electrode (354) placed in the display area (DA) may overlap with the first channel area (351C) of the first semiconductor pattern (351) with the second gate insulating layer (115) and the third gate insulating layer (116) in between. Additionally, the second gate electrode (324) placed in the display area (DA) may overlap with the second channel area (321C) of the second semiconductor pattern (321) with the third gate insulating layer (116) in between.

[0177] In this way, the gate insulating layer stacked between the first gate electrode (354) and the first semiconductor pattern (351) of the first thin-film transistor (350) placed in the display area (DA) can be formed as a stacked structure of the second gate insulating layer (115) and the third gate insulating layer (116). Additionally, the gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) placed in the display area (DA) can be composed of the third gate insulating layer (116).

[0178] Accordingly, the thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the second gate electrode (324). The thicker the gate insulating layer, the less current leakage can be reduced. Therefore, a thin-film transistor including a thick gate insulating layer can be utilized as a driving thin-film transistor for controlling the amount of current. Since the switching thin-film transistor performs a switching function that controls turn-on or turn-off, current leakage does not pose a significant problem. Therefore, the thickness of the gate insulating layer of the thin-film transistor performing the switching function can be formed to be relatively thinner than the thickness of the gate insulating layer of the thin-film transistor used as a driving thin-film transistor.

[0179] As such, when the thickness of the gate insulating layer of a thin-film transistor is formed thicker, there is an advantage in that the amount of current leakage is reduced, allowing for effective control of the current amount. However, as the thickness of the gate insulating layer of the thin-film transistor is formed thicker, the mobility decreases, and the characteristics of the switching function may deteriorate. Conversely, when the thickness of the gate insulating layer of the thin-film transistor is formed relatively thinner, there is an advantage in that the mobility increases, thereby improving the characteristics of the switching function. However, as the thickness of the gate insulating layer is formed thinner, the amount of current leakage increases, and the characteristics of the current amount control function may deteriorate. Therefore, in the display device (300) according to the embodiment of the present specification, the thickness of the gate insulating layer can be configured differently depending on the characteristics of the thin-film transistor. Accordingly, the display device (300) may include thin-film transistors having different mobilities depending on the thickness of the gate insulating layer.

[0180] Referring to FIG. 3, the first thin-film transistor (350) used as a driving thin-film transistor may include a gate insulating layer thicker than that of the second thin-film transistor (320) used as a switching thin-film transistor. Accordingly, among the thin-film transistors placed in the display area (DA), the first thin-film transistor (350) used as a driving thin-film transistor to supply current to the light-emitting element (400) may include a gate insulating layer thicker than that of the second thin-film transistor (320) used as a switching thin-film transistor.

[0181] The thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the second gate electrode (324). For example, as shown in FIG. 3, the gate insulating layer stacked between the first gate electrode (354) and the first semiconductor pattern (351) of the first thin-film transistor (350) may be formed as a stacked structure of the second gate insulating layer (115) and the third gate insulating layer (116). Also, the gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) may also be made of the third gate insulating layer (116).

[0182] The first gate electrode (354) and the second gate electrode (324) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof. Additionally, the first gate electrode (354) and the second gate electrode (324) may be formed of the same material and may be placed on the same layer.

[0183] A second interlayer insulating layer (117) may be formed on the first gate electrode (354), the second gate electrode (324), and the third gate insulating layer (116). The second interlayer insulating layer (117) may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx) based material or a multilayer thereof.

[0184] A contact hole for exposing a third semiconductor pattern (361) of a third thin-film transistor (360) can be formed by etching the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), the second buffer layer (114), the first interlayer insulating layer (113), and the first gate insulating layer (112). Accordingly, a contact hole exposing the third source region (361S) and the third drain region (361D) of the third semiconductor pattern (361) can be formed.

[0185] Additionally, the second interlayer insulating layer (117), the third gate insulating layer (116), and the second gate insulating layer (115) can be etched to form a contact hole for exposing the first semiconductor pattern (351) of the first thin-film transistor (350). Thus, a contact hole can be formed to expose the third source region (361S) and the third drain region (361D) of the third semiconductor pattern (361).

[0186] Additionally, the second interlayer insulating layer (117) and the third gate insulating layer (116) can be etched to form a contact hole for exposing the second semiconductor pattern (321) of the second thin-film transistor (320). Thus, a contact hole can be formed to expose the second source region (321S) and the second drain region (321D) of the second semiconductor pattern (321).

[0187] On the second interlayer insulating layer (117), the first source electrode (352) and first drain electrode (353) of the first thin-film transistor (350), the second source electrode (322) and second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (362) and third drain electrode (363) of the third thin-film transistor (360) may be disposed.

[0188] The first source electrode (352) and the first drain electrode (353) of the first thin-film transistor (350) can be connected to the first source region (351S) and the first drain region (351D) of the first semiconductor pattern (351) through contact holes formed in the second interlayer insulating layer (117), the third gate insulating layer (116), and the second gate insulating layer (115).

[0189] The second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320) can be connected to the second source region (321S) and the second drain region (321D) of the second semiconductor pattern (321) through contact holes formed in the second interlayer insulating layer (117) and the third gate insulating layer (116).

[0190] The third source electrode (362) and the third drain electrode (363) of the third thin-film transistor (360) can be connected to the third source region (361S) and the third drain region (361D) of the third semiconductor pattern (361) through contact holes formed in the second interlayer insulating layer (117), the third gate insulating layer (116), the second gate insulating layer (115), the second buffer layer (114), the first interlayer insulating layer (113), and the first gate insulating layer (112).

[0191] The first source electrode (352) and first drain electrode (353) of the first thin-film transistor (350), the second source electrode (322) and second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (362) and third drain electrode (363) of the third thin-film transistor (360) may be formed of the same material and may be placed on the same layer. Furthermore, they may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or alloys thereof.

[0192] A first protective layer (118) may be formed on the first source electrode (352) and first drain electrode (353) of the first thin-film transistor (350), the second source electrode (322) and second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (362) and third drain electrode (363) of the third thin-film transistor (360).

[0193] A contact hole may be formed in the first protective layer (118) to expose the first drain electrode (353) of the first thin-film transistor (350). However, it is not limited thereto, and a contact hole may be formed in the first protective layer (118) to expose the first source electrode (352) of the first thin-film transistor (350). The first protective layer (118) may be an organic material layer. For example, the first protective layer (118) may be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. As another example, the first protective layer (118) may be composed of a single layer or multiple layers thereof of inorganic materials such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0194] The auxiliary electrode (180) may be disposed on the first protective layer (118). The auxiliary electrode (180) may be connected to the first drain electrode (353) of the first thin-film transistor (350) through a contact hole of the first protective layer (118). The auxiliary electrode (180) may electrically connect the first thin-film transistor (350) and the first electrode (410) of the light-emitting element (400). The auxiliary electrode (180) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. The auxiliary electrode (180) may be formed of the same material as the second source electrode (352) and the first drain electrode (353) of the first thin-film transistor (350).

[0195] The second protective layer (119) may be disposed on the auxiliary electrode (180) and the first protective layer (118). And, as shown in FIG. 3, a contact hole may be formed in the second protective layer (119) to expose the auxiliary electrode (180). The second protective layer (119) may be an organic material layer. For example, the second protective layer (119) may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0196] A first electrode (410) of a light-emitting element (400) may be disposed on the second protective layer (119). The first electrode (410) may be electrically connected to an auxiliary electrode (180) through a contact hole formed in the second protective layer (119). Thus, the first electrode (410) may be electrically connected to a first thin-film transistor (326) by being connected to an auxiliary electrode (180) through a contact hole formed in the second protective layer (119).

[0197] The first electrode (410) may be formed as a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film may be made of a material with a relatively high work function value, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The opaque conductive film may be formed as a single layer or multilayer structure including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the first electrode (410) may have a transparent conductive film, an opaque conductive film, and a transparent conductive film formed sequentially. However, it is not limited thereto, and for example, a transparent conductive film and an opaque conductive film may be formed sequentially.

[0198] Since the display device according to the embodiment of the present specification is a top emission display device, the first electrode (410) may be an anode electrode. In the case where the display device is bottom emission, the first electrode (410) disposed on the second protective layer (119) may be a cathode electrode.

[0199] A bank layer (120) may be disposed on the first electrode (410) and the second protective layer (119). An opening may be formed in the bank layer (120) to expose the first electrode (410). Since the bank layer (120) can define a light-emitting area of ​​the display device, it may also be called a pixel defining film. A spacer (121) may be further disposed on the bank layer (120). And, a light-emitting layer (420) of a light-emitting element (400) may be further disposed on the first electrode (410).

[0200] The light-emitting layer (420) can be formed on the first electrode (410) in the order of a hole layer (HL), a light-emitting material layer (EML), and an electron layer (EL), or in reverse order.

[0201] In addition, the light-emitting layer (420) may have a first light-emitting layer and a second light-emitting layer with a charge generation layer (CGL) in between. In this case, either of the first light-emitting layer and the second light-emitting layer may generate blue light, and the other of the first light-emitting layer and the second light-emitting layer may generate yellow-green light, thereby generating white light through the first light-emitting layer and the second light-emitting layer. The white light generated through the first light-emitting layer and the second light-emitting layer may be incident on a color filter located above the light-emitting layer to create a color image. As another example, a color image may be created by generating color light corresponding to each subpixel in each light-emitting layer without a separate color filter. That is, the light-emitting layer of the red (R) subpixel may generate red light, the light-emitting layer of the green (G) subpixel may generate green light, and the light-emitting layer of the blue (B) subpixel may generate blue light.

[0202] Referring to FIG. 3, a second electrode (430) of a light-emitting element (400) may be further disposed on the light-emitting layer (420). The second electrode (430) may overlap with the first electrode (410) with the light-emitting layer (420) in between. In a display device according to an embodiment of the present specification, the second electrode (430) may be a cathode electrode.

[0203] A sealing member (500) that inhibits moisture penetration may be further disposed on the second electrode (430). The sealing member (500) may include a first sealing layer (510), a second sealing layer (520), and a third sealing layer (530). The second sealing layer (520) may include a material different from the first sealing layer (510) and the third sealing layer (530). For example, the first sealing layer (510) and the third sealing layer (530) may be inorganic insulating films formed of inorganic insulating materials, and the second sealing layer (520) may be an organic insulating film formed of organic insulating materials. The first sealing layer (510) of the sealing member (500) may be disposed on the second electrode (430). And, the second sealing layer (520) may be disposed on the first sealing layer (510). Additionally, the third bag layer (530) can be placed on the second bag layer (520).

[0204] The first sealing layer (510) and the third sealing layer (530) of the sealing member (500) may be formed from an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The second sealing layer (520) of the sealing member (500) may be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0205] FIG. 4 is a cross-sectional view of a display device according to another embodiment of the present specification. FIG. 4 is described with reference to FIG. 2, and redundant descriptions are omitted or briefly described. For example, the substrate (210), buffer layer (211), first gate insulating layer (212), second gate insulating layer (213), interlayer insulating layer (214), protective layer (215), bank layer (216), spacer (217), first metal pattern (610), second metal pattern (620), third metal pattern (630), light-emitting element (400), encapsulation member (500), and first thin-film transistor (350) are substantially identical. Accordingly, redundant descriptions of the configuration of FIG. 4, which is substantially identical to FIG. 2, are omitted or briefly described.

[0206] Referring to FIG. 4, a display device (40) according to another embodiment of the present specification may include a substrate (210), a buffer layer (211), a first gate insulating layer (212), a second gate insulating layer (213), an interlayer insulating layer (214), a protective layer (215), a bank layer (216), a spacer (217), a first metal pattern (610), a second metal pattern (620), a third metal pattern (630), a light-emitting element (400), an encapsulation member (500), a first thin-film transistor (350), a second thin-film transistor (320), and a third thin-film transistor (330).

[0207] Referring to FIG. 4, the substrate (210) of the display device (40) may have a display area (DA) composed of a plurality of pixels. Each pixel may be composed of a first thin-film transistor (350) and a second thin-film transistor (320). The first thin-film transistor (350) and the second thin-film transistor (320) may include an oxide semiconductor material. However, they are not limited thereto, and may additionally include thin-film transistors including a polysilicon (Poly-Si) material as in FIG. 1. FIG. 4 describes the second thin-film transistor (320), which is a switching thin-film transistor, and the first thin-film transistor (350), which is a driving thin-film transistor, among the thin-film transistors made of oxide semiconductors.

[0208] In the substrate (210), a non-display area (NDA) may be disposed adjacent to a display area (DA). Additionally, a driving circuit for driving pixels of the display area (DA) may be disposed in the non-display area (NDA). The driving circuit may include a third thin-film transistor (330). The third thin-film transistor (330) disposed in the non-display area (NDA) may include an oxide semiconductor.

[0209] The first thin-film transistor (350) and the second thin-film transistor (320) placed in the display area (DA) may be configured as negative-type transistors (n-type TFTs). Additionally, the third thin-film transistor (330) placed in the non-display area (NDA) may be configured as a negative-type transistor (n-type TFT).

[0210] The substrate (210) can support various components of the display device (40). The substrate (210) may be made of glass or a plastic material having flexibility. If the substrate (210) is made of a plastic material, for example, it may be made of polyimide (PI).

[0211] A display device (40) according to an embodiment of the present specification may form a first metal pattern (610), a second metal pattern (620), and a third metal pattern (630) on a substrate (210) to prevent performance degradation due to moisture penetration.

[0212] Additionally, the first metal pattern (610), the second metal pattern (620), and the third metal pattern (630) may serve as a light-blocking mechanism to prevent external light from entering the semiconductor patterns of the first thin-film transistor (350), the second thin-film transistor (320), and the third thin-film transistor (330).

[0213] The first metal pattern (610) can overlap with the first semiconductor pattern (351) of the first thin-film transistor (350). Also, the second metal pattern (620) can overlap with the second semiconductor pattern (321) of the second thin-film transistor (320). Additionally, the third metal pattern (630) can overlap with the third semiconductor pattern (331) of the third thin-film transistor (330).

[0214] A buffer layer (211) may be formed on a first metal pattern (610), a second metal pattern (620), and a third metal pattern (630). The buffer layer (211) may consist of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof. According to an embodiment of the present specification, the buffer layer (211) may be formed as a multilayer of silicon oxide (SiOx) and silicon nitride (SiNx) formed alternately.

[0215] In this way, when the buffer layer (211) is composed of a multilayer formed alternately of silicon oxide (SiOx) and silicon nitride (SiNx), the uppermost layer and the lowermost layer of the buffer layer (211) may be formed of silicon oxide (SiOx) material.

[0216] In FIG. 4, the first metal pattern (610), the second metal pattern (620), and the third metal pattern (630) are shown formed on the buffer layer (211), but are not limited thereto. For example, if the buffer layer (211) is formed in multiple layers, the first metal pattern (610), the second metal pattern (620), and the third metal pattern (630) may be located between the buffer layer (211) which is composed of multiple layers.

[0217] The first thin-film transistor (350) can be placed on the buffer layer (211). The first thin-film transistor (350) can be placed in the display area (DA) of the display device (40).

[0218] A first thin-film transistor (350) placed in a display area (DA) may include a first semiconductor pattern (351), a first gate electrode (354), a first source electrode (352), and a first drain electrode (353).

[0219] On the buffer layer (211), a first semiconductor pattern (351) of a first thin-film transistor (350), a second semiconductor pattern (321) of a second thin-film transistor (320), and a third semiconductor pattern (331) of a third thin-film transistor (330) may be formed. The first semiconductor pattern (351) and the second semiconductor pattern (321) may be placed in a display area (DA), and the third semiconductor pattern (331) may be placed in a non-display area (NDA). Additionally, the first semiconductor pattern (351) may be placed to overlap with the first metal pattern (610), and the second semiconductor pattern (321) may overlap with the second metal pattern (620). Furthermore, the third semiconductor pattern (351) may overlap with the third metal pattern (630). The first semiconductor pattern (351), the second semiconductor pattern (321), and the third semiconductor pattern (331) may be oxide semiconductor patterns made of oxide semiconductors.

[0220] A first thin-film transistor (350) including an oxide semiconductor may be a driving thin-film transistor that supplies current to a light-emitting element (400). A second thin-film transistor (320) including an oxide semiconductor may be a switching thin-film transistor. A third thin-film transistor (330) including an oxide semiconductor may be applied as a semiconductor pattern of a thin-film transistor for a gate signal of a display device (200). The thin-film transistor for a gate signal may be a switching thin-film transistor that performs a switching function.

[0221] Referring to FIG. 4, the first semiconductor pattern (351), the second semiconductor pattern (321), and the third semiconductor pattern (331) can be placed on the same layer.

[0222] A first gate insulating layer (212) may be formed on the first semiconductor pattern (351), the second semiconductor pattern (321), the third semiconductor pattern (331), and the buffer layer (211). The first gate insulating layer (212) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0223] Additionally, a second gate electrode (324) and a third gate electrode (334) may be formed on the first gate insulating layer (212). The second gate electrode (324) placed in the display area (DA) may overlap with the second channel area (321C) of the second semiconductor pattern (321) with the first gate insulating layer (212) in between. Furthermore, the third gate electrode (334) placed in the non-display area (NDA) may overlap with the third channel area (331C) of the third semiconductor pattern (331) with the first gate insulating layer (212) in between.

[0224] The gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) placed in the display area (DA) may be composed of the first gate insulating layer (212). Additionally, the gate insulating layer stacked between the third gate electrode (334) and the third semiconductor pattern (331) of the third thin-film transistor (330) placed in the non-display area (NDA) may be composed of the first gate insulating layer (212).

[0225] Referring to FIG. 4, a second gate insulating layer (213) may be formed on a second gate electrode (324), a third gate electrode (334), and a first gate insulating layer (212). The second gate insulating layer (213) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0226] A first gate electrode (354) may be formed on the second gate insulating layer (213). The first gate electrode (354) placed in the display area (DA) may overlap with the first channel area (351C) of the first semiconductor pattern (351) with the first gate insulating layer (212) and the second gate insulating layer (213) in between.

[0227] In this way, the gate insulating layer stacked between the first gate electrode (354) and the first semiconductor pattern (351) of the first thin-film transistor (350) placed in the display area (DA) can be formed as a stacked structure of the first gate insulating layer (212) and the second gate insulating layer (213). And,

[0228] Accordingly, the thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the third semiconductor pattern (331) and the second gate electrode (324) and the third gate electrode (334). The thicker the gate insulating layer, the less current leakage can be reduced. Therefore, a thin-film transistor including a thick gate insulating layer can be utilized as a driving thin-film transistor for controlling the amount of current. Since the switching thin-film transistor performs a switching function that controls turn-on or turn-off, current leakage does not pose a significant problem. Therefore, the thickness of the gate insulating layer of the thin-film transistor performing the switching function can be formed thinner than the thickness of the gate insulating layer of the thin-film transistor used as a driving thin-film transistor.

[0229] As such, when the thickness of the gate insulating layer of a thin-film transistor is formed thicker, there is an advantage in that the amount of current leakage is reduced, allowing for effective control of the current amount. However, as the thickness of the gate insulating layer of the thin-film transistor is formed thicker, the mobility decreases, and the characteristics of the switching function may deteriorate. Conversely, when the thickness of the gate insulating layer of the thin-film transistor is formed relatively thinner, there is an advantage in that the mobility increases, thereby improving the characteristics of the switching function. However, as the thickness of the gate insulating layer is formed thinner, the amount of current leakage increases, and the characteristics of the current amount control function may deteriorate. Therefore, in the display device (40) according to the embodiment of the present specification, the thickness of the gate insulating layer can be designed differently depending on the characteristics of the thin-film transistor. Accordingly, the display device (40) may include thin-film transistors having different mobilities.

[0230] Referring to FIG. 4, the first thin-film transistor (350) used as a driving thin-film transistor may include a gate insulating layer thicker than the third thin-film transistor (330) which performs a switching function as a gate signal thin-film transistor. Also, among the thin-film transistors placed in the display area (DA), the first thin-film transistor (350) used as a driving thin-film transistor that supplies current to the light-emitting element (400) may include a gate insulating layer thicker than the second thin-film transistor (320) used as a switching thin-film transistor.

[0231] Accordingly, the thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the third semiconductor pattern (331) and the third gate electrode (334). Additionally, the thickness of the gate insulating layer located between the first semiconductor pattern (351) and the first gate electrode (354) may be greater than the thickness of the gate insulating layer located between the second semiconductor pattern (321) and the second gate electrode (324). For example, as shown in FIG. 4, the gate insulating layer stacked between the first gate electrode (354) and the first semiconductor pattern (351) of the first thin-film transistor (350) may be formed as a stacked structure of the first gate insulating layer (212) and the second gate insulating layer (213). Additionally, the gate insulating layer stacked between the third gate electrode (334) and the third semiconductor pattern (331) of the third thin-film transistor (330) may be composed of the first gate insulating layer (212). Furthermore, the gate insulating layer stacked between the second gate electrode (324) and the second semiconductor pattern (321) of the second thin-film transistor (320) may also be composed of the first gate insulating layer (212).

[0232] The first gate electrode (354), the second gate electrode (324), and the third gate electrode (334) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0233] An interlayer insulating layer (214) may be formed on the first gate electrode (354) and the second gate insulating layer (213).

[0234] The interlayer insulating layer (214) may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx)-based material or multiple layers thereof.

[0235] A contact hole can be formed to expose the first semiconductor pattern (351) of the first thin-film transistor (350), the second semiconductor pattern (321) of the second thin-film transistor (320), and the third semiconductor pattern (331) of the third thin-film transistor (330) by etching the interlayer insulating layer (214), the second gate insulating layer (213), and the first gate insulating layer (212).

[0236] On the interlayer insulating layer (214), the first source electrode (352) and the first drain electrode (352) of the first thin-film transistor (350), the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330) may be disposed.

[0237] The first source electrode (352) and the first drain electrode (353) of the first thin-film transistor (350) can be connected to the first source region (351S) and the first drain region (351D) of the first semiconductor pattern (351) through contact holes formed in the interlayer insulating layer (214), the second gate insulating layer (213), and the first gate insulating layer (212).

[0238] And, the second source electrode (322) and the second drain electrode (323) of the second thin-film transistor (320) can be connected to the second source region (321S) and the second drain region (321D) of the second semiconductor pattern (321) through contact holes formed in the interlayer insulating layer (214), the second gate insulating layer (213), and the first gate insulating layer (212).

[0239] Additionally, the third source electrode (332) and the third drain electrode (333) of the third thin-film transistor (330) can be connected to the third source region (331S) and the third drain region (331D) of the third semiconductor pattern (331) through contact holes formed in the interlayer insulating layer (214), the second gate insulating layer (213), and the first gate insulating layer (212).

[0240] The first source electrode (352) and first drain electrode (353) of the first thin-film transistor (350), the second source electrode (322) and second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (332) and third drain electrode (333) of the third thin-film transistor (330) may be disposed in contact with the upper surface of the interlayer insulating layer (214). Furthermore, they may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0241] A protective layer (215) may be formed on the first source electrode (352) and first drain electrode (353) of the first thin-film transistor (350), the second source electrode (322) and second drain electrode (323) of the second thin-film transistor (320), and the third source electrode (332) and third drain electrode (333) of the third thin-film transistor (330).

[0242] A contact hole may be formed in the protective layer (215) to expose the first drain electrode (353) of the first thin-film transistor (350). However, it is not limited thereto, and a contact hole may be formed in the protective layer (215) to expose the first source electrode (352) of the first thin-film transistor (350). The protective layer (215) may be a single layer or a multilayer made of organic material. For example, the protective layer (215) may be a single layer or a multilayer formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. As another example, the protective layer (215) may be composed of a single layer of inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx) material, or a multilayer thereof. Additionally, the protective layer (215) may be a multilayer composed of an inorganic material layer and an organic material layer.

[0243] A first electrode (410) of a light-emitting element (400) may be disposed on a protective layer (215). The first electrode (410) may be electrically connected to a first thin-film transistor (350) through a contact hole formed in the protective layer (215).

[0244] The first electrode (410) can be formed into a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency.

[0245] A bank layer (216) may be disposed on the first electrode (410) and the protective layer (215). An opening may be formed in the bank layer (216) to expose the first electrode (410). Since the bank layer (216) can define a light-emitting area of ​​the display device, it may also be called a pixel defining film. A spacer (217) may be further disposed on the bank layer (216). And, a light-emitting layer (420) of a light-emitting element (400) may be further disposed on the first electrode (410).

[0246] The light-emitting layer (420) can be formed on the first electrode (410) in the order of a hole layer (HL), a light-emitting material layer (EML), and an electron layer (EL), or in reverse order.

[0247] A second electrode (430) of the light-emitting element (400) may be further disposed on the light-emitting layer (420). The second electrode (430) may overlap with the first electrode (410) with the light-emitting layer (420) in between.

[0248] A sealing member (500) that inhibits moisture penetration may be further disposed on the second electrode (430).

[0249] A display device according to an embodiment of the present specification may be described as follows.

[0250] A display device according to an embodiment of the present specification may include a substrate comprising a display area and a non-display area adjacent to the display area; a first semiconductor pattern disposed in the display area of ​​the substrate and comprising a first polysilicon; a first gate electrode overlapping with the first semiconductor pattern with a first gate insulating layer in between; and a first source electrode and a first drain electrode connected to the first semiconductor pattern; a second semiconductor pattern disposed in the display area of ​​the substrate and comprising a first oxide semiconductor; a second gate electrode overlapping with the second semiconductor pattern with a second gate insulating layer and a third gate insulating layer in between; and a second source electrode and a second drain electrode connected to the second semiconductor pattern; and a third thin-film transistor disposed in the non-display area of ​​the substrate and comprising a third semiconductor pattern comprising a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern with a third gate insulating layer in between, and a third source electrode and a third drain electrode connected to the third semiconductor pattern.

[0251] According to an embodiment of the present specification, a fourth thin-film transistor may further include a fourth semiconductor pattern comprising a second polysilicon disposed in a non-display area of ​​a substrate, a fourth gate electrode overlapping with the fourth semiconductor pattern with a first gate insulating layer in between, and a fourth source electrode and a fourth drain electrode connected to the fourth semiconductor pattern.

[0252] According to an embodiment of the present specification, a second gate insulating layer may not be located between the third semiconductor pattern and the third gate electrode.

[0253] According to an embodiment of the present specification, a third semiconductor pattern may be disposed on a second gate insulating layer.

[0254] According to an embodiment of the present specification, the second thin-film transistor is a driving thin-film transistor, and the first thin-film transistor may be a switching thin-film transistor.

[0255] According to an embodiment of the present specification, the third thin-film transistor and the fourth thin-film transistor may be thin-film transistors for gate signals that perform a switching function.

[0256] A display device according to an embodiment of the present specification may include a substrate comprising a display area and a non-display area adjacent to the display area; a first semiconductor pattern disposed in the display area of ​​the substrate and comprising a first oxide semiconductor; a first gate electrode overlapping with the first semiconductor pattern with a second gate insulating layer and a third gate insulating layer in between; and a first source electrode and a first drain electrode connected to the first semiconductor pattern; a second semiconductor pattern disposed in the display area of ​​the substrate and comprising a second oxide semiconductor; a second gate electrode overlapping with the second semiconductor pattern with a third gate insulating layer in between; and a second source electrode and a second drain electrode connected to the second semiconductor pattern; and a third thin-film transistor disposed in the non-display area of ​​the substrate and comprising a third semiconductor pattern comprising polysilicon, a third gate electrode overlapping with the third semiconductor pattern with a first gate insulating layer in between, and a third source electrode and a third drain electrode connected to the third semiconductor pattern. According to an embodiment of the present specification, the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer may be located on different layers.

[0257] According to an embodiment of the present specification, the second gate insulating layer is located on the first gate insulating layer, and the third gate insulating layer may be located on the second gate insulating layer.

[0258] According to an embodiment of the present specification, a second gate insulating layer may not be located between the second semiconductor pattern and the second gate electrode.

[0259] According to an embodiment of the present specification, the first thin-film transistor may be a driving thin-film transistor, and the second thin-film transistor may be a switching thin-film transistor. Additionally, the third thin-film transistor may be a thin-film transistor for a gate signal that performs a switching function.

[0260] Those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0261] 100: Display device 110: Substrate 111: First buffer layer 112: First gate insulating layer 113: First interlayer insulation layer 114: Second buffer layer 115: Second gate insulating layer 116: Third gate insulating layer 117: Second interlayer insulation layer 118: First protective layer 119: Second Protection Layer 120: Bank layer 121: Spacer 310: First thin-film transistor 320: Second thin-film transistor 330: Third thin-film transistor 340: 4th thin-film transistor 400: Light-emitting element 500: Bag missing 140: First storage capacitor 150: Second storage capacitor 160: First connecting electrode 170: Second connecting electrode 180: Auxiliary electrode

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