An op-amp circuit and op-amp compensating circuit to amplify an input signal with a high slew rate

Abstract

An operational amplifier compensation circuit that assists in the amplification operation of the operational amplifier of the present disclosure may include a first transistor, a second transistor, and a first load, the activation status of which is determined according to the signal level difference between the input signal and the output signal of the operational amplifier, and when the first transistor is activated, a first signal amplification circuit that generates a first gate voltage amplified for the voltage level difference between the input signal and the output signal based on the internal resistance of the second transistor and the resistance of the first load, and a third transistor that generates a first compensation current based on the amplified first gate voltage and provides the first compensation current to the operational amplifier.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to an operational amplifier circuit and an operational amplifier compensation circuit, and more specifically, to an operational amplifier circuit and an operational amplifier compensation circuit having a high slew rate. Background Technology

[0002] Display devices are widely used in smartphones, laptop computers, monitors, etc., and the display device is equipped with a display panel that displays an image, and multiple pixels are arranged on the display panel. As the pixels are driven by data signals provided by a display driver IC, an image is realized on the display panel.

[0003] At this time, the display driving circuit must shorten the settling time of the source amplifier to drive the pixels at a high refresh rate. Settling time is the time required for the output signal to enter a range where it has a stable state value in relation to the input signal; shortening the settling time can improve not only the frame rate but also the resolution of the display. The problem to be solved

[0004] The problem that the technical concept of the present disclosure aims to solve is to provide an efficient operational amplifier circuit and an operational amplifier compensation circuit for reducing settling time. means of solving the problem

[0005] According to one embodiment of the present disclosure, an operational amplifier compensation circuit that assists in the amplification operation of an operational amplifier may include a first transistor, a second transistor, and a first load, the activation status of which is determined according to the signal level difference between an input signal and an output signal of the operational amplifier; a first signal amplification circuit that, when the first transistor is activated, generates a first gate voltage amplified for the voltage level difference between the input signal and the output signal based on the internal resistance of the second transistor and the resistance of the first load; and a third transistor that generates a first compensation current based on the amplified first gate voltage and provides the first compensation current to the operational amplifier.

[0006] In addition, an operational amplifier circuit that compensates for the slew rate of an output signal may include an amplifier circuit that outputs an amplified signal in which the signal level of the input signal is amplified based on the input signal and the output signal of the operational amplifier circuit, an output circuit that generates the output signal based on the amplified signal, and a compensation circuit that receives the amplified signal and provides a compensation current generated based on the amplified signal to at least one of the amplifier circuit and the output circuit, wherein the output circuit generates the output signal in which the signal level transition time is reduced by receiving the compensation current.

[0007] An operational amplifier compensation circuit that assists in the amplification operation of an operational amplifier according to another embodiment may be characterized by including a first input transistor that generates a first current based on the signal level difference between an input signal and an output signal of the operational amplifier, a first current mirror circuit connected to the source or drain terminal of the first input transistor and outputting a second current at a level equal to the level of the first current, a second current mirror circuit that generates a third current by receiving the second current, and an additional compensation circuit that includes a first additional compensation transistor and a first load, and when the first input transistor is activated, provides an additional compensation current generated based on the internal resistance of the first additional compensation transistor and the resistance of the first load to the second current mirror circuit, and provides a compensation current that is the sum of the additional compensation current and the third current to the operational amplifier. Effects of the invention

[0008] An operational amplifier compensation circuit according to an embodiment of the present disclosure receives an input signal and an output signal, and can generate an amplified compensation current by generating a gate voltage amplified by the magnitude of the internal resistance of the transistor and the resistance of the load with respect to the level difference between the input signal and the output signal. Accordingly, the slew rate of the operational amplifier can be increased by supplying the amplified compensation current to the operational amplifier.

[0009] The effects obtainable from the exemplary embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the description below. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram illustrating an input circuit, an amplifier circuit, and an output circuit constituting an operational amplifier according to one embodiment. FIG. 2 is a block diagram illustrating an operational amplifier and an operational amplifier compensation circuit according to an embodiment of the present disclosure. FIG. 3 is a graph showing an output signal having a high slew rate generated for an input signal according to a comparative example and an embodiment of the present disclosure. FIG. 4 is a circuit diagram illustrating an operational amplifier according to one embodiment. FIG. 5 is a circuit diagram illustrating an operational amplifier compensation circuit according to one embodiment. Figures 6a and 6b are graphs showing the output signal and gate voltage of an operational amplifier circuit with and without a source degeneracy transistor. FIG. 7 is a circuit diagram illustrating an operational amplifier compensation circuit further including a source degeneracy transistor according to one embodiment. FIGS. 8A and FIGS. 8B are circuit diagrams illustrating a transistor that is activated when the voltage level of an input signal transitions in an embodiment of FIG. 7, and the resulting current flow. FIG. 9 is a circuit diagram illustrating a circuit diagram in which an additional compensation circuit is combined according to another embodiment. FIGS. 10a and FIGS. 10b are circuit diagrams illustrating a transistor that is activated when the voltage level of an input signal transitions in an embodiment of FIG. 9, and the current flow that follows. FIG. 11 is a circuit diagram illustrating an operational amplifier compensation circuit including a source degeneracy transistor according to another embodiment. FIG. 12 is an example of a hardware configuration illustrating a display driving circuit and display panel regions according to one embodiment. FIG. 13 is a circuit diagram illustrating an operational amplifier compensation circuit further including an enable transistor according to one embodiment. FIG. 14 is a circuit diagram illustrating an additional compensation circuit including an enable transistor according to another embodiment. FIG. 15 is a timing diagram illustrating an example in which the duty of an enable signal is determined corresponding to different display panel areas in an embodiment of FIG. 12. FIG. 16 is a block diagram illustrating a display device according to an embodiment of the present disclosure. Specific details for implementing the invention

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0012] FIG. 1 is a block diagram illustrating an input circuit, an amplifier circuit, and an output circuit constituting an operational amplifier according to one embodiment.

[0013] Referring to FIG. 1, the operational amplifier (10) may include an input circuit (110), an amplification circuit (120), and an output circuit (130).

[0014] The input circuit (110) receives an input signal (IN) input to the operational amplifier (10) and an output signal (OUT) output from the operational amplifier (10), and can output a differential current based on the voltage difference between the input signal (IN) and the output signal (OUT). For example, the input circuit (110) can receive the input signal (IN) through a first input terminal configured as a positive terminal (+) and can receive the output signal (OUT) through a second input terminal configured as a negative terminal (-).

[0015] The amplification circuit (120) can receive a differential current generated by the input circuit (110) and may include a plurality of resistor elements for generating an amplified voltage signal based on the differential current. For example, the amplification circuit (120) may include a plurality of passive or active resistor elements having high resistance values ​​and may output an amplified signal having a voltage level obtained by multiplying the resistance value by the level of the differential current. According to one embodiment, the amplification circuit (120) may output an amplified signal through a plurality of output terminals, and the output circuit (130) may receive an amplified signal through a plurality of input terminals.

[0016] The output circuit (130) can generate an output signal (OUT) amplified with respect to an input signal (IN) by receiving an amplification signal. For example, the output circuit (130) may include a capacitor that stores a charge received as an amplification signal, and can generate an output signal (OUT) based on the charge stored in the capacitor.

[0017] When the operational amplifier (10) generates an output signal (OUT) from an input signal (IN) based on the input circuit (110), the amplifier circuit (120), and the output circuit (130), a delay may occur during the process of charging or discharging the capacitor. Due to this delay, a delay time may be required until the output signal (OUT) for the input signal (IN) enters a range having a stable state value, and the delay time that occurs at this time may be referred to as the settling time.

[0018] FIG. 2 is a block diagram illustrating an operational amplifier (10) and an operational amplifier compensation circuit (20) according to an embodiment of the present disclosure.

[0019] Referring to FIG. 2, an operational amplifier circuit according to one embodiment of the present disclosure may further include an operational amplifier compensation circuit (20) for reducing delay. The operational amplifier compensation circuit (20) can reduce the delay of the operational amplifier (10) by providing a compensation current (Icomp) to at least one of the amplifier circuit (120) and the output circuit (130). For example, the operational amplifier compensation circuit (20) may provide a compensation current (Icomp) to a capacitor included in either the output circuit (130) or the amplifier circuit (120), and the rate at which charge is charged or discharged to the capacitor may be determined by the compensation current (Icomp).

[0020] An operational amplifier compensation circuit (20) according to an embodiment of the present disclosure can receive an input signal (IN) input to an operational amplifier (10) and an output signal (OUT) output by the operational amplifier (10), and can generate a compensation current (Icomp) based on the difference in signal levels between the input signal (IN) and the output signal (OUT). At this time, the level of the compensation current (Icomp) may be proportional to a voltage level in which the resistance value of a component included in the operational amplifier compensation circuit (20) is multiplied by the drain current level generated according to the difference in voltage levels between the input signal (IN) and the output signal (OUT). That is, the operational amplifier compensation circuit (20) of the present disclosure can provide a compensation current (Icomp) with a current level amplified based on the drain current to the operational amplifier (10). Hereinafter, the amplification level of the compensation current (Icomp) with respect to the drain current may be referred to as the gain level.

[0021] According to one embodiment, the operational amplifier compensation circuit (20) may further receive an amplification signal (AMP) distinct from the input signal (IN) and output signal (OUT) from the operational amplifier (10), and may adjust the gain level for the drain current based on the amplification signal (AMP). For example, the operational amplifier compensation circuit (20) may further include a source degeneration transistor whose activation level is determined according to the level of the amplification signal (AMP), and when the source degeneration transistor is activated, the gain level becomes smaller, but a stable compensation current (Icomp) and output signal (OUT) can be generated.

[0022] FIG. 3 is a graph showing an output signal (OUT) having a high slew rate generated for an input signal (IN) according to a comparative example and an embodiment of the present disclosure.

[0023] Referring to FIG. 3, an operational amplifier circuit further comprising the operational amplifier compensation circuit (20) of the present disclosure may have a higher slew rate compared to an operational amplifier circuit without the operational amplifier compensation circuit (20) of a comparative embodiment. An operational amplifier circuit of the present disclosure having a higher slew rate compared to a comparative embodiment may have a shorter time required until the output signal (OUT) has a steady-state value. That is, an operational amplifier circuit of the present disclosure has a smaller settling time (t) compared to a comparative embodiment. setl Can have ).

[0024] When the display device is driven at high speed, the operational amplifier circuit of the comparative example has a settling time (t) compared to the embodiment of the present disclosure. setl Since the margin of ) becomes insufficient, it is not possible to generate an output signal (OUT) with an accurate voltage level. Settling time (t setl The margin of ) is the settling time (t) for one high-speed driven cycle. setlIt may refer to the remaining time excluding ). For example, when the display device is driven at 144Hz or higher, the comparative example is the settling time (t setl The margin of ) becomes insufficient, and a reduction in display brightness equivalent to the voltage difference that has not reached the stable state value may have to be accepted, or it may remain as a potential defect factor.

[0025] In contrast, the operational amplifier circuit of the present disclosure generates a compensation current by means of an operational amplifier compensation circuit (20), thereby allowing the display device to be driven at high speed, and the settling time (t setl The margin of ) can be sufficient to stably output an image of the target brightness.

[0026] FIG. 4 is a circuit diagram illustrating an operational amplifier (10) according to one embodiment.

[0027] Referring to FIG. 4, an operational amplifier (10) according to one embodiment may include an input circuit (110), an amplification circuit (120), and an output circuit (130) composed of a plurality of transistors. The gate terminal, source terminal, and drain terminal of each transistor may be organically connected to other transistors to output an output signal (OUT) and at least one amplification signal (AMP1 and AMP2).

[0028] The input circuit (110) may be a folded cascode OTA (Operational Transconductance Amplifier). The folded cascode OTA functions to convert a voltage difference into current and transmit it. The input circuit (110) includes PMOS transistors (MP1, MP2, MP3) and NMOS transistors (MN1, MN2, MN3), and receives an input signal (IN) and an output signal (OUT) to output a differential current.

[0029] The input circuit (110) includes a first differential input circuit composed of transistors MP1 and MP2 and a second differential input circuit composed of transistors MN1 and MN2. Transistors MP3 and MN3 can perform the role of supplying bias current to the first differential input circuit and the second differential input circuit.

[0030] Transistor MP3 can apply a constant bias current to the first differential input circuit according to the first bias voltage (VB1), and transistor MN3 can apply a constant bias current to the second differential input circuit according to the second bias voltage (VB2).

[0031] Each of the first differential input circuit and the second differential input circuit separates the bias current according to the differential input signal and outputs the separated current as a differential current to the amplifier circuit (120). That is, the input circuit (110) plays the role of converting the voltage difference between the input signal (IN) and the output signal (OUT) into a current and outputting it to the amplifier circuit (120).

[0032] The amplifier circuit (120) may include current mirror circuits composed of PMOS transistors (MP4, MP5, MP6, MP7, MP8, and MP9) and NMOS transistors (MN4, MN5, MN6, MN7, MN8, and MN9). The amplifier circuit (120) may perform the function of amplifying the differential current input from the input circuit (110). The NMOS transistors (MN4, MN5, MN6, and MN7) of the amplifier circuit (120) are connected to a first differential input circuit, and the PMOS transistors (MP4, MP5, MP6, and MP7) are connected to a second differential input circuit.

[0033] Transistors MP4 and MP5 are connected in series between the power supply voltage (VDD) and transistors MP8 and MN8, and transistors MP6 and MP7 are connected in series between the power supply voltage (VDD) and transistors MP9 and MN9. Transistors MN4 and MN5 are connected in series between the ground terminal and transistors MP8 and MN8, and transistors MN6 and MN7 are connected in series between the ground terminal and transistors MP9 and MN9. A third bias voltage (VB3) is applied to the respective gate terminals of transistors MP4 and MP6, and a fourth bias voltage (VB4) is applied to the respective gate terminals of transistors MN4 and MN6.

[0034] PMOS transistor MP8 and NMOS transistor MN8 are connected in parallel to receive the fifth bias voltage (VB5) and the sixth bias voltage (VB6), respectively, and can generate a constant static bias current. PMOS transistor MP9 and NMOS transistor MN9 are connected in parallel to receive the seventh bias voltage (VB7) and the eighth bias voltage (VB9), respectively, and can generate a constant static bias current.

[0035] The output circuit (130) is composed of capacitors (C1, C2), a PMOS transistor MP10, and an NMOS transistor MN10. The output circuit (130) receives the amplified voltage output from transistors MP9 and MN9 and generates amplified signals (AMP1, AMP2). The capacitors (C1, C2) serve to stabilize the frequency characteristics of the output signal (OUT). That is, the capacitors (C1, C2) serve to prevent the output signal (OUT) from oscillating.

[0036] The source terminal of transistor MP10 of the output circuit (130) is connected to the power supply voltage (VDD), the gate terminal is connected to the drain terminal of transistor MP6, and the drain terminal is connected to the terminal where the output signal (OUT) is generated and the drain terminal of transistor MN10. The source terminal of transistor MN10 is connected to the ground terminal, the gate terminal is connected to the source terminal of transistor MN6, and the drain terminal is connected to the terminal where the output signal (OUT) is generated and the drain terminal of transistor MP10.

[0037] The input circuit (110) described above is biased by DC bias voltages (VB1, VB2), so the slew rate can be expressed as Equation 1.

[0038]

[0039] Here, I TAIL represents the DC bias current value generated by the DC bias voltage (VB1 or VB2), and C c represents the capacitance value of the capacitor (C1 or C2) of the output circuit (130).

[0040] At this time, according to an embodiment of the present disclosure, the slew rate of the operational amplifier (10) receiving the compensation current (Icomp) can be expressed as Equation 2.

[0041]

[0042] Here, Icomp may represent a compensation current (Icomp) generated by an operational amplifier compensation circuit (20). That is, the slew rate of the output signal (OUT) generated by receiving the compensation current (Icomp) may have a larger value compared to the slew rate of the output signal (OUT) generated without receiving the compensation current (Icomp).

[0043] FIG. 5 is a circuit diagram illustrating an operational amplifier compensation circuit (20a) according to one embodiment.

[0044] Referring to FIG. 5, the operational amplifier compensation circuit (20a) of the present disclosure may include a first partial compensation circuit composed of a first transistor (TR1) to a sixth transistor (TR6) and a second partial compensation circuit composed of a seventh transistor (TR7) to a twelfth transistor (TR12). The first partial compensation circuit may be controlled so that when the voltage level difference of the output signal (OUT) to the input signal (IN) is greater than the threshold voltage of the first transistor (TR1), the operational amplifier (10) provides a compensation current (Icomp) to the operational amplifier compensation circuit, and the second partial compensation circuit may be controlled so that when the voltage level difference of the input signal (IN) to the output signal (OUT) is greater than the threshold voltage of the seventh transistor (TR7), the operational amplifier (10) provides a compensation current (Icomp). That is, the first partial compensation circuit can operate when the input signal (IN) transitions from any low level to any high level, and the second partial compensation circuit can operate when the input signal (IN) transitions from any high level to any low level.

[0045] The first partial compensation circuit may include a first transistor (TR1), a first signal amplification circuit (21a), and a third transistor (TR3). The first transistor (TR1) may be activated when the voltage level difference between the input signal (IN) and the output signal (OUT) is greater than the threshold voltage. When the first transistor (TR1) is activated, the first transistor (TR1) may generate a drain current proportional to the voltage level difference between the input signal (IN) and the output signal (OUT).

[0046] The first signal amplification circuit (21a) may include a second transistor (TR2), a fifth transistor (TR5), and a sixth transistor (TR6). The gate terminal and drain terminal of the sixth transistor (TR6) are connected to the drain terminal of the first transistor (TR1), so that the sixth transistor (TR6) can be self-biased. The gate terminal of the second transistor (TR2) can be connected to the gate terminal of the sixth transistor (TR6), and the second transistor (TR2) and the sixth transistor (TR6) can be configured as a current mirror. Accordingly, the drain current of the first transistor (TR1) can be radiated to the drain current of the second transistor (TR2).

[0047] The fifth transistor (TR5) included in the first signal amplification circuit (21a) is connected to the drain terminal of the second transistor (TR2) and can operate as a load having a variable resistance value according to the voltage magnitude of the first bias signal (Bias1) by receiving the first bias signal (Bias1) through the gate terminal. In the operational amplifier compensation circuit (20a) of the present disclosure, the load located between the drain terminal of the second transistor (TR2) and the ground terminal may be an active load composed of transistors as in the embodiment of FIG. 5, but is not limited thereto and may be composed of a passive load.

[0048] The second transistor (TR2) of the first signal amplification circuit (21a) according to one embodiment can be operated as a common source amplifier with the fifth transistor (TR5) as a load. The voltage gain of the common source amplifier can be expressed by Equation 3.

[0049]

[0050] Here, Rd may be the resistance value of a load connected to the output terminal of a common source amplifier, and ro may be the internal resistance of a transistor. Referring to FIG. 5, since the load connected to the output terminal of the common source amplifier is the fifth transistor (TR5), Rd may be the internal resistance value of the fifth transistor (TR5), and ro may be the internal resistance value of the second transistor (TR2). That is, the output voltage value of the first signal amplification circuit (21a) may have an amplified voltage value based on the internal resistance of the second transistor (TR2) and the internal resistance of the fifth transistor (TR5) with respect to the difference between the input signal (IN) and the output signal (OUT).

[0051] The output voltage of the second transistor (TR2) is input to the gate terminal of the third transistor (TR3), thereby controlling the third transistor (TR3). The magnitude of the compensation current (Icomp) generated at the drain terminal of the third transistor (TR3) can be determined by the gate voltage input to the gate terminal. That is, since the voltage value is amplified based on the internal resistance of the second transistor (TR2) and the internal resistance of the fifth transistor (TR5), the current value of the compensation current (Icomp) can also have a value amplified from the drain current of the first transistor (TR1).

[0052] According to one embodiment, the third transistor (TR3) can generate a pull compensation current (Icomp) that sinks the current of the operational amplifier (10). Referring to FIG. 4, when the first amplification signal (AMP1) is at any low level, the transistor MP10 is activated so that the voltage level of the output signal (OUT) rises. Since the speed at which the second capacitor is charged from the power supply voltage (VDD) is increased by the pull compensation current (Icomp), the slew rate when the output signal (OUT) rises can be increased.

[0053] The second partial compensation circuit may include a seventh transistor (TR7), a second signal amplification circuit, and a ninth transistor (TR9). The seventh transistor (TR7) may be activated when the voltage level difference of the input signal (IN) to the output signal (OUT) is greater than the threshold voltage. When the seventh transistor (TR7) is activated, the seventh transistor (TR7) may generate a drain current proportional to the voltage level difference between the input signal (IN) and the output signal (OUT).

[0054] The second signal amplification circuit may include an eighth transistor (TR8), an eleventh transistor (TR11), and a twelfth transistor (TR12). The gate terminal and drain terminal of the twelfth transistor (TR12) are connected to the drain terminal of the seventh transistor (TR7), thereby allowing the twelfth transistor (TR12) to be self-biased. The gate terminal of the eighth transistor (TR8) may be connected to the gate terminal of the twelfth transistor (TR12), and the eighth transistor (TR8) and the twelfth transistor (TR12) may be configured as a current mirror. Accordingly, the drain current of the seventh transistor (TR7) may be generated as the drain current of the eighth transistor (TR8).

[0055] The 11th transistor (TR11) included in the second signal amplification circuit is connected to the drain terminal of the 8th transistor (TR8) and receives the second bias signal (Bias2) through the gate terminal, thereby being a load having a variable resistance value depending on the voltage magnitude of the second bias signal (Bias2). In the operational amplifier compensation circuit (20a) of the embodiment of the present disclosure, the load located between the drain terminal of the 11th transistor (TR11) and the ground terminal may be an active load composed of transistors as shown in FIG. 5, but is not limited thereto and may be composed of a passive load.

[0056] The second signal amplification circuit according to one embodiment can be operated as a common source amplifier, similar to the first signal amplification circuit (21a). Referring to FIG. 5, since the load connected to the output terminal of the common source amplifier is the 11th transistor (TR11), the voltage gain of the common source amplifier can be proportional to the parallel resistance value of the internal resistance of the 11th transistor (TR11) and the internal resistance of the 8th transistor (TR8). That is, the output voltage value of the second signal amplification circuit can have an amplified voltage value based on the internal resistance of the 7th transistor (TR7) and the internal resistance of the 11th transistor (TR11) with respect to the difference between the input signal (IN) and the output signal (OUT).

[0057] The output voltage of the eighth transistor (TR8) is input to the gate terminal of the ninth transistor (TR9), thereby allowing the ninth transistor (TR9) to be controlled. The magnitude of the compensation current (Icomp) generated at the drain terminal of the ninth transistor (TR9) can be determined by the gate voltage input to the gate terminal. That is, since the voltage value is amplified based on the internal resistance of the eighth transistor (TR8) and the internal resistance of the eleventh transistor (TR11), the current value of the compensation current (Icomp) can also have a value amplified from the drain current of the seventh transistor (TR7).

[0058] According to one embodiment, the ninth transistor (TR9) can generate a push compensation current (Icomp) that supplies current to the operational amplifier (10). Referring to FIG. 4, when the second amplification signal (AMP2) is at any high level, transistor MN10 is activated so that the voltage level of the output signal (OUT) is lowered. Since the speed of discharge from the first capacitor to the ground terminal is accelerated by the push compensation current (Icomp), the slew rate when the output signal (OUT) is falling can be increased.

[0059] Figures 6a and 6b are graphs showing the output signal (OUT) and gate voltage of an operational amplifier circuit with and without a source degenerate transistor.

[0060] According to the embodiment of FIG. 5, the operational amplifier compensation circuit (20) can transition the voltage level of the output signal (OUT) at a high slew rate by a common source amplifier having a large voltage gain. At this time, referring to FIG. 6a, the output signal (OUT) generated by the large voltage gain may be a signal that is overshooting the target level, and after the level transition, the voltage level difference between the input signal (IN) and the output signal (OUT) may be greater than the threshold voltage.

[0061] For example, in FIG. 6a, when the voltage level of the input signal (IN) is greater than the threshold voltage value than the voltage level of the output signal (OUT), the first partial compensation circuit is activated so that the input signal (IN) can transition from any low level to any high level. At this time, when the operational amplifier compensation circuit (20) amplifies the compensation current (Icomp) with a large voltage gain, an output signal (OUT) that is excessively amplified with respect to the voltage level of the input signal (IN) may be generated, and when the voltage level of the output signal (OUT) becomes greater than the threshold voltage value compared to the voltage level of the input signal (IN), the second partial compensation circuit may be activated. Accordingly, the operational amplifier circuit is lowered again, thereby generating an unstable output signal (OUT).

[0062] Referring to FIG. 6b, the amplified gate voltage generated at the gate node (GN) of the third transistor (TR3) in the first partial compensation circuit of FIG. 5 may generate multiple peak voltages during the logic level transition process. For example, when the output signal (OUT) drops as the second partial compensation circuit is activated, the voltage level of the input signal (IN) may again become greater than the voltage level of the output signal (OUT), and at this time, a peak voltage may again be generated at the gate node (GN) of the third transistor (TR3).

[0063] In contrast, when a source degeneration transistor is included in the operational amplifier compensation circuit (20), the operational amplifier circuit can generate a stable output signal (OUT) by controlling the voltage gain. Below, an embodiment in which the operational amplifier circuit can generate a stable output signal (OUT) by means of a source degeneration transistor will be described.

[0064] FIG. 7 is a circuit diagram illustrating an operational amplifier compensation circuit (20b) that further includes a source degenerate transistor according to one embodiment.

[0065] Referring to FIG. 7, the first partial compensation circuit (21b) of the operational amplifier compensation circuit (20b) may further include a fourth transistor (TR4) in the first partial compensation circuit (21a) according to the embodiment of FIG. 5. The fourth transistor (TR4) may be placed between the source terminal of the second transistor (TR2) and the power supply voltage (VDD), and the gate terminal of the fourth transistor (TR4) may receive a first amplification signal (AMP1) from the amplifier circuit (120). When activated, the fourth transistor (TR4) may be coupled to the source terminal of the second transistor (TR2) to lower the voltage gain of the common source amplifier and perform the role of a load that generates a stable output voltage. Hereinafter, the fourth transistor (TR4) may be referred to as a source degeneracy transistor.

[0066] When the fourth transistor (TR4) performs source degeneracy operation as a load, the voltage gain of the common source amplifier can be expressed as Equation 4.

[0067]

[0068] Here, Rs may be the internal resistance of the source degenerate transistor. That is, the output voltage value of the first signal amplification circuit (21b) according to the embodiment of FIG. 7 may have an amplified voltage value based on the internal resistance of the second transistor (TR2), the internal resistance of the fourth transistor (TR4), and the internal resistance of the fifth transistor (TR5) with respect to the difference between the input signal (IN) and the output signal (OUT). This may be a voltage value amplified smaller than that of the embodiment of FIG. 5, but the slewing of the operational amplifier (10) can be operated stably and excessive non-linearity can be mitigated.

[0069] A source degenerate transistor according to one embodiment of the present disclosure can receive an amplification signal (AMP) that is distinct from the input signal (IN) and output signal (OUT) of an operational amplifier (10) through a gate terminal, and the activation status can be determined according to the voltage level of the amplification signal (AMP).

[0070] Referring to FIG. 4, the operational amplifier (10) can drive the output circuit (130) by shifting the voltage level of the amplification signal (AMP) when the difference in voltage levels between the input signal (IN) and the output signal (OUT) is large. Since the timing at which the output circuit (130) is driven by the shifting of the voltage level of the amplification signal (AMP) is similar to the timing at which the operational amplifier compensation circuit (20b) of the present disclosure is driven, the operational amplifier compensation circuit (20b) can receive the amplification signal (AMP) from the operational amplifier (10) and determine whether to drive the first partial compensation circuit (21b) and the second partial compensation circuit. Below, the transistors that are activated when the first partial compensation circuit (21b) and the second partial compensation circuit are driven and the current flow therefrom will be described.

[0071] FIGS. 8A and FIGS. 8B are circuit diagrams illustrating a transistor that is activated when the voltage level of an input signal (IN) transitions in an embodiment of FIG. 7, and the current flow that follows.

[0072] Referring to FIG. 8a, when the input signal (IN) transitions from any low level to any high level but the output signal (OUT) is at any low level, the transistors of the first partial compensation circuit (21b) may be activated. The first partial compensation circuit (21b) may include a first transistor (TR1) to a sixth transistor (TR6) and may receive a first amplification signal (AMP1) of any low level and a first bias signal (Bias1) of any level from the operational amplifier (10).

[0073] When the input signal (IN) transitions to an arbitrary high level, the output signal (OUT) remains at an arbitrary low level, and the first transistor (TR1) can be activated. Additionally, the fourth transistor (TR4) can be activated by receiving the first amplifier signal (AMP1) at an arbitrary low level at its gate terminal. Accordingly, the internal resistance of the second transistor (TR2) and the internal resistance of the fifth transistor (TR5) are connected in parallel to form an output resistance of large impedance, and the common source amplifier can have a large voltage gain proportional to the output resistance.

[0074] The output voltage of the common source amplifier, amplified by a voltage gain based on the voltage level difference between the input signal (IN) and the output signal (OUT), is input to the gate terminal of the third transistor (TR3), and the third transistor (TR3) generates a compensation current (Icomp) proportional to the output voltage of the common source amplifier.

[0075] Referring to FIG. 8b, when the input signal (IN) transitions from any high level to any low level and the output signal (OUT) is at any high level, the transistors of the second partial compensation circuit may be activated. The second partial compensation circuit may include a seventh transistor (TR7) to a twelfth transistor (TR12) and may receive a second amplifier signal (AMP2) of any high level and a second bias signal (Bias2) of any level from the operational amplifier (10).

[0076] When the input signal (IN) transitions to an arbitrary low level, the output signal (OUT) remains at an arbitrary high level, and the seventh transistor (TR7) can be activated. Additionally, the tenth transistor (TR10) can be activated by receiving a second amplifier signal (AMP2) of an arbitrary high level at its gate terminal. Accordingly, the internal resistance of the eighth transistor (TR8) and the internal resistance of the eleventh transistor (TR11) are connected in parallel to form an output resistance of large impedance, and the common source amplifier can have a large voltage gain proportional to the output resistance.

[0077] The output voltage of the common source amplifier, amplified by a voltage gain based on the voltage level difference between the input signal (IN) and the output signal (OUT), is input to the gate terminal of the ninth transistor (TR9), and the ninth transistor (TR9) generates a compensation current (Icomp) proportional to the output voltage of the common source amplifier.

[0078] FIG. 9 is a circuit diagram illustrating a circuit diagram in which an additional compensation circuit (23) is combined according to another embodiment.

[0079] Referring to FIG. 9, the operational amplifier compensation circuit (20c) may provide a compensation current (Icomp) to the operational amplifier (10) by further combining an additional compensation circuit (23) with a plurality of current mirror circuits. According to one embodiment, the operational amplifier compensation circuit (20c) may generate a compensation current (Icomp) by adding an additional compensation current (Iacomp) generated by the additional compensation circuit (23) to a third current (I3) generated based on the current mirror circuits.

[0080] The additional compensation circuit (23) may be composed of a first additional compensation circuit and a second additional compensation circuit, and a plurality of transistors included in the first additional compensation circuit are activated when the input signal (IN) transitions from any low level to any high level, and a plurality of transistors included in the second additional compensation circuit may be activated when the input signal (IN) transitions from any high level to any low level.

[0081] According to one embodiment, the additional compensation circuit (23) may be activated depending on the voltage levels of the first bias signal (Bias1) and the second bias signal (Bias2). When the additional compensation circuit (23) is activated, the operational amplifier compensation circuit (20c) may provide a compensation current (Icomp) with an additional compensation current (Iacomp) added to the operational amplifier (10). Conversely, when the additional compensation circuit (23) is deactivated, the operational amplifier compensation circuit (20c) does not add an additional compensation current (Iacomp), and only the drain current of the first input transistor (ITR1) or the second input transistor (ITR2), generated based on the voltage level difference between the input signal (IN) and the output signal (OUT), may be provided to the operational amplifier (10).

[0082] In the following, embodiments are described in which a compensation current (Icomp) is provided to an operational amplifier (10) by activating the first additional compensation circuit and the second additional compensation circuit.

[0083] FIGS. 10a and FIGS. 10b are circuit diagrams illustrating a transistor that is activated when the voltage level of an input signal (IN) transitions in an embodiment of FIG. 9, and the current flow that follows.

[0084] Referring to FIG. 10a, the first partial additional compensation circuit may include a first additional compensation transistor (ACTR1), a first source degenerate transistor (SDTR1), a first active load transistor (ALTR1), and a second additional compensation transistor (ACTR2). The gate terminal of the first additional compensation transistor (ACTR1) may be connected to a first node (N1) where the drain terminal of the first input transistor (ITR1) is located. When the first input transistor (ITR1) is activated, the first additional compensation transistor (ACTR1) may be activated by receiving a first signal (Sig1) of any low level through its gate terminal.

[0085] The first active load transistor (ALTR1) is connected to the drain terminal of the first additional compensation transistor (ACTR1) and can operate as a load having a variable resistance value according to the voltage magnitude of the first bias signal (Bias1) by receiving the first bias signal (Bias1) through the gate terminal. The load connected to the drain terminal of the first additional compensation transistor (ACTR1) of the present disclosure may be an active load composed of transistors as shown in FIG. 9, but is not limited thereto and may be composed of a passive load.

[0086] The first source degeneracy transistor (SDTR1) can be activated by receiving a first amplification signal (AMP1) of any low level at its gate terminal. When the first source degeneracy transistor (SDTR1) is activated, it operates as a load connected to the source terminal of the first additional compensation transistor (ACTR1), thereby lowering the voltage gain of the common source amplifier of the first partial additional compensation circuit, but enabling the provision of a stable output voltage.

[0087] The voltage gain of a common source amplifier composed of a first additional compensation transistor (ACTR1), a first source degeneracy transistor (SDTR1), and a first active load transistor (ALTR1) may be proportional to the parallel resistance value of the internal resistances of the first additional compensation transistor (ACTR1) and the first active load transistor (ALTR1), and inversely proportional to the internal resistance value of the first source degeneracy transistor (SDTR1). The common source amplifier may provide an output voltage amplified by the voltage gain to the gate terminal of the second additional compensation transistor (ACTR2) with respect to the voltage level difference between the input signal (IN) and the output signal (OUT).

[0088] The second additional compensation transistor (ACTR2) can generate an additional compensation current (Iacomp) proportional to the output voltage input through the gate terminal, and can generate a compensation current (Icomp) by sinking the generated additional compensation current (Iacomp) to the third node (N3). At this time, the generated compensation current (Icomp) may be a full compensation current (Icomp) that sinks current from the operational amplifier (10), and the time for the voltage level of the output signal (OUT) of the operational amplifier (10) to transition can be reduced by the full compensation current (Icomp).

[0089] Referring to FIG. 10b, the second additional compensation circuit may include a third additional compensation transistor (ACTR3), a second source degeneracy transistor (SDTR2), a second active load transistor (ALTR2), and a fourth additional compensation transistor (ACTR4). The gate terminal of the third additional compensation transistor (ACTR3) may be connected to a second node (N2) where the drain terminal of the second input transistor (ITR2) is located. When the second input transistor (ITR2) is activated, the third additional compensation transistor (ACTR3) may be activated by receiving any high-level second signal (Sig2).

[0090] The second active load transistor (ALTR2) is connected to the drain terminal of the third additional compensation transistor (ACTR3) and can operate as a load having a variable resistance value according to the voltage magnitude of the second bias signal (Bias2) by receiving the second bias signal (Bias2) through the gate terminal. The load connected to the drain terminal of the third additional compensation transistor (ACTR3) of the present disclosure may be an active load composed of transistors as shown in FIG. 9, but is not limited thereto and may be composed of a passive load.

[0091] The second source degeneracy transistor (SDTR2) can be activated by receiving any high-level second amplification signal (AMP2) at its gate terminal. When the second source degeneracy transistor (SDTR2) is activated, it operates as a load connected to the source terminal of the third additional compensation transistor (ACTR3), thereby lowering the voltage gain of the common source amplifier included in the third additional compensation circuit (23) but enabling it to provide a stable output voltage.

[0092] The voltage gain of a common-source amplifier composed of a third additional compensation transistor (ACTR3), a second source degeneracy transistor (SDTR2), and a second active load transistor (ALTR2) may be proportional to the internal resistance values ​​of the third additional compensation transistor (ACTR3) and the second active load transistor (ALTR2), and inversely proportional to the internal resistance value of the second source degeneracy transistor (SDTR2). The common-source amplifier may provide an output voltage amplified by the voltage gain to the gate terminal of the fourth additional compensation transistor (ACTR4) for the voltage level difference between the input signal (IN) and the output signal (OUT).

[0093] The fourth additional compensation transistor (ACTR4) can generate an additional compensation current (Iacomp) proportional to the output voltage input through the gate terminal, and can generate a compensation current (Icomp) by providing the generated additional compensation current (Iacomp) to the fourth node (N4). At this time, the generated compensation current (Icomp) may be a push compensation current (Icomp) that provides current to the operational amplifier (10), and the time for the voltage level of the output signal (OUT) of the operational amplifier (10) to transition can be reduced by the push compensation current (Icomp).

[0094] FIG. 11 is a circuit diagram illustrating an operational amplifier compensation circuit (20d) including a source degeneracy transistor according to another embodiment.

[0095] Referring to FIG. 11, an operational amplifier compensation circuit (20d) according to another embodiment generates a compensation current (Icomp) with a current level equal to the first current (I1) generated by the first input transistor (ITR1), and at this time, the operational amplifier (10) can be controlled to generate a stable output signal (OUT) by a first source degeneracy transistor (SDTR1) connected between the first current mirror circuit (22_1) and the second current mirror circuit (22_2).

[0096] When the input signal (IN) has a voltage level above the threshold voltage compared to the output signal (OUT), the first input transistor (ITR1) is activated to generate a first current (I1) at the drain terminal. A first current mirror circuit (22_1) composed of transistors of the same specifications can generate a second current (I2) with the same value as the first current (I1) and transmit it to a second current mirror circuit (22_2) and a first source degeneracy transistor (SDTR1). The second current mirror circuit (22_2) can receive a portion of the second current (I2) by the first source degeneracy transistor (SDTR1).

[0097] The second current mirror circuit (22_2) can generate a compensation current (Icomp) based on a portion of the second current (I2) received from the first current mirror circuit (22_1). The compensation current (Icomp) generated by the second current mirror circuit (22_2) may be a full compensation current (Icomp) that sinks current from the operational amplifier (10), and the operational amplifier (10) can transition the logic level of the output signal (OUT) at a faster speed by the full compensation current (Icomp).

[0098] When the output signal (OUT) has a voltage level above the threshold voltage compared to the input signal (IN), the second input transistor (ITR2) is activated to generate a compensation current (Icomp) by the second compensation transistor (CTR2). At this time, the second source degeneracy transistor (SDTR2), which is placed between the third current mirror circuit (22_3) and the fourth current mirror circuit (22_4), can be activated by receiving a first amplification signal (AMP1) of a logic high level through its gate terminal.

[0099] The third current mirror circuit (22_3) can transfer the drain current generated by the second input transistor (ITR2) to the fourth current mirror circuit (22_4) and the second source degenerate transistor. The fourth current mirror circuit (22_4) can generate a compensation current (Icomp) based on the current received from the third current mirror circuit (22_3). The compensation current (Icomp) generated by the fourth current mirror circuit (22_4) may be a push compensation current (Icomp) that provides current to the operational amplifier (10), and the operational amplifier (10) may transition the logic level of the output signal (OUT) at a faster speed by the push compensation current (Icomp).

[0100] FIG. 12 is an example of a hardware configuration illustrating a display driving circuit (1000) and display panel regions according to one embodiment.

[0101] Referring to FIG. 12, the display panel (2000) can be divided into multiple regions, and each region can be configured to be located at a certain distance from the display driving circuit (1000). The further each region of the display panel (2000) is from the display driving circuit (1000), the greater the delay time, and accordingly, the operational amplifier (10) must be controlled so that the output signal (OUT) can reach a stable state value in a shorter time. In addition, when the operational amplifier (10) transmits the output signal (OUT) to a region far from the display driving circuit (1000), it may need to amplify the input signal (IN) with a greater gain value compared to when it transmits the output signal (OUT) to a nearby region.

[0102] For example, the first display panel area (AREA1) of the display panel (2000) is the area furthest from the display driving circuit (1000), and may require more delay time than the nth display panel area (AREAn) (n is a natural number) of the display panel (2000), and may require amplifying the input signal (IN) with a larger gain value.

[0103] In the following FIGS. 13 to 15, embodiments are described in which the operational amplifier compensation circuit (20) controls the amplification level of the output signal (OUT) by driving the operational amplifier compensation circuit (20) with an enable signal (EN) of a different duty corresponding to each area of ​​the display panel (2000).

[0104] FIG. 13 is a circuit diagram illustrating an operational amplifier compensation circuit (20e) further including an enable transistor according to one embodiment.

[0105] Referring to FIG. 13, the operational amplifier compensation circuit (20e) may further include a first enable transistor (ENTR1) and a second enable transistor (ENTR2) in the operational amplifier compensation circuit (20e) according to the embodiment of FIG. 7. For example, the first enable transistor (ENTR1) may be placed between the drain terminal of the fifth transistor (TR5) and the ground voltage, and through the gate terminal, the inverted signal of the enable signal ( It can receive ). The second enable transistor (ENTR2) can be placed between the drain terminal of the first transistor (TR11) and the power supply voltage (VDD), and can receive the enable signal (EN) through its gate terminal.

[0106] When the enable signal (EN) is at a logic high level, both the first enable transistor (ENTR1) and the second enable transistor (ENTR2) are deactivated, and when the enable signal (EN) is at a logic low level, both the first enable transistor (ENTR1) and the second enable transistor (ENTR2) can be enabled. When the first enable transistor (ENTR1) is enabled, a logic low level gate signal is input to the gate terminal of the third transistor (TR3), thereby deactivating the third transistor (TR3) so that it does not generate a compensation current (Icomp). Likewise, when the second enable transistor (ENTR2) is enabled, a logic high level gate signal is input to the gate terminal of the ninth transistor (TR9), thereby deactivating the ninth transistor (TR9) so that it does not generate a compensation current (Icomp).

[0107] That is, the operational amplifier compensation circuit (20e) according to FIG. 13 can be controlled so as not to generate a compensation current (Icomp) when receiving a logic low level enable signal (EN), and can be controlled to generate a compensation current (Icomp) only when receiving a logic high level enable signal (EN).

[0108] FIG. 14 is a circuit diagram illustrating an additional compensation circuit (23) including an enable transistor according to another embodiment.

[0109] Referring to FIG. 14, the additional compensation circuit (23a) may further include a first enable transistor (ENTR1) and a second enable transistor (ENTR2) in the additional compensation circuit (23) according to the embodiment of FIG. 9. The first enable transistor (ENTR1) may be placed between the gate terminal and the ground terminal of the second additional compensation transistor (ACTR2) in the first partial additional compensation circuit, and the second enable transistor (ENTR2) may be placed between the gate terminal and the power supply voltage (VDD) of the fourth additional compensation transistor (ACTR4) in the second partial additional compensation circuit. The first enable transistor (ENTR1) receives the inverted signal of the enable signal ( It can receive ), and the second enable transistor (ENTR2) can receive the enable signal (EN) through its gate terminal.

[0110] When the enable signal (EN) is at a logic high level, both the first enable transistor (ENTR1) and the second enable transistor (ENTR2) are deactivated, and when the enable signal (EN) is at a logic low level, both the first enable transistor (ENTR1) and the second enable transistor (ENTR2) can be enabled. When the first enable transistor (ENTR1) is enabled, a logic low level gate signal is input to the gate terminal of the second additional compensation transistor (ACTR2), thereby deactivating the second additional compensation transistor (ACTR2) so that it does not generate a compensation current (Icomp). Likewise, when the second enable transistor (ENTR2) is enabled, a logic high level gate signal is input to the gate terminal of the fourth additional compensation transistor (ACTR4), thereby deactivating the fourth additional compensation transistor (ACTR4) so ​​that it does not generate a compensation current (Icomp).

[0111] FIG. 15 is a timing diagram illustrating an example in which the duty of an enable signal (EN) is determined corresponding to different display panel areas in an embodiment of FIG. 12.

[0112] Referring to FIGS. 12 and FIGS. 15, when the display driving circuit (1000) provides an output signal (OUT) corresponding to a display panel area by line, each display panel area can be time-divided according to the HSYNC signal to provide an output signal (OUT). For example, after providing an output signal (OUT) to a first display panel area (AREA1) in one line, an output signal (OUT) can be provided to a second display panel area to provide an output signal (OUT) up to an nth display panel area (AREAn).

[0113] Referring to FIG. 15, when the HSYNC signal transitions from a logic high level to a logic low level, the SOUT_EN signal that activates the operational amplifier (10) can be transitioned to a logic high level. When SOUT_EN becomes a logic high level, the operational amplifier (10) is activated and can amplify from the input signal (IN) to the output signal (OUT). Before the operational amplifier (10) is activated by the logic high level SOUT_EN, the display driving circuit (1000) can transition the enable signal (EN) to a logic high level by the SLATCH signal. While receiving the logic high level enable signal (EN), the operational amplifier compensation circuit (20) can provide a compensation current (Icomp) to the operational amplifier (10).

[0114] At this time, the display device of the present disclosure may generate an enable signal (EN) with a large duty cycle to reduce delay when providing an output signal (OUT) to a display panel area located far from the display driving circuit (1000). In contrast, since a small delay time is required for a display area located close to it, an enable signal (EN) with a small duty cycle may be generated.

[0115] Referring to FIGS. 12 and 15, when the display driving circuit (1000) provides an output signal (OUT) to a first display panel area (AREA1) located far from the display driving circuit (1000), it can maintain an enable signal (EN) in a logic high level state for a long time, and when providing an output signal (OUT) to an nth display panel area (AREAn) located close to the display driving circuit (1000), it can maintain the enable signal (EN) for a short time. Accordingly, the display driving circuit (1000) of the present disclosure can adaptively perform the operation of the operational amplification compensation circuit (20) according to the distance between each display panel area and the display driving circuit (1000), and can perform the operational amplification operation power efficiently.

[0116] FIG. 16 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0117] Referring to FIG. 16, the display device includes a display panel (DP) and a driving circuit (DRVC).

[0118] A display panel (DP) displays images in frames. The display panel (DP) can be implemented as an LCD (liquid crystal display), LED (light emitting diode) display, OLED (organic LED) display, AMOLED (active-matrix OLED) display, and flexible display, and can also be implemented as other types of flat panel displays. For the convenience of explanation, the display panel (DP) will be described as a liquid crystal display panel.

[0119] A display panel (DP) comprises gate lines (GL1~GLb) arranged in a row direction, source lines (SL1~SLa) arranged in a column direction, and pixels (PX) formed at the intersection points of the gate lines (GL1~GLb) and source lines (SL1~SLa). In a liquid crystal display panel, a pixel (PX) includes, as illustrated, a thin-film transistor (TFT), a liquid crystal capacitor (Clc) and a storage capacitor (Cst) connected to the drain of the thin-film transistor (TFT). A common voltage (Vcom) may be connected to the other end of the liquid crystal capacitor (Clc) and the storage capacitor (Cst). When gate lines (GL1~GLb) are scanned sequentially, the thin-film transistor (TFT) of the pixel (PX) connected to the selected gate line is turned on, and then a grayscale voltage corresponding to the pixel data is applied to each source line (SL1~SLa). The grayscale voltage is applied to the liquid crystal capacitor (Clc) and storage capacitor (Cst) through the thin-film transistor (TFT) of the corresponding pixel (PX), and the liquid crystal and storage capacitors (Clc, Cst) are driven to enable display operation.

[0120] The driving circuit (DRVC) may include a source driver (1100), a gate driver (1200), a timing controller (1300), and a voltage generator (1400). The driving circuit (DRVC) may be implemented as a single semiconductor chip or multiple semiconductor chips.

[0121] The timing controller (1300) receives image data (IDATA) and a plurality of control signals, such as a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), a clock signal (DCLK), and a data enable signal (DE), from an external device (e.g., a host device (not shown)), and can generate a first control signal (CNT1) and a second control signal (CNT2) for controlling a gate driver (1200) and a source driver (1100) based on the plurality of control signals. The first control signal (CNT1) may be a control signal for the source driver (1100), and the second control signal (CNT2) may be a control signal for the gate driver (1200).

[0122] Additionally, the timing controller (1300) can generate image data (IDATA) received from the outside as data (DATA) with the format converted to match the interface specifications with the source driver (1100) and transmit it to the source driver (1100).

[0123] The gate driver (1200) and the source driver (1100) can drive the pixels (PX) of the display panel (DP) according to the first and second control signals (CNT1, CNT2) provided by the timing controller (300).

[0124] The source driver (1100) drives the source lines (SL1~SLa) of the display panel (DP) based on the first control signal (CNT1). The source driver (1100) can output a grayscale voltage corresponding to pixel data to the source lines (SL1~SLa) of the display panel (DP).

[0125] Meanwhile, the source driver (1100) may be formed as a single chip or may be formed as a plurality of source driving chips (SD1~SDn). At this time, the timing controller (1300) may divide image data (IDATA) received from the outside into a plurality of source data (SDATA1~SDATAn) according to the area of ​​the display panel (DP) driven by each source driving chip (SD1~SDn), and transmit the divided plurality of source data (SDATA1~SDATAn) to the corresponding source driving chips (SD1~SDn). In addition, when transmitting the plurality of source data (SDATA1~SDATAn), the timing controller (1300) may also transmit a control signal corresponding to each of the source driving chips (SD1~SDn).

[0126] The source driver (1100) of the present disclosure may include an operational amplifier (10), and the operational amplifier (10) may amplify an input signal (IN) and provide an output signal (OUT) to a display panel (DP). At this time, the operational amplifier compensation circuit (20) may supply a compensation current (Icomp) to the operational amplifier (10), and the slew rate of the output signal (OUT) is increased by the compensation current (Icomp), and the settling time (t) at which the logic level transitions is increased. setl ) can be shortened. Since embodiments in which the operational amplifier compensation circuit (20) of the present disclosure generates a compensation current (Icomp) have been described previously, a detailed description will be omitted.

[0127] The gate driver (1200) scans the gate lines (GL1 to GLb) of the display panel (DP) in sequence. The gate driver (1200) activates the selected gate line by applying a gate-on voltage (GON) to the selected gate line, and the source driver (1100) outputs a grayscale voltage corresponding to the pixels (PX) connected to the activated gate line. Accordingly, the display panel (DP) can display an image in units of one horizontal line, that is, one row at a time.

[0128] The voltage generator (1400) generates voltages used in the driving circuit (DRVC) and the display panel (DP). The voltage generator (1400) can generate a gate-on voltage (GON), a gate-off voltage (GOFF), a common voltage (Vcom), and a power supply voltage (VDD). The gate-on voltage (GON) and the gate-off voltage (GOFF) are provided to the gate driver (1200) and used to generate gate signals applied to the gate lines (G1 to GLb). The common voltage (Vcom) is provided commonly to the pixels (PX) of the display panel (DP). As illustrated, the common voltage (Vcom) can be provided to one end of the liquid crystal capacitor (Clc) and the storage capacitor (Cst).

[0129] A display device according to an embodiment of the present disclosure may be mounted on various electronic devices having an image display function. For example, the electronic device may include at least one of a television, a DVD (digital video disk) player, audio, a refrigerator, an air conditioner, a smartphone, a tablet PC (tablet personal computer), a mobile phone, a video phone, an e-book reader, a desktop PC (desktop personal computer), a laptop PC (laptop personal computer), a netbook computer, a PDA (personal digital assistant), a PMP (portable multimedia player), an MP3 player, a mobile medical device, a camera, or a wearable device (e.g., a head-mounted-device (HMD) such as electronic glasses, electronic clothing, an electronic bracelet, an electronic necklace, an electronic appcessory, an electronic tattoo, or a smart watch). In addition, the electronic device may include one of various medical devices, navigation devices, GPS receivers (global positioning system receivers), and ATMs (automatic teller's machines) of financial institutions. The electronic device may be a combination of one or more of the various devices mentioned above. In addition, the display device may be a flexible device.

[0130] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 An operational amplifier compensation circuit that assists the amplification operation of an operational amplifier, comprising: a first transistor whose activation is determined according to the signal level difference between an input signal and an output signal of the operational amplifier; a first signal amplification circuit including a second transistor and a first load, wherein when the first transistor is activated, the first signal amplification circuit generates a first gate voltage amplified for the voltage level difference between the input signal and the output signal based on the internal resistance of the second transistor and the resistance of the first load; and a third transistor that generates a first compensation current based on the amplified first gate voltage and provides the first compensation current to the operational amplifier, wherein the first signal amplification circuit includes a fourth transistor connected to one end of the second transistor, the activation of which is determined according to the voltage level of a first amplified signal of the operational amplifier that is distinct from the input signal and the output signal. Claim 2 An operational amplifier compensation circuit according to claim 1, wherein the first signal amplification circuit generates the amplified first gate voltage based on the internal resistance of the second transistor and the parallel resistance value of the first load. Claim 3 delete Claim 4 An operational amplifier compensation circuit according to claim 1, wherein the first signal amplification circuit generates the first gate voltage based on the internal resistance of the second transistor, the internal resistance of the first load, and the internal resistance of the fourth transistor when the fourth transistor is activated. Claim 5 An operational amplifier compensation circuit that assists the amplification operation of an operational amplifier, comprising: a first transistor whose activation is determined according to the signal level difference between an input signal and an output signal of the operational amplifier; a first signal amplification circuit comprising a second transistor and a first load, wherein when the first transistor is activated, the first signal amplification circuit generates a first gate voltage amplified for the voltage level difference between the input signal and the output signal based on the internal resistance of the second transistor and the resistance of the first load; and a third transistor that generates a first compensation current based on the amplified first gate voltage and provides the first compensation current to the operational amplifier, wherein the first load comprises a fifth transistor that receives a first bias voltage at its gate terminal and whose resistance level is determined according to the voltage value of the first bias voltage. Claim 6 An operational amplifier compensation circuit according to claim 1, wherein the first signal amplification circuit comprises a self-biased sixth transistor, the gate terminal of which is connected to the gate terminal of the second transistor. Claim 7 In claim 1, an operational amplifier compensation circuit comprising: a seventh transistor that is activated when the voltage level difference between the input signal and the output signal is a different level from the voltage level at which the first transistor is activated; a second signal amplification circuit comprising an eighth transistor and a second load, wherein when the seventh transistor is activated, the second gate voltage amplified for the voltage level difference between the input signal and the output signal is generated based on the internal resistance of the eighth transistor and the resistance of the second load; and a ninth transistor that generates a second compensation current based on the amplified second gate voltage and provides the second compensation current to the operational amplifier. Claim 8 An operational amplifier compensation circuit according to claim 7, wherein the second signal amplification circuit comprises a 10th transistor connected to one end of the 8th transistor, the activation status of which is determined according to the voltage level of the second amplification signal of the operational amplifier, which is distinguished from the input signal and the output signal. Claim 9 An operational amplifier compensation circuit according to claim 7, wherein the first transistor is composed of an NMOS transistor and the seventh transistor is composed of a PMOS transistor, wherein when the first transistor is activated, the third transistor generates a pull compensation current that sinks the current of the operational amplifier, and when the seventh transistor is activated, the ninth transistor generates a push compensation current that supplies current to the operational amplifier. Claim 10 An operational amplifier compensation circuit according to claim 7, further comprising: a first enable transistor that controls the first gate voltage such that the third transistor is deactivated when enabled, wherein the activation status is determined according to the logic state of the enable signal; and a second enable transistor that controls the second gate voltage such that the ninth transistor is deactivated when enabled, wherein the activation status is determined according to the logic state of the enable signal. Claim 11 An operational amplifier compensation circuit according to claim 10, wherein at least one of the first enable transistor and the second enable transistor determines the length of the time interval for supplying the compensation current to the operational amplifier according to the duty of the enable signal. Claim 12 An operational amplifier circuit for compensating the slew rate of an output signal, comprising: an amplifier circuit that outputs an amplified signal in which the signal level of the input signal is amplified based on an input signal and an output signal of the operational amplifier circuit; an output circuit that generates the output signal based on the amplified signal; and a compensation circuit that receives the amplified signal and provides a compensation current generated based on the amplified signal to at least one of the amplifier circuit and the output circuit, wherein the output circuit generates the output signal in which the signal level transition time is reduced by receiving the compensation current, and the compensation circuit comprises a source degeneration transistor whose activation status is determined according to the voltage level of the amplified signal by receiving the amplified signal as a gate signal. Claim 13 delete Claim 14 In claim 12, the compensation circuit comprises a compensation transistor that generates the compensation current, and the source degeneracy transistor is connected to the source terminal or drain terminal of the compensation transistor, characterized in that the operational amplifier circuit is characterized in that. Claim 15 In claim 14, the compensation circuit comprises: an input transistor that generates a first current based on the signal level difference between the input signal and the output signal; a first current mirror circuit that outputs a second current at a level equal to the level of the first current; and a second current mirror circuit that includes the compensation transistor and generates the compensation current by receiving the second current. Claim 16 An operational amplifier circuit for compensating the slew rate of an output signal comprises: an amplifier circuit that outputs an amplified signal in which the signal level of the input signal is amplified based on an input signal and an output signal of the operational amplifier circuit; an output circuit that generates the output signal based on the amplified signal; and a compensation circuit that receives the amplified signal and provides a compensation current generated based on the amplified signal to at least one of the amplifier circuit and the output circuit, wherein the output circuit generates the output signal in which the signal level transition time is reduced by receiving the compensation current, and the compensation circuit comprises: a first transistor whose activation is determined according to the signal level difference between the input signal and the output signal; a second transistor and a first load, wherein when the first transistor is activated, a first signal amplifier circuit that generates a first gate voltage amplified for the voltage level difference between the input signal and the output signal based on the internal resistance of the second transistor and the resistance of the first load; and a third transistor that generates a first compensation current based on the amplified first gate voltage and provides the first compensation current to the operational amplifier circuit. An operational amplifier circuit characterized by including a fourth transistor connected to one end of the second transistor and having its activation status determined according to the voltage level of the amplified signal. Claim 17 An operational amplifier compensation circuit that assists the amplification operation of an operational amplifier, comprising: a first input transistor that generates a first current based on the signal level difference between an input signal and an output signal of the operational amplifier; a first current mirror circuit connected to the source or drain terminal of the first input transistor and outputting a second current at a level equal to the level of the first current; a second current mirror circuit that generates a third current by receiving the second current; and an additional compensation circuit comprising a first additional compensation transistor and a first load, wherein when the first input transistor is activated, the additional compensation current generated based on the internal resistance of the first additional compensation transistor and the resistance of the first load is provided to the second current mirror circuit, and the compensation current obtained by adding the additional compensation current and the third current is provided to the operational amplifier. Claim 18 In claim 17, the additional compensation circuit further comprises a first source degeneration transistor, the activation status of which is determined based on an amplification signal of the operational amplifier distinct from the input signal and the output signal, and the source or drain terminal of which is connected to the first additional compensation transistor. Claim 19 An operational amplifier compensation circuit according to claim 17, wherein the first load comprises a first active load transistor that receives a first bias voltage at its gate and whose resistance level is determined according to the voltage value of the first bias voltage. Claim 20 An operational amplifier compensation circuit according to claim 17, further comprising: a second input transistor that generates a fourth current based on the signal level difference between the input signal and the output signal; a third current mirror circuit connected to the source or drain terminal of the second input transistor and outputting a fifth current at a level equal to the level of the fourth current; and a fourth current mirror circuit that generates a sixth current by receiving the fifth current, wherein the additional compensation circuit comprises a third additional compensation transistor and a second load, and when the second input transistor is activated, provides an additional compensation current generated based on the internal resistance of the third additional compensation transistor and the resistance of the second load to the fourth current mirror circuit, and provides a compensation current obtained by adding the additional compensation current and the sixth current to the operational amplifier.

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