Error correction device and method for generating syndromes and a partial coefficient information in a parallel

Abstract

An error correction device according to the technical concept of the present disclosure may include a syndrome generation circuit that receives data and generates a plurality of syndromes for the data; a partial coefficient generation circuit that generates partial coefficient information regarding a portion of the coefficients of an error location polynomial using the data while the plurality of syndromes are being generated; an error location determination circuit that determines the coefficients of the error location polynomial based on the plurality of syndromes and the partial coefficient information and obtains the location of an error included in the data using the error location polynomial; and an error correction circuit that corrects the error included in the data according to the location of the error.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to an error correction device and an error correction method that generate syndrome and partial counting information in parallel. Background Technology

[0002] An error correction decoder can perform error correction coding (ECC) to correct error bits contained in information data.

[0003] As communication speeds increase and data throughput grows, the number of error bits included in the information data may increase. Due to this increase in error bits, the error correction latency required from the time the error correction decoder receives information data until it outputs the corrected data may become longer. The problem to be solved

[0004] The problem that the technical concept of the present disclosure aims to solve is to reduce error correction latency by generating partial coefficients and syndromes of the error location equation in parallel. means of solving the problem

[0005] To achieve the above objectives, an error correction device according to one aspect of the present disclosure may include: a syndrome generation circuit that receives data and generates a plurality of syndromes for the data; a partial coefficient generation circuit that generates partial coefficient information regarding a portion of the coefficients of an error location polynomial using the data while the plurality of syndromes are being generated; an error location determination circuit that determines the coefficients of the error location polynomial based on the plurality of syndromes and the partial coefficient information and obtains the location of an error included in the data using the error location polynomial; and an error correction circuit that corrects the error included in the data according to the location of the error.

[0006] An error correction method according to another aspect of the present disclosure may include the steps of reading data from a memory cell array; generating a plurality of syndromes for the data; generating partial coefficient information regarding a portion of the coefficients of an error location polynomial using the data while the plurality of syndromes are being generated; determining the error location polynomial based on the plurality of syndromes and the partial coefficient information; obtaining the location of an error contained in the data using the error location polynomial; and correcting the error contained in the data based on the location of the error.

[0007] A volatile memory device according to another aspect of the present disclosure comprises a memory cell array including a plurality of memory cells and an error correction engine for correcting data read from the memory cell array, wherein the error correction engine may include a syndrome generation circuit for generating a plurality of syndromes using the read data, a partial coefficient generation circuit for generating partial coefficient information regarding a portion of the coefficients of an error location polynomial while the plurality of syndromes are being generated, an error location determination circuit for determining the coefficients of an error location polynomial based on the plurality of syndromes and the partial coefficient information and obtaining the location of an error included in the data using the error location polynomial, and an error correction circuit for correcting an error included in the data based on the location of the error. Effects of the invention

[0008] The error correction device and error correction method according to the exemplary embodiment of the present disclosure have the effect of reducing error correction latency by generating partial coefficients of the error location equation and the syndrome in parallel. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram illustrating an error correction device according to an exemplary embodiment of the present disclosure. FIG. 2 is a flowchart illustrating an error correction method according to an exemplary embodiment of the present disclosure. FIGS. 3(a) and FIGS. 3(b) are drawings for illustrating the latency of error correction according to an exemplary embodiment of the present disclosure. Figure 4 is a diagram illustrating a syndrome generation circuit. Figure 5 is a diagram illustrating an error correction polynomial generation circuit. FIG. 6 is a drawing for explaining a partial coefficient generation circuit according to an exemplary embodiment of the present disclosure. FIG. 7 is a drawing for explaining an error correction device according to another embodiment of the present disclosure. FIG. 8 is a drawing for explaining a partial coefficient generation circuit according to another embodiment of the present disclosure. FIG. 9 is a drawing for illustrating an error correction polynomial generation circuit according to an exemplary embodiment of the present disclosure. FIG. 10 is a block diagram illustrating a memory device including an ECC engine that performs syndrome generation and partial coefficient generation in parallel. Figure 11 is a diagram illustrating the ECC encoding circuit of Figure 10. Figure 12 is a diagram illustrating the ECC decoding circuit of Figure 10. FIG. 13 is a drawing illustrating a semiconductor memory device according to an embodiment of the present invention. FIG. 14 is a block diagram showing an example of applying a semiconductor memory device that generates partial coefficients and syndromes in parallel according to embodiments of the present invention to a mobile system. FIG. 15 is a block diagram showing an example of applying a semiconductor memory device that generates partial coefficients and syndromes in parallel according to embodiments of the present invention to a computing system. Specific details for implementing the invention

[0010] Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram illustrating an error correction device according to an exemplary embodiment of the present disclosure.

[0012] Referring to FIG. 1, the error correction device (100-1) may include a syndrome generation circuit (200), a partial coefficient generation circuit (300-1), an error location polynomial generation circuit (400-2), an error location determination circuit (500), an error correction circuit (600), and a data buffer (700).

[0013] The error correction device (100-1) receives a data polynomial R(x) and can correct errors contained in the data polynomial R(x). The error correction device (100-1) can output a corrected data polynomial C(x) in which the error has been corrected. The data polynomial R(x) may be source data configured to perform an error correction function in the error correction device (100-1). For example, the data polynomial R(x) may correspond to a vector representation of the readout data (RData[0:63]) and parity bit (ECCP[0:7]) to be described later in FIG. 10.

[0014] The data buffer (700) can temporarily store the received data polynomial R(x) and provide it to the error correction circuit (600).

[0015] A syndrome generation circuit (200) can receive a data polynomial R(x) and generate a syndrome polynomial S(x). The syndrome polynomial S(x) may be a polynomial indicating whether an error exists in the data polynomial R(x). If the syndrome polynomial S(x) is 0, there may be no error in the data polynomial R(x). If the syndrome polynomial S(x) is not 0, there may be an error in the data polynomial R(x).

[0016] When the syndrome polynomial S(x) is 0, the data polynomial R(x) temporarily stored in the data buffer (700) can be output outside the error correction device (100-1) without separate error correction.

[0017] If the syndrome polynomial S(x) is not zero, the syndrome polynomial S(x) can be passed to the error location polynomial generation circuit (400-2).

[0018] The partial coefficient generation circuit (300-1) can generate partial coefficient information (Partial_Coef_info) regarding a portion of the coefficients of the error location polynomial. The partial coefficient generation circuit (300-1) can reduce the latency required to correct the error included in the data polynomial R(x) by generating partial coefficient information (Partial_Coef_info) in parallel with the syndrome generation circuit (200) generating the syndrome polynomial S(x).

[0019] The error location polynomial generation circuit (400-2) is an error location polynomial used to search for the location of errors contained in the data polynomial R(x) based on the syndrome polynomial S(x) and partial coefficient information (Partial_Coef_info). It can generate an error location polynomial. The error location polynomial generation circuit (400-2) generates the error location polynomial by using the syndrome polynomial S(x) and partial coefficient information (Partial_Coef_info) together. The latency required to generate the coefficients can be reduced.

[0020] The error location polynomial generation circuit (400-2) may be referred to as a Key Equation Solver. The error location polynomial generation circuit (400-2) generates an error location polynomial using the Berlekamp-Massey algorithm, Step-By-Step (SBS) algorithm, Euclidean algorithm, or modified Euclidean algorithm. It can generate.

[0021] The error location determination circuit (500) is an error location polynomial Based on this, error locations can be calculated and an error polynomial E(x) can be generated according to the calculation result. The error location determination circuit (500) can transmit the generated error polynomial E(x) to the error correction circuit (600).

[0022] The error correction circuit (600) can correct the error of the data polynomial R(x) received from the data buffer (700) based on the error polynomial E(x) and output the corrected data polynomial C(x) with the error corrected.

[0023] FIG. 2 is a flowchart illustrating an error correction method according to an exemplary embodiment of the present disclosure.

[0024] Referring to FIG. 2, in step S201, data can be read from a memory cell array. The data may include information data and parity data. The parity data may be data required to correct the information data.

[0025] In step S203, the syndrome generation circuit (200) can generate multiple syndromes for the read data. A syndrome may be data indicating whether an error exists in the data. If the syndrome is 0, there may not be an error in the data. If the syndrome is not 0, there may be an error in the data.

[0026] In step S205, the partial coefficient generation circuit (300-1) can generate partial coefficient information, which is information regarding a part of the coefficients of an error location polynomial, using the read data in parallel with the generation of a plurality of syndromes. The error location polynomial may be a polynomial having the location of the error included in the read data as a root or the reciprocal of the root. The partial coefficient information may be information regarding a coefficient that includes a non-linear operation among the coefficients of the error location polynomial. The partial coefficient information may be information regarding a coefficient that includes a power value of any one of the syndromes among the coefficients of the error location polynomial. The partial coefficient information may be generated by performing a first summation operation among double summation operations for calculating the power value of the syndrome.

[0027] In step S207, the error location polynomial generation circuit (400-2) determines the error location polynomial based on the syndrome and partial coefficient information, and the error location determination circuit (500) can obtain the error location. The error location can be obtained by taking the reciprocal of the roots of the error location polynomial.

[0028] In step S209, the error correction circuit (600) can correct the error by flipping the bit corresponding to the error location in the data.

[0029] FIGS. 3(a) and FIGS. 3(b) are drawings for illustrating the latency of error correction according to an exemplary embodiment of the present disclosure.

[0030] Referring to FIG. 3(a), the syndrome generation circuit (200) can generate multiple syndromes for the data during a syndrome generation time Ts. The error location polynomial generation circuit (400-1) receives multiple syndromes from the syndrome generation circuit (200) and can generate coefficients of the error location polynomial during a first coefficient generation time (coefficient generation time1) Tc1.

[0031] Referring to FIG. 3(b), the partial coefficient generation circuit (300-1) can generate partial coefficients for a portion of the coefficients of the error location polynomial during the partial coefficient generation time Tp. The partial coefficient generation time Tp may overlap with the syndrome generation time Ts. That is, the partial coefficient generation circuit (300-1) can generate partial coefficients in parallel with the syndrome generation operation of the syndrome generation circuit (200). Although it has been described that the syndrome generation time Ts is longer than the partial coefficient generation time Tp, the partial coefficient generation time Tp may increase depending on which portion of the coefficients of the error location polynomial the partial coefficient generation circuit (300-1) generates. In other words, the partial coefficient generation time Tp may be longer than the syndrome generation time Ts.

[0032] The error location polynomial generation circuit (400-2) can generate the coefficients of the error location polynomial during a second coefficient generation time (coefficient generation time2) Tc2. Since partial coefficients among the coefficients of the error location polynomial have already been generated, the latency required to generate the coefficients of the error location polynomial can be reduced. That is, the second coefficient generation time (coefficient generation time2) can be shorter than the first coefficient generation time (coefficient generation time1). Consequently, when partial coefficients and syndromes are generated in parallel, the latency required during error correction can be reduced.

[0033] Figure 4 is a diagram illustrating a syndrome generation circuit.

[0034] Referring to FIG. 4, the syndrome generation circuit (200) may include a 0th syndrome generation circuit (210) to a 2t-1th syndrome generation circuit (230).

[0035] The syndrome generation circuit (200) can receive a data polynomial R(x) and generate a syndrome polynomial S(x). The received vector is When, the data polynomial R(x) is expressed as in [Equation 1], and the syndrome, which is the coefficient of the syndrome polynomial S(x), is expressed as in [Equation 2], and the syndrome polynomial S(x) can be expressed as in [Equation 3].

[0036]

[0037] Here, N can be the number of bits included in the received vector.

[0038]

[0039] Here, can be a primitive element of a Galois field. For example, is a Galois field GF( It can be a primitive element of ). Galois field GF( )={0, 1, , 쪋, It can be. That is, GF( )Is It can include several elements.

[0040]

[0041] Here, t may be the number of error-correctable bits of the error correction device.

[0042] The zero syndrome generation circuit (210) is zero syndrome It can generate. The zero syndrome generation circuit (220) generates the first syndrome It can generate the 2t-1 syndrome. The 2t-1 syndrome generation circuit (230) generates the 2t-1 syndrome It can generate. The syndrome generation circuit (200) is the zero syndrome To 2t-1 syndrome It can be generated in parallel.

[0043] The 0th syndrome generation circuit (210) to the 2t-1th syndrome generation circuit (230) may each include an AND operation unit (240), an XOR operation unit (250), and a shift register (260). The AND operation unit (240) may be a Galois multiplier that performs an AND operation on an element of a received vector and an element of a Galois field. The XOR operation unit (250) may perform an XOR operation on the ANDed value and the next element of the received vector. The shift register (260) may shift the value received from the XOR operation unit (250) and temporarily store the shifted value.

[0044] Figure 5 is a diagram illustrating an error correction polynomial generation circuit.

[0045] Referring to FIG. 5, the error correction polynomial generation circuit (400-1) when the error bits in the receiving vector are 2 or more, the first syndrome and third syndrome An error location polynomial can be generated using this. Specifically, if the error bits in the received vector are 2 or more, the error correction polynomial It can be expressed as [Equation 4].

[0046]

[0047] Error correction polynomial The constant term is the first syndrome and the coefficient of the first-order term is the square of the first syndrome and the coefficient of the quadratic term is the cube of the first syndrome and Third Syndrome It can be a combination of.

[0048] The error correction polynomial generation circuit (400-1) may include a square operation unit (401) and a cube operation unit (402). The square operation unit (401) is the first syndrome Receive, It may include AND gates and XOR gates to perform the operation. The cube operation unit (402) is the first syndrome Receive, It may include AND gates and XOR gates to perform operations.

[0049] Error location polynomial When generating, calculating the power of the syndrome may incur significant latency. For example, It can be expressed as [Mathematical Equation 5].

[0050]

[0051] Here, The part is a double summation operation, and the latency required to perform the double summation operation is the error location polynomial It can account for a large portion of the latency required to generate it.

[0052] Accordingly, the error correction device according to the present disclosure performs a portion of the double summation operation for calculating the power of a syndrome in parallel with the syndrome calculation, thereby the error location polynomial The latency required to generate it can be reduced. In this specification, a portion of the double sum operation may be a partial coefficient.

[0053] The error correction device according to the present disclosure, during a double sum operation The operation can be performed in parallel with the syndrome calculation. That is, the receiving vector The partial coefficient from By calculating in parallel with the generation of the syndrome, the time required to calculate the power of the syndrome can be reduced.

[0054] FIG. 6 is a drawing for explaining a partial coefficient generation circuit according to an exemplary embodiment of the present disclosure.

[0055] Referring to FIG. 6, the partial coefficient generating circuit (300-1) is a receiving vector It can receive and generate partial_coef_info. The partial_coef_generating circuit (300-1) depends on the value of index i It may include a plurality of partial summing circuits that perform the operation. For example, the zero partial summing circuit (301-1) when i is 0 Performs the operation, and the N-2nd partial summing circuit (301-2) when i is N-2 The operation can be performed. The partial coefficient generation circuit (300-1) can generate partial coefficient information (Partial_Coef_info) by adding all the outputs of a plurality of partial summing circuits.

[0056] FIG. 7 is a drawing for explaining an error correction device according to another embodiment of the present disclosure.

[0057] Referring to FIG. 7, the error correction device (100-2) may include a syndrome generation circuit (200), a partial coefficient generation circuit (300-2), an error location polynomial generation circuit (400-2), an error location determination circuit (500), an error correction circuit (600), and a data buffer (700). The error location polynomial generation circuit (400-2), the error location determination circuit (500), the error correction circuit (600), and the data buffer (700) are described in FIG. 1, so a description is omitted.

[0058] The partial coefficient generation circuit (300-2) can receive a syndrome term (S_term) from the syndrome generation circuit (200). The syndrome term (S_term) is a syndrome It may be a term for the summation operation required when calculating. Specifically, referring to [Equation 2], the syndrome term (S_term) is It can be. Here, i can be from 0 to N-1 and k can be from 0 to 2t-1. N is the length of the received vector and t can be the number of bits that can be corrected.

[0059] The syndrome generation circuit (200) can store a syndrome term (S_term) in a shift register (260) during the process of generating a syndrome. While the syndrome polynomial is being generated, the syndrome generation circuit (200) can transfer the syndrome term (S_term) to a partial coefficient generation circuit (300-2). The partial coefficient generation circuit (300-2) can generate partial coefficient information (Partial_Coef_info) using the syndrome term (S_term).

[0060] By using the syndrome term (S_term) generated by the syndrome generation circuit (200) to generate partial coefficient information (Partial_Coef_info), the size of the partial coefficient generation circuit (300-2) can be reduced.

[0062] FIG. 8 is a drawing for explaining a partial coefficient generation circuit according to another embodiment of the present disclosure.

[0063] Referring to FIG. 8, the partial coefficient generation circuit (300-2) receives a syndrome term (S_term) from the syndrome generation circuit (200) and can generate partial coefficient information (Partial_Coef_info).

[0064] Unlike the partial coefficient generation circuit (300-1) of FIG. 6, the partial coefficient generation circuit (300-2) depends on the value of index i It may include a plurality of partial summing circuits that perform the operation. That is, since it performs an operation of repeatedly summing the syndrome terms, it can generate partial_coef_info using the syndrome terms received from the syndrome generation circuit (200). The zero partial summing circuit (302-1) when i is 0 Performs the operation, and the N-2nd partial summing circuit (302-2) when i is N-2 The operation can be performed. The partial coefficient generation circuit (300-2) can generate partial coefficient information (Partial_Coef_info) by adding all the outputs of a plurality of partial summing circuits.

[0065] By using the syndrome term (S_term) generated by the syndrome generation circuit (200) to generate partial coefficient information (Partial_Coef_info), the size of the partial coefficient generation circuit (300-2) may be smaller than the size of the partial coefficient generation circuit (300-1) of FIG. 6.

[0066] Specifically, in the partial counting circuit (300-1) of FIG. 6, among the plurality of partial summing circuits, the 0th partial summing circuit (301-1) performs XOR and AND operations N times each, and the N-2nd partial summing circuit (301-2) performs XOR and AND operations once each. Therefore, the plurality of partial summing circuits total Performs operations n times.

[0067] In comparison, in the partial counting circuit (300-2) of FIG. 8, among the plurality of partial summing circuits, the 0th partial summing circuit (302-1) performs an XOR operation N times, and the N-2nd partial summing circuit (301-2) performs an XOR operation once. Therefore, the plurality of partial summing circuits total The operation is performed. Therefore, the partial coefficient generation circuit (300-2) may be smaller in size than the partial coefficient generation circuit (300-1) of FIG. 6.

[0068] FIG. 9 is a drawing for illustrating an error correction polynomial generation circuit according to an exemplary embodiment of the present disclosure.

[0069] Referring to FIG. 9, the error correction polynomial generation circuit (400-2) receives a syndrome from the syndrome generation circuit (200), receives partial coefficient information (Partial_Coef_info) from the partial coefficient generation circuit (300-1 or 300-2), and can generate coefficients of the error correction polynomial.

[0070] The error correction polynomial generation circuit (400-2) may include a square operation unit (401) and a cube operation unit (402-1). The square operation unit (401) is the first syndrome Receive, It may include AND gates and XOR gates to perform the operation. The cube operation unit (402-2) uses partial_coef_info It can perform operations.

[0071] Specifically, referring to [Equation 5], the cube operation unit (402-2) is a partial coefficient You can perform the remaining operations excluding .

[0072] Partial coefficients that are part of the double sum operation Since is pre-calculated by the partial coefficient generation circuit (300-1 or 300-2), the error location polynomial The latency required to generate it can be reduced.

[0073] FIG. 10 is a block diagram illustrating a semiconductor memory device including an ECC engine that performs syndrome generation and partial count generation in parallel.

[0074] Referring to FIG. 10, a semiconductor memory device (900) may include a memory cell array (1100) and an ECC engine (1000). The memory cell array (1100) may include a normal cell array (1110) and an ECC cell array (1120). The normal cell array (1110) may be a memory cell array in which write data (WData[0:63]) is stored, and the ECC cell array (1120) may be a memory cell array in which parity bits (ECCP[0:7]) are stored.

[0075] The ECC engine (1000) includes an ECC encoding circuit (1010) and an ECC decoding circuit (1020). The ECC encoding circuit (1010) can generate parity bits (ECCP[0:7]) for write data (WData[0:63]) to be written to memory cells of a normal cell array (1110). The parity bits (ECCP[0:7]) can be stored in the ECC cell array (1120).

[0076] The ECC decoding circuit (1020) can correct error bit data using read data (RData[0:63]) read from memory cells of the normal cell array (1110) and parity bits (ECCP[0:7]) read from the ECC cell array (1120), and output error-corrected data (Data[0:63]).

[0077] The ECC decoding circuit (1020) can generate syndromes and partial coefficients in parallel to correct errors contained in the readout data (RData[0:63]). The partial coefficients may be part of the coefficients of the error location polynomial. By generating syndromes and partial coefficients in parallel, the ECC decoding circuit (1020) can reduce the latency required to generate the error location polynomial.

[0078] Figure 11 is a diagram illustrating the ECC encoding circuit of Figure 10.

[0079] Referring to FIG. 11, the ECC encoding circuit (1010) may include a parity generation unit (712) that receives 64-bit write data (WData[0:63]) and basis bits (Basis Bit, B[0:7]) and generates parity bits (ECCP[0:7]) using an XOR array operation. The basis bits (B[0:7]) are bits for generating parity bits (ECCP[0:7]) for the 64-bit write data (WData[0:63]), and may be composed of, for example, b'00000000 bits. The basis bits (B[0:7]) may use other specific bits instead of b'00000000 bits.

[0080] Figure 12 is a diagram illustrating the ECC decoding circuit of Figure 10.

[0081] Referring to FIG. 12, the ECC decoding circuit (1020) includes a syndrome generation circuit (802), a partial coefficient generation circuit (803), an error location polynomial generation circuit (804), an error location determination circuit (806), and an error correction circuit (808). The syndrome generation circuit (802) can receive 64-bit readout data (RData[0:63]) and 8-bit parity bits (ECCP[0:7]) and generate syndrome data (S[0:7]) using an XOR array operation. The readout data (RData[0:63]) and the parity bits (ECCP[0:7]) may be vector representations of the data polynomial R(x). The syndrome data (S[0:7]) may be a vector representation of the syndrome polynomial S(x). The partial coefficient generation circuit (803) receives the readout data (RData[0:63]) and the parity bit (ECCP[0:7]) and can generate partial coefficient information (Partial_Coef_info) using XOR and AND operations. The error location polynomial generation circuit (804) can calculate the coefficients of the error location equation using the syndrome data (S[0:7]) and the partial coefficient information (Partial_Coef_info). The error location equation is an equation with the inverse of the error bit as its root. The error location determination circuit (806) can calculate the location of the bit error using the calculated error location equation. The error correction circuit (808) corrects the error by inverting the logic value of the bit where the error occurred in the 64-bit readout data (RData[0:63]) according to the bit error location information, and can output the error-corrected 64-bit data (Data[0:63]). 64-bit data (Data[0:63]) can be a vector representation of the correction data polynomial C(x).

[0082] FIG. 13 is a drawing illustrating a semiconductor memory device according to an embodiment of the present invention.

[0083] Referring to FIG. 13, the semiconductor memory device (900) may include control logic (910), a refresh address generator (915), an address buffer (920), bank control logic (930), a row address multiplexer (940), a column address latch (950), a row decoder, a memory cell array, a sense amplifier, an input / output gating circuit (990), a data input / output buffer (995), and an ECC engine (1000).

[0084] The memory cell array may include first to fourth bank arrays (980a, 980b, 980c, 980d). The row decoder may include first to fourth bank row decoders (960a, 960b, 960c, 960d) respectively connected to the first to fourth bank arrays (980a, 980b, 980c, 980d). The column decoder may include first to fourth bank column decoders (970a, 970b, 970c, 970d) respectively connected to the first to fourth bank arrays (980a, 980b, 980c, 980d). The sense amplifier section may include first to fourth bank sense amplifiers (985a, 985b, 985c, 985d) respectively connected to first to fourth bank arrays (980a, 980b, 980c, 980d). The first to fourth bank arrays (980a, 980b, 980c, 980d), first to fourth bank row decoders (960a, 960b, 960c, 960d), first to fourth bank column decoders (970a, 970b, 970c, 970d), and first to fourth bank sense amplifiers (985a, 985b, 985c, 985d) may each constitute the first to fourth banks. FIG. 9 illustrates an example of a semiconductor memory device (900) including four banks, but according to the embodiment, the semiconductor memory device (900) may include any number of banks.

[0085] Additionally, according to the embodiment, the semiconductor memory device (900) may be a dynamic random access memory (DRAM) such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), etc., or any volatile memory device that requires a refresh operation.

[0086] The control logic (910) can control the operation of the semiconductor memory device (900). For example, the control logic (910) can generate control signals to cause the semiconductor memory device (900) to perform a write operation or a read operation. The control logic (910) may include a command decoder (911) that decodes a command (CMD) received from a memory controller and a mode register (912) for setting the operation mode of the semiconductor memory device (900). For example, the command decoder (911) can generate control signals corresponding to the command (CMD) by decoding a write enable signal ( / WE), a row address strobe signal ( / RAS), a column address strobe signal ( / CAS), a chip select signal ( / CS), etc.

[0087] The control logic (910) may further receive a clock (CLK) and a clock enable signal (CKE) for driving the semiconductor memory device (900) in a synchronous manner. The control logic (910) may control the refresh address generator (915) to perform an auto-refresh operation in response to a refresh command, or control the refresh address generator (915) to perform a self-refresh operation in response to a self-refresh entry command.

[0088] The refresh address generator (915) can generate a refresh address (REF_ADDR) corresponding to a memory cell row on which a refresh operation is to be performed. The refresh address generator (915) can generate a refresh address (REF_ADDR) with a refresh rate that is longer than the refresh period defined in the standard of the semiconductor memory device (900). Accordingly, the refresh current and refresh power of the semiconductor memory device (900) can be reduced.

[0089] The address buffer (920) can receive an address (ADDR) including a bank address (BANK_ADDR), a row address (ROW_ADDR), and a column address (COL_ADDR) from a memory controller. Additionally, the address buffer (920) can provide the received bank address (BANK_ADDR) to the bank control logic (930), provide the received row address (ROW_ADDR) to the row address multiplexer (940), and provide the received column address (COL_ADDR) to the column address latch (950).

[0090] The bank control logic (930) can generate bank control signals in response to the bank address (BANK_ADDR). In response to the bank control signals, the bank row decoder corresponding to the bank address (BANK_ADDR) among the first to fourth bank row decoders (960a, 960b, 960c, 960d) may be activated, and the bank column decoder corresponding to the bank address (BANK_ADDR) among the first to fourth bank column decoders (970a, 970b, 970c, 970d) may be activated.

[0091] The bank control logic (930) can generate bank group control signals in response to a bank address (BANK_ADDR) that determines the bank group. In response to the bank group control signals, the row decoders of the bank group corresponding to the bank address (BANK_ADDR) among the first to fourth bank row decoders (960a, 960b, 960c, 960d) can be activated, and the column decoders of the bank group corresponding to the bank address (BANK_ADDR) among the first to fourth bank column decoders (970a, 970b, 970c, 970d) can be activated.

[0092] The row address multiplexer (940) can receive a row address (ROW_ADDR) from the address buffer (920) and a refresh row address (REF_ADDR) from the refresh address generator (915). The row address multiplexer (940) can selectively output the row address (ROW_ADDR) or the refresh row address (REF_ADDR). The row address output from the row address multiplexer (940) can be applied to the first to fourth bank row decoders (960a, 960b, 960c, 960d), respectively.

[0093] Among the first to fourth bank row decoders (960a, 960b, 960c, 960d), the bank row decoder activated by the bank control logic (930) can decode the row address output from the row address multiplexer (940) and activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line driving voltage to the word line corresponding to the row address.

[0094] The column address latch (950) receives a column address (COL_ADDR) from the address buffer (920) and can temporarily store the received column address (COL_ADDR). The column address latch (950) can gradually increase the received column address (COL_ADDR) in burst mode. The column address latch (950) can apply the temporarily stored or gradually increased column address (COL_ADDR) to the first to fourth bank column decoders (970a, 970b, 970c, 970d), respectively.

[0095] Among the first to fourth bank column decoders (970a, 970b, 970c, 970d), the bank column decoder activated by the bank control logic (930) can activate a sense amplifier corresponding to the bank address (BANK_ADDR) and the column address (COL_ADDR) through the input / output gating circuit (990).

[0096] The input / output gating circuit (990) may include, together with circuits for gating input / output data, input data mask logic, read-out data latches for storing data output from first to fourth bank arrays (980a, 980b, 980c, 980d), and a write driver for writing data to the first to fourth bank arrays (980a, 980b, 980c, 980d).

[0097] Data to be read from one of the first to fourth bank arrays (980a, 980b, 980c, 980d) can be sensed and amplified by a sense amplifier and stored in read data latches. The data (DQ) stored in the read data latch can be provided to the memory controller through the data input / output buffer (995). Data (DQ) to be written to one of the first to fourth bank arrays (980a, 980b, 980c, 980d) can be provided from the memory controller to the data input / output buffer (995). The data (DQ) provided to the data input / output buffer (995) can be written to one of the bank arrays through a write driver.

[0098] FIG. 14 is a block diagram showing an example of applying a semiconductor memory device that generates partial coefficients and syndromes in parallel according to embodiments of the present invention to a mobile system.

[0099] Referring to FIG. 14, a mobile system (1400) may include an application processor (1410), a connectivity unit (1420), a first memory device (1430), a second memory device (1440), a user interface (1450), and a power supply (1460) connected to each other via a bus (1402). The first memory device (1430) may be configured as a volatile memory device, and the second memory device (1440) may be configured as a non-volatile memory device. According to an embodiment, the mobile system (1400) may be any mobile system such as a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0100] The application processor (1410) can execute applications that provide internet browsers, games, videos, etc. According to an embodiment, the application processor (1410) may include a single processor core or a plurality of processor cores. For example, the application processor (1410) may include a dual-core, a quad-core, or a hexa-core. Additionally, according to an embodiment, the application processor (1410) may further include a cache memory located internally or externally.

[0101] The communication unit (1420) can perform wireless or wired communication with an external device. For example, the communication unit (1420) can perform Ethernet communication, Near Field Communication (NFC), Radio Frequency Identification (RFID) communication, Mobile Telecommunication, memory card communication, Universal Serial Bus (USB) communication, etc. For example, the communication unit (1420) may include a baseband chipset and may support communication such as GSM, GRPS, WCDMA, HSxPA, etc.

[0102] The first memory device (1430), which is a volatile memory device, can store data processed by the application processor (1410) or operate as a working memory. The first memory device (1430) may include a memory cell array comprising a plurality of memory cells and an ECC engine that performs an ECC operation on data read from the memory cells. The ECC engine may include a partial coefficient generation circuit that generates partial coefficient information for a portion of the coefficients of an error location polynomial in parallel while generating a plurality of syndromes for the read data. By generating partial coefficients and syndromes in parallel, the first memory device (1430) can reduce the latency required to generate the error correction polynomial.

[0103] The first memory device (1430) can output an error signal so that the mobile system (1400) can be notified of an error occurring while the device is installed in and used by the mobile system (1400). Accordingly, the mobile system (1400) can replace the memory device (1430) if it is determined that the first memory device (1430) is unsuitable for mobile system operation, taking into account the error signal and the number of ECC operations. Accordingly, the mobile system (1400) can replace the memory device (1430) before a system malfunction caused by the memory device (1430) occurs, thereby ensuring stable system operation.

[0104] The second memory device (1440), which is a non-volatile memory device, can store a boot image for booting the mobile system (1400). For example, the non-volatile memory device (1440) may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), or a similar memory.

[0105] The user interface (1450) may include one or more input devices, such as a keypad and a touch screen, and / or one or more output devices, such as a speaker and a display device. It may supply an operating voltage of a power supply (1460). Additionally, according to an embodiment, the mobile system (1400) may further include a camera image processor (CIP) and may further include storage devices such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0106] FIG. 15 is a block diagram showing an example of applying a semiconductor memory device that generates partial coefficients and syndromes in parallel according to embodiments of the present invention to a computing system.

[0107] Referring to FIG. 15, the computing system (2000) includes a processor (2010), an input / output hub (2020), an input / output controller hub (2030), a memory device (2040), and a graphics card (2050). According to an embodiment, the computing system (2000) may be any computing system such as a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital TV, a set-top box, a music player, a portable game console, a navigation system, etc.

[0108] The processor (2010) can execute various computing functions, such as specific calculations or tasks. For example, the processor (2010) may be a microprocessor or a Central Processing Unit (CPU). According to an embodiment, the processor (2010) may include a single processor core or a plurality of processor cores. For example, the processor (2010) may include a dual-core, a quad-core, a hexa-core, etc. Additionally, although FIG. 20 illustrates a computing system (2000) including a single processor (2010), according to an embodiment, the computing system (2000) may include a plurality of processors. Also, according to an embodiment, the processor (2010) may further include a cache memory located internally or externally.

[0109] The processor (2010) may include a memory controller (2011) that controls the operation of a memory device (2040). The memory controller (2011) included in the processor (2010) may be called an Integrated Memory Controller (IMC). According to an embodiment, the memory controller (2011) may be located within an input / output hub (2020). The input / output hub (2020) containing the memory controller (2011) may be called a memory controller hub (MCH).

[0110] A memory device (2040) may include a memory cell array comprising a plurality of memory cells, an ECC engine that performs an ECC operation on the memory cells and outputs an error address corresponding to an error bit corrected by the ECC operation, and an error notification unit that compares the error address with existing defective cell information and outputs an error signal if the comparison result does not match.

[0111] The memory device (2040) may include a memory cell array comprising a plurality of memory cells and an ECC engine that performs ECC operations on the memory cells. The ECC engine may include a partial coefficient generation circuit that generates partial coefficient information for a portion of the coefficients of an error location polynomial in parallel while generating a plurality of syndromes for the read-out data. By generating partial coefficients and syndromes in parallel, the memory device (2040) can reduce the latency required to generate the error correction polynomial.

[0112] The memory device (2040) can output an error signal so that the computing system (2000) can detect an error that occurs while the memory device (2040) is installed in and used by the computing system (2000). Accordingly, the computing system (2000) can replace the memory device (2040) if it is determined that the memory device (2040) is unsuitable for system operation, taking into account the error signal and the number of ECC operations. Accordingly, the computing system (2000) can replace the memory device (2040) before a system malfunction caused by the memory device (2040) occurs, thereby ensuring stable system operation.

[0113] An input / output hub (2020) can manage data transfer between devices such as a graphics card (2050) and a processor (2010). The input / output hub (2020) can be connected to the processor (2010) through various types of interfaces. For example, the input / output hub (2020) and the processor (2010) can be connected via various standard interfaces such as a Front Side Bus (FSB), System Bus, HyperTransport, Lightning Data Transport (LDT), QuickPath Interconnect (QPI), Common System Interface, and Peripheral Component Interface-Express (CSI). Although FIG. 20 illustrates a computing system (2000) including one input / output hub (2020), according to the embodiment, the computing system (2000) may include a plurality of input / output hubs.

[0114] The input / output hub (2020) can provide various interfaces with devices. For example, the input / output hub (2020) can provide an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe), a Communications Streaming Architecture (CSA) interface, etc.

[0115] A graphics card (2050) may be connected to an input / output hub (2020) via AGP or PCIe. The graphics card (2050) may control a display device (not shown) for displaying images. The graphics card (2050) may include an internal processor and an internal semiconductor memory device for processing image data. According to an embodiment, the input / output hub (2020) may include a graphics device inside the input / output hub (2020), either together with the graphics card (2050) located outside the input / output hub (2020) or instead of the graphics card (2050). The graphics device included in the input / output hub (2020) may be called Integrated Graphics. Additionally, the input / output hub (2020) including a memory controller and a graphics device may be called a Graphics and Memory Controller Hub (GMCH).

[0116] The input / output controller hub (2030) can perform data buffering and interface arbitration to enable various system interfaces to operate efficiently. The input / output controller hub (2030) can be connected to the input / output hub (2020) via an internal bus. For example, the input / output hub (2020) and the input / output controller hub (2030) can be connected via a Direct Media Interface (DMI), a hub interface, an Enterprise Southbridge Interface (ESI), PCIe, etc.

[0117] The input / output controller hub (2030) can provide various interfaces with peripheral devices. For example, the input / output controller hub (2030) can provide a Universal Serial Bus (USB) port, a Serial Advanced Technology Attachment (SATA) port, a General Purpose Input / Output (GPIO), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (SPI), PCI, PCIe, etc.

[0118] According to an embodiment, two or more components of a processor (2010), an input / output hub (2020), or an input / output controller hub (2030) may be implemented as a single chipset.

[0119] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 An error correction device comprising: a syndrome generation circuit that receives data and generates a plurality of syndromes for said data; a partial coefficient generation circuit that generates partial coefficient information regarding a portion of the coefficients of an error location polynomial using said data while said syndromes are being generated; an error location polynomial generation circuit that receives said partial coefficient information and a plurality of syndromes, calculates a first coefficient among the coefficients of said error location polynomial based on said partial coefficient information and said syndromes, determines second coefficients among said coefficients other than the first coefficient based on said syndromes, and generates said error location polynomial based on said first coefficient and said second coefficients; an error location determination circuit that obtains the location of an error included in said data using said error location polynomial; and an error correction circuit that corrects said error included in said data according to said location of the error. Claim 2 An error correction device according to claim 1, wherein the partial coefficient generation circuit generates information regarding coefficients including non-linear operations among the coefficients of the error location polynomial as the partial coefficient information while the plurality of syndromes are being generated. Claim 3 An error correction device according to claim 2, wherein the partial coefficient generation circuit generates a partial operation as partial coefficient information for calculating a power value of a target syndrome included in the first coefficient while the plurality of syndromes are being generated. Claim 4 An error correction device according to claim 3, wherein the partial coefficient generation circuit generates the partial coefficient information by performing a first summation operation among double summation operations for calculating the power value of the target syndrome while the plurality of syndromes are being generated. Claim 5 An error correction device according to claim 4, wherein the error location determination circuit calculates a power value of the target syndrome by performing a second summation operation among the double summation operations using the partial coefficient information. Claim 6 An error correction device according to claim 1, wherein the partial coefficient generation circuit generates partial coefficient information using a syndrome term already generated among a plurality of syndrome terms included in a target syndrome while the plurality of syndromes are being generated. Claim 7 In claim 6, the syndrome generation circuit is an error correction device that transmits the already generated syndrome term among the plurality of syndrome terms included in the target syndrome among the plurality of syndromes to the partial coefficient generation circuit. Claim 8 An error correction method comprising: reading data from a memory cell array; generating a plurality of syndromes for the data; generating partial coefficient information regarding a portion of the coefficients of an error location polynomial using the data while the plurality of syndromes are being generated; calculating a first coefficient among the coefficients of the error location polynomial based on the partial coefficient information and the plurality of syndromes; determining second coefficients among the coefficients excluding the first coefficient based on the plurality of syndromes; generating an error location polynomial based on the first coefficient and the second coefficients; obtaining the location of an error included in the data using the error location polynomial; and correcting the error included in the data based on the location of the error. Claim 9 An error correction method according to claim 8, wherein, while the plurality of syndromes are being generated, the step of generating partial coefficient information regarding a part of the coefficients of an error position polynomial using the data is characterized by generating a part of the operation of a nonlinear operation included in the first coefficient as the partial coefficient information. Claim 10 An error correction method according to claim 9, wherein the partial coefficient information is characterized by generating a partial operation for calculating a power value of a target syndrome included in the first coefficient as the partial coefficient information. Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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