Display apparatus

Abstract

An embodiment of the present invention discloses a display device comprising: a substrate having a transparent area and a display area surrounding the transparent area; a plurality of display elements disposed in the display area; a plurality of first horizontal lines and a plurality of second horizontal lines extending along a first direction and spaced apart from each other with the transparent area in between; a plurality of first vertical lines and a plurality of second vertical lines extending along a second direction intersecting the first direction and spaced apart from each other with the transparent area in between; and a first connecting line connecting at least one of the plurality of first vertical lines and at least one of the plurality of second vertical lines and bypassing the transparent area; wherein the first connecting line is disposed in a first layer that is in the same layer as at least one of the plurality of first horizontal lines.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device, and more specifically, to a display device including a transparent area in a display panel. Background Technology

[0002] Recently, display devices have become more diverse in their applications. In addition, there is a trend of display devices becoming thinner and lighter, expanding their range of use.

[0003] As the area occupied by the display surface of display devices is expanded, various functions integrated or linked to the display are being added. As a means to add diverse functions while expanding the surface area, research is continuing on display devices that feature an area within the display surface for adding various functions, rather than just an image display. The problem to be solved

[0004] As a method to increase the functionality that can be integrated or linked with a display device, an embodiment of the present invention may provide a display panel having a transparent area in which a camera, a sensor, etc. can be disposed on the inner side of the display area, and a display device having the same.

[0005] In addition, embodiments of the present invention can provide a display panel and a display device that can reduce the area occupied by wiring that bypasses the surrounding area of ​​the transparent region.

[0006] However, these tasks are exemplary and do not limit the scope of the invention. means of solving the problem

[0007] An embodiment of the present invention discloses a display device comprising: a substrate having a transparent area and a display area surrounding the transparent area; a plurality of display elements disposed in the display area; a plurality of first horizontal lines and a plurality of second horizontal lines extending along a first direction and spaced apart from each other with the transparent area in between; a plurality of first vertical lines and a plurality of second vertical lines extending along a second direction intersecting the first direction and spaced apart from each other with the transparent area in between; and a first connecting line connecting at least one of the plurality of first vertical lines and at least one of the plurality of second vertical lines and bypassing the transparent area; wherein the first connecting line is disposed in a first layer that is in the same layer as at least one of the plurality of first horizontal lines.

[0008] In one embodiment, a second connecting wire is included that connects at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires and bypasses the transmission area; wherein the second connecting wire may be disposed on a second layer different from the first layer.

[0009] In one embodiment, the first connecting wire and the second connecting wire are provided in plurality, and the plurality of first connecting wires and the plurality of second connecting wires can be arranged alternately around the transmission area.

[0010] In one embodiment, the first connecting wire may be connected to at least one of the plurality of first vertical wires through a contact hole.

[0011] In one embodiment, the apparatus further comprises a bridge metal connecting the first connecting wire and at least one of the plurality of first vertical wires; wherein the bridge metal is connected to the first connecting wire through a first contact hole, and the bridge metal can be connected to at least one of the plurality of first vertical wires through a second contact hole.

[0012] In one embodiment, it further includes a third horizontal wiring that extends from the display area in the first direction and is arranged to bypass the transparent area; wherein the third horizontal wiring may be arranged on a layer different from the first layer.

[0013] In one embodiment, at least one of the plurality of first horizontal wires can be connected to at least one of the plurality of second horizontal wires through a horizontal-connecting wire.

[0014] In one embodiment, the apparatus further comprises: an electrode layer arranged to surround the perforated hole and arranged to overlap with the first connecting electrode; a horizontal driving voltage line extending in the first direction; and a vertical driving voltage line extending in the second direction; wherein the horizontal driving voltage line and the vertical driving voltage line may be connected to the electrode layer.

[0015] In one embodiment, the electrode layer may overlap at least partially with the plurality of connecting wires.

[0016] In one embodiment, a third connecting wire is included that connects at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires and bypasses the transmission area; wherein the third connecting wire may be disposed in a third layer that is in the same layer as at least one of the plurality of first vertical wires.

[0017] In one embodiment, a fourth connecting wire is included that connects at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires and bypasses the transmission area; wherein the fourth connecting wire may be disposed on a fourth layer different from the third layer.

[0018] In one embodiment, it further includes a horizontal connecting wire that extends in the first direction and is arranged to bypass the permeable area; wherein the horizontal connecting wire can connect at least one of the plurality of first horizontal wires and at least one of the plurality of second horizontal wires.

[0019] In one embodiment, the apparatus further comprises a second connecting wire that connects at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires and bypasses the transmission area; wherein at least one of the plurality of first horizontal wires is disposed on a second layer different from the first layer, and the second connecting wire may be disposed on the second layer.

[0020] Another embodiment of the present invention discloses a display device comprising: a substrate having a transparent area, a display area surrounding the transparent area, and a non-display area between the transparent area and the display area; a plurality of display elements disposed in the display area; a plurality of first horizontal lines and a plurality of second horizontal lines extending along a first direction and spaced apart from each other with the transparent area in between; a plurality of first vertical lines and a plurality of second vertical lines extending along a second direction intersecting the first direction and spaced apart from each other with the transparent area in between; and a plurality of connecting lines disposed in the non-display area, each connecting at least one of the plurality of first vertical lines and at least one of the plurality of second vertical lines, and including a first connecting line, a second connecting line, a third connecting line, and a fourth connecting line disposed on different layers; wherein the first connecting line is disposed on a first layer that is on the same layer as at least one of the plurality of first horizontal lines.

[0021] In one embodiment, a thin-film transistor having a first semiconductor layer and a first gate electrode is disposed in the display area, and the first connecting wire may be disposed in the same layer as the first gate electrode.

[0022] In one embodiment, a storage capacitor including a first electrode disposed on the same layer as the first gate electrode and a second electrode disposed on the upper side of the first electrode is disposed in the display area, and the second connecting wire may be disposed on the same layer as the second electrode.

[0023] In one embodiment, the third connecting wire may be placed on a third layer that is on the same layer as at least one of the plurality of first vertical wires.

[0024] In one embodiment, the third connecting wire may have an area that overlaps with a part of the first connecting wire and a part of the second connecting wire, respectively, between the first connecting wire and the second connecting wire on a plane.

[0025] In one embodiment, the fourth connecting wire may have an area that overlaps with a part of the first connecting wire and a part of the second connecting wire, respectively, between the first connecting wire and the second connecting wire on a plane.

[0026] In one embodiment, the plurality of connecting wires may further include a fifth connecting wire disposed on a different layer from the first connecting wire, the second connecting wire, the third connecting wire, and the fourth connecting wire. Effects of the invention

[0027] A display device according to embodiments of the present invention can reduce the non-display area around the transparent area. In addition, since the wiring around the transparent area is connected through connecting wires, the display device can prevent damage caused by static electricity. These effects are exemplary and do not limit the scope of the present invention. Brief explanation of the drawing

[0028] FIG. 1 is a schematic perspective view illustrating a display device according to one embodiment of the present invention. FIGS. 2a to 2d are simplified cross-sectional views of a display device according to embodiments of the present invention. FIGS. 3a to 3c are cross-sectional views of a display device according to other embodiments of the present invention. FIG. 4 is a schematic plan view of a display panel according to one embodiment of the present invention. FIGS. 5a and FIGS. 5b are equivalent circuit diagrams showing a pixel of a display device according to one embodiment of the present invention. FIGS. 6a to 6c are schematic cross-sectional views of a display device that corresponds to the line I-I' of FIG. 4. FIG. 7 is a plan view showing wiring around a transmission area as an embodiment of the present invention. FIGS. 8a and FIGS. 8b are schematic cross-sectional views corresponding to the line II-II' of FIG. 7. FIG. 9a is a schematic plan view showing a part of a display device according to one embodiment of the present invention. FIG. 9b is a schematic plan view showing a part of a display device according to one embodiment of the present invention. FIG. 10 is a schematic plan view showing a part of a display device according to one embodiment of the present invention. FIG. 11 is a schematic cross-sectional view corresponding to the line III-III' of FIG. 10. FIG. 12 is a schematic plan view showing a part of a display device according to one embodiment of the present invention. FIG. 13 is a schematic cross-sectional view corresponding to line IV-IV of FIG. 12. FIG. 14 is a schematic plan view showing a part of a display device according to one embodiment of the present invention. FIG. 15 is a schematic plan view showing a part of a display device according to one embodiment of the present invention. Specific details for implementing the invention

[0029] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0031] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0032] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0033] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0034] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0035] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0036] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0037] In the following embodiments, when it is stated that a membrane, region, component, etc. is connected, it includes not only cases where the membrane, region, or component is directly connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect connection. For example, when it is stated in this specification that a membrane, region, component, etc. is electrically connected, it includes not only cases where the membrane, region, or component, etc. are directly electrically connected, but also cases where other membranes, regions, or components are interposed between them to form an indirect electrical connection.

[0038] FIG. 1 is a schematic perspective view illustrating a display device according to one embodiment of the present invention.

[0039] Referring to FIG. 1, the display device (1) includes a display area (DA) that emits light and a non-display area (NDA) that does not emit light. The display device (1) can provide a predetermined image using light emitted from a plurality of pixels arranged in the display area (DA).

[0040] The display device (1) includes a transmission area (TA). The transmission area (TA) may be surrounded by a display area (DA). The transmission area (TA) corresponds to an area through which light or / and sound can be transmitted, which is output from an electronic element to the outside or travels from the outside toward an electronic element. In one embodiment of the present invention, when light is transmitted through the transmission area (TA), the light transmittance may be about 50% or more, more preferably 70% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0041] A first non-display area (NDA1) is provided between the transmission area (TA) and the display area (DA). The first non-display area (NDA1) may be arranged to surround the transmission area (TA). Pixels that implement an image are not placed in the first non-display area (NDA1), and wiring that transmits electrical signals to pixels spaced apart with the transmission area (TA) in between may be placed therein.

[0042] The second non-display area (NDA2) is extended along the edge of the display device (1) and arranged to surround the display area (DA). Pixels that implement an image are not placed in the second non-display area (NDA2), and various types of wiring and built-in circuits, etc., may be placed therein.

[0043] Each pixel provided in the display device (1) may include a light-emitting diode as a display element capable of emitting light of a predetermined color. The light-emitting diode may include an organic light-emitting diode that includes an organic material as the light-emitting layer. Alternatively, the light-emitting diode may include an inorganic light-emitting diode. Alternatively, the light-emitting diode may include quantum dots as the light-emitting layer. In another embodiment, the display device (1) may be a liquid crystal display device.

[0044] For convenience of explanation, the following description is given as an example where the display device (1) is an organic light-emitting display device including an organic light-emitting diode.

[0045] In one embodiment, as shown in FIG. 1, the transparent area (TA) may be positioned at the center of the display area (DA) along the width direction of the display device (1) and positioned at the upper side along the length direction. In another embodiment, the transparent area (TA) may be positioned at the center along the length direction of the display device (1) or offset to the lower side. Alternatively, the transparent area (TA) may be positioned offset to the left or right side along the width direction.

[0046] The shape of the display area (DA) can be a circle, an ellipse, or a polygon such as a triangle or a pentagon, and the size, shape, number, and position of the transmission area (TA) can also be varied.

[0047] FIGS. 2a to 2d are simplified cross-sectional views of a display device according to embodiments of the present invention, corresponding to a cross-section along line A-A' of FIG. 1.

[0048] Referring to FIG. 2a, the display device (1) may include a display panel (10) including a display element and a component (20) corresponding to a transparent area (TA).

[0049] The display panel (10) may include a substrate (100), a sealing substrate (300) facing the substrate (100) as a sealing member, and a display element layer (200) interposed between them, and a sealing material (sealant, 350) covering the side of the display element layer (200) may be disposed between the substrate (100) and the sealing substrate (300). FIG. 2a illustrates that the sealing material (350) is disposed on both sides of the transparent area (TA), but when viewed from a direction perpendicular to the main surface of the substrate (100), the transparent area (TA) can be understood as being entirely surrounded by the sealing material (350).

[0050] The substrate (100) may comprise glass or a polymer resin. The polymer resin may comprise a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene napthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) comprising the polymer resin may have flexible, rollable, or bendable properties. The substrate (100) may have a multilayer structure comprising a layer comprising the aforementioned polymer resin and an inorganic layer (not shown). The encapsulation substrate (300) may comprise glass or the aforementioned polymer resin.

[0051] The display element layer (200) may include a circuit layer including a thin-film transistor (TFT), an organic light-emitting diode (OLED) as a display element connected to the thin-film transistor (TFT), and an insulating layer (IL) between them. The thin-film transistor (TFT) and the organic light-emitting diode (OLED) connected thereto are placed in a display area (DA), and some of the wiring (WL) of the display element layer (200) may be located in a first non-display area (NDA1). The wiring (WL) may provide a predetermined signal or voltage to pixels spaced apart from each other with a transmission area (TA) in between. In FIG. 2a, the wiring (WL) is shown as not overlapping with the sealing material (350) in the first non-display area (NDA1), but in another embodiment, a portion of the sealing material (350) may also be placed on the wiring (WL).

[0052] The display panel (10) may include a through hole (10H) corresponding to a transparent area (TA). For example, the substrate (100) and the encapsulation substrate (300) may each include through holes (100H, 300H) corresponding to a transparent area (TA). Of course, the display element layer (200) may also include a through hole corresponding to a transparent area (TA).

[0053] Although not shown, components such as an input sensing member for detecting touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may be further disposed on the display panel (10).

[0054] The component (20) may be located in the transmission area (TA). The component (20) may be an electronic element that uses light or sound. For example, the electronic element may be a sensor that receives and uses light, such as an infrared sensor; a camera that captures an image by receiving light; a sensor that outputs and detects light or sound to measure distance or recognize fingerprints, etc.; a small lamp that outputs light; or a speaker that outputs sound. In the case of an electronic element that uses light, it goes without saying that light of various wavelength bands, such as visible light, infrared light, and ultraviolet light, can be used. As shown in FIG. 2a, if the display panel (10) includes a through hole (10H) corresponding to the transmission area (TA), the light or sound output or received from the electronic element can be utilized more effectively.

[0055] Unlike the display panel (10) in FIG. 2a which includes a through hole (10H) corresponding to a transmission area (TA), some components of the display panel (10) may not include a through hole. For example, as shown in FIG. 2b, the encapsulating substrate (300) may have a through hole (300H) corresponding to a transmission area (TA), but the substrate (100) may not have a through hole. Alternatively, as shown in FIG. 2c and FIG. 2d, both the substrate (100) and the encapsulating substrate (300) may not have a through hole corresponding to a transmission area (TA). Even if the substrate (100) does not have a through hole (100H) as shown in FIG. 2b to 2d, light transmittance for electronic elements can be secured by removing parts of the display element layer (200) corresponding to the transmission area (TA). Accordingly, when the display device (1) includes the display panel (10) shown in FIGS. 2b to 2d, it may be appropriate to use an electronic element that utilizes light.

[0056] Meanwhile, as shown in FIG. 2d, the display panel (10) may not include a sealing material (350) around the transparent area (TA). This is because the display panel (10) of FIG. 2d does not have through holes corresponding to the transparent area (TA) in the substrate (100) and the encapsulating substrate (300), so outside air may not penetrate into the transparent area (TA).

[0057] The component (20) illustrated in FIGS. 2a to 2d may be positioned inside the through hole (10H) so as to overlap with the side of the display panel (10) defining the through hole (10H).

[0058] The component (20) may be a component other than the aforementioned electronic element. In one embodiment, when the display panel (10) is used as a smart watch or a vehicle instrument panel, the component (20) may be a component including a clock hand or a hand indicating certain information (e.g., vehicle speed, etc.). Alternatively, the component (20) may include a component such as an accessory that enhances the aesthetic appeal of the display panel (10).

[0059] FIGS. 3a to 3c are cross-sectional views of a display device according to other embodiments of the present invention, which may correspond to a cross-section along line A-A' of FIG. 1.

[0060] Referring to FIG. 3a, the display device (1) may include a display panel (10) and a component (20), similar to the display device (1) described above with reference to FIG. 2a. Additionally, although not illustrated, the display device (1) may further include an input sensing member for detecting touch input, an anti-reflection member, and a window, etc., disposed on the display panel (10).

[0061] Unlike the display panel (10) described above with reference to FIG. 2a, which includes a sealing substrate (300) and a sealing material (350) as sealing members, the display panel (10) according to the present embodiment may include a thin film sealing layer (300') as a sealing member, in which case the flexibility of the display panel (10) can be further improved. Hereinafter, for convenience of explanation, the differences will be explained in detail.

[0062] The thin film encapsulation layer (300') may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, FIG. 3a shows first and second inorganic encapsulation layers (310, 330) and an organic encapsulation layer (320) between them.

[0063] The first and second inorganic encapsulation layers (310, 330) may include one or more inorganic insulating materials selected from silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The organic encapsulation layer (320) may include a polymer-based material. Polymer-based materials may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0064] The display panel (10) may include a through hole (10H) corresponding to a transmission area (TA). For example, the substrate (100) and the thin film encapsulation layer (300') may include through holes (100H, 300'H) corresponding to the transmission area (TA). The first and second inorganic encapsulation layers (310, 330) and the organic encapsulation layer (320) may include a hole corresponding to the transmission area (TA). The size of the hole in the organic encapsulation layer (320) may be formed larger than the size of the holes in the first and second inorganic encapsulation layers (310, 330), so that the first and second inorganic encapsulation layers (310, 330) may come into contact with each other around the transmission area (TA).

[0065] Unlike the display panel (10) in FIG. 3a which includes a through hole (10H) corresponding to a transmission area (TA), the display panel (10) may not include a through hole. As shown in FIG. 3b, the thin film encapsulation layer (300') may have a through hole (300H) corresponding to a transmission area (TA), but the substrate (100) may not have a through hole. Alternatively, as shown in FIG. 3c, both the substrate (100) and the thin film encapsulation layer (300') may not have a through hole corresponding to a transmission area (TA). As previously stated, even if the substrate (100) does not have a through hole (100H) as shown in FIG. 3b and FIG. 3c, light transmittance for the electronic element, which is the component (20), can be secured by removing the portions of the display element layer (200) corresponding to the transmission area (TA).

[0066] In the case where the thin film encapsulation layer (300') does not have a through hole as shown in FIG. 3c, at least one inorganic encapsulation layer and at least one organic encapsulation layer can each cover the substrate (100) in the transmission region (TA). In this case, the portion of the display element layer (200) between the substrate (100) and the thin film encapsulation layer (300') corresponding to the transmission region (TA) can be removed. FIG. 3a shows that the insulating layer (IL) corresponding to the transmission region (TA) is completely removed, but only some layers of the multilayer insulating layer (IL) can be removed.

[0067] The component (20) may be positioned inside the through hole (10H) so as to overlap with the side of the display panel (10) defining the through hole (10H), for example, inside the through hole (100H) of the substrate (100) and the through hole (200H) of the display element layer (200) as shown in FIG. 3a, or inside the through hole (200H) of the display element layer (200) as shown in FIG. 3b.

[0068] FIGS. 2a to 2c illustrate a case where the display panel (10) includes only the encapsulating substrate (300) as the encapsulating member, and FIGS. 3a to 3c illustrate a case where the display panel (10) includes only the thin film encapsulating layer (300') as the encapsulating member; however, the display panel according to one embodiment may include both the encapsulating substrate (300) and the thin film encapsulating layer (300'). For example, the display panel (10) may include both the encapsulating substrate (300) illustrated in FIGS. 2a to 2c and the thin film encapsulating layer (300') illustrated in FIGS. 3a to 3c.

[0069] FIG. 4 is a schematic plan view of a display panel according to one embodiment of the present invention.

[0070] Referring to FIG. 4, the display panel (10) includes a plurality of pixels (P) arranged in a display area (DA). Each pixel (P) may include a display element such as an organic light-emitting diode. Each pixel (P) may emit light of, for example, red, green, blue, or white through the organic light-emitting diode. In this specification, a pixel (P) can be understood as a subpixel that emits light of any one of the colors red, green, blue, or white, as described above. The display area (DA) may be covered with a sealing member, as previously described with reference to FIG. 2a to 3c, to be protected from the outside air or moisture.

[0071] A transparent area (TA) can be positioned at the center with respect to the width direction (first direction) of a display area (DA) and can be partially surrounded by the display area (DA). Accordingly, a plurality of pixels (P) are arranged around the transparent area (TA). The plurality of pixels (P) can be arranged to surround at least a portion of the transparent area (TA), and a first non-display area (NDA1) in which no pixels (P) are arranged is located between the transparent area (TA) and the display area (DA). Wiring for applying a predetermined signal or power to pixels (P) spaced apart from the transparent area (TA) can bypass the first non-display area (NDA1). Additionally, some wiring can be formed by being disconnected with the transparent area (TA) in between.

[0072] Each pixel (P) can be electrically connected to built-in circuits disposed in the second non-display area (NDA2). The second non-display area (NDA2) may have a first scan driving circuit section (110), a second scan driving circuit section (120), a terminal section (140), a data driving circuit (150), a first power supply wiring (160), and a second power supply wiring (170) disposed therein.

[0073] The first scan driving circuit (110) can provide a scan signal to each pixel (P) through a scan line (SL). The first scan driving circuit (110) can provide a light emission control signal to each pixel through a light emission control line (EL). The second scan driving circuit (120) can be arranged parallel to the first scan driving circuit (110) with a display area (DA) in between. Some of the pixels (P) placed in the display area (DA) can be electrically connected to the first scan driving circuit (110), and the rest can be connected to the second scan driving circuit (120).

[0074] The first scan driving circuit unit (110) and the second scan driving circuit unit (120) can be connected to each other by a driver line (DRL). Multiple driver lines (DRL) may be provided, and each can transmit a gate driving high voltage (Vgh), a gate driving low voltage (Vgl), a start signal (FLM), etc. Here, the gate driving high voltage (Vgh) and the gate driving low voltage (Vgl) may be voltages for driving the first scan driving circuit unit (110) and the second scan driving circuit unit (120). As the first scan driving circuit unit (110) and the second scan driving circuit unit (120) are connected by the driver line (DRL), the brightness deviation of the display device (1) can be minimized.

[0075] A terminal portion (140) may be disposed on one side of the substrate (100). The terminal portion (140) may be exposed without being covered by an insulating layer and may be electrically connected to a printed circuit board (PCB). A terminal (PCB-P) of the printed circuit board (PCB) may be electrically connected to a terminal portion (140) of the display panel (10). The printed circuit board (PCB) transmits a signal or power from a control unit (not shown) to the display panel (10). A control signal generated by the control unit may be transmitted to the first and second scan driving circuits (110, 120), respectively, through the printed circuit board (PCB). The control unit can provide a driving voltage and a common voltage (ELVDD, ELVSS, see FIG. 5a and FIG. 5b described later) to the first and second power supply wires (160, 170), respectively, through the first and second connecting wires (161, 171).

[0076] The driving voltage (ELVDD) is provided to each pixel (P) through a driving voltage line (PL) connected to a first power supply line (160), and the common voltage (ELVSS) can be provided to the opposing electrode of the pixel (P) connected to a second power supply line (170). The second power supply line (170) can partially surround the display area (DA) in a loop shape with one side open.

[0077] The data driving circuit (150) is electrically connected to the data line (DL). The data signal of the data driving circuit (150) can be provided to each pixel (P) through the connection wiring (151) connected to the terminal portion (140) and the data line (DL) connected to the connection wiring (151). FIG. 4 illustrates the data driving circuit (150) being placed on a printed circuit board (PCB), but in another embodiment, the data driving circuit (150) may be placed on a substrate (100). For example, the data driving circuit (150) may be placed between the terminal portion (140) and the first power supply wiring (160).

[0078] The first power supply wiring (160) is connected to the first connection wiring (161) and can receive a driving voltage (ELVDD) from a control unit connected to the terminal unit (140). The first power supply wiring (160) is arranged to correspond to all pixel (P) columns arranged in the first direction, so that it can deliver a driving voltage (ELVDD) to each pixel (P) column.

[0079] In this embodiment, the first scan line (SLa) positioned to the left of the transmission area (TA) may be spaced apart from the second scan line (SLb) positioned to the right with the transmission area (TA) in between. Additionally, the first light emission control line (ELa) positioned to the left of the transmission area (TA) may be spaced apart from the second light emission control line (ELb) positioned to the right with the transmission area (TA) in between.

[0080] In this case, the lengths of the first scan line (SLa) and the second scan line (SLb) positioned on the same line may be substantially equal, and the lengths of the first light emission control line (ELa) and the second light emission control line (ELb) positioned on the same line may be substantially equal. Since the lengths of the first scan line (SLa) and the second scan line (SLb) are substantially equal, the luminance deviation between the pixels positioned to the left of the transmission area (TA) and the pixels positioned to the right of the transmission area (TA) can be formed uniformly. Accordingly, the first scan line (SLa) and the second scan line (SLb) may not be connected. Likewise, the first light emission control line (ELa) and the second light emission control line (ELb) may not be connected to each other.

[0081] The first scan line (SLa) and the first light emission control line (ELa) can be connected to the first scan driving circuit unit (110) and extended in the (+) first direction (X). The second scan line (SLa) and the second light emission control line (ELb) can be connected to the second scan driving circuit unit (120) and extended in the (-) first direction (-X).

[0082] FIGS. 5A and FIGS. 5B are equivalent circuit diagrams of pixels that can be applied to embodiments of the present invention.

[0083] Referring to FIG. 5a, each pixel (P) includes a pixel circuit (PC) connected to a scan line (SL) and a data line (DL), and an organic light-emitting diode (OLED) connected to the pixel circuit (PC).

[0084] The pixel circuit (PC) includes a driving thin-film transistor (T1), a switching thin-film transistor (T2), and a storage capacitor (Cst). The switching thin-film transistor (T2) is connected to a scan line (SL) and a data line (DL), and transmits a data signal (Dm) input through the data line (DL) to the driving thin-film transistor (T1) according to a scan signal (Sn) input through the scan line (SL).

[0085] The storage capacitor (Cst) is connected to the switching thin-film transistor (T2) and the driving voltage line (PL), and stores a voltage corresponding to the difference between the voltage received from the switching thin-film transistor (T2) and the first power supply voltage (ELVDD, or driving voltage) supplied to the driving voltage line (PL).

[0086] The driving thin-film transistor (T1) is connected to the driving voltage line (PL) and the storage capacitor (Cst), and can control the driving current flowing from the driving voltage line (PL) to the organic light-emitting diode (OLED) in correspondence with the voltage value stored in the storage capacitor (Cst). The organic light-emitting diode (OLED) can emit light having a predetermined brightness by the driving current.

[0087] FIG. 5a describes a case where the pixel circuit (PC) includes two thin-film transistors and one storage capacitor, but according to other embodiments, the number of thin-film transistors and the number of storage capacitors can be varied.

[0088] For example, as shown in FIG. 5b, the pixel circuit (PC) may include seven thin-film transistors and one storage capacitor.

[0089] Referring to FIG. 5b, the pixel (P) includes a pixel circuit (PC) and an organic light-emitting diode (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) may include a plurality of thin-film transistors and a storage capacitor. The thin-film transistors and the storage capacitor may be connected to signal lines (SL, SL-1, EL, DL), an initialization voltage line (VL), and a driving voltage line (PL).

[0090] FIG. 5b illustrates that each pixel (P) is connected to signal lines (SL, SL-1, EL, DL), an initialization voltage line (VL), and a driving voltage line (PL), but the present invention is not limited thereto. In another embodiment, at least one of the signal lines (SL, SL-1, EL, DL), the initialization voltage line (VL), and the driving voltage line (PL), etc., may be shared among neighboring pixels.

[0091] A plurality of thin-film transistors may include a driving thin-film transistor (T1), a switching thin-film transistor (T2), a compensation thin-film transistor (T3), a first initialization thin-film transistor (T4), an operation control thin-film transistor (T5), a light emission control thin-film transistor (T6), and a second initialization thin-film transistor (T7).

[0092] The signal line includes a scan line (SL) that transmits a scan signal (Sn), a previous scan line (SL-1) that transmits a previous scan signal (Sn-1) to a first initialization thin-film transistor (T4) and a second initialization thin-film transistor (T7), a light emission control line (EL) that transmits a light emission control signal (En) to an operation control thin-film transistor (T5) and a light emission control thin-film transistor (T6), and a data line (DL) that intersects with the scan line (SL) and transmits a data signal (Dm). The driving voltage line (PL) transmits a driving voltage (ELVDD) to a driving thin-film transistor (T1), and the initialization voltage line (VL) transmits an initialization voltage (Vint) that initializes the driving thin-film transistor (T1) and the pixel electrode.

[0093] The driving gate electrode (G1) of the driving thin-film transistor (T1) is connected to the first electrode (CE1) of the storage capacitor (Cst), the driving source electrode (S1) of the driving thin-film transistor (T1) is connected to the lower driving voltage line (PL) via the operation control thin-film transistor (T5), and the driving drain electrode (D1) of the driving thin-film transistor (T1) is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the light emission control thin-film transistor (T6). The driving thin-film transistor (T1) receives a data signal (Dm) according to the switching operation of the switching thin-film transistor (T2) and transmits a driving current (I) to the organic light-emitting diode (OLED). OLED supplies ).

[0094] The switching gate electrode (G2) of the switching thin-film transistor (T2) is connected to the scan line (SL), the switching source electrode (S2) of the switching thin-film transistor (T2) is connected to the data line (DL), and the switching drain electrode (D2) of the switching thin-film transistor (T2) is connected to the driving source electrode (S1) of the driving thin-film transistor (T1) and is connected to the lower driving voltage line (PL) via the operation control thin-film transistor (T5). The switching thin-film transistor (T2) is turned on according to the scan signal (Sn) received through the scan line (SL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the driving source electrode (S1) of the driving thin-film transistor (T1).

[0095] The compensation gate electrode (G3) of the compensation thin film transistor (T3) is connected to the scan line (SL), and the compensation source electrode (S3) of the compensation thin film transistor (T3) is connected to the driving drain electrode (D1) of the driving thin film transistor (T1) and is connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin film transistor (T6). The compensation drain electrode (D3) of the compensation thin film transistor (T3) is connected to the first electrode (CE1) of the storage capacitor (Cst), the first initialization drain electrode (D4) of the first initialization thin film transistor (T4), and the driving gate electrode (G1) of the driving thin film transistor (T1). The compensation thin film transistor (T3) is turned on according to the scan signal (Sn) received through the scan line (SL) to electrically connect the driving gate electrode (G1) and the driving drain electrode (D1) of the driving thin film transistor (T1), thereby diode-connecting the driving thin film transistor (T1).

[0096] The first initialization gate electrode (G4) of the first initialization thin film transistor (T4) is connected to the previous scan line (SL-1), and the first initialization source electrode (S4) of the first initialization thin film transistor (T4) is connected to the second initialization drain electrode (D7) of the second initialization thin film transistor (T7) and the initialization voltage line (VL), and the first initialization drain electrode (D4) of the first initialization thin film transistor (T4) is connected to the first electrode (CE1) of the storage capacitor (Cst), the compensation drain electrode (D3) of the compensation thin film transistor (T3), and the driving gate electrode (G1) of the driving thin film transistor (T1). The first initialization thin film transistor (T4) is turned on according to the previous scan signal (Sn-1) received through the previous scan line (SL-1) and transmits an initialization voltage (Vint) to the driving gate electrode (G1) of the driving thin film transistor (T1) to perform an initialization operation that initializes the voltage of the driving gate electrode (G1) of the driving thin film transistor (T1).

[0097] The operation control gate electrode (G5) of the operation control thin film transistor (T5) is connected to the light emission control line (EL), the operation control source electrode (S5) of the operation control thin film transistor (T5) is connected to the lower driving voltage line (PL), and the operation control drain electrode (D5) of the operation control thin film transistor (T5) is connected to the driving source electrode (S1) of the driving thin film transistor (T1) and the switching drain electrode (D2) of the switching thin film transistor (T2).

[0098] The light-emitting control gate electrode (G6) of the light-emitting control thin film transistor (T6) is connected to the light-emitting control line (EL), and the light-emitting control source electrode (S6) of the light-emitting control thin film transistor (T6) is connected to the driving drain electrode (D1) of the driving thin film transistor (T1) and the compensation source electrode (S3) of the compensation thin film transistor (T3), and the light-emitting control drain electrode (D6) of the light-emitting control thin film transistor (T6) is electrically connected to the second initialization source electrode (S7) of the second initialization thin film transistor (T7) and the pixel electrode of the organic light-emitting diode (OLED).

[0099] The operation control thin-film transistor (T5) and the light emission control thin-film transistor (T6) are simultaneously turned on according to the light emission control signal (En) received through the light emission control line (EL), so that the driving voltage (ELVDD) is transmitted to the organic light-emitting diode (OLED) and the driving current (I) to the organic light-emitting diode (OLED) OLED Make ) flow.

[0100] The second initialization gate electrode (G7) of the second initialization thin film transistor (T7) is connected to the previous scan line (SL-1), and the second initialization source electrode (S7) of the second initialization thin film transistor (T7) is connected to the light-emitting control drain electrode (D6) of the light-emitting control thin film transistor (T6) and the pixel electrode of the organic light-emitting diode (OLED), and the second initialization drain electrode (D7) of the second initialization thin film transistor (T7) is connected to the first initialization source electrode (S4) of the first initialization thin film transistor (T4) and the initialization voltage line (VL). The second initialization thin film transistor (T7) is turned on according to the previous scan signal (Sn-1) received through the previous scan line (SL-1) to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0101] FIG. 5b illustrates a case where the initialization thin film transistor (T4) and the second initialization thin film transistor (T7) are connected to the previous scan line (SL-1), but the present invention is not limited thereto. In another embodiment, the initialization thin film transistor (T4) is connected to the previous scan line (SL-1) and driven according to the previous scan signal (Sn-1), and the second initialization thin film transistor (T7) is connected to a separate signal line (e.g., a subsequent scan line) and driven according to the signal transmitted to the signal line.

[0102] The second electrode (CE2) of the storage capacitor (Cst) is connected to the driving voltage line (PL), and the counter electrode of the organic light-emitting diode (OLED) is connected to the common voltage (ELVSS). Accordingly, the organic light-emitting diode (OLED) receives a driving current (I) from the driving thin-film transistor (T1). OLED An image can be displayed by receiving ) and emitting light.

[0103] In FIG. 5b, the compensation thin film transistor (T3) and the initialization thin film transistor (T4) are shown having dual gate electrodes, but the compensation thin film transistor (T3) and the initialization thin film transistor (T4) may have a single gate electrode.

[0104] FIGS. 6a to 6c are cross-sectional views showing a part of the stacked structure of a display device that can be applied to embodiments of the present invention.

[0105] Referring to FIG. 6a, the display device may include a substrate (100), thin-film transistors (TFT1, 2) disposed on the substrate (100), a storage capacitor (Cst), an organic light-emitting diode (OLED), and first to third wiring layers (WL1~WL3).

[0106] A buffer layer (111) may be disposed on the substrate (100). The buffer layer (111) may reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100) and may provide a flat surface on the substrate (100). The buffer layer (111) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials. A barrier layer (not shown) that blocks the penetration of outside air may be further included between the substrate (100) and the buffer layer (111).

[0107] The first thin-film transistor (TFT1) includes a first semiconductor layer (A1), a first gate electrode (G1), a first source electrode (S1), and a first drain electrode (D1), and the second thin-film transistor (TFT2) may include a second semiconductor layer (A2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2). The first thin-film transistor (TFT1) may be connected to an organic light-emitting diode (OLED) and function as a driving thin-film transistor to drive the organic light-emitting diode (OLED). The second thin-film transistor (TFT2) may be connected to a data line (DL) and function as a switching thin-film transistor. Although two thin-film transistors are shown in the drawing, they are not limited thereto. The number of thin-film transistors can be varied in many ways, such as from 2 to 7.

[0108] The first semiconductor layer (A1) and the second semiconductor layer (A2) may include amorphous silicon or polycrystalline silicon. In another embodiment, the semiconductor layers (A1, A2) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layers (A1, A2) may include a channel region, an impurity-doped source region, and a drain region.

[0109] A first gate electrode (G1) and a second gate electrode (G2) may be disposed on the first semiconductor layer (A1) and the second semiconductor layer (A2), respectively, with a first gate insulating layer (112) in between. The first gate electrode (G1) and the second gate electrode (G2) may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be composed of a single layer or multiple layers. As an example, the first gate electrode (G1) and the second gate electrode (G2) may be a single layer of Mo.

[0110] The first gate insulating layer (112) is silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0111] A second gate insulating layer (113) may be provided to cover the first gate electrode (G1) and the second gate electrode (G2). The second gate insulating layer (113) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0112] The first electrode (CE1) of the storage capacitor (Cst) can overlap with the first thin-film transistor (TFT1). For example, the first gate electrode (G1) of the first thin-film transistor (TFT1) can function as the first electrode (CE1) of the storage capacitor (Cst).

[0113] The second electrode (CE2) of the storage capacitor (Cst) overlaps with the first electrode (CE1) with the second gate insulating layer (113) in between. In this case, the second gate insulating layer (113) can function as a dielectric layer of the storage capacitor (Cst). The second electrode (CE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the second electrode (CE2) may be a single layer of Mo or a multilayer of Mo / Al / Mo.

[0114] The first source electrode (S1) and the first drain electrode (D1), and the second source electrode (S2) and the second drain electrode (D2) may be disposed on an interlayer insulating layer (114). The first source electrode (S1) and the first drain electrode (D1), and the second source electrode (S2) and the second drain electrode (D2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the first source electrode (S1) and the first drain electrode (D1), and the second source electrode (S2) and the second drain electrode (D2) may be formed as a multilayer structure of Ti / Al / Ti.

[0115] A first flattening layer (116) is positioned on the first source electrode (S1) and the first drain electrode (D1), and on the second source electrode (S2) and the second drain electrode (D2), and an organic light-emitting diode (OLED) may be positioned on the first flattening layer (116).

[0116] The first flattening layer (116) may have a flat upper surface so that the pixel electrode (210) can be formed flat. The first flattening layer (116) may be formed as a single layer or a multilayer film made of organic material. Such first flattening layer (116) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, polymethylmethacrylate (PMMA), or polystylene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0117] An organic light-emitting diode (OLED) is disposed on the first planarization layer (116). The organic light-emitting diode (OLED) includes a pixel electrode (210), an intermediate layer (220) including an organic light-emitting layer, and a counter electrode (230).

[0118] The first planarization layer (116) has a via hole that exposes either the first source electrode (S1) or the first drain electrode (D1) of the first thin-film transistor (TFT1), and the pixel electrode (210) can be electrically connected to the first thin-film transistor (TFT1) by contacting the first source electrode (S1) or the first drain electrode (D1) through the via hole.

[0119] The pixel electrode (210) may be a light-transmitting electrode or a reflective electrode. In some embodiments, the pixel electrode (210) may have a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective film. The transparent or translucent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).

[0120] A pixel defining film (119) may be disposed on the upper portion of the first flattening layer (116). The pixel defining film (119) may serve to define the light-emitting region of a pixel by having an opening (119OP) corresponding to each subpixel, that is, an opening (119OP) that exposes at least the central portion of the pixel electrode (210). Additionally, the pixel defining film (119) may serve to prevent arcs from occurring at the edge of the pixel electrode (210) by increasing the distance between the edge of the pixel electrode (210) and the opposing electrode (230) above the pixel electrode (210). The pixel defining film (119) may be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0121] A spacer (SPC) may be disposed on the upper surface of the pixel defining film (119). The spacer (SPC) is disposed between a plurality of display elements and may be provided protruding in a direction away from the substrate (100). In one embodiment, the spacer (SPC) may be configured to prevent scratching during the mask process. In another embodiment, the spacer (SPC) may serve to change the light path. The spacer (SPC) may be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin. In some embodiments, the spacer (SPC) may be simultaneously formed with the same material as the pixel defining film (119) by a process using a halftone mask.

[0122] The intermediate layer (220) of the organic light-emitting diode (OLED) may include an organic light-emitting layer. The organic light-emitting layer may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be optionally further disposed below and above the organic light-emitting layer. In some embodiments, the intermediate layer (220) may be disposed corresponding to each of the plurality of pixel electrodes (210). In other embodiments, the intermediate layer (220) may include a layer that is integral across the plurality of pixel electrodes (210). For example, the organic light-emitting layer may be disposed corresponding to each of the plurality of pixel electrodes (210), and the functional layer disposed above and / or below the organic light-emitting layer may be integrally provided across the plurality of pixels. In another embodiment, the intermediate layer (220) may be integrally provided across a plurality of pixel electrodes (210).

[0123] The counter electrode (230) may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode (230) may be a transparent or translucent electrode and may be formed from a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film. The counter electrode (230) may be formed integrally in a plurality of organic light-emitting diodes (OLEDs) and may correspond to a plurality of pixel electrodes (210).

[0124] On the upper side of the counter electrode (230), a capping layer (not shown) to improve light extraction efficiency and / or a protective layer (not shown) to protect the organic light-emitting diode (OLED) during a subsequent process may be further disposed.

[0125] The first to third wirings (WL1 to WL3) can transmit electrical signals and / or constant voltage to thin-film transistors (TFT1, TFT2) included in the pixel circuit.

[0126] The first wiring (WL1) is placed on the first gate insulating layer (112), which is in the same layer as the gate electrodes (G1, G2), and can function as a scan line (SL, SL-1, see FIG. 5a, FIG. 5b) that transmits a scan signal to the pixel circuit. Alternatively, the first wiring (WL1) can function as a light emission control line (EL, see FIG. 5b).

[0127] The second wiring (WL2) is placed on the second gate insulating layer (113), which is on the same layer as the second electrode (CE2) of the storage capacitor (Cst), and can function as a scan line (SL) and / or a light emission control line (EL).

[0128] The third wiring (WL3) is placed on the interlayer insulation layer (114) and can function as a data line (DL) that transmits a data signal to the pixel circuit. Alternatively, the third wiring (WL3) can function as a driving voltage line (PL, see FIG. 5a and FIG. 5b) that transmits a driving voltage to the pixel circuit.

[0129] 6b is a cross-sectional view showing a part of a display device that can be applied to embodiments of the present invention. In FIG. 6b, the same reference numerals as in FIG. 6a indicate the same components, so a redundant description thereof is omitted.

[0130] Referring to FIG. 6b, the display device may further include a second flattening layer (117) on top of the first flattening layer (116). Accordingly, a fourth wiring (WL4) may be arranged between the first flattening layer (116) and the second flattening layer (117).

[0131] The second flattening layer (117) may have a flat upper surface so that the pixel electrode (210) can be formed flat. The second flattening layer (117) may be formed as a single layer or a multilayer film made of organic material. Such second flattening layer (117) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, polymethylmethacrylate (PMMA), or polystylene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0132] An organic light-emitting diode (OLED) is disposed on the second flattening layer (117). The pixel electrode (210) of the organic light-emitting diode (OLED) can be connected to a first thin-film transistor (TFT1) through a connecting electrode (CM) disposed on the first flattening layer (116).

[0133] A fourth wire (WL4) may be disposed on the first flattening layer (116). In some embodiments, the fourth wire (WL4) may function as a driving voltage line that transmits a driving voltage to a pixel circuit. In other embodiments, the fourth wire (WL4) may function as a data line that transmits a data signal to a pixel circuit.

[0134] 6c is a cross-sectional view showing a part of a display device that can be applied to embodiments of the present invention. In FIG. 6c, the same reference numerals as in FIG. 6b indicate the same components, so a redundant description thereof is omitted.

[0135] Referring to FIG. 6c, the display device of the present embodiment may further include a third thin-film transistor (TFT3) in which a third semiconductor layer (A3) is disposed on a layer different from the first semiconductor layer (A1) of the first thin-film transistor (TFT1). In addition, in the present embodiment, the interlayer insulating layer (114) may be provided with a first interlayer insulating layer (114a) and a second interlayer insulating layer (114b). Additionally, a third flattening layer (118) may be further disposed on top of the second flattening layer (117).

[0136] The third thin-film transistor (TFT3) may include a third semiconductor layer (A3), a third gate electrode (G3), a third source electrode (S3), and a third drain electrode (D3). The third semiconductor layer (A3) may be disposed on the first interlayer insulating layer (114a). That is, the third semiconductor layer (A3) may be disposed on a layer different from the first semiconductor layer (A1). The third semiconductor layer (A3) may include a channel region and source and drain regions disposed on both sides of the channel region. In some embodiments, the third semiconductor layer (A3) may be provided as an oxide semiconductor. For example, the third semiconductor layer (A3) may be formed of a Zn oxide-based material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. Alternatively, the third semiconductor layer (A3) may be provided with an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductor containing metals such as indium (In), gallium (Ga), and tin (Sn) in ZnO.

[0137] The source and drain regions of the third semiconductor layer (A3) can be formed by making them conductive by controlling the carrier concentration of the oxide semiconductor. For example, the source and drain regions of the third semiconductor layer (A3) can be formed by increasing the carrier concentration in the oxide semiconductor through plasma treatment using a hydrogen (H) series gas, a fluorine (F) series gas, or a combination thereof.

[0138] A third gate electrode (G3) is disposed overlapping with the channel region of the third semiconductor layer (A3), and a third gate insulating layer (115) may be disposed between the third semiconductor layer (A3) and the third gate electrode (G3). That is, the third gate electrode (G3) can be insulated from the third semiconductor layer (A3) by the third gate insulating layer (115). The third gate insulating layer (115) may be patterned according to the shape of the third gate electrode (G3).

[0139] The third gate insulating layer (115) may include an inorganic material comprising an oxide or a nitride. For example, the third gate insulating layer (115) may include silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. The third gate electrode (G3) is disposed on the third gate insulating layer (115) and may be composed of a single layer or multiple layers, including molybdenum (Mo), copper (Cu), titanium (Ti), etc.

[0140] The second interlayer insulating layer (114b) covers the third gate electrode (G3) of the third thin-film transistor (TFT3) and can be disposed on the upper surface of the substrate (100). The third source electrode (S3) and the third drain electrode (D3) can be disposed on the upper surface of the second interlayer insulating layer (114b).

[0141] The third source electrode (S3) and the third drain electrode (D3) can contact the source region and the drain region of the third semiconductor layer (A3), respectively, through a contact hole penetrating the second interlayer insulating layer (114b). The third source electrode (S3) and the third drain electrode (D3) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. The third source electrode (S3) and the third drain electrode (D3) may be placed on the same layer as the third wiring (WL3).

[0142] A third gate insulating layer (115) and a fifth wiring (WL5) may be disposed on the upper portion of the first interlayer insulating layer (114a). The third gate insulating layer (115) may be patterned according to the shape of the fifth wiring (WL5). In some embodiments, the fifth wiring (WL5) may function as a scan line that transmits a scan signal to a pixel circuit. In other embodiments, the fifth wiring (WL5) may function as a light emission control line that transmits a light emission control signal to a pixel circuit.

[0143] A third flattening layer (118) may be disposed between the second flattening layer (117) and the pixel electrode (210).

[0144] The third flattening layer (118) may have a flat upper surface so that the pixel electrode (210) can be formed flat. The third flattening layer (118) may be formed as a single layer or a multilayer film made of organic material. Such third flattening layer (118) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, polymethylmethacrylate (PMMA), or polystylene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0145] An organic light-emitting diode (OLED) is disposed on the third flattening layer (118). The pixel electrode (210) of the organic light-emitting diode (OLED) can be connected to a first thin-film transistor (TFT1) through an additional connecting electrode (CM') disposed on the second flattening layer (117) and a connecting electrode (CM) disposed on the first flattening layer (116).

[0146] A sixth wire (WL6) may be disposed on the second flattening layer (117). In some embodiments, the sixth wire (WL6) may function as a driving voltage line that transmits a driving voltage to a pixel circuit. In other embodiments, the sixth wire (WL6) may function as a data line that transmits a data signal to a pixel circuit.

[0147] FIG. 7 is an enlarged plan view corresponding to the area around the transmission region (TA) of a display device according to one embodiment, and FIG. 8a and FIG. 8b are schematic cross-sectional views corresponding to the line II-II' of FIG. 7.

[0148] Referring to FIG. 7, a first non-display area (NDA1) is placed around a transparent area (TA), and a display area (DA) is placed surrounding the transparent area (TA) and the first non-display area (NDA1).

[0149] A plurality of pixels (P) and a plurality of signal lines providing electrical signals to the plurality of pixels (P) may be arranged in the display area (DA). Scan lines (SLa, SLb) and light emission control lines (ELa, ELb) may be extended along a first direction (X), and data lines (DL) may be extended in a second direction (Y) that intersects the first direction (X).

[0150] In this embodiment, the wiring extending in the first direction and positioned to the left of the transmission area (TA) is referred to as the first horizontal wiring (HLa), and the wiring positioned to the right is referred to as the second horizontal wiring (HLb). Additionally, the wiring extending in the second direction and positioned above the transmission area (TA) is referred to as the first vertical wiring (VLa), and the wiring positioned below is referred to as the second vertical wiring (VLb).

[0151] The first horizontal wiring (HLa) may include a first scan line (SLa) and a first light emission control line (ELa). Additionally, although not illustrated, the first horizontal wiring (HLa) may further include wiring positioned to the left of the transmission area (TA) among the previous scan line and / or subsequent scan line described with reference to FIG. 5b.

[0152] The second horizontal wiring (HLb) may include a second scan line (SLb) and a second light emission control line (ELb). Additionally, the second horizontal wiring (HLb) may further include wiring positioned to the right of the transmission area (TA) among the previous scan line and / or subsequent scan line described with reference to FIG. 5b.

[0153] The first vertical wiring (VLa) includes a first data line (DLa), and the second vertical wiring (VLb) may include a second data line (DLb).

[0154] A first scan line (SLa) positioned to the left of the transmission area (TA) may be spaced apart from a second scan line (SLb) positioned to the right of the transmission area (TA) with the transmission area (TA) in between. Additionally, a first light emission control line (ELa) positioned to the left of the transmission area (TA) may be spaced apart from a second light emission control line (ELb) positioned to the right with the transmission area (TA) in between.

[0155] In some embodiments, the lengths of the first scan line (SLa) and the second scan line (SLb) placed on the same line are substantially equal, and the lengths of the first light emission control line (ELa) and the second light emission control line (ELb) placed on the same line may be substantially equal.

[0156] In some embodiments, the number of pixels connected to the first scan line (SLa) and the number of pixels connected to the second scan line (SLb) may be the same.

[0157] In some embodiments, the load applied to the first scan line (SLa) and the load applied to the second scan line (SLb) may be substantially provided.

[0158] In such structures, even if the first scan line (SLa) and the second scan line (SLb) are not connected to each other, there may be no delay in the scan signal between the pixels located on the left side of the transmission area (TA) and the pixels located on the right side of the transmission area (TA).

[0159] That is, in the present embodiment, even if the first scan lines (SLa) positioned to the left of the transmission area (TA) and the second scan lines (SLb) positioned to the right of the transmission area (TA) are not connected, a high-quality image can be realized in the display area (DA). Similarly, the first light emission control line (ELa) and the second light emission control line (ELb) may not be connected to each other.

[0160] If the scan lines around the transmission area (TA) are not disconnected around the transmission area (TA) but are arranged to bypass the transmission area (TA), the number of wires arranged in the first non-display area (NDA1) increases, and accordingly, the area of ​​the first non-display area (NDA1) may increase. However, in the present embodiment, the area of ​​the first non-display area (NDA1) can be reduced by not connecting at least some of the signal lines arranged to the left of the transmission area (TA) and the signal lines arranged to the right.

[0161] Meanwhile, the first data line (DLa) positioned above the transmission area (TA) may be spaced apart from the second data line (DLb) positioned below the transmission area (TA) with the transmission area (TA) in between. The first data lines (DLa) and the second data lines (DLb) positioned on the same line along the second direction may be connected by connecting wires (CL).

[0162] These connecting wires (CL) may be placed in a first non-display area (NDA) surrounding a transparent area (TA). The connecting wires (CL) may extend along a second direction (Y direction) to connect a first data line (DLa) and a second data line (DLb), but may bypass along the edge of the transparent area (TA) from the first non-display area (NDA1).

[0163] For example, if the transmission area (TA) is provided in a circular shape, the connecting wires (CL) may be provided to be curved with curvature along the edge of the transmission area (TA). Although the connecting wires (CL) are depicted in the drawing as arc curves, the bypass portion may be provided as a zigzag bent line.

[0164] The first data line (DLa) and the second data line (DLb) are spaced apart from the transmission area (TA) to protect the pixels (P) from electrostatic discharge (ESD) that may occur near the transmission area (TA).

[0165] Electrostatic charges may accumulate around a transparent area (TA) that may include at least one opening, and there is a high probability that electrostatic discharge may occur. If the wiring placed around the transparent area (TA) is formed continuously as a single conductive layer, a large voltage due to electrostatic discharge may be directly applied to the pixels (P).

[0166] However, in this embodiment, the first vertical lines (VLa) and the second vertical lines (VLb) placed around the transmission area (TA) are connected by connecting lines (CL), thereby preventing a large voltage caused by electrostatic discharge from being directly applied to the pixels (P).

[0167] The connecting wires (CL) may include a first connecting wire (CL1) disposed on the same layer as at least one of the first horizontal wires (HLa). For example, the first connecting wire (CL1) may be disposed on the same layer as the first wire (WL1) described with reference to FIGS. 6a to 6c. That is, the first connecting wire (CL1) may be disposed on the same layer as the first gate electrode (G1) of the first thin-film transistor (TFT1).

[0168] In some embodiments, the connecting wires (CL) may further include a second connecting wire (CL2) disposed on a different layer from the first connecting wire (CL1). For example, the second connecting wire (CL2) may be disposed on the same layer as the second wire (WL2) described with reference to FIGS. 6a through 6c. That is, the second connecting wire (CL2) may be disposed on the same layer as the second electrode (CE2) of the storage capacitor (Cst).

[0169] In another embodiment, the first connecting wire (CL1) may be placed on the same layer as any one of the second wire (WL2) to the sixth wire (WL6), and the second connecting wire (CL2) may be placed on the same layer as the wire placed on a different layer from the first connecting wire (CL1) among the first wire (WL1) to the sixth wire (WL6).

[0170] The second connecting wire (CL2) may be placed on the same floor as at least one of the first horizontal wires (HLa). That is, some of the first horizontal wires (HLa) may be placed on the same floor as the first connecting wire (CL1), and some of the first horizontal wires (HLa) may be placed on the same floor as the second connecting wire (CL2).

[0171] In some embodiments, the first scan line (SLa) may be placed on the same floor as the first connecting wire (CL1), and the first light-emitting control line (ELa) may be placed on the same floor as the second connecting wire (CL2). In some embodiments, some of the first scan lines (SLa) may be placed on the same floor as the first connecting wire (CL1), and other parts may be placed on the same floor as the second connecting wire (CL2).

[0172] These first connecting wires (CL1) and second connecting wires (CL2) can be arranged alternately in the first non-display area (NDA1). Since the first connecting wires (CL1) and second connecting wires (CL2) are arranged on different layers, the spacing between the first connecting wires (CL1) and second connecting wires (CL2) can be narrowed, thereby reducing the area of ​​the first non-display area (NDA1).

[0173] FIGS. 8A and 8B are schematic cross-sectional views illustrating an embodiment corresponding to the line II-II' of FIG. 7. In FIGS. 8A and 8B, the same reference numerals as in FIG. 6A refer to the same components, so a redundant description is omitted.

[0174] Referring to FIG. 8a, the first connecting wire (CL1) may be placed on the first gate insulating layer (112), and the second connecting wire (CL2) may be placed on the second gate insulating layer (113). That is, the second gate insulating layer (113) may be placed between the first connecting wire (CL1) and the second connecting wire (CL2). The first connecting wire (CL1) and the second connecting wire (CL2) may be placed alternately in the first non-display area (NDA1). Although the drawings show the first connecting wire (CL1) and the second connecting wire (CL2) as not overlapping, in some embodiments, the first connecting wire (CL1) and the second connecting wire (CL2) may be placed so as to overlap.

[0175] The first data wiring (DLa), which is the first vertical wiring (VLa), can be placed on the interlayer insulation layer (114). In this case, the first data wiring (DLa) can be connected to the connecting wiring (CL) through a contact hole (CNT) that penetrates the interlayer insulation layer (114).

[0176] In some embodiments, the first data line (DLa) and the connection line (CL) may be connected through a bridge metal (BM) placed on a different layer.

[0177] For example, as illustrated in FIG. 8b, the bridge metal (BM) may be placed on the first flattening layer (116) and connected to the connecting wire (CL) through a first contact hole (CNT1) penetrating the first flattening layer (116) and the interlayer insulation layer (114). Additionally, the bridge metal (BM) may be connected to the first data wire (DLa) through a second contact hole (CNT2) penetrating the first flattening layer (116). In some embodiments, the connecting wire (CL) and the first data wire (DLa) may be placed so as not to overlap.

[0178] FIGS. 9a and 9b are plan views showing a portion of a display device according to some embodiments. Specifically, they show the area around the transmission region (TA). In FIGS. 9a and 9b, the same reference numerals as in FIG. 7 refer to the same components, so a redundant description is omitted.

[0179] Referring to FIG. 9a, the display device may further include a third horizontal line (SLc) that extends in a first direction from a display area (DA) and bypasses a transmission area (TA). The third horizontal line (SLc) may be a scan line that transmits a scan signal or a light emission control line that transmits a light emission control signal.

[0180] The third horizontal wiring (SLc) can be placed on a different floor from the connecting wiring (CL).

[0181] In some embodiments, the third horizontal wiring (SLc) may be placed on the same layer as the first wiring (WL1) described with reference to FIGS. 6a through 6c, and the connecting wiring (CL) may be placed on the same layer as the second wiring (WL2). In other embodiments, the third horizontal wiring (SLc) may be placed on the same layer as the second wiring (WL2) described with reference to FIGS. 6a through 6c, and the connecting wiring (CL) may be placed on the same layer as the first wiring (WL1).

[0182] In some embodiments, the connecting wires (CL) may include connecting wires (CL) placed on different floors. For example, when the third horizontal wire (SLc) is placed on the same floor as the first wire (WL1), some of the connecting wires (CL) may be placed on the same floor as the second wire (WL2), and other parts may be placed on the same floor as the third wire (WL3).

[0183] Referring to FIG. 9b, the display device may further include a horizontal connecting wire (HCL) connecting at least one of the first horizontal wires (SLa) and at least one of the second horizontal wires (SLb).

[0184] The wiring connected by the horizontal connection wiring (HCL) may be a scan line that transmits a scan signal. Alternatively, the wiring connected by the horizontal connection wiring (HCL) may be a light emission control line that transmits a light emission control signal.

[0185] In some embodiments, the horizontal-connecting wire (HCL) is placed on a different layer from the first horizontal wire (HLa) and the second horizontal wire (HLb) and can be connected to the first horizontal wire (HLa) and the second horizontal wire (HLb) through a contact hole.

[0186] In another embodiment, the horizontal connecting wire (HCL) can be connected to the first horizontal wire (HLa) and the second horizontal wire (HLb) through a bridge metal. In this case, the horizontal connecting wire (HCL) can be placed on the same layer as the first horizontal wire (HLa).

[0187] In some embodiments, the horizontal-connecting wiring (HCL) may be placed on the same layer as the first wiring (WL1) or second wiring (WL2) described with reference to FIGS. 6a through 6c.

[0188] FIG. 10 is a plan view showing a part of a display device according to some embodiment, and FIG. 11 shows a cross-section corresponding to the line III-III' of FIG. 10. In FIG. 10 and FIG. 11, the same reference numerals as in FIG. 7 and FIG. 6a refer to the same components, so a redundant description is omitted.

[0189] Referring to FIGS. 10 and 11, the display device may further include an electrode layer (PM) surrounding a transmission area (TA). The electrode layer (PM) may be connected to a horizontal driving voltage line (PLa) extending in a first direction. Additionally, the electrode layer (PM) may be connected to a vertical driving voltage line (PLb) extending in a second direction.

[0190] A horizontal driving voltage line (PLa) and / or a vertical driving voltage line (PLb) can transmit a driving voltage (ELVDD) to a plurality of pixels (P). The horizontal driving voltage line (PLa) may extend from the second electrode (CE2) of the storage capacitor (Cst). The vertical driving voltage line (PLb) may extend from the first power supply line (160, see FIG. 4) outside the display area (DA). The horizontal driving voltage line (PLa) and the vertical driving voltage line (PLc) may be formed on different layers and connected by contact holes. A mesh structure may be formed by a plurality of horizontal driving voltage lines (PLa) and a plurality of vertical driving voltage lines (PLc).

[0191] The electrode layer (PLM) may be arranged to overlap at least partially with a plurality of connecting wires (CL). Accordingly, the area of ​​the first non-display area (NDA1) can be reduced. In some embodiments, as shown in the drawings, the electrode layer (PLM) may be placed on the first flattening layer (116). In other embodiments, the electrode layer (PLM) may be placed on the interlayer insulation layer (114).

[0192] The electrode layer (PM) may be provided in a ring shape that surrounds the transmission region (TA). Since the driving voltage lines (PLa, PLb) on the left, right, top, and bottom of the transmission region (TA) can be connected by the electrode layer (PM), the driving voltage (ELVDD) can be provided uniformly around the transmission region (TA).

[0193] FIG. 12 is a plan view showing a part of a display device according to some embodiments. Specifically, it shows the area around the transmission region (TA). FIG. 13 is a schematic cross-sectional view corresponding to the line IV-IV' of FIG. 12. In FIG. 12, the same reference numerals as in FIG. 7 refer to the same components, so a redundant description is omitted.

[0194] Referring to FIG. 12, in this embodiment, a plurality of connecting wires (CL) may include a first connecting wire (CL1), a second connecting wire (CL2), a third connecting wire (CL3), and a fourth connecting wire (CL4) arranged on different layers.

[0195] In this case, the first connecting wire (CL1) may be placed on the same layer as at least one of the plurality of first horizontal wires (HLa). For example, the first connecting wire (CL1) may be placed on the same layer as the first wire (WL1) described with reference to FIGS. 6a to 6c. That is, the first connecting wire (CL1) may be placed on the same layer as the first gate electrode (G1) of the first thin-film transistor (TFT1).

[0196] The second connecting wire (CL2) is placed on a different layer from the first connecting wire (CL1), but may be placed on the same layer as at least one of the plurality of first horizontal wires (HLa). For example, the second connecting wire (CL2) may be placed on the same layer as the second wire (WL2) described with reference to FIGS. 6a to 6c. That is, the second connecting wire (CL2) may be placed on the same layer as the second electrode (CE2) of the storage capacitor (Cst).

[0197] The third connecting wire (CL3) may be placed on the same floor as at least one of the plurality of first vertical wires (VLa). For example, the third connecting wire (CL3) may be placed on the same floor as the third wire (WL3) described with reference to FIGS. 6a to 6c. That is, the third connecting wire (CL3) may be placed on the same floor as the data line (DL).

[0198] The fourth connecting wire (CL4) may be placed on a different layer from the first to third connecting wires (CL1 to CL3). For example, the fourth connecting wire (CL4) may be placed on the same layer as the fourth wire (WL4) described with reference to FIGS. 6b and 6c.

[0199] The positions of the first to fourth connecting wires (CL1 to CL4) can be varied. For example, the first to fourth connecting wires (CL1 to CL4) can be appropriately selected from the first to sixth wires (WL1 to WL6) described with reference to FIG. 6c.

[0200] The first to fourth connecting wires (CL1 to CL4) may be arranged in a repeating sequence, such as the first connecting wire (CL1), the fourth connecting wire (CL4), the second connecting wire (CL2), and the third connecting wire (CL3), in the direction from the transmission area (TA) to the display area (DA).

[0201] These connecting wires (CL) may be placed in a first non-display area (NDA) surrounding a transparent area (TA). The connecting wires (CL) may extend along a second direction (Y direction) to connect a first data line (DLa) and a second data line (DLb), but may bypass along the edge of the transparent area (TA) from the first non-display area (NDA1).

[0202] For example, if the transmission area (TA) is provided in a circular shape, the connecting wires (CL) may be provided to curve with curvature along the edge of the transmission area (TA). In this case, the connecting wires (CL) positioned closer to the transmission area (TA) may curve with a larger curvature along the edge of the transmission area (TA), and the curvature of the connecting wires (CL) may decrease as they move further away from the transmission area (TA). Meanwhile, although the connecting wires (CL) are depicted in the drawing as arc curves, the bypassed portion may be provided as a zigzag bent line.

[0203] Multiple connecting wires (CL) may include areas that overlap each other.

[0204] Referring to FIG. 13, the third connecting wire (CL3) may be positioned in a plane between the first connecting wire (CL1) and the second connecting wire (CL2). In this case, the third connecting wire (CL3) may have an area that overlaps with a part of the first connecting wire (CL1) and a part of the second connecting wire, respectively.

[0205] The fourth connecting wire (CL4) may be positioned between the first connecting wire (CL1) and the second connecting wire (CL2) on a plane. In this case, it may have an area that overlaps with a part of the first connecting wire (CL1) and a part of the second connecting wire (CL2), respectively.

[0206] For example, the first connecting wire (CL1) may have a first overlap length (OL1) with the second connecting wire (CL3). The first overlap length (OL1) may have a length of about 15 to 35% of the width (Wt1) of the first connecting wire (CL1). In some embodiments, the width (Wt1) of the first connecting wire (CL1) may be about 1.5 µm to 3 µm, and the first overlap length (OL1) may be about 0.5 µm to about 1 µm.

[0207] The first connecting wire (CL1) may have a second overlapping length (OL2) with the fourth connecting wire (CL4). The second overlapping length (OL2) may have a length of about 15 to 35% of the width (Wt1) of the first connecting wire (CL1). In some embodiments, the width (Wt1) of the first connecting wire (CL1) may be about 1.5 µm to 3 µm, and the second overlapping length (OL2) may be about 0.5 µm to about 1 µm.

[0208] The second connecting wire (CL2) may have a third overlapping length (OL3) with the fourth connecting wire (CL4). The third overlapping length (OL3) may have a length of about 15 to 35% of the width (Wt2) of the second connecting wire (CL2). In some embodiments, the width (Wt2) of the second connecting wire (CL2) may be about 1.5 µm to 3 µm, and the third overlapping length (OL3) may be about 0.5 µm to about 1 µm.

[0209] The second connecting wire (CL2) may have a third connecting wire (CL3) and a fourth overlapping length (OL4). The fourth overlapping length (OL4) may have a length of about 15 to 35% of the width (Wt2) of the second connecting wire (CL2). In some embodiments, the width (Wt2) of the second connecting wire (CL2) may be about 1.5 µm to 3 µm, and the fourth overlapping length (OL4) may be about 0.5 µm to 1 µm.

[0210] In some embodiments, the spacing along the upper surface of the substrate (110) of the first connecting wire (CL1) and the second connecting wire (CL2) may be about 0.5 µm to 1 µm.

[0211] In some embodiments, the spacing along the upper surface of the substrate (110) of the third connecting wire (CL3) and the fourth connecting wire (CL4) may be about 0.5 µm to 1 µm.

[0212] As multiple connecting wires (CL) have overlapping areas, the area of ​​the non-display area (NDA1) can be reduced.

[0213] FIGS. 14 and 15 are plan views showing a part of a display device according to some embodiments. Specifically, they show the area around a transparent region (TA). In FIGS. 14 and 15, the same reference numerals as in FIG. 12 refer to the same components, so a redundant description is omitted.

[0214] Referring to FIG. 14, at least one of the first horizontal wires (HLa) and at least one of the second horizontal wires (HLb) may be connected by a horizontal connecting wire (HCL). The horizontal connecting wire (HCL) may be placed on the same floor as the first wire (WL1). In this case, a plurality of connecting wires (CL) may be provided as connecting wires (CL) placed on a different floor from the horizontal connecting wire (HCL). For example, the plurality of connecting wires (CL) may be composed of a second connecting wire (CL2), a third connecting wire (CL3), and a fourth connecting wire (CL4).

[0215] In addition, a third horizontal wiring (not shown) extending from the display area (DA) and bypassing the transmission area (TA) may be further included.

[0216] Referring to FIG. 15, a plurality of connecting wires (CL) may include a first connecting wire (CL1), a second connecting wire (CL2), a third connecting wire (CL3), a fourth connecting wire (CL4), a fifth connecting wire (CL5), and a sixth connecting wire (CL6) arranged on different layers.

[0217] The fifth connecting wire (CL5) and the sixth connecting wire (CL6) may be placed on a different layer from the first to fourth connecting wires (CL1 to CL4). For example, the fifth connecting wire (CL5) may be placed on the same layer as the fifth wire (WL5) described with reference to FIG. 6c. The sixth connecting wire (CL6) may be placed on the same layer as the sixth wire (WL6) described with reference to FIG. 6c.

[0218] As described above, by using multiple connecting wires (CL) in various layers, the area of ​​the first non-display area (NDA1) can be reduced.

[0219] Meanwhile, at least one of the first horizontal wires (HLa) may be connected to at least one of the second horizontal wires (HLb). Additionally, a third horizontal wire may be further included, positioned to bypass the transparent area (TA) from the display area (DA).

[0220] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0221] 1: Display device 10: Display panel DA: Display area NDA1: 1st Non-display Area NDA2: Second Non-display Area TA: Transmission area HLa, HLb: Horizontal wiring VLa, VLb: Vertical wiring CL: Connection wiring PL: Driving voltage line DL: Data line

Claims

Claim 1 A substrate having a transparent area and a display area surrounding the transparent area; a plurality of display elements disposed in the display area; a plurality of first horizontal lines and a plurality of second horizontal lines extending along a first direction and spaced apart from each other with the transparent area in between; a plurality of first vertical lines and a plurality of second vertical lines extending along a second direction intersecting the first direction and spaced apart from each other with the transparent area in between; a first connecting line connecting at least one of the plurality of first vertical lines and at least one of the plurality of second vertical lines and bypassing the transparent area; A display device comprising: a bridge metal connecting the first connecting wire and at least one of the plurality of first vertical wires; wherein the bridge metal is connected to the first connecting wire through a first contact hole and connected to at least one of the plurality of first vertical wires through a second contact hole, and the first connecting wire is disposed on a first layer that is on the same layer as at least one of the plurality of first horizontal wires. Claim 2 A display device according to claim 1, comprising: a second connecting wire connecting at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires, and bypassing the transmission area; wherein the second connecting wire is disposed on a second layer different from the first layer. Claim 3 A display device according to paragraph 2, wherein the first connecting wire and the second connecting wire are provided in plurality, and the plurality of first connecting wires and the plurality of second connecting wires are alternately arranged around the periphery of the transmission area. Claim 4 A display device according to claim 1, wherein the first connecting wire is connected to at least one of the plurality of first vertical wires through a contact hole. Claim 5 delete Claim 6 A display device according to claim 1, further comprising a third horizontal wiring extending from the display area in the first direction and arranged to bypass the transparent area, wherein the third horizontal wiring is arranged on a layer different from the first layer. Claim 7 A display device according to claim 1, wherein at least one of the plurality of first horizontal wires is connected to at least one of the plurality of second horizontal wires through a horizontal-connecting wire. Claim 8 A display device according to claim 1, further comprising: an electrode layer arranged to surround the transmission area and arranged to overlap with the first connecting wire; a horizontal driving voltage line extending in the first direction; and a vertical driving voltage line extending in the second direction, wherein the horizontal driving voltage line and the vertical driving voltage line are connected to the electrode layer. Claim 9 delete Claim 10 A display device according to claim 1, comprising: a third connecting wire that connects at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires and bypasses the transmission area; wherein the third connecting wire is disposed on a third layer that is in the same layer as at least one of the plurality of first vertical wires. Claim 11 A display device according to claim 10, comprising: a fourth connecting wire connecting at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires and bypassing the transmission area; wherein the fourth connecting wire is disposed on a fourth layer different from the third layer. Claim 12 A display device according to claim 11, further comprising a horizontal connecting wire extending in the first direction and arranged to bypass the permeable area, wherein the horizontal connecting wire connects at least one of the plurality of first horizontal wires and at least one of the plurality of second horizontal wires. Claim 13 A display device according to claim 12, further comprising: a second connecting wire connecting at least one of the plurality of first vertical wires and at least one of the plurality of second vertical wires, and bypassing the transmission area; wherein at least one of the plurality of first horizontal wires is disposed on a second layer different from the first layer, and the second connecting wire is disposed on the second layer. Claim 14 A substrate having a transparent area, a display area surrounding the transparent area, and a non-display area between the transparent area and the display area; a plurality of display elements disposed in the display area; a plurality of first horizontal lines and a plurality of second horizontal lines extending along a first direction and spaced apart from each other with the transparent area in between; a plurality of first vertical lines and a plurality of second vertical lines extending along a second direction intersecting the first direction and spaced apart from each other with the transparent area in between; and a plurality of connecting lines disposed in the non-display area, each connecting at least one of the plurality of first vertical lines and at least one of the plurality of second vertical lines, and including a first connecting line, a second connecting line, a third connecting line, and a fourth connecting line disposed on different layers. A display device comprising: a plurality of bridge metals connecting each of the plurality of connecting wires and each of the plurality of first vertical wires; wherein each of the plurality of bridge metals is connected to each of the plurality of connecting wires through a first contact hole, and each of the plurality of bridge metals is connected to each of the plurality of first vertical wires through a second contact hole, wherein the first connecting wire is disposed on a first layer that is on the same layer as at least one of the plurality of first horizontal wires, and the plurality of connecting wires are provided curved along the edge of the transmission area, and the curvature of the plurality of connecting wires is provided differently depending on the distance from the transmission area. Claim 15 A display device according to claim 14, wherein a thin-film transistor having a first semiconductor layer and a first gate electrode is disposed in the display area, and the first connecting wire is disposed in the same layer as the first gate electrode. Claim 16 In claim 15, a storage capacitor comprising a first electrode disposed on the same layer as the first gate electrode and a second electrode disposed on the upper side of the first electrode is disposed in the display area, and the second connecting wire is disposed on the same layer as the second electrode, a display device. Claim 17 In paragraph 14, the display device wherein the third connecting wire is disposed on a third layer that is on the same layer as at least one of the plurality of first vertical wires. Claim 18 A display device according to claim 14, wherein the third connecting wire has an area that overlaps with a part of the first connecting wire and a part of the second connecting wire, respectively, between the first connecting wire and the second connecting wire on a plane. Claim 19 A display device according to claim 14, wherein the fourth connecting wire has an area that overlaps with a part of the first connecting wire and a part of the second connecting wire, respectively, between the first connecting wire and the second connecting wire on a plane. Claim 20 A display device according to claim 14, wherein the plurality of connecting wires further include a fifth connecting wire disposed on a different layer from the first connecting wire, the second connecting wire, the third connecting wire, and the fourth connecting wire.

Images