Pixel and display apparatus comprising the same

Abstract

The present invention relates to a pixel with improved device characteristics and defects through structural improvement of a pixel circuit, and to a display device having the same, comprising: a substrate including a display area where pixel circuits are located; a first active layer located on the substrate and including a first source area, a first active area located adjacent to the first source area, and a first drain area located adjacent to the first active area; a first gate layer located on a layer covering the first active layer and including a first gate electrode that overlaps with the first active area; a second gate layer located on a layer covering the first gate layer and including an initial line extending in a first direction and having a fourth gate electrode; a second active layer located on a layer covering the second gate layer and including a fourth active area that overlaps with the fourth gate electrode; a third gate layer located on a layer covering the second active layer and including a fourth gate electrode that overlaps with the fourth active area and has an isolated shape. A display device is provided having a first source drain layer located on a layer covering the third gate layer and including a first connecting wire extended in the first direction.

Description

Technology Field

[0001] Embodiments of the present invention relate to a pixel and a display device having the same, and more specifically, to a pixel with improved element characteristics and defects and a display device having the same. Background Technology

[0002] Among display devices, organic light-emitting diode (OLED) displays are attracting attention as next-generation display devices due to their advantages, including a wide viewing angle, excellent contrast, and fast response speed.

[0003] Generally, organic light-emitting display devices form thin-film transistors and organic light-emitting diodes on a substrate, and operate by the organic light-emitting diodes emitting light themselves. Such organic light-emitting display devices are used as display units for small products, such as mobile phones, or for large products, such as televisions.

[0004] Meanwhile, such a display device includes a thin film transistor (TFT), a capacitor, etc. for driving. Here, the thin film transistor may include a semiconductor layer comprising an active region, a source region, and a drain region, and a gate electrode that is electrically insulated from the semiconductor layer by a gate insulating layer. The problem to be solved

[0005] However, these conventional display devices had a problem in that defects could occur due to changes in device characteristics caused by structural issues with the pixel circuit.

[0006] Embodiments of the present invention are intended to solve various problems, including those described above, and can provide a pixel with improved device characteristics and defects through structural improvement of the pixel circuit, and a display device equipped with the same. However, these problems are exemplary and the scope of the present invention is not limited by them. means of solving the problem

[0007] According to one aspect of the present invention, a substrate including a display area where pixel circuits are located; a first active layer located on the substrate and including a first source area, a first active area located adjacent to the first source area, and a first drain area located adjacent to the first active area; a first gate layer located on a layer covering the first active layer and including a first gate electrode that overlaps with the first active area; a second gate layer located on a layer covering the first gate layer and including an initial line extending in a first direction and having a fourth gate electrode; a second active layer located on a layer covering the second gate layer and including a fourth active area that overlaps with the fourth gate electrode; a third gate layer located on a layer covering the second active layer and including a fourth gate electrode that overlaps with the fourth active area and has an isolated shape; and a fourth gate electrode located on a layer covering the third gate layer and extending in the first direction A display device is provided having a first source drain layer including a first connecting wire.

[0008] According to the present embodiment, the first connecting wire may not overlap with the 4-1 gate electrode and the 4-2 gate electrode.

[0009] According to the present embodiment, the 4-1 gate electrode and the 4-2 gate electrode can be electrically connected through a first gate contact hole formed in a layer interposed between the second gate layer and the third gate layer.

[0010] According to the present embodiment, the first gate contact hole exposes the upper surface of the fourth-1 gate electrode and includes an inner surface that is inclined with the upper surface of the fourth-1 gate electrode, and the fourth-2 gate electrode can cover the upper surface of the fourth-1 gate electrode exposed through the first gate contact hole and the inner surface.

[0011] According to the present embodiment, the diameter of the upper surface of the 4th-1st gate electrode exposed through the 1st gate contact hole may be smaller than the distance between the end of the 1st gate contact hole in the direction of the 4th active region and the end of the 4th active region in the direction of the 1st gate contact hole.

[0012] According to the present embodiment, the cross-sectional area of ​​the first gate contact hole parallel to the upper surface of the fourth-1 gate electrode may increase as it moves away from the fourth-1 gate electrode.

[0013] According to the present embodiment, the 4-2 gate electrode may have a portion extending from the portion located within the 1 gate contact hole and located on the layer covering the 2 active layer.

[0014] According to the present embodiment, the pixel circuits include a first pixel circuit and a second pixel circuit, and the first pixel circuit and the second pixel circuit may be symmetric with respect to a virtual axis passing between the first pixel circuit and the second pixel circuit.

[0015] According to the present embodiment, the 4-1 gate electrode of the first pixel circuit and the 4-1 gate electrode of the second pixel circuit are integral, the 4-2 gate electrode of the first pixel circuit and the 4-2 gate electrode of the second pixel circuit are integral, and the first gate contact hole may be located on the virtual axis.

[0016] According to the present embodiment, the third gate layer further includes a gate initialization voltage line extended in the first direction, and the first connection wiring can overlap with the gate initialization voltage line.

[0017] According to the present embodiment, the gate initialization voltage line can be electrically connected to the second active layer through a second gate contact hole formed in a layer covering the second active layer.

[0018] According to the present embodiment, a second source drain layer may be further provided, the second connecting wire being located on a layer covering the first source drain layer, extending in a second direction intersecting the first direction, and electrically connected to the first connecting wire.

[0019] According to the present embodiment, the first active layer may include a silicon semiconductor, and the second active layer may include an oxide semiconductor.

[0020] According to another aspect of the present invention, a pixel is provided comprising: an organic light-emitting diode, a first semiconductor layer comprising a silicon semiconductor, and a first gate electrode, wherein the first transistor controls the current flowing to the organic light-emitting diode in response to a voltage applied to the first gate electrode; a fourth semiconductor layer electrically connected to the first transistor and comprising an oxide semiconductor, a fourth-1 gate electrode located below the fourth semiconductor layer, and a fourth-2 gate electrode located above the fourth semiconductor layer and having an isolated shape; and the fourth-2 gate electrode, wherein the pixel comprises an initial line extending in a first direction and a first connection line extending in the first direction that does not overlap with the initial line.

[0021] According to the present embodiment, the first connecting wire may not overlap with the 4-1 gate electrode and the 4-2 gate electrode.

[0022] According to the present embodiment, the 4-1 gate electrode and the 4-2 gate electrode are electrically connected through a first gate contact hole, and the first gate contact hole exposes the upper surface of the 4-1 gate electrode and includes an inner surface that is inclined with the upper surface of the 4-1 gate electrode, and the 4-2 gate electrode can cover the upper surface of the 4-1 gate electrode exposed through the first gate contact hole and the inner surface.

[0023] According to the present embodiment, the diameter of the upper surface of the 4th-1st gate electrode exposed through the 1st gate contact hole may be smaller than the distance between the end of the 1st gate contact hole in the direction of the 4th active region of the 4th semiconductor layer and the end of the 4th active region in the direction of the 1st gate contact hole.

[0024] According to the present embodiment, the cross-sectional area of ​​the first gate contact hole parallel to the upper surface of the fourth-1 gate electrode may increase as it moves away from the upper surface of the fourth-1 gate electrode.

[0025] According to the present embodiment, the 4-2 gate electrode may have a portion that extends from the portion located within the 1st gate contact hole and is located on the layer covering the 4th semiconductor layer.

[0026] According to the present embodiment, a second connecting wire may be further provided that extends in a second direction intersecting the first direction and is electrically connected to the first connecting wire.

[0027] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention. Effects of the invention

[0028] According to one embodiment of the present invention as described above, a pixel with improved device characteristics and defects and a display device equipped with the same can be realized through the structural improvement of the pixel circuit. Of course, the scope of the present invention is not limited by such effects. Brief explanation of the drawing

[0029] FIG. 1 is a conceptual diagram schematically illustrating a display device according to one embodiment of the present invention. Figure 2 is an equivalent circuit diagram of a pixel included in the display device of Figure 1. FIG. 3 is a schematic layout diagram illustrating the pixel circuits included in the display device of FIG. 1. FIGS. 4 to 10 are layout diagrams schematically illustrating the pixel circuits of FIG. 3 layer by layer. Figure 11 is a layout diagram showing only some of the layers of Figure 3. FIG. 12 is a cross-sectional view taken along the line I-I' of FIG. 3. FIG. 13 is a cross-sectional view taken along the line II-II' of FIG. 3. Specific details for implementing the invention

[0030] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0032] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0033] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0034] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0035] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0036] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0037] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0038] In this specification, “A and / or B” indicates the case where it is A, B, or both A and B. And, “at least one of A and B” indicates the case where it is A, B, or both A and B.

[0039] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0040] In the following embodiments, the meaning of "extending in a first direction or a second direction" includes not only extending in a straight line shape, but also extending in a zigzag or curved shape along the first direction or the second direction.

[0041] In the following embodiments, "overlapping" of the first component with the second component means that the first component is located above or below the second component.

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0043] FIG. 1 is a conceptual diagram schematically illustrating a display device according to one embodiment of the present invention.

[0044] The organic light-emitting display device according to the present embodiment may be implemented as an electronic device such as a smartphone, mobile phone, navigation device, game console, TV, vehicle head unit, notebook computer, laptop computer, tablet computer, PMP (Personal Media Player), PDA (Personal Digital Assistants), etc. In addition, the electronic device may be a flexible device.

[0045] Hereinafter, an organic light-emitting display device including an organic light-emitting diode is described as an example according to one embodiment of the present invention, but is not limited thereto. The light-emitting diode of the display device may be an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN diode including inorganic semiconductor-based materials. When a forward voltage is applied to a PN junction diode, holes and electrons are injected, and the energy generated by the recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. The aforementioned inorganic light-emitting diode may have a width of several to several hundred micrometers, and in some embodiments, the inorganic light-emitting diode may be referred to as a micro LED.

[0046] As illustrated in FIG. 1, the display device according to the present embodiment may include a display area (DA) including pixels (PX), a scan driver (SD), a data driver (DD), and a timing controller (TC) for controlling the scan driver (SD) and the data driver (DD).

[0047] The scan driver (SD) supplies scan signals (GW[1] to GW[n]), initialization signals (GI[1] to GI[n]), compensation control signals (GC[1] to GC[n]), and light emission control signals (EM[1] to EM[n]) to gate signal lines extended in the first direction (DR1) under the control of the timing controller (TC). For example, the scan driver (SD) sequentially supplies scan signals (GW[1] to GW[n]), initialization signals (GI[1] to GI[n]), compensation control signals (GC[1] to GC[n]), and light emission control signals (EM[1] to EM[n]) to each of the scan lines, initialization lines, compensation control lines, and light emission control lines.

[0048] The data driver (DD) supplies data signals (D[1] to D[m]) to data lines extended in the second direction (DR2) under the control of the timing controller (TC). The data driver (DD) supplies data signals (D[1] to D[m]) so as to be synchronized with scan signals (GW[1] to GW[n]), and accordingly, the data signals (D[1] to D[m]) are supplied to pixels (PX) selected by the scan signals (GW[1] to GW[n]).

[0049] The timing controller (TC) controls the scan driver (SD) and data driver (DD) in response to synchronization signals supplied from the outside.

[0050] Power supply voltage (ELVDD) and electrode voltage (ELVSS) are supplied to pixels (PX) within the display area (DA). Pixels (PX) supplied with power supply voltage (ELVDD) and electrode voltage (ELVSS) control the amount of current flowing from the driving voltage line through the organic light-emitting diode to the electrode power line in response to data signals (D[1] to D[m]), thereby generating light of brightness corresponding to the data signals (D[1] to D[m]). Power supply voltage (ELVDD) is applied to the driving voltage line, and electrode voltage (ELVSS) is applied to the electrode power line.

[0051] In FIG. 1, pixels (PX) are shown arranged sequentially along a first direction (DR1) and a second direction (DR2) within a display area (DA), but the present invention is not limited thereto. For example, pixels (PX) can be arranged in various forms, such as a pentile arrangement or a mosaic arrangement, in addition to a stripe arrangement. Also, in FIG. 1, the display area (DA) is shown as a rectangular shape in the layout diagram, but it is not limited thereto. For example, the display area (DA) may have a polygonal shape such as a triangle, pentagon, or hexagon, or a circular, elliptical, or irregular shape.

[0052] Figure 2 is an equivalent circuit diagram of a pixel included in the display device of Figure 1.

[0053] Referring to FIG. 2, a pixel (PX) includes a first transistor (T1) through a seventh transistor (T7), a storage capacitor (Cst), an organic light-emitting diode (OLED), a gate initialization voltage line (VIL1), an anode initialization voltage line (VIL2), a driving voltage line (PL), and signal lines. The signal lines may include a data line (DL), a scan line (SL), an initialization line (IL), a compensation control line (CL), and a light emission control line (EL). At least one of the signal lines, the gate initialization voltage line (VIL1), the anode initialization voltage line (VIL2), and / or the driving voltage line (PL), may be shared among neighboring pixels.

[0054] The driving voltage line (PL) can transmit a power supply voltage (ELVDD) to the first transistor (T1). The gate initialization voltage line (VIL1) can transmit a first initialization voltage (Vint1) that initializes the first transistor (T1) to the pixel (PX). The anode initialization voltage line (VIL2) can transmit a second initialization voltage (Vint2) that initializes the organic light-emitting diode (OLED) to the pixel (PX).

[0055] In FIG. 2, among the first transistor (T1) to the seventh transistor (T7), the third transistor (T3) and the fourth transistor (T4) are implemented as NMOS (n-channel MOSFET), and the rest are implemented as PMOS (p-channel MOSFET), but are not limited thereto.

[0056] The first transistor (T1) may be a driving transistor. The first transistor (T1) is connected to the driving voltage line (PL) via the fifth transistor (T5) and is electrically connected to the organic light-emitting diode (OLED) via the sixth transistor (T6). A driving current (I) receives a data signal (D[j]) according to the voltage applied to the first gate electrode (G1) and flows from the node connected to the driving voltage line (PL) to the electrode power line via the organic light-emitting diode (OLED). OLED Controls the amount of ).

[0057] The second transistor (T2) may be a switching transistor. The second transistor (T2) is connected to the scan line (SL) and the data line (DL), and is connected to the driving voltage line (PL) via the fifth transistor (T5). The second transistor (T2) of the i-th row among a total of n rows is turned on according to the scan signal (GW[i]) received through the scan line (SL), and performs a switching operation to transmit the data signal (D[j]) transmitted to the data line (DL) of the j-th column among a total of m columns to the node connected to the first transistor (T1). Here, i is a natural number greater than or equal to 1 and less than or equal to n, and j is a natural number greater than or equal to m.

[0058] The third transistor (T3) may be a compensation control transistor. The third transistor (T3) is connected to the compensation control line (CL) and is connected to the organic light-emitting diode (OLED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the compensation control signal (GC[i]) received through the compensation control line (CL) to diode-connect the first transistor (T1).

[0059] The fourth transistor (T4) may be a gate initialization transistor. The fourth transistor (T4) is connected to an initialization line (IL) and a gate initialization voltage line (VIL1), and is turned on according to an initialization signal (GI(i)) received through the initialization line (IL) to transmit a first initialization voltage (Vint1) from the gate initialization voltage line (VIL1) to the first gate electrode of the first transistor (T1) to initialize the voltage of the first gate electrode of the first transistor (T1).

[0060] The fifth transistor (T5) may be an operation control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are connected to a light emission control line (EL), and are simultaneously turned on according to a light emission control signal (EM[i]) received through the light emission control line (EL), thereby transmitting a driving current (I) from the driving voltage line (PL) toward the organic light-emitting diode (OLED). OLED Forms a current path so that ) can flow.

[0061] The seventh transistor (T7) may be an anode initialization transistor. The seventh transistor (T7) is connected to the light emission control line (EL) and the anode initialization voltage line (VIL2), and is turned on according to the light emission control signal (EM[n]) received through the light emission control line (EL) to transmit the second initialization voltage (Vint2) from the anode initialization voltage line (VIL2) to the organic light emission diode (OLED) to initialize the organic light emission diode (OLED). The seventh transistor (T7) may be omitted.

[0062] The storage capacitor (Cst) includes a lower electrode (CE1) and an upper electrode (CE2). The lower electrode (CE1) is connected to the first gate electrode of the first transistor (T1), and the upper electrode (CE2) is connected to the driving voltage line (PL). At this time, the lower electrode (CE1) may be integral with the first gate electrode. The storage capacitor (Cst) can maintain the voltage applied to the first gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages of the driving voltage line (PL) and the first gate electrode of the first transistor (T1).

[0063] An organic light-emitting diode (OLED) has a pixel electrode, a counter electrode, and an intermediate layer interposed between them and including a light-emitting layer. An electrode voltage (ELVSS) is applied to the counter electrode formed integrally in a plurality of pixels. The organic light-emitting diode (OLED) receives a driving current (I) from a first transistor (T1). OLED By receiving and emitting light, the display device is enabled to display an image. For reference, the counter electrode extends outward from the display area and is connected to the electrode power line, and an electrode voltage (ELVSS) is applied to the electrode power line.

[0064] FIG. 3 is a schematic layout diagram illustrating pixel circuits included in the display device of FIG. 1.

[0065] Figure 3 illustrates a pair of pixel circuits arranged in the same row of adjacent columns. For reference, the organic light-emitting diode (OLED) is omitted from the illustration in Figure 3 for convenience. The pixel circuits (PCs) can be arranged to form a matrix along the D1 and D2 directions, and Figure 3 illustrates a pair of pixel circuits (PC1, PC2) arranged in the same row of adjacent columns.

[0066] In one embodiment, as shown in FIG. 3, the first pixel circuit (PC1) positioned on the left and the second pixel circuit (PC2) positioned on the right may have a left-right symmetric structure. That is, the first pixel circuit (PC1) and the second pixel circuit (PC2) may be symmetric with respect to a virtual axis (AX) passing between them.

[0067] Each pixel circuit includes the aforementioned first transistor (T1) to seventh transistor (T7) and storage capacitor (Cst).

[0068] Each of the first transistor (T1) to the seventh transistor (T7) includes a semiconductor layer and a gate electrode that overlaps with the active region of the semiconductor layer. Additionally, each of the semiconductor layers of the first transistor (T1) to the seventh transistor (T7) includes a semiconductor layer having a source region, an active region located adjacent to the source region, and a drain region located adjacent to the active region.

[0069] In one embodiment, at least one of the first transistor (T1) to the seventh transistor (T7) comprises a semiconductor layer comprising an oxide semiconductor, and the others comprise a semiconductor layer comprising a silicon semiconductor. For example, the first transistor (T1), which directly affects the brightness of the display device, is provided with a semiconductor layer comprising polycrystalline silicon having high reliability, thereby enabling the implementation of a high-resolution display device.

[0070] Meanwhile, since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even during long driving times. That is, in the case of a thin-film transistor containing an oxide semiconductor, the change in image color due to voltage drop is not significant even during low-frequency driving. As such, oxide semiconductors have the advantage of low leakage current. For example, at least one of the third transistor (T3) and the fourth transistor (T4) connected to the first gate electrode of the first transistor (T1) can be made to contain an oxide semiconductor, thereby preventing leakage current from flowing to the first gate electrode of the first transistor (T1) while simultaneously reducing power consumption.

[0071] As a specific example, the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be provided as transistors including silicon semiconductors, that is, the semiconductor layers of each of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are formed to be included in the first active layer (AL1) including polycrystalline silicon semiconductors, thereby being placed in the same layer and including the same material.

[0072] Additionally, the third transistor (T3) and the fourth transistor (T4) may be provided as transistors including an oxide semiconductor. Each semiconductor layer of the third transistor (T3) and the fourth transistor (T4) is formed to be included in the second active layer (AL2) including an oxide semiconductor, thereby being disposed in the same layer and containing the same material.

[0073] The semiconductor layer comprising the first active layer (AL1) and the second active layer (AL2) is connected to each other and can be bent into various shapes. For example, by having a part of the semiconductor layer bent into a shape such as 'C', 'Omega (Ω)', 'S', 'M', 'W', etc., a long channel length can be formed within a narrow space. Through this, the active region of the transistors is formed long, thereby widening the driving range of the gate voltage applied to the gate electrode. Accordingly, the gradation of light emitted from the organic light-emitting diode (OLED) can be controlled more precisely, and the display quality can be improved. Of course, if necessary, a part of the semiconductor layer may have a straight shape rather than a bent shape.

[0074] The first transistor (T1) includes a first semiconductor layer and a first gate electrode (G1). The first semiconductor layer includes a first active region (A1), a first source region (S1) and a first drain region (D1) on both sides of the first active region (A1). The first gate electrode (G1) is formed to have an isolated shape and is configured to overlap the first active region (A1) and the first gate insulating film (103, see FIG. 12) with the first active region (A1) in between.

[0075] The storage capacitor (Cst) can be positioned overlapping with the first transistor (T1). The first capacitor (Cst) includes a lower electrode (CE1) and an upper electrode (CE2). The first gate electrode (G1) can perform the function of a control electrode for the first transistor (T1) as well as the function of a lower electrode (CE1) for the storage capacitor (Cst). That is, the first gate electrode (G1) and the lower electrode (CE1) can be formed as a single unit. The upper electrode (CE2) of the storage capacitor (Cst) is provided to overlap with the lower electrode (CE1) and the second gate insulating film (105, see FIG. 12) in between. At this time, the second gate insulating film can serve as the dielectric layer of the storage capacitor (Cst).

[0076] The second transistor (T2) includes a second semiconductor layer and a second gate electrode (G2). The second semiconductor layer includes a second active region (A2), a second source region (S2) and a second drain region (D2) on both sides of the second active region (A2). The second source region (S2) is electrically connected to a data line (DL), and the second drain region (D2) is connected to a first source region (S1). The second gate electrode (G2) overlaps with the second active region (A2) and may be provided as part of a scan line (SL).

[0077] The fifth transistor (T5) includes a fifth semiconductor layer and a fifth gate electrode (G5). The fifth semiconductor layer includes a fifth active region (A5), a fifth source region (S5) on both sides of the fifth active region (A5), and a fifth drain region (D5). The fifth source region (S5) is electrically connected to a driving voltage line (PL), and the fifth drain region (D5) may be connected to a first source region (S1). The fifth gate electrode (G5) overlaps with the fifth active region (A5) and may be provided as part of a light emission control line (EL).

[0078] The sixth transistor (T6) includes a sixth semiconductor layer and a sixth gate electrode (G6). The sixth semiconductor layer includes a sixth active region (A6), a sixth source region (S6) on both sides of the sixth active region (A6), and a sixth drain region (D6). The sixth source region (S6) is connected to the first drain region (D1), and the sixth drain region (D6) can be electrically connected to the pixel electrode of an organic light-emitting diode (OLED). The sixth gate electrode (G6) overlaps with the sixth active region (A6) and can be provided as part of a light-emitting control line (EL).

[0079] The seventh transistor (T7) includes a seventh semiconductor layer and a seventh gate electrode (G7). The seventh semiconductor layer includes a seventh active region (A7), a seventh source region (S7) on both sides of the seventh active region (A7), and a seventh drain region (D7). The seventh source region (S7) may be electrically connected to an anode initialization voltage line (VIL2), and the seventh drain region (D7) may be connected to a sixth drain region (D6). The seventh gate electrode (G7) overlaps with the seventh active region (A7) and may be provided as part of the initialization line (IL).

[0080] A second gate insulating film (105, see FIG. 12) is located on the first, second, fifth to seventh transistors (T1, T2, T5, T6, T7) comprising silicon semiconductors, and a third transistor (T3) and a fourth transistor (T4) may be located on the second gate insulating film.

[0081] The semiconductor layers of the third transistor (T3) and the fourth transistor (T4), respectively, are placed on the same layer and contain the same material. For example, the semiconductor layers of the third transistor (T3) and the fourth transistor (T4), respectively, can be formed to be included in the second active layer (AL2) containing an oxide semiconductor.

[0082] The third transistor (T3) includes a third semiconductor layer comprising an oxide semiconductor and a third gate electrode (G3). The third semiconductor layer includes a third active region (A3), and a third source region (S3) and a third drain region (D3) on both sides of the third active region (A3). The third source region (S3) can be bridge-connected to the first gate electrode (G1) through a bridge electrode. Additionally, the third source region (S3) can be connected to a fourth drain region (D4) disposed in the same layer. The third drain region (D3) can be electrically connected to the first semiconductor layer of the first transistor (T1) and the sixth semiconductor layer of the sixth transistor (T6). Meanwhile, the third transistor (T3) may have a dual-gate structure having control electrodes on the upper and lower sides of the third semiconductor layer, respectively. Specifically, the third gate electrode (G3) may include a third-1 gate electrode (G3-1) located on a layer covering the first gate layer (GL1) and provided as part of a compensation control line (CL), and a third-2 gate electrode (G3-2) located on a layer covering the second active layer (AL2) and provided as part of an anode initialization voltage line (GIL2).

[0083] The fourth transistor (T4) includes a fourth semiconductor layer comprising an oxide semiconductor and a fourth gate electrode (G4). The fourth semiconductor layer includes a fourth active region (A4), a fourth source region (S4) on both sides of the fourth active region (A4), and a fourth drain region (D4). The fourth source region (S4) may be electrically connected to a gate initialization voltage line (VIL1), and the fourth drain region (D4) may be bridge-connected to the first gate electrode (G1) through a bridge electrode. Meanwhile, the fourth transistor (T4) may have a dual-gate structure having control electrodes on the upper and lower sides of the fourth semiconductor layer, respectively. Specifically, the fourth gate electrode (G4) may include a fourth-1 gate electrode (G4-1) located on a layer covering the first gate layer (GL1) and provided as part of an initial line (GI), and a fourth-2 gate electrode (G4-2) located on a layer covering the second active layer (AL2) and having an isolated shape.

[0084] Meanwhile, the 4-1 gate electrode (G4-1) and the 4-2 gate electrode (G4-2) can be electrically connected through a first gate contact hole (81) formed in a layer interposed between the second gate layer (GL2) and the third gate layer (GL3). A detailed description of the first gate contact hole (81) will be provided later with reference to FIGS. 11 to 13.

[0085] Scan line (SL), initial line (IL), compensation control line (CL), light emission control line (EL), gate initial voltage line (VIL1), anode initial voltage line (VIL2), and first connection line (BL1) extend in a first direction (DR1) and may be spaced apart from each other in each row. Data line (DL), driving voltage line (PL), and second connection line (BL2) extend in a second direction (DR2) that intersects the first direction (DR1) and may be spaced apart from each other in each column.

[0086] FIGS. 4 to 10 are layout diagrams schematically illustrating the pixel circuits of FIG. 3 layer by layer.

[0087] As shown sequentially in FIGS. 4 to 10, the first active layer (AL1) of FIG. 4, the first gate layer (GL1) of FIG. 5, the second gate layer (GL2) of FIG. 6, the second active layer (AL2) of FIG. 7, the third gate layer (GL3) of FIG. 8, the first source drain layer (SDL1) of FIG. 9, and the second source drain layer (SDL2) of FIG. 10 are arranged in a direction from a location close to the substrate (100, see FIG. 12) to a direction away from the substrate.

[0088] And insulating films are interposed between these layers. Specifically, a first gate insulating film (103, see FIG. 12) is interposed between the first active layer (AL1) of FIG. 4 and the first gate layer (GL1) of FIG. 5, a second gate insulating film (105, see FIG. 12) is interposed between the first gate layer (GL1) of FIG. 5 and the second gate layer (GL2) of FIG. 6, a third gate insulating film (107, see FIG. 12) is interposed between the second gate layer (GL2) of FIG. 6 and the second active layer (AL2) of FIG. 7, a fourth gate insulating film (109, see FIG. 12) is interposed between the second active layer (AL2) of FIG. 7 and the third gate layer (GL3) of FIG. 8, and a first interlayer insulating film (111, FIG. 8) is interposed between the third gate layer (GL3) of FIG. 8 and the first source drain layer (SDL1) of FIG. 9. (See Fig. 12) may be interposed, and a second interlayer insulating film (113, see Fig. 12) may be interposed between the first source drain layer (SDL1) of Fig. 9 and the second source drain layer (SDL2) of Fig. 10. These insulating films may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. Each of the insulating films may have a single-layer or multi-layer structure as needed. Of course, components of different layers may be electrically connected to each other through contact holes formed in these insulating films.

[0089] The first active layer (AL1) of FIG. 4 includes semiconductor layers of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7), respectively.

[0090] In one embodiment, the first active layer (AL1) of FIG. 4 may be a semiconductor layer comprising a polycrystalline silicon semiconductor. The source regions and drain regions of the first active layer (AL1) may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and drain region may correspond to the source electrode and drain electrode, respectively. The source region and drain region may be interchanged depending on the properties of the transistor. Hereinafter, the terms source region and drain region are used instead of source electrode or drain electrode. In the equivalent circuit diagram of FIG. 2, specific parts of the first active layer (AL1) are doped with P-type impurities so that the first transistor (T1), the second transistor (T2), and the fifth transistor (T5) to the seventh transistor (T7) are implemented as PMOS (p-channel MOSFET). Of course, other parts of the first active layer (AL1) may also be doped with impurities to serve as wiring that electrically connects transistors and / or capacitors, or as capacitor electrodes.

[0091] The first active layer (AL1) of FIG. 4 is located on a substrate. The substrate may include glass, metal, or a polymer resin. If the substrate has flexible or bendable properties, the substrate may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Of course, various modifications are possible, such as the substrate having a multilayer structure comprising two layers each containing such a polymer resin and a barrier layer containing an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, etc.) interposed between the layers.

[0092] Other layers may be interposed between the substrate and the first active layer (AL1). For example, a buffer layer (101, see FIG. 12) comprising one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer may be interposed between the substrate and the first active layer (AL1). This buffer layer may serve to increase the smoothness of the upper surface of the substrate or to prevent or minimize the penetration of impurities from the substrate into the first active layer (AL1). The buffer layer may have a single-layer or multi-layer structure as needed. In the case of a multi-layer structure, some layers may be referred to as barrier layers.

[0093] The first gate layer (GL1) of FIG. 5 includes the gate electrodes of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7), respectively. Additionally, the first gate layer (GL1) includes a scan line (SL) and a light emission control line (EL) extended in a first direction (DR1). At this time, the scan line (SL) and the light emission control line (EL) are formed integrally in adjacent pixels. Meanwhile, the lower electrode (CE1) of the storage capacitor (Cst) can be formed integrally with the first gate electrode (G1) of the first transistor (T1).

[0094] Specifically, the first gate layer (GL1) of FIG. 5 includes a first gate electrode (G1) in an isolated shape, a second gate electrode (G2) and a seventh gate electrode (G7) that are part of a scan line (SL), and a fifth gate electrode (G5) and a sixth gate electrode (G6) that are part of a light emission control line (EL).

[0095] The second gate layer (GL2) of FIG. 6 includes a third-1 gate electrode (G3-1) which is the lower gate electrode of the third transistor (T3), a fourth-1 gate electrode (G4-1) which is the lower gate electrode of the fourth transistor (T4), and an upper electrode (CE2) of the storage capacitor (Cst). Additionally, the second gate layer (GL2) includes an initial line (IL) and a compensation control line (CL) extended in a first direction (DR1). At this time, the initial line (IL) and the compensation control line (CL) are formed as a single unit in adjacent pixels.

[0096] Specifically, the second gate layer (GL2) of FIG. 6 includes a third-1 gate electrode (G3-1) which is part of the compensation control line (CL), a fourth-1 gate electrode (G4-1) which is part of the initialization line (IL), and an upper electrode (CE2) having an opening (SOP). The opening (SOP) is formed by removing a part of the upper electrode (CE2) and may have a closed shape. Within such an opening (SOP), a contact hole may be located, formed in the second gate insulating film to the fourth gate insulating film and the first interlayer insulating film, to electrically connect the first gate electrode (G1) to the layer located above. Meanwhile, the upper electrode (CE2) may be formed integrally with an adjacent pixel and may have a bridge portion for this purpose. In this case, the bridge portion refers to a portion protruding from the upper electrode (CE2) in a first direction (DR1).

[0097] Each of the first gate layer (GL1) of FIG. 5, the second gate layer (GL2) of FIG. 6, and the third gate layer (GL3) of FIG. 8 described later may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), etc. Of course, each of these layers may have a single-layer structure or a multi-layer structure, and if it has a multi-layer structure, it may include various materials. For example, the first gate layer (GL1) of FIG. 5, the second gate layer (GL2) of FIG. 6, and the third gate layer (GL3) of FIG. 8, each may have a two-layer structure of molybdenum layer / aluminum layer or a three-layer structure of molybdenum layer / aluminum layer / molybdenum layer.

[0098] The second active layer (AL2) of FIG. 7 includes the semiconductor layer of the third transistor (T3) and the semiconductor layer of the fourth transistor (T4). At this time, the semiconductor layer of the third transistor (T3) and the semiconductor layer of the fourth transistor (T4) can be formed integrally across adjacent pixels (e.g., PC1, PC2).

[0099] In one embodiment, the second active layer (AL2) of FIG. 7 may be a semiconductor layer containing an oxide. For example, the second active layer (AL2) may include a Zn oxide-based material, such as Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. Of course, since various modifications are possible, the second active layer (AL2) may include an oxide semiconductor such as IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O), in which metals such as indium (In), gallium (Ga), and tin (Sn) are contained in ZnO.

[0100] The third gate layer (GL3) of FIG. 8 includes a third-2 gate electrode (G3-2) which is the upper gate electrode of the third transistor (T3), a fourth-2 gate electrode (G4-2) which is the upper gate electrode of the fourth transistor (T4), and a gate initialization voltage line (VIL1). For reference, contact holes including the first gate contact hole (81) and the second gate contact hole (83) shown in FIG. 8 are formed in at least one of the first gate insulating film to the fourth gate insulating film, so that the layers shown in FIG. 8 can be electrically connected to a layer located below them.

[0101] Specifically, the third gate layer (GL3) of FIG. 8 includes a third-2 gate electrode (G3-2) extending in the first direction (DR1), a fourth-2 gate electrode (G4-2) in an isolated shape, and a gate initialization voltage line (VIL1) extending in the first direction (DR1).

[0102] In one embodiment, the 4-1 gate electrode (G4-1) and the 4-2 gate electrode (G4-2) may be formed integrally with adjacent pixels. Specifically, the 4-1 gate electrode (G4-1) of the first pixel circuit (PC1) and the 4-1 gate electrode (G4-1) of the second pixel circuit (PC2) may be integrally formed in an isolated shape. Additionally, the 4-2 gate electrode (G4-2) of the first pixel circuit (PC1) and the 4-2 gate electrode (G4-2) of the second pixel circuit (PC2) may be integrally formed to extend in a first direction (DR1).

[0103] Meanwhile, as shown in FIG. 8, a first gate contact hole (81) is formed in a layer interposed between the second gate layer (GL2) of FIG. 6 and the third gate layer (GL3) of FIG. 8. The first gate contact hole (81) electrically connects the fourth-1 gate electrode (G4-1) and the fourth-2 gate electrode (G4-2). This allows that when design space is limited, only the fourth-1 gate electrode (G4-1), which is the lower gate electrode among the gate electrodes of the fourth transistor (T4) having a double gate structure, can be formed in a wiring form, and the fourth-2 gate electrode (G4-2), which is the upper gate electrode, can be formed in an isolated shape rather than a wiring form. That is, the 4-2 gate electrode (G4-2) included in the 3rd gate layer (GL3) is electrically connected to the 4-1 gate electrode (G4-1) included in the 1st gate layer (GL1) through the 1st gate contact hole (81), thereby allowing the 4-1 gate electrode (G4-1) in the form of wiring to be utilized as a control signal transmission path.

[0104] As a specific example of a case where the design space is limited, a first connecting wire (BL1) extending in a first direction (DR1) is added to an area adjacent to the fourth transistor (T4), so that the space to form all of the gate electrodes (G4-1, G4-2) of the fourth transistor (T4) in a wiring form is limited. A detailed description of the first connecting wire (BL1) will be given later with reference to FIG. 9.

[0105] The gate initialization voltage line (VIL1) can be electrically connected to the second active layer (AL2) through a second gate contact hole (83) formed in a layer covering the second active layer (AL2). Specifically, the second gate contact hole (83) is formed in a layer interposed between the second active layer (AL2) and the third gate layer (GL3), and can be electrically connected to the gate initialization voltage line (VIL1) included in the third gate layer (GL3) and the fourth source region (S4) of the semiconductor layer of the fourth transistor (T4) included in the second active layer (AL2). At this time, the second gate contact hole (83) is not formed for each pixel but can be shared between adjacent pixels. For example, the second gate contact hole (83) can be located on a virtual axis (AX) passing between the first pixel circuit (PC1) and the second pixel circuit (PC2). Additionally, the gate initialization voltage line (VIL1) extends in a first direction (DR1) across the first pixel circuit (PC1) and the second pixel circuit (PC2) and is formed integrally, and the fourth source region (S4) of the first pixel circuit (PC1) and the fourth source region (S4) of the second pixel circuit (PC2) can also be formed integrally. In this case, the gate initialization voltage line (VIL1) can be connected to the fourth source region (S4) of the first pixel circuit (PC1) and the fourth source region (S4) of the second pixel circuit (PC2), respectively, through a single second gate contact hole (83).

[0106] The first source drain layer (SDL1) of FIG. 9 includes a first connection wire (BL1) and an anode initialization voltage line (VIL2) extended in a first direction (DR1). For reference, contact holes including the connection wire contact hole (91) shown in FIG. 9 are formed in the first gate insulating film to the fourth gate insulating film and / or the first interlayer insulating film to electrically connect the layers shown in FIG. 9 to the layer located below them.

[0107] The first connecting wire (BL1) may not overlap with the 4-1 gate electrode (G4-1) and the 4-2 gate electrode (G4-2). That is, by positioning the first connecting wire (BL1) apart from the gate electrodes of the 4th transistor (T4) without overlapping, the influence of the first connecting wire (BL1) on the 4th transistor (T4) can be minimized. The reduced design space resulting from this can be improved by forming the 4-2 gate electrode (G4-2) into an isolated shape as described above, and electrically connecting the wiring-shaped 4-1 gate electrode (G4-1) and the 4-2 gate electrode (G4-2) through the first gate contact hole (81). Alternatively, the first connecting wire (BL1) may overlap with components that are not significantly affected even if positioned overlapping with the first connecting wire (BL1). For example, the first connection wire (BL1) can overlap with the gate initialization voltage line (VIL1).

[0108] In one embodiment, the first connecting wire (BL1) may be a wire added to reduce the area of ​​dead space. As a specific example, the first connecting wire (BL1) may be a wire connecting a data line (DL) and an input line (not shown). The data lines (DL) extend from a non-display area into a display area. Additionally, the input lines are intended to input data signals to be applied to the data lines (DL) and may be located spaced apart from each other in the non-display area. Each of the input lines is connected to correspond to the data lines (DL). At this time, the data lines (DL) may form dead space by bypassing the edge area of ​​the display panel and being densely packed to connect with the input lines. To reduce the area of ​​such dead space, the input lines may be located relatively in the center of the display panel rather than near the corresponding data lines (DL). Through this structure, the area of ​​dead space in the outer vicinity of the display area can be drastically reduced.

[0109] According to the present embodiment, the first connecting wire (BL1) extends in a first direction (DR1), and one end is electrically connected to a data line (DL). The other end passes over the upper part of an adjacent data line (DL) and through a display area so as not to make contact with an adjacent data line (DL), and is electrically connected to a second connecting wire (BL2) through a connecting wire contact hole (91). Additionally, the second connecting wire (BL2) extends in a second direction (DR2) that intersects the first direction (DR1) and is electrically connected to an input line in a non-display area. Thus, the data line (DL) can be connected to an input line through a path passing through a display area using the first connecting wire (BL1) and the second connecting wire (BL2).

[0110] The second source drain layer (SDL2) of FIG. 10 includes a driving voltage line (PL), a data line (DL), and a second connecting wire (BL2). Specifically, the second source drain layer (SDL2) includes a driving voltage line (PL), a data line (DL), and a second connecting wire (BL2) that extend in a second direction (DR2) intersecting a first direction (DR1). For reference, the contact holes shown in FIG. 10 are formed in the second interlayer insulating film to electrically connect the layers shown in FIG. 10 to the layer located below them.

[0111] The driving voltage line (PL) can be shared between adjacent pixels. For example, the driving voltage line (PL) is located between the first pixel circuit (PC1) and the second pixel circuit (PC2) and can be electrically connected to each of the first pixel circuit (PC1) and the second pixel circuit (PC2) to supply a driving voltage (ELVDD). At this time, the driving voltage line (PL) is electrically connected to a part of the first source drain layer (SDL1) through a contact hole formed in a layer interposed between the first source drain layer (SDL1) and the second source drain layer (SDL2), and the part of the first source drain layer (SDL1) connected to the driving voltage line (PL) is electrically connected to the fifth source region (S5) of the fifth transistor (T5) through a contact hole formed in a layer interposed between the first source drain layer (SDL1) and the first active layer (AL1), so that the driving voltage line (PL) and the fifth transistor (T5) can finally be electrically connected.

[0112] The data line (DL) is electrically connected to a part of the first source drain layer (SDL1) through a contact hole formed in a layer interposed between the first source drain layer (SDL1) and the second source drain layer (SDL2), and the part of the first source drain layer (SDL1) connected to the data line (DL) is electrically connected to the second source region (S2) of the second transistor (T2) through a contact hole formed in a layer interposed between the first source drain layer (SDL1) and the first active layer (AL1), so that the data line (DL) and the second transistor (T2) can finally be electrically connected.

[0113] The second connecting wire (BL2) is electrically connected to the first connecting wire (BL1) through a connecting wire contact hole (91) formed in a layer interposed between the first source drain layer (SDL1) and the second source drain layer (SDL2), and is electrically connected to an input line in a non-display area.

[0114] Each of the first source drain layer (SDL1) of FIG. 9 and the second source drain layer (SDL2) of FIG. 10 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), etc. Of course, each of these layers may have a single-layer structure or a multi-layer structure, and if it has a multi-layer structure, it may include various materials. For example, each of the first source drain layer (SDL1) of FIG. 9 and the second source drain layer (SDL2) of FIG. 10 may have a two-layer structure of titanium layer / aluminum layer or a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0115] Meanwhile, a planarization film (not shown) covering the second source drain layer (SDL2) may be located on the second source drain layer (SDL2). A contact hole (not shown) may be formed in the planarization film to electrically connect the pixel electrode of an organic light-emitting diode (OLED) located on the planarization film to the second source drain layer (SDL2). The planarization film may include organic materials such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane). Of course, the present invention is not limited thereto, and the planarization film may include inorganic materials as needed, and may have a single-layer structure or a multi-layer structure.

[0116] Hereinafter, the first gate contact hole (81) will be described in detail with reference to FIGS. 11 to 13.

[0117] FIG. 11 is a layout drawing showing only some of the layers of FIG. 3, FIG. 12 is a cross-sectional view taken along line I-I' of FIG. 3, and FIG. 13 is a cross-sectional view taken along line II-II' of FIG. 3. Specifically, FIG. 11 is a layout drawing showing the second gate layer (GL2) of FIG. 6 and the third gate layer (GL3) of FIG. 8 extracted from the layout drawing of FIG. 3, while omitting the other layers.

[0118] As illustrated in FIGS. 11 to 13, the first gate contact hole (81) is formed in a layer interposed between the fourth-1 gate electrode (G4-1) and the fourth-2 gate electrode (G4-2), thereby exposing a portion of the upper surface of the fourth-1 gate electrode (G4-1). Additionally, the second gate contact hole (83) includes an inner surface that forms an incline with the exposed upper surface of the fourth-1 gate electrode (G4-1). The fourth-2 gate electrode (G4-2) is formed on the upper surface of the fourth-1 gate electrode (G4-1) to cover the upper surface of the fourth-1 gate electrode (G4-1) exposed through the first gate contact hole (81) and the inner surface of the first gate contact hole (81). The 4-2 gate electrode (G4-2) can be electrically connected by contacting the 4-1 gate electrode (G4-1) at the exposed portion of the 4-1 gate electrode (G4-1). Therefore, even if the 4-2 gate electrode (G4-2) is not formed in a wiring shape extending in the first direction (DR1) or the second direction (DR2) and has an isolated shape, it can perform the role of a control electrode by receiving a control signal using the 4-1 gate electrode (G4-1) formed in a wiring shape. Through this, the space occupied by the 4-2 gate electrode (G4-2) can be reduced, thereby securing design space.

[0119] The first gate contact hole (81) is not provided for each pixel (or pixel circuit) but can be shared with adjacent pixels (or pixel circuits). For example, as shown in FIG. 11, the first gate contact hole (81) can be located on a virtual axis (AX) passing between the first pixel circuit (PC1) located in the first pixel and the second pixel circuit (PC2) located in the second pixel. That is, the first gate contact hole (81) is located at the center of the 4-1 gate electrode (G4-1) in an isolated shape and serves to electrically connect the 4-1 gate electrode (G4-1) and the 4-2 gate electrode (G4-2), which are integrally formed in the first pixel circuit (PC1) and the second pixel circuit (PC2), which are adjacent pixels.

[0120] In one embodiment, the diameter (L1) of the upper surface of the fourth-1 gate electrode (G4-1) exposed through the first gate contact hole (81) can be formed to be smaller than the distance (L2) between the end of the first gate contact hole (81) in the direction of the fourth active region (A4) of the fourth transistor (T4) and the end of the fourth active region (A4) of the fourth transistor (T4) in the direction of the first gate contact hole (81). As shown in FIGS. 11 and 12, the first gate contact hole (81) is positioned to be interposed between the fourth active regions (A4) of the fourth transistor (T4). At this time, if the gap between the first gate contact hole (81) and the fourth active area (A4) is insufficient, defects may occur due to changes in device characteristics, such as a short circuit of the fourth transistor (T4) or an increase in circuit resistance, during manufacturing or use of the display device. According to the present embodiment, by forming the diameter (L1) of the first gate contact hole (81) to be smaller than the distance from the first gate contact hole (81) to the fourth active area (A4), the device characteristics can be improved and defects that may occur during manufacturing or use can be prevented in advance.

[0121] For example, the diameter (L1) of the first gate contact hole (81) is 2.6 μm or less, and the distance (L2) between the end of the first gate contact hole (81) in the direction of the fourth active region (A4) of the fourth transistor (T4) and the end of the fourth active region (A4) of the fourth transistor (T4) in the direction of the first gate contact hole (81) is 2.2 μm or more, L1 can be formed to be larger than L2.

[0122] In another embodiment, the cross-sectional area parallel to the upper surface of the 4-1 gate electrode (G4-1) of the 1st gate contact hole (81) can be formed to increase as it moves away from the 4-1 gate electrode (G4-1). That is, as shown in FIGS. 12 and 13, the inner surface of the 1st gate contact hole (81) can be formed to be inclined toward the outside. Accordingly, the 4-2 gate electrode (G4-2) covering the inner surface of the 1st gate contact hole (81) is also positioned to be inclined toward the outside of the 1st gate contact hole (81). Through this, the problem of hydrogen flowing into the 4th active region (A4) and changing device characteristics due to defects (e.g., CVD seam) that may occur when forming an insulating film on the 4-2 gate electrode (G4-2) can be prevented in advance.

[0123] Meanwhile, as a specific example of a method for adjusting the angle of inclination of the inner surface of the first gate contact hole (81), there is a method of changing the profile of the photoresist pattern or the etching gas used in the etching process. For example, the inner surface of the first gate contact hole (81) may be inclined toward the outside by using an etching gas of the CF4 / O2 or CHF3 / Ar series in the etching process, but it is not limited thereto.

[0124] In another embodiment, the 4-2 gate electrode (G4-2) may include a portion (81-1) covering the upper surface of the 4-1 gate electrode (G4-1) exposed by the 1 gate contact hole (81), a portion (81-2) covering the inner surface of the 1 gate contact hole (81), and a portion (81-3) extending from the portion located within the 1 gate contact hole (81) and located on a layer covering the 2 active layer (AL2). In this case, each portion (81-1, 81-2, 81-3) of the 4-2 gate electrode (G4-2) is integral. By having a portion (81-3) located on the layer covering the second active layer (AL2) and extending without being severed from the end of the portion (81-2) covering the inner surface of the first gate contact hole (81), the insulating film formed on the fourth-second gate electrode (G4-2) can be formed with superior quality. For example, the fourth-second gate electrode (G4-2) can be positioned so as to overlap the end of the fourth-first gate electrode (G4-1) in the second direction (DR2) by extending from the portion (81-2) covering the inner surface of the first gate contact hole (81).

[0125] Although the present invention has primarily described pixels and display devices equipped with such pixels, it is not limited thereto. For example, a method for manufacturing a display device for producing such pixels and display devices equipped with such pixels is also considered to fall within the scope of the present invention.

[0126] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0127] 81 : 1st Gate Contact Hole 83 : 2nd Gate Contact Hole 91 : Connection wiring contact hole 100 : Circuit board 101: Buffer layer 103: First gate insulating film 105 : 2nd gate insulating film 107 : 3rd gate insulating film 109: 4th gate insulating film 111: 1st interlayer insulating film 113: Second layer interlayer insulation film

Claims

Claim 1 A substrate including a display area where pixel circuits are located; a first active layer located on the substrate and including a first source area, a first active area located adjacent to the first source area, and a first drain area located adjacent to the first active area; a first gate layer located on a layer covering the first active layer and including a first gate electrode that overlaps with the first active area; a second gate layer located on a layer covering the first gate layer and including a gate signal line that extends in a first direction and has a fourth gate electrode; a second active layer located on a layer covering the second gate layer and including a fourth active area that overlaps with the fourth gate electrode; a third gate layer located on a layer covering the second active layer and including a fourth gate electrode that overlaps with the fourth active area and has an isolated shape; and a first connecting wire located on a layer covering the third gate layer and extending in the first direction A display device comprising: a first source drain layer including; and a second source drain layer located on a layer covering the first source drain layer, and including a data line and a second connecting wire extending in a second direction intersecting the first direction; wherein one end of the first connecting wire is electrically connected to the data line and the other end of the first connecting wire is electrically connected to the second connecting wire. Claim 2 A display device according to claim 1, wherein the first connecting wire does not overlap with the 4-1 gate electrode and the 4-2 gate electrode. Claim 3 A display device according to claim 1, wherein the 4-1 gate electrode and the 4-2 gate electrode are electrically connected through a 1 gate contact hole formed in a layer interposed between the 2 gate layer and the 3 gate layer. Claim 4 A display device according to claim 3, wherein the first gate contact hole exposes the upper surface of the fourth-1 gate electrode and includes an inner surface that forms an incline with the upper surface of the fourth-1 gate electrode, and the fourth-2 gate electrode covers the upper surface of the fourth-1 gate electrode exposed through the first gate contact hole and the inner surface. Claim 5 A display device according to claim 4, wherein the diameter of the upper surface of the 4th gate electrode exposed through the 1st gate contact hole is smaller than the distance between the end of the 1st gate contact hole in the direction of the 4th active region and the end of the 4th active region in the direction of the 1st gate contact hole. Claim 6 A display device according to claim 4, wherein the cross-sectional area of ​​the first gate contact hole parallel to the upper surface of the fourth-1 gate electrode increases as it moves away from the fourth-1 gate electrode. Claim 7 A display device according to claim 4, wherein the 4-2 gate electrode has a portion extending from a portion located within the 1st gate contact hole and a portion located on a layer covering the 2nd active layer. Claim 8 A display device according to claim 4, wherein the pixel circuits include a first pixel circuit and a second pixel circuit, and the first pixel circuit and the second pixel circuit are symmetric with respect to a virtual axis passing between the first pixel circuit and the second pixel circuit. Claim 9 A display device according to claim 8, wherein the 4-1 gate electrode of the first pixel circuit and the 4-1 gate electrode of the second pixel circuit are integral, the 4-2 gate electrode of the first pixel circuit and the 4-2 gate electrode of the second pixel circuit are integral, and the first gate contact hole is located on the virtual axis. Claim 10 A display device according to claim 1, wherein the third gate layer further includes a gate initialization voltage line extended in the first direction, and the first connecting wire overlaps with the gate initialization voltage line. Claim 11 A display device according to claim 10, wherein the gate initialization voltage line is electrically connected to the second active layer through a second gate contact hole formed in a layer covering the second active layer. Claim 12 delete Claim 13 A display device according to claim 1, wherein the first active layer comprises a silicon semiconductor and the second active layer comprises an oxide semiconductor. Claim 14 A pixel comprising: an organic light-emitting diode; a first transistor comprising a first semiconductor layer including a silicon semiconductor and a first gate electrode, and controlling a current flowing to the organic light-emitting diode in response to a voltage applied to the first gate electrode; a fourth transistor electrically connected to the first transistor and comprising a fourth semiconductor layer including an oxide semiconductor, a fourth-1 gate electrode located below the fourth semiconductor layer, and a fourth-2 gate electrode located above the fourth semiconductor layer and having an isolated shape; a gate signal line extending in a first direction including the fourth-1 gate electrode; and a first connection wire extending in the first direction; wherein one end of the first connection wire is electrically connected to a corresponding data line and the other end of the first connection wire is electrically connected to a corresponding second connection wire. Claim 15 In paragraph 14, the pixel, wherein the first connecting wire does not overlap with the 4-1 gate electrode and the 4-2 gate electrode. Claim 16 In claim 14, the 4-1 gate electrode and the 4-2 gate electrode are electrically connected through a first gate contact hole, the first gate contact hole exposes the upper surface of the 4-1 gate electrode and includes an inner surface that is inclined with the upper surface of the 4-1 gate electrode, and the 4-2 gate electrode covers the upper surface of the 4-1 gate electrode exposed through the first gate contact hole and the inner surface, a pixel. Claim 17 In claim 16, the diameter of the upper surface of the 4th-1st gate electrode exposed through the 1st gate contact hole is smaller than the distance between the end of the 4th active region of the 4th semiconductor layer of the 1st gate contact hole and the end of the 4th active region of the 1st gate contact hole. Claim 18 In claim 16, the cross-sectional area of ​​the first gate contact hole parallel to the upper surface of the fourth-1 gate electrode increases as it moves away from the upper surface of the fourth-1 gate electrode, in a pixel. Claim 19 In claim 16, the pixel, wherein the 4-2 gate electrode has a portion extending from a portion located within the 1st gate contact hole and a portion located on a layer covering the 4th semiconductor layer. Claim 20 delete

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