Radar device and operation method thereof

Abstract

A radar device according to an embodiment of the present invention includes a transmitting circuit that radiates a first transmitting signal and a second transmitting signal, and a receiving circuit that receives a first receiving signal associated with the first transmitting signal and a second receiving signal associated with the second transmitting signal, converts the first receiving signal into first data, converts the second receiving signal into second data, and outputs a first compensation signal that synchronizes the phase of the second receiving signal with the phase of the first receiving signal based on the first data and the second data. The receiving circuit includes a preprocessing circuit that generates first encoding data based on the first data, generates second encoding data based on the second data, and generates preprocessing data based on the first encoding data and the second encoding data; a phase compensation circuit that generates compensation data based on the preprocessing data and a phase compensation table; and a digital-to-analog converter that outputs a first compensation signal, which is an analog signal, based on the compensation data.

Description

Technology Field

[0001] The present invention relates to a radar device and a method of operating the same, and more specifically, to a radar device and a method of operating the same for improving the coherence of a distributed radar. Background Technology

[0002] Recently, various radar-based technologies for detecting human lives in wide-area disaster environments are being developed. One of these technologies is distributed radar coherence, which utilizes a distributed radar system.

[0003] Distributed radar systems detect common targets by utilizing multiple radars deployed at different locations. By employing coordinate technology, distributed radar systems can generate high-resolution images from data collected by these multiple radars. Due to these characteristics, distributed radar systems are utilized in various fields, including military, aerospace, and disaster relief. However, distributed radar systems suffer from low utility due to their limited operating modes. Therefore, to enhance the utility of distributed radar systems, methods to improve their coordinate technology are required. The problem to be solved

[0004] The objective of the present invention is to provide a radar device and a method of operation thereof for improving the coherence of a distributed radar. means of solving the problem

[0005] A radar device according to an embodiment of the present invention includes a transmitting circuit that radiates a first transmitting signal and a second transmitting signal, and a receiving circuit that receives a first receiving signal associated with the first transmitting signal and a second receiving signal associated with the second transmitting signal, converts the first receiving signal into first data, converts the second receiving signal into second data, and outputs a first compensation signal that synchronizes the phase of the second receiving signal with the phase of the first receiving signal based on the first data and the second data. The receiving circuit includes a preprocessing circuit that generates first encoding data based on the first data, generates second encoding data based on the second data, and generates preprocessing data based on the first encoding data and the second encoding data; a phase compensation circuit that generates compensation data based on the preprocessing data and a phase compensation table; and a digital-to-analog converter that outputs a first compensation signal, which is an analog signal, based on the compensation data.

[0006] For example, the preprocessing circuit includes a quantizer that generates first quantized data and second quantized data based on first data and second data, an encoder that generates first encoded data and second encoded data based on first quantized data and second quantized data, and a subtractor that performs a subtraction operation on first encoded data and second encoded data to generate preprocessed data, wherein a first part of the preprocessed data is coarse phase difference data and a second part of the preprocessed data is fine phase difference data.

[0007] For example, the subtractor generates first preprocessed data corresponding to a first time point and second preprocessed data corresponding to a second time point prior to the first time point, and the subtractor outputs first fine phase difference data, which is a second part of the first preprocessed data, and second fine phase difference data, which is a second part of the second preprocessed data, to a phase compensation circuit.

[0008] For example, the phase compensation circuit includes a comparator that performs a comparison operation on first phase difference data and second phase difference data to generate first phase difference data associated with a first time point, and a compensator that generates first compensation data associated with a first time point based on first phase difference data, first course data which is a first part of first preprocessed data, and a phase compensation table.

[0009] For example, the compensator combines the first phase difference data and the first course data, searches for the combined data in the phase compensation table, and generates the first compensation data based on the search result.

[0010] For example, the compensator generates second compensation data related to a third time point after the first time point, and the digital-to-analog converter outputs a first compensation signal based on the first compensation data and the second compensation data.

[0011] For example, the phase compensation circuit further includes an error corrector that corrects an error in the first compensation data.

[0012] For example, an error corrector compares an error with a predetermined threshold value, and corrects the error if the error is within the threshold value as a result of the comparison.

[0013] For example, the receiving circuit includes a control circuit that controls the operation of a preprocessing circuit and a phase compensation circuit, and the error corrector transmits a result signal to the control circuit when the error resulting from the comparison exceeds a threshold value, and the control circuit transmits a re-proceeding signal to the preprocessing circuit after receiving the result signal.

[0014] For example, the preprocessing circuit changes the number of bits of the first encoded data and the second encoded data after receiving a re-processing signal.

[0015] For example, the phase compensation table is stored in the ROM included in the receiving circuit.

[0016] For example, the second received signal is one of a pulse signal, a continuous wave signal, or a frequency-modulated continuous wave signal.

[0017] For example, a transmitting circuit radiates a third transmitting signal, and a receiving circuit receives a third receiving signal associated with the third transmitting signal, converts the third receiving signal into third data, and outputs a second compensation signal that synchronizes the phase of the third receiving signal with the phase of the first receiving signal based on the first data and the third data.

[0018] For example, the second received signal and the third received signal are two different signals among a pulse signal, a continuous wave signal, and a frequency-modulated continuous wave signal.

[0019] A method of operating a radar device according to one embodiment of the present invention comprises the steps of: receiving a first receiving signal associated with a first transmitting signal and a second receiving signal associated with a second transmitting signal; converting the first receiving signal and the second receiving signal into first data and second data; generating first encoded data and second encoded data based on the first data and second data; generating preprocessed data based on the first encoded data and second encoded data; generating compensation data based on the preprocessed data and a phase compensation table; and outputting a first compensation signal based on the compensation data.

[0020] For example, the step of generating first encoding data and second encoding data includes the step of generating first quantization data and second quantization data based on first data and second data, and the step of generating preprocessing data includes the step of performing a subtraction operation on first encoding data and second encoding data, and the first part of the preprocessing data is coarse phase difference data and the second part of the preprocessing data is fine phase difference data.

[0021] For example, the step of generating preprocessed data includes the step of generating first preprocessed data corresponding to a first time point and the step of generating second preprocessed data corresponding to a second time point prior to the first time point, and the step of generating compensation data includes the step of generating first phase difference data related to the first time point by performing a comparison operation on first fine phase difference data which is a second part of the first preprocessed data and second fine phase difference data which is a second part of the second preprocessed data, and the step of generating first compensation data related to the first time point based on the first phase difference data, first course data which is a first part of the first preprocessed data, and a phase compensation table.

[0022] For example, the step of generating first compensation data includes combining first phase difference data and first course data, searching for the combined data in a phase compensation table, and generating first compensation data based on the search result.

[0023] For example, the step of generating compensation data includes the step of generating second compensation data related to a third time point after a first time point, and the step of outputting a first compensation signal includes the step of outputting a first compensation signal based on the first compensation data and the second compensation data.

[0024] For example, the method further includes a step of correcting an error in the first compensation data. Effects of the invention

[0025] According to the present invention, a radar device can synchronize the phases of various radar signals in the digital domain with the phase of a reference signal. Accordingly, by synchronizing the phases of radar signals without limitations on the driving method, the radar device can improve the coherence of a distributed radar device.

[0026] According to the present invention, since the radar device performs calculations on a portion of the data, the computational burden of the radar device can be reduced and the computational speed improved.

[0027] According to the present invention, since the laser device has no limitations on the driving method, the radar device can be utilized to efficiently detect and rescue human lives in disaster environments. Brief explanation of the drawing

[0028] FIG. 1 shows a radar device according to one embodiment of the present invention. FIG. 2 shows a radar device according to one embodiment of the present invention. FIG. 3 shows a phase synchronization circuit according to one embodiment of the present invention. Figure 4 shows an example of the preprocessing circuit of Figure 3. FIGS. 5A and FIGS. 5B are drawings for illustrating preprocessed data according to an embodiment of the present invention. Figure 6 shows an example of the phase compensation circuit of Figure 3. Figure 7 shows another example of the phase compensation circuit of Figure 3. Figure 8 shows the digital-to-analog converter of Figure 3. FIG. 9 shows an example of operation of a radar device according to one embodiment of the present invention. Specific details for implementing the invention

[0029] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0030] FIG. 1 shows a radar device according to one embodiment of the present invention. Referring to FIG. 1, the radar device (100) may include a clock generation circuit (110), a transmission circuit (130), a reception circuit (150), and a signal processing circuit (170). In one embodiment, the radar device (100) may be included in a system for rescuing people in a disaster environment.

[0031] The clock generation circuit (110) can generate a clock (hereinafter, transmission clock; CLK1) used to generate a transmission signal in the transmission circuit (130). The clock generation circuit (110) can generate a clock (hereinafter, reception clock; CLK2) used to process a signal in the reception circuit (150). The clock generation circuit (110) can output the transmission clock (CLK1) to the transmission circuit (130) and output the reception clock (CLK2) to the reception circuit (150).

[0032] Each of the transmit clock (CLK1) and the receive clock (CLK2) may periodically have a logic low value or a logic high value. The logic high value and the logic low value of the transmit clock (CLK1) and the receive clock (CLK2) may each correspond to the magnitude of a specific voltage.

[0033] The clock generation circuit (110) can output a receiving clock (CLK2) to the receiving unit (130) after a delay has elapsed since the time when the transmitting clock (CLK1) is output to the transmitting circuit (130). The delay may be related to the detection range of the radar device (100). The clock generation circuit (110) can adjust the detection range of the radar device (100) by adjusting the delay. For example, the longer the delay, the longer the detection range of the radar device (100). The shorter the delay, the shorter the detection range of the radar device (100).

[0034] In one embodiment, the clock generation circuit (110) may include a delay locked loop (DLL) to output a transmit clock (CLK1) and a receive clock (CLK2) based on a delay. The delay locked loop (DLL) may include a voltage controlled delay line (VCDL). The voltage controlled delay line can generate clocks with various delays using a reference clock (CLK). For example, the voltage controlled delay line (VCDL) can generate clocks that are delayed by a time in which the period of the reference clock (CLK) is divided equally. The delay locked loop (DLL) can generate a transmit clock (CLK1) using the clocks generated by the voltage controlled delay line (VCDL). Additionally, the delay locked loop (DLL) can generate a receive clock (CLK2) that is delayed longer than the transmit clock (CLK1). Accordingly, the clock generation circuit (110) can adjust the delay using clocks generated by the multi-stage voltage-controlled delay element (VCDL).

[0035] The transmitting circuit (130) can receive a transmitting clock (CLK1) from the clock generation circuit (110). The transmitting circuit (130) can radiate a transmitting signal to a target (10) based on the transmitting clock (CLK1). For example, the transmitting circuit (130) can radiate a transmitting signal to a target (10) through a transmitting antenna (131) by using the transmitting clock (CLK1) as a transmitting trigger signal.

[0036] The receiving circuit (150) can receive a receiving clock (CLK2) from the clock generation circuit (110). Based on the receiving clock (CLK2), the receiving circuit (150) can receive an echo signal (or receiving signal) reflected from the target (10). For example, the receiving circuit (150) can receive an echo signal through the receiving antenna (151) based on the receiving clock (CLK2). The echo signal may be associated with a transmitting signal and may represent information associated with the position and speed of the target (10). The receiving circuit (150) can process the echo signal and output a signal (S1).

[0037] The signal processing circuit (170) can receive a signal (S1) from the receiving circuit (150). The signal processing circuit (170) can calculate values ​​associated with the target (10) based on the signal (S1). For example, the signal processing circuit (170) can calculate the position and speed of the target (10), etc., based on the signal (S1). The signal processing circuit (170) can output a signal (S2) to the clock generation circuit (110) to control the delay between the transmission clock (CLK1) and the reception clock (CLK2).

[0038] FIG. 2 shows a radar device according to an embodiment of the present invention. Referring to FIG. 2, the radar device (200) may include a clock generation circuit (210), a transmission circuit (230), a reception circuit (250), and a signal processing circuit (270).

[0039] The clock generation circuit (210) may include a reference clock generator (211) and a clock generator (213). The reference clock generator (211) may generate a reference clock (CLK) and output the reference clock (CLK) to the clock generator (213).

[0040] The clock generator (213) can generate a transmission clock (CLK1) and output the transmission clock (CLK1) to the transmission circuit (230). The clock generator (213) can generate a reception clock (CLK2) and output the transmission clock (CLK2) to the reception circuit (250).

[0041] The transmitting circuit (230) may include first to nth transmitters (233_1 to 233_n). Each of the first to nth transmitters (233_1 to 233_n) may receive a transmission clock (CLK1) from a clock generator (213). The first to nth transmitters (233_1 to 233_n) may radiate first to nth transmission signals (TS1 to TSn) through first to nth transmission antennas (231_1 to 231_n) based on the transmission clock (CLK1). For example, the first transmitter (233_1) can radiate a first transmission signal (TS1) through the first transmission antenna (231_1), the second transmitter (233_2) can radiate a second transmission signal (TS2) through the second transmission antenna (231_2), and the nth transmitter (233_n) can radiate an nth transmission signal (TSn) through the nth transmission antenna (231_n).

[0042] In FIG. 2, the first to nth transmitters (233_1 to 233_n) are shown receiving the same transmission clock (CLK1), but the present invention is not limited thereto. For example, each of the first to nth transmitters (233_1 to 233_n) may receive two or more different transmission clocks.

[0043] In one embodiment, the first to nth transmission signals (TS1 to TSn) may be signals of various forms. For example, each of the first to nth transmission signals (TS1 to TSn) may be a signal among a pulse signal, a continuous wave (CW) signal, and a frequency modulated continuous wave (FMCW) signal. However, the present invention is not limited thereto.

[0044] In one embodiment, the first transmission signal (TS1) may be a reference transmission signal that serves as a reference for the second to nth transmission signals (TS2~TSn).

[0045] The receiving circuit (250) may include first to n analog-to-digital converters (255_1 to 255_n) and first to n amplifiers (253_1 to 253_n). The first to n amplifiers (253_1 to 253_n) may receive first to n echo signals (RS1 to RSn) through first to n receiving antennas (251_1 to 251_n). For example, the first amplifier (253_1) may receive the first echo signal (RS1) through the first receiving antenna (251_1), the second amplifier (253_2) may receive the second echo signal (RS2) through the second receiving antenna (251_2), and the n amplifier (253_n) may receive the n echo signal (RSn) through the n receiving antenna (251_n).

[0046] In one embodiment, each of the first to nth echo signals (RS1 to RSn) may be associated with the first to nth transmission signals (TS1 to TSn). For example, the first echo signal (RS1) may be associated with the first transmission signal (TS1), the second echo signal (RS2) may be associated with the second transmission signal (TS2), and the nth echo signal (RSn) may be associated with the nth transmission signal (TSn).

[0047] In one embodiment, the first echo signal (RS1) may be a reference echo signal that serves as a reference for synchronizing each phase of the second to nth echo signals (RS2 to RSn).

[0048] The first to nth amplifiers (253_1 to 253_n) can amplify the received first to nth echo signals (RS1 to RSn). For example, the first amplifier (253_1) can amplify the first echo signal (RS1), the second amplifier (253_2) can amplify the second echo signal (RS2), and the nth amplifier (253_n) can amplify the nth echo signal (RSn).

[0049] The first to nth analog-to-digital converters (255_1 to 255_n) can receive signals amplified from the first to nth amplifiers (253_1 to 253_n). The first to nth analog-to-digital converters (255_1 to 255_n) can convert the received amplified signals into digital signals. For example, the first analog-to-digital converter (255_1) can convert the amplified signal received from the first amplifier (253_1) into the first data (D1), the second analog-to-digital converter (255_2) can convert the amplified signal received from the second amplifier (253_2) into the second data (D2), and the nth digital-to-analog converter (255_n) can convert the amplified signal received from the nth amplifier (253_n) into the nth data (Dn). In other words, the first to n analog-to-digital converters (255_1 to 255_n) can convert analog signals received from the first to n amplifiers (253_1 to 253_n) into digital signals.

[0050] In one embodiment, the first to n analog-to-digital converters (255_1 to 255_n) can convert amplified signals received from the first to n amplifiers (253_1 to 253_n) into digital signals by performing sampling, quantization, and encoding.

[0051] The phase synchronization circuit (257) can receive first to nth data (D1 to Dn) from first to nth analog-to-digital converters (255_1 to 255_n). The phase synchronization circuit (257) can perform calculations on the received first to nth data (D1 to Dn) so that the phases of the first to nth echo signals (RS1 to RSn) are synchronized. Alternatively, the phase synchronization circuit (257) can perform calculations on the first to nth data (D1 to Dn) so that the phases of the first to nth data (D1 to Dn) are synchronized. The phase synchronization circuit (257) can output first to nth analog signals (AS1 to ASn) which are the result of calculations on the first to nth data (D1 to Dn).

[0052] In one embodiment, the first analog signal (AS1) may be a signal in which the first data (D1) is converted into an analog signal.

[0053] In one embodiment, the second to nth analog signals (AS2 to ASn) may be the result of calculating the first to nth data (D1 to Dn) such that each phase of the second to nth echo signals (RS2 to RSn) is synchronized with the phase of the first echo signal (RS1). For example, the second analog signal (AS2) may be the result of calculating the first and second data (D1, D2) such that the phase of the second echo signal (RS2) is synchronized with the phase of the first echo signal (RS1). For example, the nth analog signal (ASn) may be the result of calculating the first and nth data (D1, Dn) such that the phase of the nth echo signal (RSn) is synchronized with the phase of the first echo signal (RS1). In other words, the second to nth analog signals (AS2~ASn) may be first to (n-1) compensation signals in which the phases of the second to nth echo signals (RS2~RSn) are synchronized with the phase of the first echo signal (RS1).

[0054] In FIG. 2, the phase synchronization circuit (257) is shown to output the first to nth analog signals (AS1 to ASn) to the signal processing circuit (270), but the present invention is not limited thereto. For example, the phase synchronization circuit (257) may output a single analog signal in which each phase of the second to nth echo signals (RS2 to RSn) is synchronized with the phase of the first echo signal (RS1).

[0055] The signal processing circuit (270) can receive the first to nth analog signals (AS1 to ASn) from the phase synchronization circuit (257). The signal processing circuit (270) can calculate values ​​associated with a target based on the first to nth analog signals (AS1 to ASn). The signal processing circuit (270) can output a signal to the clock generation circuit (210) to control the delay between the transmit clock (CLK1) and the receive clock (CLK2).

[0056] In FIG. 2, the phase synchronization circuit (257) is shown as being included in the receiving circuit (250), but is not limited thereto and the phase synchronization circuit (257) may be included in the signal processing circuit (270).

[0057] FIG. 3 shows a phase synchronization circuit according to an embodiment of the present invention. Referring to FIG. 3, the phase synchronization circuit (300) receives first and second data (D1, D2) and can generate a first compensation signal (CMPS1) that synchronizes the phase of the second data (D2) with the phase of the first data (D1) based on the first and second data (D1, D2). The first data (D1) may be reference data that serves as a reference for phase compensation.

[0058] In FIG. 3, the phase synchronization circuit (300) is shown receiving first and second data (D1, D2) and outputting a first compensation signal (CMPS1) based on the first and second data (D1, D2), but the present invention is not limited thereto. For example, the phase synchronization circuit (300) may further receive third data and further output a second compensation signal (CMPS2) based on the first data (D1) and the third data. That is, the phase synchronization circuit (300) may generate a plurality of compensation signals, which are analog signals, based on a plurality of data, which are digital signals.

[0059] The phase synchronization circuit (300) may include a preprocessing circuit (310), a phase compensation circuit (330), a digital-to-analog converter (DAC; 350), a memory (370), and a control circuit (390).

[0060] The preprocessing circuit (310) can receive the first data (D1) and the second data (D2). The preprocessing circuit (310) can preprocess the first data (D1) and the second data (D2) to generate preprocessed data.

[0061] In one embodiment, the preprocessing circuit (310) can quantize the first data (D1) and the second data (D2), encode the quantized first data (D1) and the quantized second data (D2), and generate preprocessed data by performing a subtraction operation on the encoded first data (D1) and the encoded second data (D2).

[0062] In one embodiment, the preprocessing data may include coarse phase difference data (CPDD) that roughly represents the phase difference between the first data (D1) and the second data (D2), and fine phase difference data (FPDD) that finely represents the phase difference between the first data (D1) and the second data (D2). For example, some bits of the preprocessing data may represent the coarse phase difference data (CPDD), and some bits may represent the fine phase difference data (FPDD).

[0063] In one embodiment, the preprocessing circuit (310) can output course phase difference data (CPDD) to memory (370) or a register (not shown) and output fine phase difference data (FPDD) to a phase compensation circuit (330).

[0064] The phase compensation circuit (330) can output compensation data that synchronizes the phase of the second data (D2) with the phase of the first data (D1) based on the data received from the preprocessing circuit (310).

[0065] In one embodiment, the phase compensation circuit (330) may receive a plurality of fine phase difference data (FPDD) corresponding to a plurality of time points (e.g., a plurality of encoding time points) from the preprocessing circuit (310). The phase compensation circuit (330) may output compensation data that synchronizes the phase of the second data (D2) with the phase of the first data (D1) based on the plurality of fine phase difference data (FPDD).

[0066] For example, the phase compensation circuit (330) can receive a plurality of fine phase difference data (FPDD) corresponding to a plurality of time points from the preprocessing circuit (310). Based on the plurality of fine phase difference data (FPDD), the phase compensation circuit (330) can output a plurality of compensation data corresponding to a plurality of time points to a digital-to-analog converter (350).

[0067] In one embodiment, the phase compensation circuit (330) can correct an error or error (hereinafter, error) in the compensation data. For example, the phase compensation circuit (330) can compare the error in the compensation data with a preset threshold value. If, as a result of the comparison, the error is within the threshold value, the phase compensation circuit (330) can correct the error and output it to the digital-to-analog converter (350). If, as a result of the comparison, the error exceeds the threshold value, the phase synchronization circuit (300) can perform the preprocessing operation and the phase compensation operation again.

[0068] The digital-to-analog converter (350) can convert data output from the phase compensation circuit (330) to generate an analog signal. For example, the digital-to-analog converter (350) can convert compensation data output from the phase compensation circuit (330) to generate a first compensation signal (CMPS1) which is an analog signal.

[0069] In one embodiment, the digital-to-analog converter (350) can generate a first compensation signal (CMPS1) based on a plurality of compensation data corresponding to a plurality of time points.

[0070] The memory (370) may include ROM (read only memory) or RAM (random access memory). The memory (370) may store various information and data related to the operation of the phase synchronization circuit (300). For example, the memory (370) may include a phase compensation table (CMPTBL). The phase compensation table (CMPTBL) may include various information necessary to synchronize the phase of the second data (D2) with the phase of the first data (D1), such as information on phase angles at multiple points in time of the first data (D1), which is reference data, bit sequence information corresponding to the phase angles, and phase delay information associated with the phase angles.

[0071] In one embodiment, the phase compensation table (CMPTBL) may be stored in ROM. Therefore, when the phase compensation table (CMPTBL) is stored in ROM, power consumption may be reduced compared to when it is stored in RAM.

[0072] The control circuit (390) can control the overall operation of the phase synchronization circuit (300). For example, the control circuit (390) can generate control signals to control the preprocessing circuit (310), the phase compensation circuit (330), the digital-to-analog converter (350), and the memory (370), and transmit the control signals to the preprocessing circuit (310), the phase compensation circuit (330), the digital-to-analog converter (350), and the memory (370), respectively.

[0073] FIG. 4 shows an example of the preprocessing circuit of FIG. 3. Referring to FIG. 3 and FIG. 4, the preprocessing circuit (310) may include a quantizer (311), an encoder (313), and a subtractor (315). The quantizer (311) may receive first data (D1) and second data (D2). The quantizer (311) may generate first quantized data (QD1) and second quantized data (QD2) based on the first data (D1) and second data (D2). For example, the quantizer (311) may quantize the first data (D1) to generate first quantized data (QD1) and quantize the second data (D2) to generate second quantized data (QD2).

[0074] In one embodiment, the first quantized data (QD1) and the second quantized data (QD2) may be data obtained by approximating the first data (D1) and the second data (D2) respectively with a predetermined representative value.

[0075] The quantizer (311) can output the first quantized data (QD1) and the second quantized data (QD2) to the encoder (313).

[0076] The encoder (313) can receive first quantized data (QD1) and second quantized data (QD2) from the quantizer (311). The encoder (313) can generate first encoded data (ED1) and second encoded data (ED2) based on the first quantized data (QD1) and second quantized data (QD2). For example, the encoder (313) can generate first encoded data (ED1) by encoding the first quantized data (QD1) and generate second encoded data (ED2) by encoding the second quantized data (QD2).

[0077] In one embodiment, the encoder (313) can encode the first quantized data (QD1) and the second quantized data (QD2) such that the number of bits of the first quantized data (QD1) and the second quantized data (QD2) changes. For example, the encoder (313) can encode the first quantized data (QD1) and the second quantized data (QD2) such that the number of bits of the first quantized data (QD1) and the second quantized data (QD2) decreases.

[0078] The encoder (313) can output the first encoded data (ED1) and the second encoded data (ED2) to the subtractor (315).

[0079] The subtractor (315) can receive first encoding data (ED1) and second encoding data (ED2) from the encoder (313). The subtractor (315) can generate preprocessed data (PRED) based on the first encoding data (ED1) and second encoding data (ED2).

[0080] In one embodiment, the subtractor (315) can generate preprocessed data (PRED) based on the number of bits of the first encoding data (ED1) and the second encoding data (ED2). For example, the subtractor (315) can generate preprocessed data (PRED) having the same number of bits as the number of bits of the first encoding data (ED1) and the second encoding data (ED2).

[0081] The preprocessed data (PRED) may include coarse phase difference data (CPDD) and fine phase difference data (FPDD). The subtractor (315) may output the coarse phase difference data (CPDD) to the memory (370) of FIG. 3 and output the fine phase difference data (FPDD) to the phase compensation circuit (330) of FIG. 3.

[0082] In one embodiment, the subtractor (315) can generate preprocessed data (PRED) by performing a subtraction operation on the first encoding data (ED1) and the second encoding data (ED2).

[0083] In one embodiment, a first part of the preprocessed data (PRED) may represent coarse phase difference data (CPDD), and a second part of the preprocessed data (PRED) may represent fine phase difference data (FPDD). For example, if the preprocessed data (PRED) is 'm' bits, the upper 'k' bits of the preprocessed data (PRED) may represent coarse phase difference data (CPDD), and the lower 'mk' bits of the preprocessed data (PRED) may represent fine phase difference data (FPDD).

[0084] In one embodiment, the subtractor (315) can generate preprocessed data (PRED) based on each portion of the first encoding data (ED1) and the second encoding data (ED2). For example, the subtractor (315) can generate coarse phase difference data (CPDD) based on a first portion of the first encoding data (ED1) and a first portion of the second encoding data (ED2). For example, the subtractor (315) can generate fine phase difference data (FPDD) based on a second portion of the first encoding data (ED1) and a second portion of the second encoding data (ED2).

[0085] In one embodiment, the preprocessing circuit (310) can preprocess the first data (D1) and the second data (D2) at each time point (e.g., each sampling time point of the analog-to-digital converters of FIG. 1) to generate time-specific course phase difference data (CPDD) and fine phase difference data (FPDD).

[0086] FIGS. 5a and 5b are drawings for illustrating preprocessed data (PRED) according to an embodiment of the present invention. Referring to FIGS. 3 to 5a, the phase angle can be represented as '9' bit data. In this case, the phase angles are divided into 512 phase steps, and the interval between adjacent phase angles can be '(pi / 2)*(1 / 128)' radians. That is, the resolution of the phase synchronization circuit (300) can be about '0.7' degrees. In FIG. 5a, the value of the bit sequence of data corresponding to '0' radians is '000000000', the value of the bit sequence of data corresponding to 'pi / 2' radians is '010000000', the value of the bit sequence of data corresponding to 'pi' radians is '100000000', and the value of the bit sequence corresponding to '3pi / 2' radians is '110000000'. In FIG. 5a, the value of the bit sequence of data corresponding to the first phase step is '000000001', and the phase angle corresponding to the first phase step may be '(pi / 2)*(1 / 128)' radians.

[0087] Preprocessed data (PRED) can correspond to one of the phase stages. That is, in FIG. 5a, preprocessed data (PRED) can be represented as '9' bits of data. The upper '2' bits of preprocessed data (PRED) represent coarse phase difference data (CPDD), and the remaining '7' bits, excluding the upper '2' bits, can represent fine phase difference data (FPDD). If preprocessed data (PRED) is in the first quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '00'. If preprocessed data (PRED) is in the second quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '01'. If preprocessed data (PRED) is in the third quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '10'. If preprocessed data (PRED) is in the fourth quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '11'.

[0088] The fine phase difference data (FPDD) of the preprocessed data (PRED) can be repeated based on '(pi / 2)'. For example, if the preprocessed data (PRED) corresponds to the first phase step, the 129th phase step, the 257th phase step, or the 385th phase step, the value of the bit sequence of the fine phase difference data (FPDD) can be '0000001'.

[0089] Referring to FIGS. 3, FIGS. 4 and FIGS. 5b, the phase angle can be represented by '7' bits of data. In this case, the phase angles are divided into 128 phase steps, and the interval between adjacent phase angles can be '(pi / 2)*(1 / 32)' radians. That is, the resolution of the phase synchronization circuit (300) can be about '2.8' degrees. In FIGS. 5b, the value of the bit sequence of data corresponding to '0' radians is '0000000', the value of the bit sequence of data corresponding to 'pi / 2' radians is '0100000', the value of the bit sequence of data corresponding to 'pi' radians is '1000000', and the value of the bit sequence corresponding to '3pi / 2' radians is '1100000'. In FIG. 5b, the value of the bit sequence of data corresponding to the first phase step is '0000001', and the phase angle corresponding to the first phase step may be '(pi / 2)*(1 / 32)' radians.

[0090] Preprocessed data (PRED) can correspond to one of the phase stages. That is, in FIG. 5b, preprocessed data (PRED) can be represented as '7' bits of data. The upper '2' bits of preprocessed data (PRED) represent coarse phase difference data (CPDD), and the remaining '5' bits excluding the upper '2' bits represent fine phase difference data (FPDD). If preprocessed data (PRED) is in the first quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '00'. If preprocessed data (PRED) is in the second quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '01'. If preprocessed data (PRED) is in the third quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '10'. If preprocessed data (PRED) is in the fourth quadrant, the value of the bit sequence of coarse phase difference data (CPDD) can be '11'.

[0091] The fine phase difference data (FPDD) of the preprocessed data (PRED) can be repeated based on '(pi / 2)'. For example, if the preprocessed data (PRED) corresponds to the first phase step, the 33rd phase step, the 65th phase step, or the 97th phase step, the value of the bit sequence of the fine phase difference data (FPDD) can be '00001'.

[0092] As described in FIGS. 5a and 5b, the course phase difference data (CPDD) can be determined according to the quadrant to which the preprocessed data (PRED) belongs. Accordingly, the phase compensation circuit (330) of FIG. 3 can perform calculations using fine phase difference data (FPDD), which is a part of the preprocessed data (PRED), rather than the entire preprocessed data (PRED), in order to simplify the calculation process. After performing calculations, the phase compensation circuit (330) of FIG. 3 can refer to the course phase difference data (CPDD).

[0093] FIG. 6 shows an example of the phase compensation circuit of FIG. 3. Referring to FIG. 3, FIG. 4 and FIG. 6, the phase compensation circuit (330) may include a comparator (331) and a compensator (333).

[0094] The comparator (331) can receive a first fine phase difference data (FPDD1) corresponding to a first time point and a second fine phase difference data (FPDD2) corresponding to a second time point from the subtractor (315). In one embodiment, the first time point may be any time point, and the second time point may be a time point prior to the first time point. For example, the first time point may be any sampling time point associated with the first data (D1) and the second data (D2), and the second time point may be a sampling time point immediately preceding the sampling time point corresponding to the first time point.

[0095] The comparator (331) can generate a first phase difference data (PDD1) based on the first phase difference data (FPDD1) and the second phase difference data (FPDD2). For example, the comparator (331) can generate a first phase difference data (PDD1) associated with a first time point by performing a comparison operation on the first phase difference data (FPDD1) and the second phase difference data (FPDD2). The comparator (331) can output the first phase difference data (PDD1) to the compensator (333).

[0096] In one embodiment, the first phase difference data (PDD1) may represent the difference in phase differences between the first data (D1) and the second data (D2) at different points in time. For example, the first phase difference data (PDD1) may represent the difference between the fine phase difference between the first data (D1) and the second data (D2) at a first point in time and the fine phase difference between the first data (D1) and the second data (D2) at a second point in time.

[0097] The compensator (333) can output the first compensation data (CMPD1) by compensating the phase of the second data (D2) associated with the first time point based on the first phase difference data (PDD1), the course phase difference data (CPDD1) corresponding to the first time point, and the phase compensation table (CMPTBL).

[0098] In one embodiment, the phase compensation table (CMPTBL) may include information regarding phase angles at multiple time points of the first data (D1), which is reference data, bit sequence information corresponding to the phase angles, phase delay information associated with the phase angles, and bit count information of the preprocessed data (PRED). However, the present invention is not limited thereto, and the phase compensation table (CMPTBL) may include various information necessary to compensate the phase of the second data (D2).

[0099] In one embodiment, the compensator (333) may search for a compensation delay corresponding to the first phase difference data (PDD1) and the first course phase difference data (CPDD1) by referring to the phase compensation table (CMPTBL). For example, the compensator (333) may combine the first phase difference data (PDD1) and the first course phase difference data (CPDD1) to search for a compensation delay corresponding to the combined data. For example, the compensator (333) may combine the bit sequence value '10' of the first course phase difference data (CPDD1) and the bit sequence value '11111' of the first phase difference data (PDD1) to search for a compensation delay corresponding to the combined data '1011111'.

[0100] In one embodiment, the compensator (333) can compensate for the searched compensation delay in the second data (D2). For example, the compensator (333) can compensate for the searched compensation delay in the second data (D2) corresponding to the first time point and output the first compensation data (CMPD1) corresponding to the first time point.

[0101] In one embodiment, the phase compensation table (CMPTBL) may be stored in memory (370). For example, the phase compensation table (CMPTBL) may be stored in the ROM of memory (370).

[0102] In one embodiment, the first course phase difference data (CPDD1) may be stored in memory (370) or a register (not shown).

[0103] In FIG. 6, the phase compensation circuit (330) is shown to output a first compensation data (CMPD1) associated with a first time point, but is not limited thereto. The phase compensation circuit (330) can repeat the operations described in FIG. 6 to output multiple compensation data associated with multiple time points.

[0104] FIG. 7 shows another example of the phase compensation circuit of FIG. 3. Referring to FIG. 7, the phase compensation circuit (300a) may include a comparator (331a), a compensator (333a), and an error corrector (335a). In FIG. 7, the comparator (331a) and the compensator (333a) perform the same operation as the comparator (331) and the compensator (333) of FIG. 6, respectively. Therefore, redundant descriptions are omitted.

[0105] The error corrector (335a) can receive first compensation data (CMPD1) from the compensator (333a). The error corrector (335a) can correct the error in the first compensation data (CMPD1) to generate first error correction data (ECD1).

[0106] In one embodiment, the error of the first compensation data (CMPD1) may mean the difference between the phase angle of the first compensation data (CMPD1) and the phase angles of adjacent phase steps. For example, if the phase angle of the first compensation data (CMPD1) falls within the region between the first phase step and the second phase step, the error of the first compensation data (CMPD1) may mean the difference between the phase angles of the first compensation data (CMPD1) and the first phase step, or the difference between the phase angles of the first compensation data (CMPD1) and the second phase step.

[0107] In one embodiment, the error corrector (335a) can determine whether to correct the error of the first compensation data (CMPD1) based on a predetermined threshold value.

[0108] For example, if the error of the first compensation data (CMPD1) is within a threshold value, the error corrector (335a) can correct the error of the first compensation data (CMPD1).

[0109] For example, if the error of the first compensation data (CMPD1) exceeds a threshold value, the phase synchronization circuit (300) of FIG. 3 can perform the preprocessing operation and the phase compensation operation again.

[0110] In one embodiment, if the error of the first compensation data (CMPD1) exceeds a threshold value, the preprocessing circuit (310) may encode the first data (D1) and the second data (D2) so that the number of bits of the preprocessing data (PRED) changes. For example, if the error of the first compensation data (CMPD1) exceeds a threshold value, the error corrector (335a) may transmit a result signal to the control circuit (390) of FIG. 3. In response to receiving the result signal, the control circuit (390) may transmit a re-proceeding signal to the preprocessing circuit (310) and the phase compensation circuit (330). In response to receiving the re-proceeding signal, the preprocessing circuit (310) may encode the first data (D1) and the second data (D2) so that the number of bits of the preprocessing data (PRED) changes.

[0111] The error corrector (335a) can output the first error correction data (ECD1). In one embodiment, if no error occurs in the first compensation data (CMPD1), the error corrector (335a) can output the first compensation data (CMPD1) as the first error correction data (ECD1).

[0112] In FIG. 7, the phase compensation circuit (300a) is shown to output a first error correction data (ECD1) associated with a first time point, but is not limited thereto. The phase compensation circuit (300a) can repeat the operations described in FIG. 7 to output multiple error correction data associated with multiple time points.

[0113] FIG. 8 shows the digital-to-analog converter of FIG. 3. The first compensation data (CMPD1) of FIG. 8 may correspond to the first compensation data (CMPD1) of FIG. 6.

[0114] Referring to FIGS. 3 and FIGS. 7, the digital-to-analog converter (350) may receive first compensation data (CMPD1) associated with a first time point, second compensation data (CMPD2) associated with a second time point, and third compensation data (CMPD3) associated with a third time point. In one embodiment, the first time point, the second time point, and the third time point may be three consecutive time points.

[0115] The digital-to-analog converter (350) can output a first compensation signal (CMPS1) that synchronizes the phase of the second data (D2) with the phase of the first data (D1) based on the first to third compensation data (CMPD1, CMPD2, CMPD3).

[0116] For example, the digital-to-analog converter (350) can output a first compensation signal (CMPS1), which is an analog signal, based on information contained in the first to third compensation data (CMPD1, CMPD2, CMPD3), which are digital signals.

[0117] In FIG. 8, the digital-to-analog converter (350) is shown to receive first to third compensation data (CMPD1, CMPD2, CMPD3), but the digital-to-analog converter (350) may receive first to third error correction data (ECD1, ECD2, ECD3).

[0118] In one embodiment, the digital-to-analog converter (350) can receive first error correction data (ECD1) associated with a first time point, second error correction data (ECD2) associated with a second time point, and third error correction data (ECD3) associated with a third time point.

[0119] In one embodiment, the digital-to-analog converter (350) can output a first compensation signal (CMPS1) that synchronizes the phase of the second data (D2) with the phase of the first data (D1) based on the first to third error correction data (ECD1, ECD2, ECD3).

[0120] For example, the digital-to-analog converter (350) can output a first compensation signal (CMPS1), which is an analog signal, based on information contained in the first to third error correction data (ECD1, ECD2, ECD3), which are digital signals.

[0121] FIG. 9 shows an example of operation of a radar device according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 9, in step S110, the radar device (200) can transmit first and second transmission signals (TS1, TS2). For example, the radar device (200) can transmit the first and second transmission signals (TS1, TS2) to a target through first and second transmission antennas (231_1, 231_2).

[0122] In step S120, the radar device (200) can receive first and second reception signals (RS1, RS2). For example, the radar device (200) can receive first and second reception signals (RS1, RS2) through first and second reception antennas (251_1, 251_2).

[0123] In step S130, the radar device (200) can generate first and second data (D1, D2) based on first and second received signals (RS1, RS2). For example, the radar device (200) can amplify the first and second received signals (RS1, RS2). The radar device (200) can convert the amplified first and second received signals (RS1, RS2) to generate first and second data (D1, D2) which are digital signals.

[0124] In step S140, the radar device (200) can generate first and second encoded data (ED1, ED2) based on first and second data (D1, D2). For example, the radar device (200) can generate first and second quantized data (QD1, QD2) by quantizing the first and second data (D1, D2). The radar device (200) can generate first and second encoded data (ED1, ED2) by encoding the first and second quantized data (QD1, QD2).

[0125] In step S150, the radar device (200) can generate preprocessed data (PRED) based on the first and second encoding data (ED1, ED2). For example, the radar device (200) can generate preprocessed data (PRED) by performing a subtraction operation on the first and second encoding data (ED1, ED2).

[0126] In step S160, the radar device (200) can generate compensation data (CMPD) based on preprocessed data (PRED) and a phase compensation table (CMPTBL).

[0127] In step S170, the radar device (200) can determine whether an error has occurred in the compensation data (CMPD). If an error has occurred in the compensation data (CMPD), in step S180, the radar device (200) can determine whether the error is within a threshold value. If no error has occurred in the compensation data (CMPD), in step S200, the radar device (200) can generate a first compensation signal (CMPS1), which is an analog signal, based on the compensation data (CMPD).

[0128] Returning to step S180, if the error is within the threshold, the radar device (200) can correct the error in the compensation data (CMPD) in step S190 and generate a first compensation signal (CMPS1) based on the compensation data (CMPD) with the error corrected in step S200. If the error exceeds the threshold, the radar device (200) can generate first and second encoded data (ED1, ED2) with a changed number of bits based on the first and second data (D1, D2) in step S140. Subsequently, the radar device (200) can repeat steps S150 through S170.

[0129] In the embodiments described above, components according to the technical concept of the present invention have been described using terms such as first, second, third, etc. However, terms such as first, second, third, etc. are used to distinguish the components from one another and do not limit the present invention. For example, terms such as first, second, third, etc. do not imply a sequential order or any numerical meaning.

[0130] The description above describes specific examples for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be easily modified or simply changed. Furthermore, the present invention will include technologies that can be easily modified and implemented in the future using the embodiments described above. Explanation of the symbols

[0132] 100, 200: Radar device

Claims

Claim 1 A transmitting circuit that radiates a first transmitting signal and a second transmitting signal; and a receiving circuit that receives a first receiving signal associated with the first transmitting signal and a second receiving signal associated with the second transmitting signal, converts the first receiving signal into first data which is a digital signal, converts the second receiving signal into second data which is a digital signal, and outputs a first compensation signal that synchronizes the phase of the second receiving signal with the phase of the first receiving signal based on the first data and the second data, wherein the receiving circuit comprises: a preprocessing circuit that generates first encoding data based on the first data, generates second encoding data based on the second data, and generates preprocessing data including course phase difference data and fine phase difference data based on the first encoding data and the second encoding data; and a phase compensation circuit that generates compensation data based on the preprocessing data and a phase compensation table. A radar device comprising: a digital-to-analog converter that outputs a first compensation signal, which is an analog signal, based on the above compensation data, and the preprocessing circuit comprises: a quantizer that generates a first quantized data based on the first data and generates a second quantized data based on the second data; an encoder that generates a first encoded data by encoding the first quantized data such that the number of bits changes and generates a second encoded data by encoding the second quantized data such that the number of bits changes; and a subtractor that generates the preprocessed data by performing a subtraction operation on the first encoded data and the second encoded data, wherein the preprocessed data is 'm' bits, the coarse phase difference data corresponds to a first part which is the upper 'k' bit of the preprocessed data, and the fine phase difference data corresponds to a second part which is the lower 'mk' bit of the preprocessed data. Claim 2 delete Claim 3 A radar device according to claim 1, wherein the subtractor generates first preprocessed data corresponding to a first time point and second preprocessed data corresponding to a second time point prior to the first time point, and the subtractor outputs first fine phase difference data which is a second part of the first preprocessed data and second fine phase difference data which is a second part of the second preprocessed data to the phase compensation circuit. Claim 4 In claim 3, the phase compensation circuit comprises: a comparator that performs a comparison operation on the first phase difference data and the second phase difference data to generate first phase difference data associated with the first time point; and a compensator that generates first compensation data associated with the first time point based on the first phase difference data, first course data which is a first part of the first preprocessed data, and the phase compensation table. Claim 5 In claim 4, the compensator comprises: combining the first phase difference data and the first course data; searching the combined data in the phase compensation table; and generating the first compensation data based on the search result. Claim 6 In claim 4, the compensator generates second compensation data related to a third time point after the first time point, and the digital-to-analog converter outputs the first compensation signal based on the first compensation data and the second compensation data. Claim 7 In claim 4, the phase compensation circuit further comprises an error corrector that corrects an error in the first compensation data. Claim 8 In claim 7, the error correction device compares the error with a predetermined threshold value, and corrects the error when the result of the comparison is within the threshold value. Claim 9 A radar device according to claim 8, wherein the receiving circuit includes a control circuit that controls the operation of the preprocessing circuit and the phase compensation circuit, and the error corrector transmits a result signal to the control circuit when the error exceeds the threshold value as a result of the comparison, and the control circuit transmits a re-proceeding signal to the preprocessing circuit after receiving the result signal. Claim 10 In claim 9, the preprocessing circuit is a radar device that changes the number of bits of the first encoding data and the second encoding data after receiving the re-progress signal. Claim 11 In claim 1, the phase compensation table is a radar device stored in a ROM included in the receiving circuit. Claim 12 In claim 1, the second received signal is a radar device that is one of a pulse signal, a continuous wave signal, or a frequency-modulated continuous wave signal. Claim 13 A radar device according to claim 1, wherein the transmitting circuit radiates a third transmitting signal, and the receiving circuit receives a third receiving signal associated with the third transmitting signal; converts the third receiving signal into third data; and outputs a second compensation signal that synchronizes the phase of the third receiving signal with the phase of the first receiving signal based on the first data and the third data. Claim 14 In claim 13, the radar device wherein the second received signal and the third received signal are two different signals among a pulse signal, a continuous wave signal, and a frequency modulated continuous wave signal. Claim 15 A method of operating a radar device comprises: receiving a first receiving signal associated with a first transmitting signal and a second receiving signal associated with a second transmitting signal; converting the first receiving signal and the second receiving signal into digital signals, namely first data and second data; generating first encoding data and second encoding data based on the first data and second data; generating preprocessing data including coarse phase difference data and fine phase difference data based on the first encoding data and second encoding data; generating compensation data based on the preprocessing data and a phase compensation table; and outputting a first compensation signal based on the compensation data, wherein the step of generating the first encoding data and second encoding data comprises: generating first quantization data and second quantization data based on the first data and second data; and generating first encoding data by encoding the first quantization data such that the number of bits changes. A method comprising the step of generating a second encoded data by encoding the second quantized data such that the number of bits of the second quantized data changes, and the step of generating the preprocessed data including the coarse phase difference data and the fine phase difference data comprises: the step of performing a subtraction operation on the first encoded data and the second encoded data, wherein the preprocessed data is 'm' bits, the coarse phase difference data corresponds to a first part which is the upper 'k' bit of the preprocessed data, and the fine phase difference data corresponds to a second part which is the lower 'mk' bit of the preprocessed data. Claim 16 delete Claim 17 In claim 15, the step of generating the preprocessing data comprises: generating a first preprocessing data corresponding to a first time point; and generating a second preprocessing data corresponding to a second time point prior to the first time point, and the step of generating the compensation data comprises: generating a first phase difference data related to the first time point by performing a comparison operation on a first fine phase difference data which is a second part of the first preprocessing data and a second fine phase difference data which is a second part of the second preprocessing data; and generating a first compensation data related to the first time point based on the first phase difference data, a first course data which is a first part of the first preprocessing data, and the phase compensation table. Claim 18 In claim 17, the step of generating the first compensation data comprises: combining the first phase difference data and the first course data; searching for the combined data in the phase compensation table; and generating the first compensation data based on the search result. Claim 19 A method according to claim 17, wherein the step of generating the compensation data includes the step of generating second compensation data related to a third time point after the first time point, and the step of outputting the first compensation signal includes the step of outputting the first compensation signal based on the first compensation data and the second compensation data. Claim 20 A method according to claim 17, further comprising the step of correcting an error in the first compensation data.

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