Semiconductor device and method of detecting semiconductor wafer centered on tape

Abstract

Semiconductor manufacturing equipment includes a wafer tape comprising a plurality of alignment holes formed through the wafer tape. A semiconductor wafer is placed on the wafer tape. The semiconductor wafer has a circular or rectangular form factor. A light source is placed beneath the wafer tape. The semiconductor wafer is misaligned on the wafer tape, and light passes through one or more alignment holes. The semiconductor wafer is placed in the center of the wafer tape, and light does not pass through one or more alignment holes. The wafer tape has a plurality of wafer alignment marks for semiconductor wafers of various sizes. A photodetector is placed on the semiconductor wafer to detect light passing through the wafer tape. A control arm can be attached to the semiconductor wafer to provide the ability to move the semiconductor wafer according to a control signal from the photodetector.

Description

Technology Field

[0001] The present invention generally relates to a semiconductor device, and more specifically to a method for detecting a semiconductor wafer placed at the center of a semiconductor device and a tape. Background Technology

[0002] Semiconductor devices are commonly found in modern electrical products. They perform various functions, including signal processing, high-speed computing, electromagnetic signal transmission and reception, electrical device control, optoelectronics, and the generation of visual images for television displays. Semiconductor devices are used in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They are also used in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] A semiconductor wafer typically contains multiple semiconductor dies separated by a top street. Semiconductor wafers are generally mounted on tape to hold them in place during various manufacturing operations, such as cleaning and dicing. The semiconductor wafer must be positioned in the center of the tape to be properly aligned with a jig or other dicing tool. The center of the tape can be found by manually moving the wafer. However, because the tape is not transparent, manual centering is, at best, only an estimate. If centering is incorrect, the wafer may be cut inaccurately, leading to reduced yield and higher manufacturing costs. Brief explanation of the drawing

[0004] FIGS. 1a-1d shows a semiconductor wafer having multiple semiconductor dies separated by top streets; FIGS. 2a-2i show a wafer tape with alignment holes for centering a semiconductor wafer; FIG. 3 shows a semiconductor wafer that is the subject of a manufacturing operation; FIG. 4 shows a semiconductor wafer of a second size placed in the center of the wafer tape by an alignment hole; FIG. 5 shows a semiconductor wafer of a third size placed in the center of the wafer tape by an alignment hole; Figure 6 shows a rectangular semiconductor wafer positioned in the center of a wafer tape by an alignment hole; FIG. 7 shows a control arm that moves a semiconductor wafer to the center of a wafer tape; Figures 8a-8h show a wafer tape with alignment holes for centering a reconstructed wafer. Figure 9 shows a printed circuit board (PCB) with various types of packages placed on the surface of the PCB. Specific details for implementing the invention

[0005] The present invention is described in the following description with reference to the drawings for one or more embodiments, wherein the same numbers denote identical or similar elements. Although the present invention has been described in the best mode for achieving the purposes of the invention, those skilled in the art will recognize that it is intended to include alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, and equivalents supported by the following disclosure and drawings. Features shown in the drawings are not necessarily drawn to scale. Elements having similar functions are assigned the same reference number in the drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms and can therefore refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are generally manufactured through two complex processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, have the function of controlling the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the function of the electrical circuit.

[0007] Backend manufacturing refers to the process of cutting or integrating a finished wafer into individual semiconductor dies and packaging them for structural support, electrical interconnection, and environmental isolation. To integrate the semiconductor dies, the wafer is scored and cut along the top street or scribe, which are non-functional regions of the wafer. The wafer is integrated using a laser cutting tool or a saw blade. After integration, the individual semiconductor dies are placed on a package substrate containing pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor dies are connected to the contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, or wire bonds. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical insulation. Finally, when the finished semiconductor package is inserted into an electrical system, the functionality of the semiconductor device becomes available to other system components.

[0008] FIG. 1a illustrates a semiconductor wafer (100) having a base substrate material (102) such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor dies or electrical components (104) are formed on the wafer (100) separated by an inactive, inter-die wafer area or a top street (106). The top street (106) provides a cutting area for integrating the semiconductor wafer (100) into individual semiconductor dies (104). The semiconductor wafer (100) has a circular form factor. In one embodiment, the semiconductor wafer (100) has a width or diameter of 100 to 450 millimeters (mm).

[0009] FIG. 1b shows a cross-sectional view of a portion of a semiconductor wafer (100). Each semiconductor die (104) has a back or inactive surface (108) and an active surface (110) comprising an analog or digital circuit implemented by an active device, a passive device, a conductive layer, and a dielectric layer formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface (110) to implement an analog or digital circuit, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a memory, or other signal processing circuit. The semiconductor die (104) may also include IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

[0010] An electrically conductive layer (112) is formed on an active surface (110) using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (112) may be one or more layers made of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layer (112) acts as a contact pad electrically connected to a circuit of the active surface (110).

[0011] FIG. 2a shows a back coating (BSC) or wafer tape (120) made of a polymer or epoxy containing silver, silica, or alumina fillers. FIG. 2b is a top view of the BSC tape (120). The BSC tape (120) supports and protects a semiconductor wafer (100). The thickness of the BSC tape (120) is 110 micrometers (mm), which is wider than the maximum wafer coverage area. FIG. 2c is a more detailed drawing of the BSC (120) comprising a polyethylene terephthalate (PET) release film (121) with a thickness of 38 mm, a double-sided tape (123) having a PVC base film with a thickness of 60 mm, a thermosetting back coating film (125) with a thickness of 25 mm, an acrylic release layer (127) with a thickness of 5 mm, and a polyolefin base film (129) with a thickness of 80 mm. The BSC tape (120) is opaque and blocks infrared (IR).

[0012] In FIG. 2b, a first wafer alignment circle or mark (122) for a 200 mm diameter wafer is shown. A second wafer alignment circle or mark (124) is shown for a 300 mm diameter wafer. A third wafer alignment circle or mark (126) is shown for a 450 mm diameter wafer. For each wafer alignment circle, a plurality of alignment openings or holes are formed in the BSC tape (120) by stencil and punch, laser direct removal (LDA), or etching processes. Typically, each wafer alignment circle has at least three alignment holes. Four alignment holes (130a, 130b, 130c, and 130d) are spaced at equal intervals, i.e., at 90-degree intervals, around the wafer alignment circuit (122). There are four alignment holes (132a, 132b, 132c, 132d) spaced at equal intervals around the wafer alignment circuit (124), and six alignment holes (134a, 134b, 134c, 134d, 134e, 134f) spaced at equal intervals around the wafer alignment circuit (126) due to their larger size. The alignment holes (130-134) are generally circular with a diameter of 5.0 mm for circular wafers, but may have different geometric shapes depending on the wafer. Each alignment circle may have any number of alignment holes. Since the alignment holes (130-134) are formed just inside the wafer alignment circle, when the semiconductor wafer (100) is placed on the alignment circle and centered at the center (128), the alignment circuit is visible, but all alignment holes for that alignment circle are obscured by the semiconductor wafer and are not visible. In this case, the semiconductor wafer (100) is considered to be ideally aligned with the center (128) of the BSC tape (120).

[0013] In FIG. 2d, the semiconductor wafer (100) of FIG. 1b is placed on the BSC tape (120). In this example, the diameter of the semiconductor wafer (100) is 450 mm. FIG. 2e shows the active surface (110) of the semiconductor wafer (100) placed on and in contact with the surface (136) of the BSC tape (120). In another embodiment, FIG. 2f shows the back surface (108) of the semiconductor wafer (100) placed on and in contact with the surface (136) of the BSC tape (120). Any orientation of the semiconductor wafer (100) is applicable.

[0014] FIG. 2g shows the position of a light source (140) under the BSC tape (120). The light source (140) emits light waves (142) onto the surface (144) of the BSC tape (120). Depending on the position of the semiconductor wafer (100), the light waves (142) may or may not pass through the alignment holes (134a-134f). Assume that the semiconductor wafer (100) is off-center relative to the center (128). Again, alignment holes (134a-134f) are formed just inside the wafer alignment circle (126). Any material misalignment of the semiconductor wafer (100) relative to the center (128) allows the light waves (142) to pass through one or more alignment holes (134a-134f). That is, if misaligned with respect to the center (128), the semiconductor wafer (100) does not cover all alignment holes (134a-134f), and light waves (142) pass through one or more uncovered alignment holes. In the plan view of FIG. 2h, the semiconductor wafer (100) is misaligned with respect to the center (128), and the semiconductor wafer (100) does not cover the alignment holes (134e and 134f). Light waves (142) pass through the alignment holes (134e and 134f) and can be observed or detected on the opposite side of the BSC tape (120), i.e., on the surface (136). Light waves (142) can be observed by the human eye or detected by a light detector (146). The photodetector (146) may provide a visible or auditory signal that a light wave (142) has been detected on the surface (136) after passing through one or more of the alignment holes (134a-134f). The alignment holes (130a-130d and 132a-132d) are for smaller semiconductor wafers and are not suitable for 450mm semiconductor wafers.

[0015] In FIG. 2b, if the semiconductor wafer (100) is off-center with respect to the center (128), the position of the semiconductor wafer with respect to the center (128) can be moved or adjusted until the semiconductor wafer covers all alignment holes (134a-134f). In this case, light cannot be observed or detected in any of the alignment holes (134a-134f). As in FIG. 2i, if there is no light that can be observed or detected through any of the alignment holes (134a-134f), the semiconductor wafer (100) is considered to be centered with respect to the center (128).

[0016] Once placed in the center, the semiconductor wafer (100) can be applied to various semiconductor manufacturing processes. For example, the semiconductor wafer (100) is unified along the top street (106) as shown in FIG. 3. As described above, the alignment of the semiconductor wafer (100) with respect to the center (128) allows for precise control of the position of the dicing operation. Alternatively, the semiconductor wafer (100) may be subject to pick-and-place operations, cleaning, and inspection.

[0017] FIG. 4 shows a semiconductor wafer (100) mounted on a BSC tape (120). In this case, the diameter of the semiconductor wafer (100) is 300 mm. When the semiconductor wafer (100) is misaligned with respect to the center (128), the light wave (142) passes through one or more alignment holes (132a-132d) inside the wafer alignment circle (124). That is, when misaligned with respect to the center (128), the semiconductor wafer (100) does not cover all the alignment holes (132a-132d), and similar to FIG. 2h, the light wave (142) passes through the un-covered alignment holes. The light wave (142) passes through the un-covered alignment holes and can be observed or detected on the opposite side of the BSC tape (120), i.e., on the surface (136). Again, the light waves (142) can be observed by the human eye or detected by a light detector (146). Since the light waves (142) are focused into the alignment holes (132a-132d), all light passing through the alignment holes (134a-134f) is ignored or can be ignored.

[0018] If the semiconductor wafer (100) is off-center with respect to the center (128), the position of the semiconductor wafer relative to the center (128) can be moved or adjusted until the semiconductor wafer covers all alignment holes (132a-132d). In this case, light cannot be observed or detected through any of the alignment holes (132a-132d). As shown in FIG. 4, if light is not observed or detected through any of the alignment holes (132a-132d), the semiconductor wafer (100) is considered to be centered with respect to the center (128). The alignment holes (130a-130d) are for smaller semiconductor wafers and are not suitable for 300mm semiconductor wafers.

[0019] FIG. 5 shows a semiconductor wafer (100) mounted on a BSC tape (120). In this case, the diameter of the semiconductor wafer (100) is 200 mm. When the semiconductor wafer (100) is misaligned with respect to the center (128), the light wave (142) passes through one or more alignment holes (130a-130d) inside the wafer alignment circle (122). That is, when misaligned with respect to the center (128), the semiconductor wafer (100) does not cover all the alignment holes (130a-130d), and the light wave (142) passes through one or more un-covered alignment holes, similar to FIG. 2h. The light wave (142) passes through the un-covered alignment holes and can be observed or detected on the opposite side of the BSC tape (120), i.e., on the surface (136). Again, the light waves (142) can be observed by the human eye or detected by a light detector (146). Since the light waves (142) are focused into the alignment holes (130a-130d), any light passing through the alignment holes (134a-134f and 132a-132d) can be ignored or ignored.

[0020] If the semiconductor wafer (100) is off-center with respect to the center (128), the position of the semiconductor wafer with respect to the center (128) can be moved or adjusted until the semiconductor wafer covers all alignment holes (130a-130d). In this case, light cannot be observed or detected through any of the alignment holes (130a-102d). As shown in FIG. 5, if light is not observed or detected through any of the alignment holes (130a-130d), the semiconductor wafer (100) is considered to be centered with respect to the center (128).

[0021] In another embodiment, the semiconductor wafer (100) may be moved or adjusted by a control arm (148) in response to a photodetector (146), as shown in FIG. 6. The control arm (148) is attached to the semiconductor wafer (100). When the photodetector (146) detects a light wave (142), a control signal is transmitted to the control arm (148) to move the semiconductor wafer (100) and adjust the wafer position. Given an alignment hole where light is detected, the control arm (148) has information about the position to which the semiconductor wafer (100) is to be moved. For example, as in FIG. 2h, when light is detected through the alignment holes (134e-134f), the photodetector (146) transmits a control signal to the control arm (148) to move the semiconductor wafer (100) downward relative to the center (128). Once the adjustment is complete, the photodetector (146) reads again in a similar manner and performs additional adjustments if necessary until the semiconductor wafer (100) covers all alignment holes (134a-134f) and the light wave (142) is not transmitted through the BSC (120).

[0022] In another embodiment, the semiconductor wafer (200) has a rectangular form factor. The semiconductor wafer (200) is manufactured similarly to FIG. 1a-1b. FIG. 7 shows a rectangular semiconductor wafer (200) placed on a BSC tape (120). In this case, the wafer alignment mark becomes rectangular. The semiconductor wafer (200) follows a description similar to FIG. 2-6 with a rectangular form factor. If the semiconductor wafer (200) is misaligned, light waves are transmitted through one or more alignment holes and corrective measures are taken, similar to FIG. 2h-2i. When the semiconductor wafer (200) is correctly aligned, light waves do not pass through any of the alignment holes of the BSC tape (120), and the semiconductor wafer is considered to be correctly centered.

[0023] Returning to FIG. 1c, an electrically conductive bump material is deposited onto a conductive layer (112) using evaporation, electroplating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, and a flux solution is optional. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is adhered to the conductive layer (112) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump (114). In one embodiment, the bump (114) is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The bump (114) may also be compression bonded or thermally compression bonded to the conductive layer (112). The bump (114) represents a type of interconnect structure that can be formed on the conductive layer (112). Bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects may also be used for the interconnect structure.

[0024] In FIG. 1d, a semiconductor wafer (100) is unitized into individual semiconductor dies (104) via a saw street (106) using a saw blade or a laser cutting tool (118). After unitization, the individual semiconductor dies (104) can be inspected and electrically tested to identify known good dies (KGD) or known good units (KGU).

[0025] FIG. 8a illustrates a temporary substrate or carrier (150) comprising a sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost hard material for structural support. The substrate (150) has a main surface (152) and a main surface (154) opposite the surface (152). In one embodiment, the carrier (150) is a support structure having a temporary bonding layer (158) formed on the carrier. The temporary bonding layer (158) may be a film or foil adhered to the surface (152).

[0026] In FIG. 8b, electrical components (156a-156c) are placed on the surface (152) of the substrate (150). The electrical components (156a-156c) may be similar to, or manufactured similarly to, the semiconductor die (104) of FIG. 1d having bumps (114) facing the surface (152) of the substrate (150). Alternatively, the electrical components (156a-156c) may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0027] Electrical components (156a-156c) are placed on the substrate (150) using a pick-and-place operation. Electrical components (156a-156b) come into contact with the bonding layer (158). FIG. 8c illustrates the electrical components (156a-156c) bonded to the substrate (150) as a reconfigured wafer-level package (WLP) (160). FIG. 8d is a top view of the reconfigured WLP (160) with the electrical components (156a-156c) bonded to the substrate (150). In this example, the diameter of the reconfigured WLP (160) is 450 mm.

[0028] In FIG. 8e, the reconfigured WLP (160) is placed on the BSC tape (120) similarly to FIG. 2d. The same reference number is assigned to parts with similar functions. FIG. 8f shows the surface (154) of the reconfigured WLP (160) placed on the surface (136) of the BSC tape (120) and in contact with it.

[0029] A light source (162) is located beneath the BSC tape (120). The light source (162) emits light waves (164) onto the surface (144) of the BSC tape (120). Depending on the position of the reconfigured WLP (160), the light waves (164) may or may not pass through the alignment holes (134a-134f). As shown in FIG. 8g, it is assumed that the reconfigured WLP (160) is misaligned with respect to the center (128). Again, alignment holes (134a-134f) are formed just inside the wafer alignment circle (126). The material misalignment of the reconfigured WLP (160) with respect to the center (128) allows the light waves (164) to pass through one or more alignment holes (134a-134f). That is, if misaligned with respect to the center (128), the reconstructed WLP (160) does not cover all alignment holes (134a-134f), and light waves (164) pass through one or more uncovered alignment holes. In this case, light waves (164) passing through the alignment holes (134e and 134f) can be observed or detected on the opposite side of the BSC tape (120), i.e., on the surface (136). The light waves (164) can be observed by the human eye or detected by a light detector (166). The light detector (166) can provide a visible or auditory signal that the light waves (164) have been detected on the surface (136) after passing through one or more of the alignment holes (134a-134f).

[0030] If the reconfigured WLP (160) is off-center with respect to the center (128), the position of the reconfigured WLP (160) with respect to the center (128) can be moved or adjusted until the reconfigured WLP (160) covers all alignment holes (134a-134f). In this case, light cannot be observed or detected through any of the alignment holes (134a-134f). As shown in FIG. 8h, if light is not observed or detected through any of the alignment holes (134a-134f), the reconfigured WLP (160) is considered to be centered with respect to the center (128).

[0031] Once placed at the center, the semiconductor wafer (160) can be applied to various semiconductor manufacturing processes. For example, the semiconductor wafer (100) is unified along the top street (106) similar to FIG. 3. As described above, the alignment of the semiconductor wafer (100) with respect to the center (128) allows for precise control of the position of the dicing operation.

[0032] FIG. 9b is a drawing illustrating an electronic device (400) having a PCB (402) or a chip carrier substrate having a plurality of semiconductor packages including semiconductor dies (104) disposed on the surface of the PCB (402). The electronic device (400) may have one type of semiconductor package or multiple types of semiconductor packages depending on the application.

[0033] The electrical device (400) may be a standalone system that performs one or more electrical functions using a semiconductor package. Alternatively, the electrical device (400) may be a sub-component of a larger system. For example, the electrical device (400) may be part of a tablet, mobile phone, digital camera, communication system, or other electrical device. Alternatively, the electrical device (400) may be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component. Miniaturization and lightweighting are essential for the product to be accepted in the market. The distance between semiconductor devices can be reduced to achieve higher density.

[0034] In FIG. 9, the PCB (402) provides a general substrate for structural support and electrical interconnection of semiconductor packages placed on the PCB. Conductive signal traces (404) are formed on the surface or within a layer of the PCB (402) using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (404) provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces (404) also provide power and ground connections to each semiconductor package.

[0035] In some embodiments, the semiconductor device has two packaging levels. Level 1 packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Level 2 packaging is a process of mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only level 1 packaging in which the die is mechanically and electrically placed directly onto the PCB.

[0036] For illustration purposes, various types of first-stage packaging, including bond wire packages (406) and flip chips (408), are shown on the PCB (402). Additionally, various types of second-stage packaging, such as ball grid arrays (BGA) (410), bump chip carriers (BCC) (412), land grid arrays (LGA) (416), multi-chip modules (MCM) or SIP modules (418), quad planar lead-free packages (QFN) (420), quad planar packages (422), embedded wafer-level ball grid arrays (eWLB) (424), and wafer-level chip scale packages (WLCSP) (426), are placed on the PCB (402). In one embodiment, the eWLB (424) is a fan-out wafer-level package (Fo-WLP), and the WLCSP (426) is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages consisting of one-stage and two-stage packaging styles and other electrical components can be connected to the PCB (402). In some embodiments, the electrical device (400) includes a single attached semiconductor package, but in other embodiments, multiple interconnected packages are required. Manufacturers can combine one or more semiconductor packages on a single substrate to integrate prefabricated components into electrical devices and systems. Because semiconductor packages contain sophisticated functions, electrical devices can be manufactured using cheaper components and simplified manufacturing processes. Devices produced in this way have a lower failure rate and lower manufacturing costs, allowing them to be provided to consumers at a lower cost.

[0037] Although one or more embodiments of the present invention have been described in detail, those skilled in the art will understand that modifications and variations to these embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims

Claim 1 A semiconductor manufacturing equipment comprising: a wafer tape configured to accommodate a semiconductor wafer above - the wafer tape includes a plurality of alignment holes formed through the wafer tape -; and a light source disposed below the wafer tape - the plurality of alignment holes and the light source are spaced apart and configured to indicate a misaligned position of the semiconductor wafer on the wafer tape by light passing through one or more alignment holes -. Claim 2 A semiconductor manufacturing equipment according to claim 1, wherein a plurality of alignment holes and a light source are spaced apart and configured such that light does not pass through one or more alignment holes and the center position of the semiconductor wafer is positioned at the center of the wafer tape. Claim 3 In claim 1, the wafer tape comprises a plurality of wafer alignment marks for semiconductor wafers of different sizes, semiconductor manufacturing equipment. Claim 4 In paragraph 3, the alignment holes are each located inside the wafer alignment mark, in a semiconductor manufacturing equipment. Claim 5 A semiconductor manufacturing equipment according to claim 1, further comprising a photodetector disposed on a semiconductor wafer to detect light passing through a wafer tape. Claim 6 A semiconductor manufacturing equipment comprising: a wafer tape configured to accommodate a semiconductor wafer above - the wafer tape includes a plurality of alignment holes formed through the wafer tape -; and a light source disposed below the wafer tape - the plurality of alignment holes and the light source are spaced apart and configured to indicate a misaligned position of the semiconductor wafer on the wafer tape without light passing through one or more alignment holes -. Claim 7 A semiconductor manufacturing equipment according to claim 6, wherein a plurality of alignment holes and a light source are spaced apart and configured to indicate the position in which a semiconductor wafer is placed at the center of a wafer tape by light passing through one or more alignment holes. Claim 8 In paragraph 6, the wafer tape comprises a plurality of wafer alignment marks for semiconductor wafers of different sizes, semiconductor manufacturing equipment. Claim 9 In paragraph 8, the alignment holes are each located inside the wafer alignment mark, in a semiconductor manufacturing equipment. Claim 10 In claim 6, the semiconductor manufacturing equipment further comprises a photodetector disposed on a semiconductor wafer to detect light passing through a wafer tape. Claim 11 A method for manufacturing a semiconductor device comprising: providing a wafer tape having a plurality of alignment holes formed through the wafer tape; placing a semiconductor wafer on the wafer tape to cover the alignment holes; and placing a light source under the wafer tape—when the light does not pass through one or more alignment holes, the semiconductor wafer is placed at the center of the wafer tape. Claim 12 In paragraph 11, a method in which a semiconductor wafer is misaligned on a wafer tape when light passes through one or more alignment holes. Claim 13 In claim 11, the wafer tape comprises a plurality of wafer alignment marks for semiconductor wafers of different sizes. Claim 14 A method according to claim 11, further comprising the step of placing a photodetector on a semiconductor wafer to detect light passing through a wafer tape. Claim 15 A method according to claim 14, further comprising the step of attaching a control arm to a semiconductor wafer to provide a function of moving the semiconductor wafer in response to a control signal from a photodetector.

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