Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a source / drain at one end of the semiconductor body. The vertical transistor also includes a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The vertical transistor further includes a silicide. At least a portion of the silicide is over the source / drain. The area of ​​the silicide is larger than the area of ​​the first surface of the source / drain. The first surface is perpendicular to the first direction.

Description

Technology Field

[0001] This application is a continuation of International Application No. PCT / CN2023 / 093907, filed on May 12, 2023, titled “Semiconductor structure and method for forming the same,” claiming priority to U.S. Provisional Application No. 63 / 348,354, filed on June 2, 2022, the contents of which are all incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor structure and a method for forming the same. Background Technology

[0003] When the feature size of semiconductor technology is reduced to less than a deep submicron, the width of the source and drain regions of the transistor continues to decrease, and the series resistance of the source and drain regions of the device increases. In addition, the size of the interconnect contact holes at the back end continues to decrease, and as the size of the contact holes decreases, the contact resistance of the individual contact holes also increases. To reduce the series resistance and contact resistance of the source and drain regions, a metal silicide is formed on the active region.

[0004] In one aspect, a semiconductor structure comprising a vertical transistor is provided. The vertical transistor comprises a semiconductor body extending in a first direction. The semiconductor body comprises a source / drain at one end of the semiconductor body. The vertical transistor also comprises a gate structure coupled to at least one side of the semiconductor body. The gate structure comprises a gate dielectric and a gate electrode. The vertical transistor further comprises a silicide. At least a portion of the silicide is over the source / drain. The area of ​​the silicide is larger than the area of ​​the first surface of the source / drain. The first surface is perpendicular to the first direction.

[0005] In some implementations, the silicified material partially covers at least one second surface of the source / drain, and at least one second surface is perpendicular to the first surface.

[0006] In some implementations, the semiconductor structure further includes an epitaxial structure formed between the source / drain and the silicide.

[0007] In some implementations, the semiconductor structure further includes a first isolation layer surrounding the semiconductor body. A first surface of the source / drain is exposed from the first isolation layer, and an epitaxial structure covers the first surface of the source / drain.

[0008] In some implementations, the semiconductor structure further includes a first insulating layer surrounding the semiconductor body. At least a portion of the second surface of the source / drain and the first surface are exposed from the first insulating layer, and an epitaxial structure covers at least a portion of the second surface of the source / drain and the first surface.

[0009] In some implementations, the semiconductor structure further includes a second insulating layer surrounding the epitaxial structure. A first top surface of the epitaxial structure is exposed from the second insulating layer, and silicide covers the first top surface of the epitaxial structure.

[0010] In some implementations, the semiconductor structure further includes a second insulating layer surrounding the silicide, and the second top surface of the silicide is exposed from the second insulating layer.

[0011] In some implementations, the silicide is isolated from the gate structure, and the minimum distance between the silicide and the gate structure is greater than the critical distance.

[0012] In some implementations, the semiconductor structure further comprises a landing layer covering the silicide and a metal contact extending through the landing layer and in contact with a second top surface of the silicide. The surface area of ​​the metal contact in contact with the silicide is smaller than or equal to the area of ​​the second top surface of the silicide.

[0013] In some implementations, the silicide comprises elements of titanium (Ti), cobalt (Co), or nickel-platinum alloy (NiPt), and the silicide comprises titanium disilicide (TiSi2) with a face-centered orthorhombic structure (C54 phase).

[0014] In another aspect, a semiconductor system is provided. The semiconductor system includes a semiconductor structure having a plurality of vertical transistors and a memory controller coupled to the semiconductor structure and configured to control the semiconductor structure. Each of at least some of the plurality of vertical transistors includes a semiconductor body extending in a first direction. The semiconductor body includes a source / drain at one end of the semiconductor body. The semiconductor body also includes a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The semiconductor body further includes a silicide. At least a portion of the silicide is over the source / drain, and the area of ​​the silicide is larger than the area of ​​the first surface of the source / drain. The first surface is perpendicular to the first direction.

[0015] In some implementations, the silicified material partially covers at least one second surface of the source / drain, and at least one second surface is perpendicular to the first surface.

[0016] In some implementations, the semiconductor system further includes an epitaxial structure formed between the source / drain and the silicide.

[0017] In some implementations, the semiconductor system further includes a first insulating layer surrounding the semiconductor body. A first surface of the source / drain is exposed from the first insulating layer, and an epitaxial structure covers the first surface of the source / drain.

[0018] In some implementations, the semiconductor system further includes a first insulating layer surrounding the semiconductor body. At least a portion of the second surface of the source / drain and the first surface are exposed from the first insulating layer, and an epitaxial structure covers at least a portion of the second surface of the source / drain and the first surface.

[0019] In some implementations, the semiconductor system further includes a second insulating layer surrounding the epitaxial structure. A first top surface of the epitaxial structure is exposed from the second insulating layer, and silicide covers the first top surface of the epitaxial structure.

[0020] In some implementations, the semiconductor system further includes a second insulating layer surrounding the silicide, and the second top surface of the silicide is exposed from the second insulating layer.

[0021] In some implementations, the silicide is insulated from the gate structure, and the minimum distance between the silicide and the gate structure is greater than the critical distance.

[0022] In some implementations, the semiconductor system further includes a landing layer covered with silicide and a metal contact extending through the landing layer and in contact with the silicide. The surface area of ​​the metal contact in contact with the silicide is smaller than or equal to the area of ​​the silicide.

[0023] In some implementations, the silicide contains elements of titanium (Ti), cobalt (Co), or nickel-platinum alloy (NiPt), and the silicide contains titanium disilicide (TiSi2) with a face-centered orthorhombic structure (C54 phase).

[0024] In another aspect, a method for forming a semiconductor structure is provided. The method comprises: forming a semiconductor body of the semiconductor structure extending in a first direction from a substrate; forming a gate structure on at least one side of the semiconductor body; forming a source / drain at a distal end of the semiconductor body away from the substrate; forming a first insulating layer surrounding the semiconductor body and the gate structure; and forming a silicide. At least a portion of the silicide is over the source / drain. The area of ​​the silicide is larger than the area of ​​the first surface of the source / drain, and the first surface is perpendicular to the first direction.

[0025] In some implementations, at least a portion of the second surface of the source / drain and the first surface are exposed from the first insulating layer, the second surface is perpendicular to the first surface, and silicide is formed on at least a portion of the second surface of the source / drain and the first surface.

[0026] In some embodiments, after the step of forming a silicide, the method further comprises the step of forming a second insulating layer surrounding the silicide, and the first surface of the silicide is exposed from the second insulating layer.

[0027] In some embodiments, the step of forming a silicide includes the step of depositing a metal layer covering at least a portion of the second surface of the source / drain exposed from the first insulating layer and the first surface, and the step of heating the metal layer to form a silicide by a reaction between the metal layer and the source / drain.

[0028] In some implementations, the step of heating the metal layer includes the step of performing a first rapid thermal annealing (RTA) on the metal layer at a first temperature lower than the critical temperature.

[0029] In some implementations, the step of heating the metal layer further includes the step of performing a second RTA on the metal layer at a second temperature higher than the critical temperature.

[0030] In some implementations, the step of forming the silicide further includes the step of depositing a metal nitride on a metal layer before performing the first RTA.

[0031] In some embodiments, after the step of forming a silicified material, the method further comprises the step of forming a landing layer covering the silicified material; the step of forming a through hole on the landing layer to expose the silicified material, wherein the cross-sectional area of ​​the through hole is greater than or equal to the area of ​​the second top surface of the silicified material; and the step of forming a source / drain contact that contacts the silicified material through a metal contact formed in the through hole.

[0032] In some implementations, the first surface of the source / drain is exposed from the first insulating layer. This method further includes the step of growing an epitaxial structure from the first surface of the source / drain prior to the step of forming a silicide. The area of ​​the first surface of the epitaxial structure is larger than the area of ​​the first surface of the source / drain. The silicide is formed based on the epitaxial structure.

[0033] In some embodiments, after the step of forming a first insulating layer, the method further comprises the step of etching the first insulating layer to expose at least a portion of the second surface of the source / drain, and the second surface of the source / drain is perpendicular to the first surface of the source / drain.

[0034] In some implementations, the step of growing an epitaxial structure further includes the step of growing an epitaxial structure from at least a portion of the second surface of the source / drain exposed from the first insulating layer.

[0035] In some implementations, after the step of growing the epitaxial structure, the method further includes the step of forming a second insulating layer covering the epitaxial structure before forming a silicide, wherein the second insulating layer is aligned with the epitaxial structure and the first top surface of the epitaxial structure is exposed from the second insulating layer.

[0036] In some implementations, after the step of forming a silicide, the step of forming a second insulating layer covering the silicide is further included, the second insulating layer is aligned with the silicide, and the second top surface of the silicide is exposed from the second insulating layer.

[0037] In some embodiments, the step of forming a silicide includes the step of forming a second insulating layer covering an epitaxial structure, wherein the second insulating layer is aligned with the epitaxial structure. At least a first surface of the epitaxial structure is exposed from the second insulating layer. The step of forming a silicide further includes the step of depositing a metal layer covering at least the first surface of the epitaxial structure exposed from the second insulating layer, and heating the metal layer to form a silicide.

[0038] In some implementations, the step of heating the metal layer includes the step of performing a first rapid thermal annealing (RTA) on the metal layer at a first temperature lower than the critical temperature.

[0039] In some implementations, the step of heating the metal layer further includes the step of performing a second RTA on the metal layer at a second temperature higher than the critical temperature.

[0040] In some implementations, the step of forming the silicide further includes the step of depositing a metal nitride on a metal layer before performing the first RTA.

[0041] In some embodiments, after the step of forming a silicified material, the method further comprises the step of forming a landing layer covering the silicified material; the step of forming a through hole on the landing layer to expose the silicified material, wherein the cross-sectional area of ​​the through hole is greater than or equal to the area of ​​the second top surface of the silicified material; and the step of forming a source / drain contact that contacts the silicified material through a metal contact formed in the through hole. Brief explanation of the drawing

[0042] The accompanying drawings included in and forming part of this specification serve to illustrate aspects of the present disclosure, further explain the principles of the present disclosure together with the description, and enable those skilled in the art to make and use the present disclosure. FIG. 1 illustrates a perspective view of a vertical transistor according to some aspects of the present disclosure. FIG. 2 illustrates a schematic diagram of a memory device comprising an array of memory cells, each having a peripheral circuit and a vertical transistor, according to some aspects of the present disclosure. FIG. 3a illustrates a schematic circuit diagram of a memory device including peripheral circuitry and an array of dynamic random-access memory (DRAM) cells, according to some aspects of the present disclosure. FIG. 3b illustrates a schematic circuit diagram of a memory device including peripheral circuitry and an array of phase-change memory (PCM) cells, according to some aspects of the present disclosure. FIG. 4 illustrates a block diagram of an exemplary system having a memory device according to some aspects of the present disclosure. FIG. 5a illustrates a plan view of an array of vertical transistors of a semiconductor device according to some aspects of the present disclosure. FIG. 5b illustrates a perspective view of the semiconductor structure of a vertical transistor. FIG. 5c illustrates a graph between a silicide transformation temperature T1, an aggregation temperature T2, and a silicide linewidth according to some aspects of the present disclosure. FIGS. 6a through 6p illustrate a manufacturing process for forming a semiconductor structure according to some aspects of the present disclosure. FIG. 6q illustrates a perspective view of a semiconductor structure illustrated in FIG. 6a through 6p according to some aspects of the present disclosure. FIGS. 6r to 6s illustrate another manufacturing process for forming a semiconductor structure according to some aspects of the present disclosure. FIG. 6t illustrates a perspective view of a semiconductor structure illustrated in FIG. 6r to FIG. 6s according to some aspects of the present disclosure. FIGS. 7a through 7e illustrate a manufacturing process for forming a semiconductor device of FIG. 7 according to some aspects of the present disclosure. FIG. 7f illustrates a perspective view of a semiconductor structure illustrated in FIG. 7a through 7d according to some aspects of the present disclosure. FIGS. 7g through 7h illustrate another manufacturing process for forming a semiconductor structure according to some aspects of the present disclosure. FIGS. 8a and 8b illustrate a manufacturing process for forming a semiconductor structure according to some aspects of the present disclosure. FIG. 8c illustrates a perspective view of a semiconductor structure illustrated in FIG. 8a to FIG. 8b according to some aspects of the present disclosure. FIG. 9 illustrates a flowchart of a method for forming a semiconductor device including a vertical transistor according to some aspects of the present disclosure. FIG. 10 illustrates a flowchart of a method for forming another semiconductor device including a vertical transistor according to some aspects of the present disclosure. Specific details for implementing the invention

[0043] It should be understood that while specific configurations and arrangements are discussed, they are done solely for illustrative purposes. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be adopted for various other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified in ways not specifically illustrated in the drawings, and such combinations, adjustments, and modifications are within the scope of this disclosure.

[0044] Generally, terms can be understood at least partially through their usage in context. For example, the term "one or more" as used herein may, depending on the context, be used at least partially to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, even without the use of the suffix "s," it may be understood at least partially, depending on the context, to convey a singular or plural usage. Furthermore, the term "based on" is not necessarily intended to convey an exclusive set of factors; instead, it may be understood to allow for the existence of additional factors that do not need to be explicitly described, at least partially, depending on the context.

[0045] It should be readily understood that in the present disclosure, the meanings of “on,” “above,” and “over” are to be interpreted in the broadest sense, including not only “immediately on” something, but also “on” something that has an intermediate feature or a layer in between, and “above” or “over” are to include not only the meaning of “above” or “over” something, but also the meaning of “above” or “over” something that has no intermediate feature or a layer in between (immediately above something).

[0046] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used for convenience of description to explain the relationship of features to one element or other element(s) or feature(s), as exemplified in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and the spatially relative descriptions used herein may likewise be interpreted accordingly.

[0047] As used herein, the term "substrate" refers to a material to which a subsequent layer of material is added. The substrate itself can be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate may be made of electrically nonconductive materials, such as glass, plastic, or sapphire wafers.

[0048] In this specification, the term “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper structure, or may have a range smaller than that of the underlying or upper structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes on those surfaces. A layer may extend along a horizontal, vertical, and / or tapered surface. A substrate may be a layer and may contain one or more layers within it and / or have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, an interconnect layer may comprise one or more conductors and contact layers (on which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0049] Transistors are used as switch or select devices in memory cells of some memory devices, such as DRAM, PCM, and FRAM (ferroelectric DRAM). However, planar transistors commonly used in conventional memory cells have a horizontal structure in which word lines are embedded in the substrate and bit lines are embedded on the substrate. Since the source and drain of a planar transistor are positioned laterally at different locations, the area occupied by the transistor increases. The design of planar transistors also complicates the arrangement of interconnected structures, such as word lines and bit lines coupled to the memory cell, and limits, for example, the pitch of word lines and / or bit lines, thereby increasing manufacturing complexity and reducing production yield.

[0050] When the feature size of semiconductor technology is reduced to sub-micron levels, the width of the source and drain regions of the transistor continues to decrease, causing the series resistance of the source and drain regions of the device to increase. Additionally, as the size of the interconnect contact holes continues to decrease, the contact resistance of each contact hole increases. For technology platforms with a feature size smaller than or equal to 0.25 µm, the contact hole size is smaller than 0.32 µm. As a result, the contact resistance of a single contact hole increased to over 200 ohms. To reduce the source / drain contact resistance, metal silicides are formed on the source / drain by reacting a metal (e.g., titanium (Ti), cobalt (Co), or nickel-platinum alloy (NiPt)) with the silicon in direct contact with the source / drain. Silicides can reduce the resistance-capacitance (RC) lag of the circuit, thereby reducing the source / drain contact resistance and improving the speed of the circuit.

[0051] Taking Ti silicide as an example, Ti silicide has two crystal structures: a body-centered orthorhombic crystal structure (C49 phase) and a face-centered orthorhombic crystal structure (C54 phase). The C54 phase silicide has a low resistance and stable state. Generally, the temperature at which the C49 phase silicide is formed is lower than the temperature at which the C54 phase silicide is formed. However, as the feature size of the process decreases and the thickness / linewidth of the silicide decreases, the temperature at which Ti silicide transforms from the C49 phase to the C54 phase increases, while the temperature for the aggregation of the C54 phase decreases. If the temperature at which the C54 phase aggregates is lower than the temperature at which it transforms from the C49 phase to the C54 phase, the Ti silicide aggregates directly into the C49 phase, and the low-resistance metallic silicide of the C54 phase disappears. Therefore, Ti silicide cannot be used in processes with a feature size smaller than 0.2 µm.

[0052] To solve one or more of the aforementioned problems, the present disclosure introduces a semiconductor structure and a method for manufacturing the same that increases the linewidth of a silicide by increasing the area over which the silicide is formed. According to some aspects of the present disclosure, an epitaxial structure having a larger surface area is formed on a source / drain. As the silicide is formed on the surface of the epitaxial structure, the area of ​​the silicide increases. According to some aspects of the present disclosure, in addition to the top surface of the source / drain, the area over which the silicide is formed is extended to include the side surface of the source / drain. By removing a portion of the insulating layer surrounding the source / drain, at least a portion of the side surface of the source / drain is exposed to form the silicide. As the linewidth of the silicide increases, the limitation on the feature size is removed, and the silicide can be applied to processes with a feature size smaller than 2 μm.

[0053] FIG. 1 illustrates a perspective view of a vertical transistor (100) according to some aspects of the present disclosure. In some embodiments, unlike a planar transistor in which an active region is formed on a substrate, the vertical transistor (100) comprises a semiconductor body (102) that extends vertically (in the z-direction) over a substrate (not shown). That is, the semiconductor body (102) may extend over the top surface of the substrate so that a channel may be formed not only on the top surface of the semiconductor body (102) but also on one or more side surfaces thereof. Note that FIG. 1 includes x, y, and z axes to further illustrate the spatial relationships of components of a semiconductor device having a vertical transistor (100). The substrate of the semiconductor device comprises two lateral surfaces extending laterally in the xy plane: the top surface of the front side of the wafer on which the semiconductor device may be formed and the bottom surface of the back side opposite the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device is determined with respect to the substrate of the semiconductor device in the z-direction (a vertical direction perpendicular to the xy plane, e.g., the thickness direction of the substrate) when the substrate is located at the lowest plane of the semiconductor device in the z-direction. The same concept for describing spatial relationships applies throughout this disclosure.

[0054] As illustrated in FIG. 1, the semiconductor body (102) may have a rectangular shape exposing its four sides. It is understood that the semiconductor body (102) may have any suitable three-dimensional (3D) shape, such as a polyhedral shape or a cylindrical shape. That is, in a plan view (e.g., xy plane), the cross-section of the semiconductor body (102) may have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other suitable shape. According to the scope of this disclosure, in the case of a semiconductor body in which the cross-section in a plan view is circular or elliptical, the semiconductor body may still be considered to have multiple sides, so that a gate structure is in contact with one or more sides of the semiconductor body. As described below in relation to the manufacturing process, the semiconductor body (102) may be formed from a substrate (e.g., by etching) and thus has the same semiconductor material (e.g., silicon crystalline silicon) as the substrate (e.g., silicon substrate).

[0055] As illustrated in FIG. 1, the vertical transistor (100) may also include a gate structure (104) on one or more planes of the side surface(s) of the active region that are in contact with one or more sides of the semiconductor body (102), for example. In other words, the active region of the vertical transistor (100), for example, the semiconductor body (102), may be at least partially surrounded by the gate structure (104). The gate structure (104) may include a gate dielectric (108) that is in contact with one or more sides of the semiconductor body (102), for example, four side surfaces of the semiconductor body (102), as illustrated in FIG. 1. The gate structure (104) may also include a gate electrode (106) that is in contact with and over the gate dielectric (108). The gate dielectric (108) may include any suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant dielectric. As used herein, the high dielectric constant dielectric material may include any dielectric having a dielectric constant or k-value (k > 7) higher than that of silicon nitride. For example, the gate dielectric (108) may include silicon oxide in the form of a gate oxide. The gate electrode (106) may include any suitable conductive material such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide. For example, the gate electrode (106) may include doped polysilicon in the form of a gate poly. In some embodiments, the gate electrode (106) includes a plurality of conductive layers, such as a W layer on top of a TiN layer. In a semiconductor device having a vertical transistor (100), it is understood that the gate electrode (106) and the word line (not shown in FIG. 1) may be a continuous conductive structure in some examples.In other words, the gate electrode (106) can be viewed as part of a word line (not shown in FIG. 1) forming a gate structure (104), or the word line can be viewed as an extension of the gate electrode (106) to be coupled to a peripheral circuit.

[0056] As illustrated in FIG. 1, a vertical transistor (100) may include a pair of source and drain (110) (S / D, dope regions, also known as source electrode and drain electrode) formed at each of the two terminals (ends) of a semiconductor body (102) in the vertical direction (z direction). The source and drain (110) may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain (110) may be separated in the vertical direction (z direction) by a gate structure (104). In other words, the gate structure (104) is formed vertically between the source and drain (110). Consequently, when the gate voltage applied to the gate electrode (106) of the gate structure (104) is higher than the threshold voltage of the vertical transistor (100), one or more channels (not shown) of the vertical transistor (100) may be formed vertically in the semiconductor body (102) between the source and drain (110). That is, according to some implementations, each channel of the vertical transistor (100) is also formed in a vertical direction in which the semiconductor body (102) extends.

[0057] In some implementations, as illustrated in FIG. 1, the vertical transistor (100) is a multi-gate transistor. That is, the gate structure (104) may form one or more gates by contacting one or more sides of the semiconductor body (102) (e.g., four sides in FIG. 1), and one or more channels may be formed between the source and drain (110) during operation. That is, unlike a planar transistor that includes only a single planar gate (and results in a single planar channel), the vertical transistor (100) illustrated in FIG. 1 may include multiple vertical gates on multiple sides of the semiconductor body (102) due to the 3D structure of the semiconductor body (102) and the gate structure (104) surrounding multiple sides of the semiconductor body (102). As a result, compared to a planar transistor, the vertical transistor (100) illustrated in FIG. 1 may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. Because the channel is completely depleted, the leakage current of the vertical transistor (100) Ioff ) can also be significantly reduced.

[0058] In FIG. 1, the vertical transistor (100) is depicted as a multi-gate transistor, but it is understood that the vertical transistor disclosed herein may include a single-gate transistor, which is described in detail below. That is, the gate structure (104) may be in contact with a single side of the semiconductor body (102), for example, for the purpose of increasing transistor density. Also, although the gate dielectric (108) is depicted as being separated (separate structure) from other gate dielectrics (not shown) of adjacent vertical transistors, it is understood that the gate dielectric (108) may be part of a continuous dielectric layer having multiple gate dielectrics of vertical transistors.

[0059] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), the active region, such as the semiconductor body (e.g., Fin), extends laterally (in the xy plane), and the source and drain are positioned at different locations in the same lateral plane (xy plane). In contrast, in a vertical transistor (100), the semiconductor body (102) extends vertically (in the z direction), and the source and drain (110) are positioned in different lateral planes depending on some implementation. In some implementations, the source and drain (110) are formed at two terminals of the semiconductor body (102) in the vertical direction (z direction), respectively, and thus overlap in the planar view. Consequently, the area occupied by the vertical transistor (100) (in the xy plane) can be reduced compared to planar transistors and lateral multi-gate transistors. Additionally, since interconnections can be routed in different planes, the metal wiring coupled to the vertical transistor (100) can also be simplified.

[0060] FIG. 2 illustrates a schematic diagram of a memory device (200) comprising an array of memory cells, each having a peripheral circuit and a vertical transistor (100), according to some aspects of the present disclosure. The memory device (200) may include a memory cell array (201) and a peripheral circuit (202) coupled to the memory cell array (201). The memory cell array (201) may be any suitable memory cell array in which each memory cell (208) comprises a vertical transistor (100) and a storage unit (212) coupled to the vertical transistor (100). In some embodiments, the memory cell array (201) is a DRAM cell array, and the storage unit (212) is a capacitor for storing charge as binary information stored by individual DRAM cells. In some embodiments, the memory cell array (201) is a PCM cell array, and the storage unit (212) is a PCM element (e.g., including a chalcogenide alloy) for storing binary information of individual PCM cells based on different resistivityes of the PCM element in the amorphous phase and the crystalline phase. In some embodiments, the memory cell array (201) is a ferroelectric RAM (FRAM) cell array, and the storage unit (212) is a ferroelectric capacitor for storing binary information of individual FRAM cells based on switching between two polarization states of the ferroelectric material under an external electric field.

[0061] As illustrated in FIG. 2, memory cells (208) may be arranged in a two-dimensional (2D) array having rows and columns. The memory device (200) may include a word line (204) that combines a peripheral circuit (202) and a memory cell array (201) to control the switch of a vertical transistor (100) of a memory cell (208) located in a row, as well as a bit line (206) that combines a peripheral circuit (202) and a memory cell array (201) to transmit data to the memory cells (208) located in a column and / or receive data from the memory cells (208). That is, each word line (204) is combined to an individual row of memory cells (208), and each bit line is combined to an individual column of memory cells (208).

[0062] According to the scope of the present disclosure, a vertical transistor (100), such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET), can replace a planar transistor as a pass transistor of a memory cell (208), thereby reducing the area occupied by the pass transistor, coupling capacitance, and interconnect routing complexity. For example, a bit line (206) and a storage unit (212) may be formed on opposite sides of the vertical transistor (100). In one example, the bit line (206) may be coupled to a source or drain (110) at the upper end of the semiconductor body (102), while the storage unit (212) may be coupled to another source or drain (110) at the lower end of the semiconductor body (102).

[0063] As illustrated in FIG. 2, a storage unit (212) may be coupled to the source or drain (110) of a vertical transistor (100). The storage unit (212) may include any device capable of storing binary data (e.g., 0 and 1), including but not limited to capacitors for DRAM cells and FRAM cells and PCM elements for PCM cells. In some implementations, the vertical transistor (100) controls the selection and / or state switch of individual storage units (212) coupled to the vertical transistor (100). In some implementations, as illustrated in FIG. 3, each memory cell (208) is a DRAM cell (302) comprising a transistor (304) (e.g., implemented using the vertical transistor (100) of FIG. 1 and 2) and a capacitor (306) (e.g., an example of the storage unit (212) of FIG. 2). The gate of the transistor (304) (e.g., corresponding to the gate electrode (106)) may be coupled to the word line (204), one of the source and drain of the transistor (304) may be coupled to the bit line (206), the other of the source and drain of the transistor (304) may be coupled to one electrode of the capacitor (306), and the other electrode of the capacitor (306) may be coupled to ground. In some implementations, as shown in FIG. 3b, each memory cell (208) is a PCM cell (312) comprising a transistor (314) (e.g., implemented using the vertical transistor (100) of FIG. 1 and 2) and a PCM element (316) (e.g., an example of the storage unit (212) of FIG. 2). The gate of the transistor (314) (e.g., corresponding to the gate electrode (106)) can be coupled to the word line (204), one of the source and drain of the transistor (314) can be coupled to ground, the other of the source and drain of the transistor (314) can be coupled to one electrode of the PCM element (316), and the other electrode of the PCM element (316) can be coupled to the bit line (206).

[0064] Peripheral circuitry (202) (also known as control and sensing circuitry) may be coupled to the memory cell array (201) via bit lines (206), word lines (204), and any other suitable metal wiring. Peripheral circuitry (202) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array (201) by applying voltage signals and / or current signals to each memory cell (208) via word lines (204) and bit lines (206) and sensing from each memory cell (208). For example, the peripheral circuit (202) may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the above-mentioned functional circuit (e.g., subcircuit), or any active or passive component of the circuit (e.g., transistor, diode, resistor, or capacitor). The peripheral circuit (202) uses complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented, for example, by a logic process (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0065] FIG. 4 illustrates a block diagram of a system (400) having a memory device according to some aspects of the present disclosure. The system (400) may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or other suitable electronic device having storage therein. As illustrated in FIG. 4, the system (400) may include a host (408) and a memory system (402) having one or more memory devices (404) and a memory controller (406). The host (408) may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host (408) may be configured to transmit data to the memory device (404) or to receive data from the memory device (404).

[0066] According to some implementations, a memory controller (406) is coupled to a memory device (404) and a host (408) and configured to control the memory device (404). The memory controller (406) can manage data stored in the memory device (404) and communicate with the host (408). The memory controller (406) may be configured to control operations of the memory device (404), such as read, write, and refresh operations. The memory controller (406) may also be configured to manage various functions related to data stored or to be stored in the memory device (404), including but not limited to refresh and timing control, command / request conversion, buffer and scheduling, and power management. In some implementations, the memory controller (406) is further configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Any other suitable functions may also be performed by the memory controller (406). The memory controller (406) can communicate with an external device (e.g., host (408)) according to a specific communication protocol. For example, the memory controller (406) can communicate with an external device through at least one of various interface protocols such as USB protocol, MMC protocol, PCI (peripheral component interconnection) protocol, PCI-E (PCI-express) protocol, ATA (advanced technology attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (small computer small interface) protocol, ESPI (enhanced small disk interface) protocol, IDE (integrated drive electronic) protocol, Firewire protocol, etc.

[0067] According to some aspects of the present disclosure, the vertical transistor disclosed herein comprises a single-gate transistor (also known as a single-side gate transistor) which may have a thicker insulating layer (and / or an air gap) on the opposite side of the gate to reduce coupling between adjacent vertical transistors. According to some aspects of the present disclosure, the vertical transistor disclosed herein may comprise a multi-gate transistor (e.g., having a dual-side gate, a triple-side gate, or an all-around gate) which may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. The vertical transistors having different gate structures described herein are for illustrative purposes only and should not be construed as limiting the present disclosure. FIGS. 5a and FIGS. 5b illustrate a plan view and a perspective view, respectively, of an array of vertical transistors (502) of a semiconductor device (500) according to some aspects of the present disclosure. As illustrated in FIGS. 5a and 5b, the semiconductor device (500) may each include a plurality of word lines (504) extending in a first lateral direction (x direction, referred to herein as the word line direction). The semiconductor device (500) may also include a plurality of bit lines (506) extending in a second lateral direction (y direction, referred to herein as the bit line direction) perpendicular to the first lateral direction. FIG. 5a does not illustrate a cross-section of the semiconductor device (500) in the same lateral plane, and the word lines (504) and bit lines (506) may be formed in different lateral planes for ease of routing, as described in detail below.

[0068] A vertical transistor (502) may be formed at the intersection of a word line (504) and a bit line (506). In some implementations, each vertical transistor (502) includes a semiconductor body (508) and a gate structure (510). As shown in FIG. 5b, the semiconductor body (508) may extend on the substrate (501) in a vertical direction (z-direction) perpendicular to the first lateral direction and the second lateral direction. The vertical transistor (502) may be a single-gate transistor in which the gate structure (510) is coupled to a single side (e.g., one of the four sides in FIG. 5a and FIG. 5b) of the semiconductor body (508) (an active region where a channel is formed). As illustrated in FIGS. 5a and 5b, the vertical transistor (502) is a single-gate transistor in which, in a plan view, the gate structure (510) contacts one side of the semiconductor body (508) (having a rectangular or square cross section) in the bit line direction (y direction). According to some implementations, the gate structure (510) does not surround or contact the other three sides of the semiconductor body (508). The gate structure (510) may include a gate dielectric (512) that contacts one side of the semiconductor body (508) in a plan view, and a gate electrode (514) that contacts the gate dielectric (512). In some implementations, the gate dielectric (512) is positioned laterally between the gate electrode (514) and the semiconductor body (508) in the bit line direction (y direction).

[0069] As described above, the gate electrode (514) may be part of the word line (504), and the word line (504) may be an extension of the gate electrode (514). That is, in the word line direction (x direction), the gate electrodes (514) of adjacent vertical transistors (502), for example in the same row, are continuous and are part of a continuous conductive layer having, for example, the gate electrode (514) and the word line (504). Similarly, in the word line direction, the gate dielectrics (512) of adjacent vertical transistors (502), for example in the same row, are continuous and are part of a continuous dielectric layer having the gate dielectric (512), which extends in the word line direction to contact, for example, the vertical transistor (502) in the same row on the same side. Thus, the gate structure (510) can be viewed as part of a continuous structure that extends in the word line direction to contact the vertical transistor (502) in the same row on the same side. According to some implementations, the gate electrodes (514) and gate dielectrics (512) of the row of vertical transistors (502) are continuous in the word line direction.

[0070] As illustrated in FIG. 5a, the semiconductor device (500) may further include a plurality of parallel dielectric insulating layers (516) each extending in the word line direction (x-direction). Each dielectric insulating layer (516) is positioned laterally between two adjacent rows of vertical transistors (502) in the bit line direction (y-direction) to reduce the coupling effect between adjacent rows of vertical transistors (502). As described in detail below, the thickness of the dielectric insulating layer (516) (dimensions in the bit line direction) and / or whether an air gap is formed in the dielectric insulating layer (516) may affect the efficiency of coupling reduction.

[0071] The vertical transistor (502) further includes a source and a drain (referred to as 518 since both positions are interchangeable) positioned at the two ends (upper end and lower end) of the semiconductor body (508), respectively, in the vertical direction (z direction). In some implementations, one of the source / drain (518) (e.g., at the upper end in FIG. 5b) is coupled to a capacitor (not shown) through a metal contact (520), and the other of the source / drain (518) (e.g., at the lower end in FIG. 5b) is coupled to a bit line (506). That is, the vertical transistor (502) may have a first terminal in the positive z direction and a second terminal opposite the first terminal in the negative z direction, as shown in FIG. 5b. In some implementations, a metal bit line (e.g., a bit line (506) made of a metal material) is coupled to the second terminal of the vertical transistor (502). Additional structures are formed on the source / drain (518) to reduce the contact resistance of the source / drain (518). For example, high-dose ion implantation is implied for the source / drain (518) to increase the doping concentration of the source / drain (518) to reduce the resistance. In this embodiment, a metal silicide (522) is formed on the top surface of the source / drain (518) to reduce the resistance of the source / drain (518). The additional structures described herein are for illustrative purposes only and should not be construed as limiting the disclosure. A metal contact (520) contacts the metal silicide (522). The metal silicide (522) may be WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having higher conductivity than doped silicon.

[0072] Taking Ti-silicon as an example, as the silicon thickness or linewidth decreases, the temperature T1 at which Ti-silicon transforms from the C49 phase to the C54 phase increases, as exemplified in Fig. 5c, while the temperature T2 for the aggregation of the C54 phase decreases, resulting in a critical point where T1 = T2. In situations where T2 is lower than T1, Ti-silicon will aggregate immediately after the C49 phase, and the C54 phase will disappear, forming a high-resistance metallic silicon. Therefore, Ti-silicon technology is used only in large-scale processes, such as those with feature sizes of 0.5 µm to 0.25 µm. Furthermore, in the case of silicon, since there is relatively little silicon available to participate in the reaction at the edge, the thickness of the metallic silicon formed at the edge will also become thinner accordingly. Consequently, the resistance of the edge will increase. For processes with a linewidth of less than 0.18 µm, this characteristic will be very severe.

[0073] Referring to FIG. 6q, in some implementations, a semiconductor structure (600A) is provided to increase the linewidth of a silicide in a process having a relatively small feature size. The semiconductor structure (600A) includes a plurality of vertical transistors (502) and a memory controller (not shown) coupled to the semiconductor structure (600A) and configured to control the semiconductor structure (600A). Each of at least some of the plurality of vertical transistors (502) includes a semiconductor body (508) extending from a substrate (501) in a first direction (i.e., the z-direction in FIG. 6q). The semiconductor body (508) includes a source / drain (518) at one end of the semiconductor body. A gate structure (510) is coupled to at least one side of the semiconductor body (508). The gate structure (510) includes a gate dielectric (512) and a gate electrode (514). A source / drain epitaxial structure is formed on a source / drain (518) located far from the substrate (501). The projection of the source / drain epitaxial structure on the substrate (501) is larger than the projection of the source / drain (518), as illustrated in FIG. 6q. Silicate (540) is formed on at least some of the side surfaces and the top surface of the source / drain epitaxial structure. In FIG. 6, the silicate (540) covers all surfaces exposed from the insulating layer (530) to maximize the area of ​​the silicate (540), and the area of ​​the silicate (540) is larger than the area of ​​the first surface of the source / drain (518). FIG. 6t illustrates another embodiment in which the side surface of a source / drain epitaxial structure is covered by a second insulating layer (664) and a silicide (672) is formed on the top surface of the source / drain epitaxial structure. This embodiment is applied when the distance between two adjacent transistors is small and a short circuit may occur due to the silicide formed on the side surface.

[0074] FIGS. 6a through 6r illustrate a manufacturing process for forming a semiconductor device comprising a vertical transistor having an increased linewidth according to some aspects of the present disclosure. FIG. 9 illustrates a flowchart of a method (900) for forming a semiconductor device comprising a vertical transistor having an increased linewidth according to some aspects of the present disclosure. It is understood that the operations illustrated in the method (900) are not exhaustive and that other operations may be performed before, after, or between any of the operations illustrated. Additionally, some operations may be performed simultaneously or in a different order than that illustrated in FIG. 9.

[0075] Referring to FIG. 9, the method (900) begins with an operation (902) in which a semiconductor body of a vertical transistor extending in a first direction on a substrate is formed. The substrate may be a silicon substrate.

[0076] As illustrated in FIG. 6a, a plurality of parallel semiconductor walls (605) are formed in the y direction (bit line direction). To form the semiconductor walls (605), a plurality of parallel trenches are formed in the silicon substrate (602) in the y direction. In some implementations, a lithography process is performed to pattern the trenches and semiconductor walls (605) using an etching mask (604) (e.g., a photoresist mask and / or a hard mask) based, for example, on the design of the bit line, and a wet etching process, such as dry etching and / or reactive ion etching (RIE), is performed to etch the trenches of the silicon substrate (602). Thus, semiconductor walls (605) extending in a vertical direction on the silicon substrate (602) can be formed. Since the semiconductor wall (605) is formed by etching the silicon substrate (602), the semiconductor wall (605) may have the same material as the silicon substrate (602), such as single-crystal silicon. FIG. 6a illustrates both a side view of a cross-section along the x-direction (e.g., the word line direction in the AA plane) (the bottom part of FIG. 6a) and a top view of a cross-section in the xy plane (e.g., the BB plane passing through the semiconductor wall (605)) (the top part of FIG. 6a).

[0077] As illustrated in FIG. 6a, trench isolation (608) is formed in the trench. In some embodiments, a dielectric material, such as silicon oxide and / or silicon nitride, is deposited to completely fill the trench using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove excess dielectric material deposited beyond the top surface of the etching mask (604). Consequently, parallel semiconductor walls (605) can be separated by the trench isolation (608). It is understood that in some examples, before depositing the trench insulation (608), a liner layer (e.g., a natural oxide layer, not shown) may be formed on the sidewall of the semiconductor wall (605) to treat defects that occurred on the sidewall of the semiconductor wall (605) by an etching process.

[0078] As illustrated in FIG. 6b, a plurality of parallel trenches (610) extending in the x direction (word line direction) are formed to form an array of semiconductor bodies (606) extending in the vertical direction on the silicon substrate (602). In some embodiments, a lithography process is performed to pattern the trenches (610) perpendicular to the trench insulation (608) using an etching mask (e.g., a photoresist mask and / or a hard mask) based on the design of the word line, for example, and one or more wet etching processes, such as dry etching and / or RIE, are performed on the silicon substrate (602) and the trench insulation (608) to etch the trenches (610) of the silicon substrate (602). Consequently, semiconductor walls (605) (shown in FIG. 8a) can be cut by trenches (610) to form an array of semiconductor bodies (606) extending vertically on each silicon substrate (602). Since the semiconductor bodies (606) are formed by etching the silicon substrate (602), the semiconductor bodies (606) may have the same material as the silicon substrate (602), such as single-crystal silicon. FIG. 6b illustrates both a side view of a cross-section along the y-direction (bit line direction, e.g., plane AA passing through the semiconductor bodies (606)) (bottom part of FIG. 6b) and a top view of a cross-section along the xy-plane (e.g., plane BB passing through the semiconductor bodies (606)) (top part of FIG. 6b).

[0079] As illustrated in FIG. 6c, a liner layer (611) is formed on the top surface and sidewalls of the semiconductor body (606). The liner layer (611) is formed, for example, for thermal oxidation (e.g., in situ vapor generation ( on siteThe natural oxide layer of the semiconductor body (606) having single-crystal silicon grown using steam generation (ISSG) oxidation may be a natural oxide layer that can heal defects on the surface of the semiconductor body (606) caused by the etching process. The pad layer (612) is formed on the top of the silicon substrate (602) at the bottom of the trench (610) by depositing a dielectric, such as silicon nitride and / or a high-dielectric constant (high-k) dielectric (e.g., Al2O3), using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to partially fill the trench (610). In some embodiments, the pad layer (612) has silicon nitride. Deposition conditions, such as deposition rate and / or time, may be controlled to control the thickness of the pad layer (612) and prevent the trench (610) from being completely filled. Consequently, the bottom surface of the trench (610) can be raised so as to be above the bottom surface of the semiconductor body (606). As described below, the pad layer (612) is used as a stop layer when removing the silicon substrate (602) and later forms a step between the semiconductor body (606) and the gate electrode, so the thickness (dimension in the vertical direction) of the pad layer (612) can be determined based on the step and / or substrate removal process.

[0080] FIG. 6c illustrates both a side view of a cross section along the y-direction (e.g., the bit line direction in the AA plane passing through the semiconductor body (606)) (the bottom part of FIG. 6c) and a top view of a cross section in the xy-plane (e.g., the BB plane passing through the semiconductor body (606) and the pad layer (612)) (the top part of FIG. 6c). As illustrated in the side view, opposite sides of the semiconductor body (606) in the y-direction are partially exposed by the trench (610) (without considering the liner layer (611); as illustrated in the top view, the other opposite sides of the semiconductor body (606) in the x-direction are in contact with the trench insulation (608). In other words, the semiconductor body (606) is surrounded by the trench (610) and the trench insulation (608).

[0081] As illustrated in FIG. 6d, a sacrificial layer (615) is formed on the sidewalls and top surface of the semiconductor body (606). For each semiconductor body (606), as illustrated in the top view, two sacrificial layers (615) may be formed on opposite sides of each semiconductor body (606) in the bit line direction (y direction). As illustrated in the side view, the sacrificial layer (615) may be a continuous layer in the bit line direction, as it may be deposited on the top surface of the semiconductor body (606) and the bottom surface of the trench (610). In some embodiments, the sacrificial layer (615) is formed by depositing one or more materials different from the materials of the pad layer (612) and the liner layer (611) on the pad layer (612) and the liner layer (611) using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to partially fill the trench (610). For example, a high dielectric constant such as Al2O3 may be deposited to form a sacrificial layer (615) on a pad layer (612) having silicon nitride and a liner layer (611) having silicon oxide. FIG. 6d illustrates both a side view of a cross-section along the y-direction (e.g., the bit line direction in the AA plane passing through the semiconductor body (606)) (the bottom part of FIG. 6d) and a top view of a cross-section along the xy-plane (e.g., the BB plane passing through the semiconductor body (606) and the sacrificial layer (615)) (the top part of FIG. 6d).

[0082] In some implementations, the first sacrificial layer formed on the first side and the second side of the semiconductor body is separated from each other. As illustrated in FIG. 6e, a portion of the sacrificial layer (615) formed on the top surface of the semiconductor body (606) and the bottom surface of the trench (610) is removed, leaving only the sacrificial layer (615) formed on the side wall of the semiconductor body (606) in the bit line direction. That is, by removing a portion of the sacrificial layer (615) on the bottom surface of the trenches (610), the continuous layer can be separated into individual pieces in the bit line direction. Thus, two sacrificial layers (615) can be separated from each other on opposite sides of each semiconductor body (606) in the bit line direction. In some implementations, some of the sacrificial layers (615) formed over the bottom surface of the trenches (610) are removed by a dry etching process such as RIE, and some of the sacrificial layers (615) formed over the top surface of the semiconductor bodies (606) are removed by the same dry etching process and / or a planarization process such as CMP.

[0083] As illustrated in FIG. 6e, a sacrificial layer (617) is formed on the sidewall of the sacrificial layer (615) to fill the trench (610) (illustrated in FIG. 6d). Each sacrificial layer (617) may be a continuous layer in the direction of the word line as illustrated in the plan view and may be surrounded by the sacrificial layer (615). In some embodiments, the sacrificial layer (617) is formed by depositing one or more materials different from the materials of the pad layer (612) and the sacrificial layer (615) on the pad layer (612) and the sacrificial layer (615) using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to completely fill the trench (610). For example, polysilicon may be deposited to form a sacrificial layer (617) on a pad layer (612) having silicon nitride and a sacrificial layer (615) having a high dielectric constant (e.g., Al2O3). Similar to the sacrificial layer (615), any excess material of the sacrificial layer (617) on the top surface of the semiconductor body (606) and the sacrificial layer (615) may be removed by a dry etching process such as RIE and / or a planarization process such as CMP, so that the sacrificial layer (617) can be separated into individual pieces in the bit line direction. Thus, for each semiconductor body (606), depending on some implementation, a pair of sacrificial layers (615, 617) are sequentially formed on one side in the bit line direction, and another pair of sacrificial layers (615, 617) are sequentially formed on the opposite side in the bit line direction. FIG. 6e illustrates both a side view of a cross-section along the y-direction (e.g., the bit line direction in the AA plane passing through the semiconductor body (606)) (the bottom part of FIG. 6e) and a plan view of a cross-section along the xy-plane (e.g., the BB plane passing through the semiconductor body (606) and the sacrificial layers (615, 617)) (the top part of FIG. 6e).

[0084] Next, this method (900) proceeds to method (904) to form a gate structure on at least one side of the semiconductor body (606) according to a self-aligned gate process. The self-aligned gate process can be used to form both single-gate transistors and multi-gate transistors. There are various methods for forming the gate structure of a vertical transistor. The self-aligned gate process described herein is for illustrative purposes only and should not be construed as limiting the present disclosure.

[0085] As illustrated in FIG. 6f, a trench (631) is formed by removing a sacrificial layer (615) (shown in FIG. 6e) on one side of the semiconductor body (606) in the bit line direction where a gate structure is not to be formed, and the opposite side of the semiconductor body (606) where a gate structure is not to be formed is exposed. To remove the sacrificial layer (615), a lithography process such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) can be performed to pattern the trench (631) using an etching mask (629) (e.g., a photoresist mask and / or a hard mask), which exposes the sacrificial layer (615) on one side of the semiconductor body (606) in the bit line direction where the gate structure will not be formed, but covers and protects the sacrificial layer (615) on the other side of the semiconductor body (606) in the bit line direction where the gate structure will be formed, as shown in FIG. 6f. Then, one or more selective etching processes, such as wet etching, are performed through an etching mask (629) to etch away only the sacrificial layer (615) on one side of the semiconductor body (606) in the bit line direction where the gate structure is not to be formed, while leaving the sacrificial layer (615) on the opposite side of the semiconductor body (606) intact. The etching agent may have a relatively high selectivity (e.g., more than 5 times) of the sacrificial layer (615) with respect to the sacrificial layer (617) and the liner layer (611), so that the sacrificial layer (617) and the liner layer (611) may also be left intact without protection by the etching mask. For example, the sacrificial layer (615) having Al2O3 can be selectively removed using an etching agent having phosphoric acid (H3PO4) without removing the sacrificial layer (617) having polysilicon and the liner layer (611) having silicon oxide.

[0086] As illustrated in FIG. 6g, a dielectric insulating layer (618) is formed on an exposed side of a semiconductor body (606) from which a sacrificial layer (615) is optionally removed. To form the dielectric insulating layer (618), dielectric material(s), such as silicon oxide, are deposited using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to fill a trench (631) (as illustrated in FIG. 6f). Depending on the lateral dimension of the trench (631), the trench (631) may not be completely filled with the dielectric material (e.g., silicon oxide) deposited when forming the dielectric insulating layer (618), and thus may have an air gap therein according to a self-aligning gate process to form a "thick gate" as illustrated in FIG. 6g. In some examples, it is understood that when the lateral dimensions of the trench (631) are sufficiently large, the dielectric material(s) can completely fill the trench (631) while forming the dielectric insulating layer (618), thereby eliminating the air gap.

[0087] As illustrated in FIG. 6h, to form a trench (613), the sacrificial layer (617) and the remaining sacrificial layer (615) are selectively removed, exposing the side of the semiconductor body (606) on which the gate structure is to be formed. To etch away the sacrificial layer (617) and the remaining sacrificial layer (615), a selective etching process, such as wet etching, may be performed sequentially. The first etchant may have a relatively high selectivity (e.g., more than 5 times) of the sacrificial layer (617) with respect to the dielectric insulating layer (618) and the liner layer (611), and the second etchant may have a relatively high selectivity (e.g., more than 5 times) with respect to the dielectric insulating layer (618) and the liner layer (611), so that the dielectric insulating layer (618) and the liner layer (611) are left intact. For example, a sacrificial layer (617) having polysilicon can be selectively removed using a first etching agent having potassium hydroxide (KOH), and a sacrificial layer (615) having Al2O3 can be selectively removed using a second etching agent having phosphoric acid (H3PO4) without a dielectric insulating layer (618) and liner layer (611) having silicon oxide. As illustrated in FIG. 6h, the pad layer (612) may remain even after the sacrificial layers (615, 617) are removed.

[0088] As illustrated in FIG. 6i, the gate dielectric (614) is formed on the exposed side of the semiconductor body (606) in the trench (613) (illustrated in FIG. 6h). According to some embodiments, the gate dielectric (614) is not formed on the opposite side of the semiconductor body (606) in the bit line direction where the dielectric insulating layer (618) is formed. In some embodiments, the gate dielectric (614) is formed by depositing a layer of dielectric, such as silicon oxide, across the exposed sidewall of the semiconductor body (606) using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, without completely filling the trench (613). In some examples, it is understood that the gate dielectric (614) may not be part of a continuous dielectric layer. For example, a thermal oxidation process, such as ISSG oxidation, is performed to further grow a natural oxide (e.g., silicon oxide) from the liner layer (611) onto the semiconductor body (606) (e.g., single-crystal silicon) so as to become the gate dielectric (614). It is also understood that since the gate dielectric (614) and the liner layer (611) may have the same material, such as silicon oxide, the interface and boundary between the gate dielectric (614) and the liner layer (611) may become indistinguishable. Accordingly, for ease of explanation, the liner layer (611) in contact with the gate dielectric (614) may be exemplified in the present disclosure as part of the gate dielectric (614), for example, as shown in FIG. 6i.

[0089] As illustrated in FIG. 6i, a gate electrode (616) is formed on the side of the gate dielectric (614) in a trench (613) (illustrated in FIG. 6h). The gate electrode (616) may be formed between the gate dielectric (614) and the dielectric insulating layer (618) in the direction of the bit line to fill the trench (613). In some embodiments, the gate electrode (616) includes a gate conductor (621) and a barrier layer (619) surrounding the gate conductor (621). In some embodiments, the gate electrode (616) is formed by depositing one or more layers of a conductive layer, such as a metal or a metal compound, on the exposed sidewall of the gate dielectric (614) using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, and completely fills the trench (613). For example, a TiN layer and a W layer may be sequentially deposited into a trench (613) to form a barrier layer (619) having TiN and a gate conductor (621) having W, respectively. That is, the self-aligned gate process disclosed herein may allow the gate conductor (621) deposited later to be surrounded by the first deposited barrier layer (619) when filling the trench (613).

[0090] After the gate structure is formed, the method (900) proceeds to operations (906 and 908) to form a source / drain at the distal end of the semiconductor body (606) away from the silicon substrate (602) and to form a first insulating layer surrounding the semiconductor body (606) and the gate structure. At least a portion of the second surface of the source / drain and the first surface are exposed from the first insulating layer. The second surface is perpendicular to the first surface.

[0091] As illustrated in FIG. 6j, the upper portion of the gate electrode (616) is replaced by a dielectric plug (640) so that the top end of the gate electrode (616) is located below the top end of the semiconductor body (606). To form the dielectric plug (640), the gate electrode (616) can be etched back (recessed) from the top by wet etching and / or dry etching so that the upper end of the gate electrode (616) is located below the top surface of the semiconductor body (606), and consequently, the recess can be filled with the dielectric plug (640) by depositing a dielectric, such as silicon oxide, using one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. The dielectric insulating layer (618) and the dielectric plug (640) form a first insulating layer (642) surrounding the semiconductor body (606). It is understood that since the dielectric insulating layer (618) and the dielectric plug (640) may have the same material, such as silicon oxide, the interface and boundary between the dielectric insulating layer (618) and the dielectric plug (640) may become indistinguishable. The gate dielectric (614) in contact with the gate electrode (616) and the remaining part of the gate electrode (616) (hereinafter referred to as "gate electrode (616)" for convenience of explanation) become a gate structure (655) that is coupled to one side of the semiconductor body (606) in the bit line direction, according to some implementations as illustrated in FIG. 6j. FIG. 6j illustrates both a side view of a cross-section along the y-direction (e.g., the bit line direction in the AA plane passing through the semiconductor body (606)) (the bottom part of FIG. 6j) and a plan view of a cross-section in the xy-plane (e.g., the BB plane passing through the semiconductor body (606), the gate electrode (616) and the gate dielectric (614)) (the top part of FIG. 6j).

[0092] As illustrated in FIG. 6j, the exposed upper end of the semiconductor body (606) (e.g., the end separated from the silicon substrate (602) in the vertical direction) is doped to form a drain or source (624) of a vertical transistor (see “source / drain (624”) below). For example, the source / drain (624) may be the source terminal of the vertical transistor. In some implementations, an injection process and / or a thermal diffusion process are performed to form the source / drain (624) to dope a P-type dopant or an N-type dopant to the exposed upper end of the semiconductor body (606).

[0093] After the source / drain (624) and the first insulating layer (642) are formed, the method (900) proceeds to operation (910) to grow an epitaxial structure from the first surface of the source / drain (624). The area of ​​the first surface of the epitaxial structure is larger than the area of ​​the first surface of the source / drain (624).

[0094] As illustrated in FIG. 6k, an epitaxial structure (660) is formed on the top surface of the source / drain (624) via CVD, PVD, ALD, or any combination thereof. The crystal plane orientation significantly influences the shape and size of the epitaxial structure (660) formed by epitaxy. For example, in the CVD process, when the crystal plane orientations used for epitaxial growth are (111), (110), and (100), the resulting shapes of the epitaxially grown epitaxial structure (660) are hexagonal, trapezoidal, and rectangular, respectively. By selecting the crystal plane orientation and controlling the parameters of the CVD, it is possible to produce an epitaxial structure (660) having a desired shape and size. For example, in FIG. 6k, a rectangular epitaxial structure is designed to form a cuboid epitaxial structure. It is understood that the epitaxial structure (660) may be of any suitable shape and size, as long as the projection of the epitaxial structure (660) on the silicon substrate (602) is larger than the projection of the source / drain (624) on the silicon substrate (602).

[0095] After the epitaxial structure (660) is formed, the method (900) proceeds to operation (912) to form a silicified material based on the epitaxial structure (660).

[0096] As illustrated in FIG. 6L, a silicide (662) is formed to cover the epitaxial structure (660). To form the silicide (662), the first step is to deposit a layer of metal (Ti, Co, NiPt, etc.) on the epitaxial structure (660) using PVD. Then, to form the silicide (662) on the exposed surface of the epitaxial structure (660), two rapid thermal annealing (RTA) processes and one selective wet etching process are performed. Metallic silicides including TiSi2, CoSi2, and NiPtSi are formed. Metals such as Ti, Co, or NiPt do not react with the dielectric material, i.e., the first insulating layer (642), to form the metallic silicide. They will only react with the epitaxial structure (660) in direct contact to form the metallic silicide. Silicate (662) can reduce the square resistance and contact resistance of the epitaxial structure (660).

[0097] In this embodiment, taking the titanium disilide process as an example, two RTA processes are required to form the silicide (662). First, a layer of Ti film is deposited, and then a layer of TiN film covering the Ti film is deposited. The purpose of depositing the TiN film is to prevent Ti from flowing during rapid thermal annealing. The temperature of the first RTA is relatively low, only 450 to 650°C, at which point Ti reacts with the silicon of the epitaxial structure (660) to form high-resistance metal silicide Ti2Si having a body-centered tetragonal crystal structure (C49 phase). Since Ti does not react with silicon dioxide to form metal silicide, the surface TiN film and the Ti film that does not react with silicon dioxide can be removed using selective wet etching. The second RTA has a high temperature of at least 750°C, and some process platforms require high temperatures up to 950°C. The second RTA can convert the high-resistance metallic silicide Ti2Si on the C49 phase into the low-resistance metallic silicide TiSi2 with a face-centered orthorhombic crystal structure (C54 phase). TiSi2 has excellent thermodynamic properties and is very stable. If only one RTA is used to produce the low-resistance metallic silicide TiSi2, the process temperature of this step will be very high. In a high-temperature environment, silicon diffuses along the grain boundaries of TiSi2, which can cause excessive growth of TiSi2 on the silicon dioxide boundaries, which cannot be removed by wet etching and can cause a short circuit.

[0098] As illustrated in FIG. 6m, after the silicide (662) is formed, a second insulating layer (664) is formed to surround the silicide (662), and the second insulating layer (664) is aligned with the silicide (662) by exposing the top surface of the silicide (662) from the second insulating layer (664). As illustrated in FIG. 6n, a landing layer (626) is formed on the second insulating layer (664) and the silicide (662). The landing layer (626) is a dielectric layer configured to separate the silicide (662) from a metal layer formed on a vertical transistor. The landing layer (626) may be formed by depositing silicon oxide and / or silicon nitride on the second insulating layer (664) and the silicide (662) via PVD. Next, the deposited dielectric material is planarized to remove excess material and create a smooth, flat surface, forming a metal layer such as a CMP.

[0099] As illustrated in FIG. 6o, a through hole (627) is formed on the landing layer (626) to expose the silicide (662) using a patterning process (e.g., dry / wet etching and photolithography of the dielectric material of the landing layer (626)), so that the source / drain (624) can be connected to the metal layer through a contact formed in the through hole (627). The minimum cross-sectional area of ​​the through hole (627) is greater than or equal to the area of ​​the top surface of the silicide (662) to reduce contact resistance. In this embodiment, the area of ​​the top surface of the silicide (662) is greatly enhanced by the formation of an epitaxial structure (660). For example, referring to FIG. 6o in this embodiment, the minimum cross-sectional area of ​​the through hole (627) is more than twice the area of ​​the top surface of the source / drain (624). The aspect ratio of the through hole is the ratio of the depth to the width. In this implementation, the aspect ratio of the through hole (627) is significantly reduced due to the increase in the width of the through hole (627). This makes it easier to control the etching process and remove residual material from the bottom of the through hole (627). Additionally, as the etching window area of ​​the etching process increases, the difficulty of the process for etching the through hole (627) is reduced, effectively preventing open circuits caused by incomplete etching and damage to the source / drain (624) caused by excessive etching.

[0100] After the through hole (627) is formed, as illustrated in FIG. 60, a metal contact (628) in contact with the silicide (662) is formed in the through hole (627) to connect the silicide (662) to the metal layer or source / drain contact for further connection. The metal contact (628) may be tungsten (W), copper (Cu), aluminum (Al), etc., and metal compounds (e.g., titanium nitride (TiN) or tantalum nitride (TaN), etc.). The metal contact (628) may be formed by sputtering, evaporation, or electroplating. An increased aspect ratio of the through hole (627) also reduces the difficulty of forming the metal contact (628).

[0101] Another embodiment of the present disclosure is illustrated in FIGS. 6r through 6t. This embodiment differs from the aforementioned embodiment in the order in which the second insulating layer (664) and the silicide (672) are formed. Referring to FIGS. 6r and 6t, the second insulating layer (664) is formed before the silicide (672) to surround the epitaxial structure (660), so that all side surfaces of the epitaxial structure (660) are covered by the second insulating layer (664) and only the top surface of the epitaxial structure (660) is exposed to the outside. Accordingly, the silicide (672) may be formed only on the top surface of the epitaxial structure (660), and as shown in FIGS. 6l and 6s, the distance D2 between the silicides (672) of two adjacent transistors in this embodiment is greater than the distance D2 between the silicides (662) of two adjacent transistors in the aforementioned embodiment. In this way, a short circuit caused by the possibility of contact of silicide between two adjacent transistors is prevented. FIG. 6t illustrates a perspective view of a semiconductor structure (600B) of the present embodiment according to FIG. 6l and FIG. 6s, and it is clear that the silicide (672) is formed only on the top surface of the epitaxial structure (660) and the side surface of the epitaxial structure (660) is surrounded by a second insulating layer (664).

[0102] Referring to FIG. 7f and FIG. 8c, according to another embodiment of the present disclosure, semiconductor structures (700) and (800) are provided to increase the linewidth of a silicide in a process having a relatively small feature size. Semiconductor structures (700 and 800) differ from semiconductor structure (600A) in the formation and structure of the silicide in each vertical transistor (502). To form the silicide (662 or 672) in semiconductor structure (600A), since the side surface of the source / drain (624) is covered by the first insulating layer (642) and cannot be used for epitaxial growth, the epitaxial structure is formed based on the top surface of the source / drain (624), and is formed only based thereon. While forming the silicide in the semiconductor structures (700 and 800), the first insulating layer (642) is etched to expose at least some side surfaces of the source / drain (624). In the semiconductor structure (700), the linewidth of the silicide (762) can be increased as much as possible by forming an epitaxial structure based on at least some side surfaces and the top surface of the source / drain (624) to obtain a larger volume epitaxial structure. In the semiconductor structure (800), the epitaxial structure is removed, and the silicide (810) is formed directly on at least some side surfaces and the top surface of the source / drain (624) without forming an epitaxial structure, thereby simplifying the manufacturing process and reducing costs while increasing the linewidth of the silicide.

[0103] FIGS. 7a through 7f illustrate differences in structure and manufacturing process between semiconductor structure (700A) and semiconductor structure (600A). FIGS. 8a through 8c illustrate differences in structure and manufacturing process between semiconductor structure (800A) and semiconductor structure (600A). FIG. 10 illustrates a flowchart of a method (1000) for forming a semiconductor device including a vertical transistor having a silicide having an increased linewidth. It is understood that the operations illustrated in the method (1000) are not complete and that other operations may be performed before, after, or between any of the illustrated operations. Additionally, some operations may be performed simultaneously or in a different order than that illustrated in FIG. 10.

[0104] Referring to FIG. 10, the method (1000) begins with an operation (1002 to 1006) in which a semiconductor body of a vertical transistor extending in a first direction on a substrate is formed. Then, a gate structure is formed on at least one side of the semiconductor body, and a source / drain is formed at a distal end of the semiconductor body away from the substrate. The manufacturing process and structure in operation (1002 to 1006) may be the same as the method (900) described in FIG. 6a to 6g, which is not repeated here. After that, the method (1000) proceeds to an operation (1008) in which a first insulating layer surrounding the semiconductor body (606) and the gate structure, at least a portion of a second surface of the source / drain, and the first surface are exposed from the first insulating layer, and the second surface is perpendicular to the first surface.

[0105] As illustrated in FIG. 7a, the recessed dielectric plug (740) is formed by etching at least a portion of the dielectric plug (640) to expose at least a portion of the side surface of the source / drain (624). To prevent a short circuit between the source / drain (624) and the gate electrode (616), the dielectric plug (640) cannot be completely removed. The thickness of the recessed dielectric plug (740) is the distance between the silicide (762) and the gate electrode (616). The thickness of the recessed dielectric plug (740) is greater than the critical distance to maintain the silicide insulated from the gate structure. The critical distance is the minimum distance between the silicide (762) and the gate electrode (616) to prevent strike-through. The critical distance depends on the feature size of the semiconductor structure (700). For example, the critical distance is longer than half the length of the gate electrode (616).

[0106] Referring to FIG. 10, the method (1000) carries out an operation (1010) in which silicified material is formed on at least a portion of at least one second surface of the source / drain and on the first surface.

[0107] FIGS. 7a through 7e illustrate an implementation in which an epitaxial structure (760) is formed before the silicification is formed. As illustrated in FIG. 7b, the epitaxial structure (760) is formed based on at least a portion of the side surface of the source / drain (624) and the top surface via CVD, PVD, ALD, or any combination thereof. In the CVD process, for example, when the crystal plane orientations used for epitaxial growth are (111), (110), and (100), the resulting shapes of the epitaxially grown epitaxial structure (760) are hexagonal, trapezoidal, and rectangular, respectively. Note that the crystal plane orientation of the top surface is different from the crystal plane orientation of the side surface of the source / drain (624). Therefore, compared to FIG. 6k, it is more complex to produce an epitaxial structure (760) having the desired shape and size. By using additional lateral surfaces of the source / drain (624) as a basis for growing the epitaxial structure, it is easier to form an epitaxial structure having a larger area than the source / drain (624). For example, in FIG. 7b, a rectangular epitaxial structure is designed to form a cuboid epitaxial structure. It is understood that the epitaxial structure (760) can be any suitable shape and size as long as the projection of the epitaxial structure (760) on the silicon substrate (602) is larger than the projection of the source / drain (624) on the silicon substrate (602). For example, trapezoidal or other irregular shapes are also applicable to the present disclosure.

[0108] After the epitaxial structure (760) is formed, as illustrated in FIG. 7c, a silicide (762) is formed based on the epitaxial structure (760) to cover the epitaxial structure (760). To form the silicide (762), the first step is to deposit a layer of metal (Ti, Co, NiPt, etc.) on the epitaxial structure (660) using PVD. Then, two rapid thermal annealing (RTA) processes and one selective wet etching process are performed to form the silicide (762) on the exposed surface of the epitaxial structure (760). Metallic silicides including TiSi2, CoSi2, and NiPtSi are formed. Metals such as Ti, Co, or NiPt do not react with the dielectric material, i.e., the first insulating layer (742), to form the metal silicide. These will only react with the epitaxial structure (760) in direct contact to form a metal silicide. The silicide (762) can reduce the square resistance and contact resistance of the epitaxial structure (760).

[0109] In this embodiment, taking the Ti-silicon process as an example, two RTA processes are required to form the silicon (762). First, a layer of Ti film is deposited, and then a layer of TiN film covering the Ti film is deposited. The purpose of depositing the TiN film is to prevent Ti from flowing during rapid thermal annealing. The temperature of the first RTA is relatively low, only 450 to 650°C, at which point Ti reacts with the silicon of the epitaxial structure (760) to form high-resistance metal silicon Ti2Si having a body-centered tetragonal crystal structure (C49 phase). Since Ti does not react with silicon dioxide to form metal silicon, the surface TiN film and the Ti film that does not react with silicon dioxide can be removed using selective wet etching. The second RTA has a high temperature of at least 750°C, and some process platforms require high temperatures up to 950°C. The second RTA can convert the high-resistance metallic silicide Ti2Si on the C49 phase into the low-resistance metallic silicide TiSi2 with a face-centered orthorhombic crystal structure (C54 phase). TiSi2 has excellent thermodynamic properties and is very stable. If only one RTA is used to produce the low-resistance metallic silicide TiSi2, the process temperature of this step will be very high. In a high-temperature environment, silicon diffuses along the grain boundaries of TiSi2, and TiSi2 may grow excessively on the silicon dioxide boundaries, which cannot be removed by wet etching and can cause a short circuit.

[0110] The thickness of the silicide is positively related to the duration of the first RTA process. As the RTA process is prolonged, more silicon is consumed and the silicide becomes thicker. FIG. 7c illustrates a silicide (762) formed under the first RTA duration, and FIG. 7d illustrates a silicide (792) formed under an extended first RTA duration. In FIG. 7c, silicon of the epitaxial structure (760) is consumed to form the silicide (762). In FIG. 7d, as the first RTA process is extended, after the silicon of the epitaxial structure (760) is depleted, at least a portion of the silicon of the source / drain (518) is consumed and reacts with metallic Ti to form the silicide (792). The silicide (792) has a larger volume than the silicide (762). By adjusting the duration of the first RTA process, the thickness and shape of the silicified material (762) can be precisely controlled to obtain the desired thickness.

[0111] As illustrated in FIG. 7e, after the silicified material (762) is formed, a second insulating layer (764) is formed to surround the silicified material (762), and the second insulating layer (764) is aligned with the silicified material (762) by exposing the top surface of the silicified material (762) from the second insulating layer (764). After the silicified material (762) is formed, a landing layer is formed to cover the silicified material, and a through hole on the landing layer is formed to expose the silicified material. The area of ​​the cross-section of the through hole is greater than or equal to the area of ​​the second top surface of the silicified material. Then, a source / drain contact is formed to contact the silicified material through a metal contact formed in the through hole. The process after the silicified material (762) is the same as the method (900) described in FIG. 6m through FIG. 6p and is not repeated.

[0112] FIGS. 7g and 7h illustrate another embodiment according to the method (1000), wherein the order of forming the second insulating layer (764) and the silicide (772) is as follows. Referring to FIGS. 7g and 7h, the second insulating layer (764) is formed before the silicide (772) to surround the epitaxial structure (760), so that all side surfaces of the epitaxial structure (760) are covered by the second insulating layer (764) and only the top surface of the epitaxial structure (760) is exposed to the outside. Thus, the silicide (772) can be formed only on the top surface of the epitaxial structure (760), and as illustrated in FIG. 7e, the distance between the silicides (772) of two adjacent transistors in this embodiment is longer than the distance between the silicides (762) of two adjacent transistors in the embodiment described above. In this way, a short circuit caused by the possibility of silicified contact between two adjacent transistors is prevented.

[0113] FIGS. 8a and 8b illustrate an implementation in which an epitaxial structure is removed to simplify the manufacturing process. As illustrated in FIG. 8a, a recessed dielectric plug (840) is formed by etching at least a portion of the dielectric plug (640) to expose at least a portion of the side surface of the source / drain (624). To avoid a short circuit between the source / drain (624) and the gate electrode (616), the dielectric plug (640) cannot be completely removed. The thickness of the recessed dielectric plug (840) is the distance between the silicide (862) and the gate electrode (616). The thickness of the recessed dielectric plug (840) is greater than the critical distance to maintain the silicide insulated from the gate structure. The critical distance is the minimum distance between the silicide (862) and the gate electrode (616) to prevent strike-through. The critical distance depends on the feature size of the semiconductor structure (800). For example, the critical distance is longer than half the length of the gate electrode (616).

[0114] After at least a portion of the side surface of the source / drain (624) is exposed, a silicide (862) is formed based on the exposed side surface of the source / drain (624), as illustrated in FIG. 8b. To form the silicide (862), the first step is to deposit a layer of metal (Ti, Co, NiPt, etc.) on the source / drain (624) using PVD. Then, two rapid thermal annealing (RTA) processes and one optional wet etching process are performed to form the silicide (862) on the exposed surface of the source / drain (624). Metallic silicides including TiSi2, CoSi2, and NiPtSi are formed. Metals such as Ti, Co, or NiPt do not react with the dielectric material, i.e., the first insulating layer (842), to form the metal silicide. These react only with the source / drain (624) in direct contact to form a metal silicide. The silicide (862) can reduce the square resistance and contact resistance of the source / drain (624). The method and process for forming the silicide (862) are the same as the implementation described above, so they will not be repeated here.

[0115] By increasing the area of ​​the source / drain for forming the silicide in a three-dimensional semiconductor device, the linewidth of the silicide formed on the source / drain of the semiconductor structure is significantly improved. As a result, the silicide can be used in a manufacturing process having a small feature size. According to some aspects of the present disclosure, an epitaxial structure having a larger surface area is formed on the source / drain to increase the linewidth of the silicide. According to some aspects of the present disclosure, in addition to the top surface of the source / drain, the area where the silicide is formed can be extended to include the side surface of the source / drain to increase the linewidth of the silicide. By applying the present disclosure, the limitation on the feature size of the silicide process is removed.

[0116] The foregoing description of a specific implementation may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed implementation based on the teachings and guidelines set forth herein.

[0117] The breadth and scope of the present disclosure shall not be limited by any of the exemplary embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A semiconductor structure comprising a vertical transistor, wherein the vertical transistor comprises: a semiconductor body extending in a first direction, wherein the semiconductor body comprises a source / drain at one end of the semiconductor body; a gate structure coupled to at least one side of the semiconductor body, wherein the gate structure comprises a gate dielectric and a gate electrode; and a silicide, wherein an epitaxial structure is formed between the source / drain and the silicide, wherein at least a portion of the silicide is over the source / drain, and the area of ​​the silicide is larger than the area of ​​the first surface of the source / drain, and the first surface is perpendicular to the first direction. Claim 2 A semiconductor structure according to claim 1, further comprising a first insulating layer surrounding the semiconductor body, wherein the first surface of the source / drain is exposed from the first insulating layer, and the epitaxial structure covers the first surface of the source / drain. Claim 3 A semiconductor structure according to claim 1, further comprising a first insulating layer surrounding the semiconductor body, wherein at least a portion of the second surface of the source / drain and the first surface are exposed from the first insulating layer, and the epitaxial structure covers at least a portion of the second surface of the source / drain and the first surface. Claim 4 A semiconductor structure according to claim 1, further comprising a second insulating layer surrounding the epitaxial structure, wherein a first top surface of the epitaxial structure is exposed from the second insulating layer, and the silicide covers the first top surface of the epitaxial structure. Claim 5 A semiconductor structure according to claim 1, further comprising a second insulating layer surrounding the silicified material, wherein the second upper surface of the silicified material is exposed from the second insulating layer. Claim 6 A semiconductor structure according to claim 1, wherein the silicide is insulated from the gate structure, and the minimum distance between the silicide and the gate structure is greater than the critical distance. Claim 7 A semiconductor structure according to claim 1, further comprising: a landing layer covering the silicified material; and a metal contact extending through the landing layer and in contact with a second upper surface of the silicified material, wherein the surface area of ​​the metal contact in contact with the silicified material is smaller than or equal to the surface area of ​​the second upper surface of the silicified material. Claim 8 In claim 1, the silicified material comprises a semiconductor structure including an element of titanium (Ti), cobalt (Co), or nickel-platinum alloy (NiPt). Claim 9 In claim 8, the silicide is a semiconductor structure comprising titanium disilicide (TiSi2) having a face-centered orthorhombic structure (C54 phase). Claim 10 A semiconductor system comprising: a semiconductor structure including a plurality of vertical transistors; and a memory controller coupled to the semiconductor structure and configured to control the semiconductor structure, wherein each of at least some of the plurality of vertical transistors comprises: a semiconductor body extending in a first direction, wherein the semiconductor body includes a source / drain at one end of the semiconductor body; a gate structure coupled to at least one side of the semiconductor body, wherein the gate structure includes a gate dielectric and a gate electrode; and a silicide, wherein an epitaxial structure is formed between the source / drain and the silicide, wherein at least a portion of the silicide is over the source / drain, and the area of ​​the silicide is larger than the area of ​​a first surface of the source / drain, and the first surface is perpendicular to the first direction. Claim 11 A method for forming a semiconductor structure comprising: forming a semiconductor body of the semiconductor structure extending in a first direction from a substrate; forming a gate structure on at least one side of the semiconductor body; forming a source / drain at a distal end of the semiconductor body away from the substrate; forming a first insulating layer surrounding the semiconductor body and the gate structure; and forming a silicide, wherein an epitaxial structure is formed between the source / drain and the silicide, at least a portion of the silicide is over the source / drain, the area of ​​the silicide is larger than the area of ​​a first surface of the source / drain, and the first surface is perpendicular to the first direction. Claim 12 In claim 11, the first surface of the source / drain is exposed from the first insulating layer, and the method for forming the semiconductor structure further comprises the step of growing the epitaxial structure from the first surface of the source / drain before forming the silicide, wherein the area of ​​the first surface of the epitaxial structure is larger than the area of ​​the first surface of the source / drain, and the silicide is formed based on the epitaxial structure. Claim 13 A method for forming a semiconductor structure according to claim 12, further comprising, after the step of forming the first insulating layer, the step of etching the first insulating layer to expose at least a portion of the second surface of the source / drain—wherein the second surface of the source / drain is perpendicular to the first surface of the source / drain—and wherein the epitaxial structure is formed on at least a portion of the second surface of the source / drain exposed from the first insulating layer and growing from the first surface. Claim 14 A method for forming a semiconductor structure according to claim 12, wherein the step of forming the silicide comprises: forming a second insulating layer covering the epitaxial structure—the second insulating layer being aligned with the epitaxial structure, and at least a first surface of the epitaxial structure being exposed from the second insulating layer—; depositing a metal layer covering at least the first surface of the epitaxial structure exposed from the second insulating layer; and heating the metal layer to form the silicide. Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete Claim 26 delete Claim 27 delete Claim 28 delete Claim 29 delete Claim 30 delete Claim 31 delete Claim 32 delete Claim 33 delete Claim 34 delete Claim 35 delete Claim 36 delete Claim 37 delete Claim 38 delete Claim 39 delete Claim 40 delete

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