System and method for defragmentation of memory device

Abstract

In a specific aspect, the memory controller includes a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a controller processor, wherein the controller processor controls the memory device, receives a mapping update command, and is configured to update the L2P address mapping table according to the mapping update command by replacing the original logical address of the file's logical block address (LBA) segment with a new contiguous logical address of the file's merged LBA segment, and changing the original mapping relationship between the original logical address of the file's LBA segment and the file's physical address to a new mapping relationship between the new contiguous logical address of the file's merged LBA segment and the file's physical address.

Description

Technology Field

[0001] This application is a continuation of international application number PCT / CN2021 / 139955 filed on December 21, 2021, under the title “System and method for defragmenting a memory device,” the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a system and method for defragmenting a memory device. Background Technology

[0003] Data stored in system and memory devices becomes fragmented over time. This degrades the performance of system and memory devices by reducing access and processing speeds. Occasionally, this leads to additional undesirable corruption and data loss. Defragmentation is a process that reduces the degree of fragmentation by reorganizing data on storage devices for faster access and better system performance.

[0004] In one aspect, the memory controller includes a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file, and a controller processor, wherein the controller processor controls the memory device, receives a mapping update command, and is configured to update the L2P address mapping table according to the mapping update command by replacing the original logical address of the file's logical block address (LBA) segment with a new contiguous logical address of the file's merged LBA segment, and changing the original mapping relationship between the original logical address of the file's LBA segment and the file's physical address to a new mapping relationship between the new contiguous logical address of the file's merged LBA segment and the file's physical address.

[0005] In some implementations, the controller memory includes volatile controller memory for storing L2P address mapping tables corresponding to files.

[0006] In some implementations, the controller memory further includes non-volatile controller memory. The controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

[0007] In some implementations, the controller processor is configured to send a command to the host acknowledging that the L2P address mapping table has been updated.

[0008] In some implementations, the controller processor is configured to generate a merge log by recording a new mapping relationship between the new contiguous logical addresses of the file's merged LBA segments and the file's physical addresses.

[0009] In some implementations, in response to a sudden power loss, the controller processor is configured to rebuild the volatile L2P address mapping table based on a merge log that records the new mapping relationship between the new contiguous logical addresses of the file's merged LBA segments and the file's physical addresses since the memory system was restarted.

[0010] In some implementations, the controller processor is configured to scan the physical-to-logical (P2L) address mapping tables of the merge log and metadata blocks, and in response to updates to the merge log, the controller processor is configured to rebuild the P2L address mapping tables based on the merge log.

[0011] In another aspect, the memory system comprises a memory device containing physical data blocks and a memory controller, the memory controller comprising a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file and a controller processor, the controller processor is configured to control the memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by replacing the original logical address of the file's logical block address (LBA) segment with a new contiguous logical address of the file's merged LBA segment, and changing the original mapping relationship between the original logical address of the file's LBA segment and the file's physical address to a new mapping relationship between the new contiguous logical address of the file's merged LBA segment and the file's physical address.

[0012] In some implementations, the controller memory includes volatile controller memory for storing L2P address mapping tables corresponding to files.

[0013] In some implementations, the controller memory further includes non-volatile controller memory. The controller processor is configured to store the updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

[0014] In some implementations, the controller processor is configured to send a command to the host acknowledging that the L2P address mapping table has been updated.

[0015] In some implementations, the controller processor is configured to generate a merge log by recording a new mapping relationship between the new contiguous logical addresses of the file's merged LBA segments and the file's physical addresses.

[0016] In some implementations, in response to a sudden power loss, the controller processor is configured to rebuild the L2P address mapping table based on a merge log that records the new mapping relationship between the new contiguous logical addresses of the file's merged LBA segments and the file's physical addresses since the memory system was restarted.

[0017] In some implementations, the controller processor is configured to scan the physical-to-logical (P2L) address mapping tables of the merge log and metadata blocks, and in response to updates to the merge log, the controller processor is configured to rebuild the L2P address mapping tables based on the merge log.

[0018] In another aspect, the system comprises a host including a host memory configured to store a file, and a host processor configured to execute a merge LBA command to relocate the original logical address of a file’s logical block address (LBA) segment to a new contiguous logical address of a file’s merged LBA segment and transmit a mapping update command, and a memory system, wherein the memory system comprises a memory device including a physical data block and a memory controller, wherein the memory controller comprises a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file and a controller processor, wherein the controller processor is configured to control the memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by replacing the original logical address of a file’s LBA segment with a new contiguous logical address of a file’s merged LBA segment and changing the original mapping relationship between the original logical address of a file’s LBA segment and a file’s physical address to a new mapping relationship between the new contiguous logical address of a file’s merged LBA segment and a file’s physical address.

[0019] In some implementations, the controller memory includes volatile controller memory for storing L2P address mapping tables corresponding to files.

[0020] In some implementations, the host processor is configured to rewrite the original logical address of the file's LBA segment to the new logical address of the file's merged LBA segment by rewriting all logical addresses of the file's LBA segment to an empty or unused LBA segment with logical addresses in a contiguous and sequential order such that the original logical address of the file's LBA segment becomes the new contiguous logical address of the file's merged LBA segment.

[0021] In some implementations, the host processor is configured to send a mapping update command that causes the memory controller to update the L2P address mapping table according to the new contiguous logical addresses of the merged LBA segments of the file.

[0022] In some implementations, the host processor is configured to receive a command from the memory controller acknowledging that the L2P address mapping table has been updated.

[0023] In some implementations, the host processor is configured to update the index node of the file after acknowledging that the L2P address mapping table has been updated.

[0024] In some implementations, the host processor is configured to update the file's index node by pointing the new LBA segment to the new contiguous logical address of the merged LBA segment.

[0025] In another aspect, a method for operating a memory controller comprises the steps of receiving a mapping update command from a host, and updating a logical-to-physical (L2P) address mapping table according to the mapping update command by replacing the original logical address of the file's LBA segment with a new contiguous logical address of the file's merged LBA segment, and changing the original mapping relationship between the original logical address of the file's LBA segment and the file's physical address to a new mapping relationship between the new contiguous logical address of the file's merged LBA segment and the file's physical address.

[0026] In some implementations, this method further includes the step of sending a command to the host acknowledging that the L2P address mapping table has been updated.

[0027] In some implementations, this method further includes the steps of writing a new mapping relationship between the new contiguous logical address of the merged LBA segment of the file and the physical address of the file to the merge log, and rebuilding the L2P address mapping table according to the merge log after the memory system is restarted in response to a sudden power loss.

[0028] In some implementations, the step of constructing an L2P address mapping table includes scanning the physical-to-logical (P2L) address mapping table of the merge log and metadata block, and, in response to a determination that the merge log is being updated, reconstructing the L2P address mapping table based on the merge log. Brief explanation of the drawing

[0029] The accompanying drawings, which are incorporated into and form part of this specification, illustrate aspects of the present disclosure and, together with the description, explain the present disclosure and further serve to enable a person skilled in the art to practice and use the present disclosure. FIG. 1 illustrates a block diagram of an exemplary system having a host and a memory system according to some aspects of the present disclosure. FIG. 2a illustrates a drawing of an exemplary memory card having a memory device according to some aspects of the present disclosure. FIG. 2b illustrates an exemplary solid-state drive (SSD) having a memory device according to some aspects of the present disclosure. FIG. 3 illustrates a schematic diagram of an exemplary memory device including peripheral circuitry according to some aspects of the present disclosure. FIG. 4a illustrates a block diagram of an exemplary memory system including a memory controller and a memory device according to some aspects of the present disclosure. FIG. 4b illustrates a block diagram of an exemplary memory system including a memory controller and a memory device according to some aspects of the present disclosure. FIG. 5 illustrates a block diagram of an exemplary system including a host and a memory controller according to some aspects of the present disclosure. FIG. 6 illustrates a block diagram illustrating an exemplary method of assembling pieces according to some aspects of the present disclosure. FIG. 7 illustrates a block diagram illustrating an exemplary method of assembling pieces according to some aspects of the present disclosure. FIG. 8 illustrates a block diagram illustrating an exemplary defragmentation method under sudden power loss, according to some aspects of the present disclosure. FIG. 9 illustrates a flowchart of an exemplary method for operating a memory controller according to some aspects of the present disclosure. FIG. 10 illustrates a flowchart of an exemplary method for operating a host according to some aspects of the present disclosure. Aspects of the present disclosure will be described with reference to the accompanying drawings. Specific details for implementing the invention

[0030] Specific configurations and arrangements are discussed, but should be understood to be for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be utilized in various other applications. Functional and structural features as described in this disclosure may be combined, adjusted, and modified in ways not specifically illustrated in the drawings, and such combinations, adjustments, and modifications are within the scope of this disclosure.

[0031] Generally, terms may be understood at least in part from their use in context. For example, the term “one or more” as used herein may, depending at least in part by context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms in the singular sense may again be understood, depending at least in part by context, to convey either a singular or a plural usage. Additionally, the term “based on” may not necessarily be intended to convey an exclusive set of factors, but instead may also, depending at least in part by context, allow for the existence of additional factors that are not necessarily explicitly described.

[0032] Disk defragmentation is a technique that allows users to defragment not only hard disk drives (HDDs) but also other removable storage devices. For example, Windows systems such as Windows 7 include a disk defragmentation utility called Microsoft Drive Optimizer or Disk Defragmenter, which allows users to defragment their hard disks and increase data access speeds by rearranging files stored on the disk to occupy contiguous storage locations and improve the computer's overall performance. However, disk defragmentation is not considered effective for solid-state drives (SSDs). In fact, defragmenting SSDs is generally not recommended because it consumes all of the SSD's write cycles and can potentially cause the SSD to fail prematurely. Nevertheless, due to the advancement of SSDs and the increase in their storage capacity, the software's input / output stack (I / O stack) is becoming a bottleneck in the system. In other words, fragmented files at the logical level degrade system performance.

[0033] One solution to address defragmentation at the logical level is to use a defragmenter such as e2defrag. e2defrag can read every segment of a file's logical address and select contiguous logical address blocks to write to. However, e2defrag not only updates logical address blocks but also updates physical blocks whenever a logical address block is updated. This increases the write amplification effect, an undesirable phenomenon associated with flash memory and solid-state drives, where the actual amount of information physically written to the storage medium is a multiple of the logical amount intended to be written. This write amplification can exhaust the SSD faster than expected and shorten its lifespan. Furthermore, conventional e2defrag is time-consuming due to the lengthy process of regularly updating physical address blocks whenever a segment is read and a logical address block is updated. This is not sufficiently effective for resolving fragmentation issues at the logical level.

[0034] Furthermore, conventional defragmentation tools may not be well-designed for power loss protection to ensure that data is not lost while the SSD is writing data in the event of a sudden power failure. A sudden power loss while the defragmentation process is in progress can cause serious system damage or data loss. A mechanism to prevent data loss due to sudden power loss during defragmentation is highly desirable.

[0035] To address one or more of the aforementioned problems, the present disclosure introduces a solution designed such that a merged logical block address (LBA) command merges an LBA segment of a file into a merged LBA segment of the file and updates a logical-to-physical (L2P) address mapping table based on the merged LBA segment of the file. Furthermore, a merge log is generated to record the mapping relationship between the L2P address mapping table and the physical-to-logical (P2L) address mapping table before updating the L2P address mapping table. Thus, after a sudden power loss, L2P can be rebuilt or recovered by using the merge log and the P2L address mapping table.

[0036] FIG. 1 illustrates a block diagram of an exemplary system (100) having a memory device according to some aspects of the present disclosure. The system (100) may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device inside. As illustrated in FIG. 1, the system (100) may include a host (108) having a host memory (110) and a host processor (112), and a memory system (102) having one or more memory devices (104) and a memory controller (106).

[0037] The host (108) may be an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host (108) may be coupled to a memory controller (106) and configured to transmit or receive data to or from a memory device (104) via the memory controller (106). For example, the host (108) may transmit program data in a program operation or receive read data in a read operation. The host processor (112) may be a control unit (CU) or an arithmetic and logic unit (ALU). The host memory (110) may be a memory unit including a register or a cache memory. The host (108) is configured to receive and transmit commands and instructions to and from the memory controller (106) of the memory system (102), and to execute or perform a number of functions and operations provided in the present disclosure, which will be described later.

[0038] The memory device (104) may be any memory device disclosed in this disclosure, such as a NAND flash memory device, comprising a page buffer having several parts, for example, four quarters. It is noted that NAND flash is merely an example of a memory device for illustrative purposes. It may include any suitable solid-state non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), spin-transfer torque magnetic random-access memory (STT-RAM), or resistive random-access memory (RRAM). In some implementations, the memory device (104) comprises a three-dimensional (3D) NAND flash memory device.

[0039] The memory controller (106) may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuit, and other suitable hardware, firmware, and / or software configured to perform various functions described in detail below.

[0040] A memory device (106) is coupled to a memory device (104) and a host (108) according to some implementation and configured to control the memory device (104). The memory controller (106) can manage data stored in the memory device (104) and communicate with the host (108). In some implementations, the memory controller (106) is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller (106) is designed to operate in a high-duty-cycle environment, such as an SSD or an embedded multi-media-card (eMMC), used as a data storage for mobile devices such as smartphones, tablets, laptop computers, etc., and as an enterprise storage array. The memory controller (106) may be configured to control the operations of the memory device (104), such as read, erase, and program operations, by providing commands, such as read commands, to the memory device (104). For example, the memory controller (106) may be configured to control read operations by providing read commands to the peripheral circuits of the memory device (104). The memory controller (106) may also be configured to manage various functions, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling, for data stored or to be stored in the memory device (104). In some implementations, the memory controller (106) is additionally configured to process an error correction code (ECC) for data read from or written to the memory device (104).Any other suitable function can be performed by the memory controller (106), for example, not only formatting the memory device (104).

[0041] The memory controller (106) can communicate with an external device (e.g., a host (108)) according to a specific communication protocol. For example, the memory controller (106) can communicate with an external device through at least one of various interface protocols such as the USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0042] The memory controller (106) and one or more memory devices (104) may be integrated into various types of storage devices contained in the same package, such as, for example, a universal flash storage (UFS) package or an eMMC package. That is, the memory system (102) may be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 2a, the memory controller (106) and a single memory device (104) may be integrated into a memory card (202). The memory card (202) may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card (202) may further include a memory card connector (204) that connects the memory card (202) to a host (e.g., the host (108) of FIG. 1). In another example as illustrated in FIG. 2b, a memory controller (106) and a plurality of memory devices (104) may be integrated into an SSD (206). The SSD (206) may further include an SSD connector (208) that connects the SSD (206) to a host (e.g., the host (108) of FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD (206) is greater than that of the memory card (202).

[0043] The memory controller (106) is configured to receive and transmit commands to and from the host (108) and to execute or perform a number of functions and operations provided in the present disclosure, which will be described later.

[0044] FIG. 3 illustrates a schematic circuit diagram of an exemplary memory device (300) including peripheral circuitry according to some aspects of the present disclosure. The memory device (300) may be an example of the memory device (104) of FIG. 1. It is noted that the NAND flash disclosed herein is merely an example of a memory device for illustrative purposes. It may include any suitable solid-state non-volatile memory, such as NOR Flash, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device (300) may include a memory cell array (301) and peripheral circuitry (302) coupled to the memory cell array (301). The memory cell array (301) may be a NAND flash memory cell array provided in the form of an array of NAND memory strings (308) in which memory cells (306) are each extended vertically over a substrate (not shown). In some implementations, each NAND memory string (308) includes a plurality of memory cells (306) that are combined in series and stacked vertically. Each memory cell (306) may have a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell (306). Each memory cell (306) may be a floating gate type memory cell including a floating gate transistor or a charge trap type memory cell including a charge trap transistor.

[0045] In some implementations, each memory cell (306) is a single-level cell (SLC) capable of having two possible memory states and storing 1 bit of data accordingly. For example, the first memory state “0” may correspond to a first range of voltage, and the second memory state “1” may correspond to a second range of voltage. In some implementations, each memory cell (306) is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC can store 2 bits per cell, 3 bits per cell (also known as a triple-level cell (TLC)), or 4 bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. For example, if each MLC stores 2 bits of data, the MLC can be programmed to take one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0046] As illustrated in FIG. 3, each NAND memory string (308) may include a source select gate (SSG) transistor (310) at its source end and a drain select gate (DSG) transistor (312) at its drain end. The SSG transistor (310) and the DSG transistor (312) may be configured to activate the selected NAND memory string (308) (a column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings (308) of the same block (304) are combined through the same source line (SL) (314), for example, a common SL. In other words, all NAND memory strings (308) of the same block (304) have an array common source (ACS) depending on some implementations. The drain of the DSG transistor (312) of each NAND memory string (308) is coupled to each bit line (316) through which data can be read or written via an output bus (not shown), depending on some implementation. In some implementations, each NAND memory string (308) is configured to be selected or deselected by applying a select voltage (e.g., 0V) (e.g., exceeding the threshold voltage of the DSG transistor (312)) to the gate of each DSG transistor (312) through one or more DSG lines (313) and / or by applying a select voltage (e.g., 0V) (e.g., exceeding the threshold voltage of the SSG transistor (310)) to the gate of each SSG transistor (310) through one or more SSG lines (315).

[0047] As illustrated in FIG. 3, a NAND memory string (308) may be composed of a plurality of blocks (304), each of which may have a common source line (314) coupled to, for example, an ACS. In some implementations, each block (304) is a basic data unit for an erase operation, that is, all memory cells (306) on the same block (304) are erased simultaneously. To erase memory cells (306) in a selected block (304), the source line (314) coupled to the selected block (304), as well as the unselected block (304) in the same plane as the selected block (304), may be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or more). Memory cells (306) of adjacent NAND memory strings (308) can be combined via word lines (318) that select which row of memory cells (306) is affected by read and program operations. In some implementations, each word line (318) is combined with a page (320) of memory cells (306) which is the basic data unit for program and read operations. The bit size of one page (320) may be related to the number of NAND memory strings (308) combined by word lines (318) in one block (304). Each word line (318) may include a plurality of control gates (gate electrodes) of each memory cell (306) within each page (320) and a gate line combining the control gates. Peripheral circuits (302) can be coupled to the memory cell array (301) through bit lines (316), word lines (318), source lines (314), SSG lines (315) and DSG lines (313).The peripheral circuit (302) may include any suitable analog, digital, and mixed-signal circuits to enable the operation of the memory cell array (301) by applying and detecting voltage signals and / or current signals to and from each target memory cell (306) through bit lines (316), word lines (318), source lines (314), SSG lines (315), and DSG lines (313). The peripheral circuit (302) may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0048] FIG. 4a illustrates a block diagram of an exemplary memory system (102) including a memory controller (106) and a memory device (104) according to some aspects of the present disclosure. As shown in FIG. 4a, the memory controller (106) may include a controller processor (408), such as a memory chip controller (MCC) or a memory controller unit (MCU). The controller processor (408) is configured to control the module to perform the functions disclosed in the present disclosure by executing commands or instructions. The controller processor (408) may also be configured to control the operation of each peripheral circuit by generating and transmitting various control signals, such as read commands for read operations. The controller processor (408) may also transmit a clock signal to another peripheral circuit (302) at a desired frequency, period, and duty cycle to organize the operation of each peripheral circuit (302) for synchronization, for example. The memory controller (106) may further include volatile controller memory (411) and non-volatile controller memory. The volatile controller memory (411) may include a register or cache memory that enables data stored therein to be read, written, and erased at faster access and processing speeds, while failing to retain stored information after power is removed. In some implementations, the volatile controller memory (411) includes dynamic random-access memory (DRAM) and static random-access memory (SRAM). The non-volatile controller memory (413) may retain stored information even after power is removed. In some implementations, the non-volatile controller memory (413) includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM.The memory device (104) may include a memory cell array such as the memory cell array (301) of FIG. 3. In some implementations, the non-volatile controller memory (413) may not be provided to the memory controller (106), for example, the non-volatile controller memory (413) is placed outside the memory controller (106) but is coupled to the memory controller (106). In some implementations, the controller memory (e.g., 411 or 413) is configured to store an L2P address mapping table (e.g., 4271, 4273) corresponding to a file (e.g., 129).

[0049] FIG. 4b illustrates a block diagram of an exemplary memory system (102) comprising a memory controller (106) and a memory device (104) according to some aspects of the present disclosure. As illustrated in FIG. 4b, the memory controller (106) may include a memory controller interface (429) configured to receive and transmit commands or instructions to and from a host (e.g., the host (108) of FIG. 1). In some implementations, the memory controller interface (429) is coupled to a controller processor (408) to receive and transmit commands or instructions that cause the controller processor (408) to perform the functions disclosed in the present disclosure.

[0050] The memory controller (106) may also include an update module (421) configured to generate and update a volatile L2P address mapping table (4271), a volatile merge log (4251), a non-volatile L2P mapping table (4273), and a non-volatile merge log (4253). The update module (421) may be implemented through a firmware program within the firmware of the controller processor (408). In some implementations, the update module (421) is configured to update a physical data block (431) and / or a metadata block (433) of the memory device (104). In some implementations, the update module (421) may be within the controller processor (408) or coupled to the controller processor (408) and may be controlled by the controller processor (408) to execute commands and instructions from the host (108). For example, the update module (421) is configured to execute a mapping update command received from the host (108) and to update the volatile L2P address mapping table (4271) according to the mapping update command. In some implementations, the update module (421) is configured to update the volatile L2P address mapping table (4271) by rewriting the contiguous logical address of the file's merged LBA segment to the volatile L2P address mapping table (4271). In some implementations, the update module (421) is configured to update the volatile L2P address mapping table (4271) by replacing the original logical address of the file's LBA segment with the new contiguous logical address of the file's merged LBA segment, and by changing the original mapping relationship between the file's original logical address of the file's LBA segment and the file's physical address to the new mapping relationship between the file's merged LBA segment and the file's physical address. The process of forming the contiguous logical address of the file's merged LBA segment will be described later.And after updating the L2P address mapping table (4271), the update module (421) of the controller processor (408) will send a corresponding command to the host (108) acknowledging that the volatile L2P address mapping table (4271) has been updated, and thus the host (108) can update the index node of the file in the host memory (110).

[0051] In some implementations, the volatile L2P address mapping table (4271) is stored and processed in the volatile controller memory (411) and configured to be transferred to and updated with the non-volatile L2P address mapping table (4273) stored in the physical data block (431) so that the data is not erased after power is turned off. In some implementations, after the system is restarted, the volatile L2P address mapping table (4271) in the volatile controller memory (411) may periodically be loaded from the non-volatile L2P address mapping table (4273) in the physical data block (431) for faster access and processing speeds. In some implementations, the non-volatile L2P address mapping table (4273) may also be stored in the non-volatile controller memory (413) of the memory controller (106).

[0052] The merge logs (e.g., volatile merge log (4251) and non-volatile merge log (4253)) are configured to record the mapping relationship between the L2P address mapping table (e.g., 4271 or 4273) and the physical address of the physical data block (431) before updating the L2P address mapping table. In some implementations, the merge logs are configured to record the new mapping relationship between the physical address of the file (129) and the new contiguous logical address of the merged LBA segment of the file (129), which respectively update the L2P address mapping table. Thus, after a sudden power loss, the volatile L2P address mapping table (4271), which may not yet be updated, can be reconstructed or recovered by using the physical address of the physical data block (431) and the non-volatile merge log (4253) after the system (e.g., 100) is restarted. In some implementations, the update rate of the non-volatile merge log (4253) is faster than that of the non-volatile L2P address mapping table (4273), which has already been written during the sudden power loss, but is relatively small data compared to the non-volatile L2P address mapping table (4273), so it may not cause excessive write amplification. Specifically, in response to the sudden power loss, the recovery module (423) of the controller processor (408) can scan the physical-logical (P2L) address mapping table (435) and the non-volatile merge log (4253) within the metadata block (433) of the memory device (104), and in response to the update of the non-volatile merge log (4253), the volatile L2P address mapping table (4271) can be reconstructed based on the physical address of the physical data block (431) maintained before the sudden power loss and the non-volatile merge log (4253).And in response to the non-volatile merge log (4253) not being updated, the volatile L2P address mapping table (4271) is reconstructed according to the physical address of the physical data block (431) and the physical-logical (P2L) address mapping table (435) of the metadata block (433) that were maintained prior to the sudden power loss. It is noted that the metadata block (433) is a relatively small part of the data block in the memory cell array (301). The metadata block (433) is configured to store logical address information of the data stored in the physical data block (431). When data is written to the physical data block (431), the logical address information is simultaneously written to the metadata block (433), so that the data can be recovered after the sudden power loss. In some implementations, the volatile merge log (4251) is stored and processed in the volatile controller memory (411) and configured to be transferred to and updated with the non-volatile merge log (4253) stored in the physical data block (431) so that the data is not erased after power is turned off. In some implementations, after the system is restarted, the volatile merge log (4251) in the volatile controller memory (411) may be periodically loaded from the non-volatile merge log (4253) in the physical data block (431) for faster access and processing speeds. In some implementations, the non-volatile merge log (4253) may also be stored in the non-volatile controller memory (413) of the memory controller (106). The recovery module (423) may be implemented via a firmware program in the firmware of the controller processor (408).

[0053] FIG. 5 illustrates a block diagram of an exemplary system (100) comprising a host (108) and a memory controller (106) according to some aspects of the present disclosure. As illustrated in FIG. 5, the host (108) may include a host interface (125), a host memory (110), and a host processor (112). The host interface (125) is configured to receive commands or instructions from a user to perform or execute specific functions or operations. The host memory (110) may store logical addresses, such as the logical block address (LBA) of a file (e.g., file (129)) and an index node (127) of a file (e.g., an inode). The host processor (112) may include an index node update module (121) (e.g., an inode update module) and a merge LBA module (123), or may be coupled to these. The index node update module (121) is configured to update the index node (127) of a file after the controller processor (408) of the memory controller (106) (e.g., FIG. 4b) sends a command to the host (108) acknowledging that the volatile L2P address mapping table (4271) has been updated. The index node update module (121) may also update the index node (127) of a file after receiving a command that the physical data block (431) (e.g., FIG. 4b) has been updated. It is noted that an index node (e.g., an inode) may be a data structure of a Unix-style file system that describes a file system object such as a file or a directory. It may be a file data structure that stores information about any Linux file, excluding its name and data. It stores metadata of the file, including the file size, the device on which the file is stored, the user and group IDs associated with the file, or the permissions required to access the file.In some implementations, the host processor (112) is configured to update the index node (127) of the file (129) by pointing to a new LBA segment with a contiguous logical address of the merged LBA segment.

[0054] A merge LBA module (123) included in or combined with a host processor (112) is configured to execute a merge LBA command to rearrange LBA segments of a file (129) (e.g., fragments of logical addresses of logical blocks) into merged LBA segments. For example, as shown in FIG. 6, file A (129) may contain one or more LBA segments (e.g., LBA segment 1, LBA segment 2, LBA segment 3, …, LBA segment N). Whenever a file is modified in the operating system, the number of LBA segments increases and the file becomes fragmented. When using a conventional e2defrag tool, as mentioned above, it may be necessary to read multiple LBA segments one by one and find a contiguous block of logical addresses to write the file's Segment New. Then, the 2edefrag tool will update the physical data blocks according to the file's Segment New. Thus, as the physical data blocks are updated whenever the logical address blocks are updated, excessive write amplification occurs. Accordingly, the merge LBA module (123) provided in the present disclosure can execute a merge LBA command to rearrange the LBA segments of a file (129) into merged LBA segments. Specifically, rearranging the LBA segments of a file (129) involves rewriting all logical addresses of the LBA segments of the file (129) in a continuous and sequential order into empty or unused logical address blocks (e.g., empty or unused LBA segments) so that they become a continuous logical block address block (e.g., merged LBA segment). Unlike conventional e2defrag tools, the merged LBA segments will not be used to update physical data blocks (e.g., physical data blocks (431) of FIG. 4b). The merged LBA segments are used only to update the volatile L2P address mapping table (4271) of FIG. 4b.By doing this, write amplification is minimized because the physical data block is not updated every time the logical address block is updated.

[0055] After executing the merge LBA command, the host processor (112) may transmit a mapping update command to the controller processor (e.g., 408 in FIG. 4a) within the memory controller (106) to update the volatile L2P address mapping table (4271) according to the merged LBA segment. As illustrated in FIG. 7, the volatile L2P address mapping table (4271) having the original discontinuous and discrete logical addresses (e.g., LBA 9, LBA 11, LBA 13, LBA 18) corresponding to the logical addresses of the LBA segments (e.g., LBA 9, LBA 11, LBA 13, LBA 18) in the file (129) is updated to become a continuous logical address block (e.g., LBA 114, LBA 115, LBA 116, LBA 117). The physical addresses of the updated volatile L2P address mapping table (4271) pointing to the corresponding physical addresses of the physical data block (431) (e.g., PA 333, PA 337, PA 339, PA 440) remain unchanged in the above update process. Therefore, after the defragmentation process, the physical data block (431) is not written and remains the same.

[0056] FIG. 8 illustrates a block diagram illustrating an exemplary defragmentation method under sudden power loss according to some aspects of the present disclosure. As previously mentioned, when a sudden power loss occurs, the volatile L2P address mapping table (4271) may not be updated or may fail to complete the current update, and thus physical data may not be updated and data may be lost. A metadata block (e.g., metadata block (433) of FIG. 4b) of a memory device (e.g., memory device (104)) may have an old and incorrect P2L mapping table (e.g., P2L address mapping table (435) of FIG. 4b) that records the physical addresses of an old L2P address mapping table (e.g., LBA 9, LBA 11, LBA 13, LBA 18). Since the non-volatile merge log (4253) stores the mapping relationship between the P2L address mapping table (435) and the volatile L2P address mapping table (4271) after updating the volatile L2P address mapping table (4271) (e.g., LBA 9 of P2L points to LBA 114 of the new L2P, LBA 11 of P2L points to LBA 115 of the new L2P, LBA 13 of P2L points to LBA 116 of the new L2P, and LBA 18 of P2L points to LBA 117 of the new L2P), the new volatile L2P address mapping table (4271) can be reconstructed by using the non-volatile merge log (4253) and the maintained P2L address mapping table (435) according to the mapping relationship.

[0057] FIG. 9 illustrates a flowchart of an exemplary method for operating a memory controller according to some aspects of the present disclosure. The memory controller may be any suitable memory controller disclosed herein, such as the memory controller (106) of FIG. 4b. The method (900) may be partially or wholly implemented by the memory controller (106) as in FIG. 4a. The operations illustrated in the method (900) may not be comprehensive, and it is understood that other operations may be performed before, after, or in between any of the illustrated operations. Additionally, some of the operations may be performed in a different order or simultaneously than those illustrated in FIG. 9.

[0058] Referring to FIG. 9, the method (900) begins with an operation (902) in which a memory controller (e.g., a memory controller (106) as in FIG. 4a) receives a mapping update command from a host (e.g., a host (108) in FIG. 5). In some implementations, the mapping update command may cause the memory controller (106) to start an update module (421).

[0059] The method (900) proceeds to an operation (904) in which an L2P address mapping table (e.g., the volatile L2P address mapping table (4271) of FIG. 4b) stored in a memory controller (106), as illustrated in FIG. 9, is updated according to a mapping update command. In some implementations, updating the L2P address mapping table involves rewriting the contiguous logical addresses of the merged LBA segments of a file (e.g., the file (129) of FIG. 5-7) to the L2P address mapping table.

[0060] The method (900) proceeds to an operation (906) in which, after updating the L2P address mapping table as exemplified in FIG. 9, a command acknowledging that the L2P address mapping table has been updated is sent to the host. In some implementations, when the update of the L2P address mapping table is completed, the update module is configured to send a command to the host through an interface (e.g., the memory controller interface (429) of FIG. 4b). The host can then update the index node of a file stored in host memory.

[0061] Furthermore, the method (900) may further include an action in which sudden power loss protection is implemented. Specifically, the method (900) may also include the step of recording the mapping relationship between the P2L address mapping table (e.g., P2L mapping table in FIG. 4b) and the L2P address mapping table of a metadata block (e.g., metadata block (433) in FIG. 4b) in a merge log (e.g., non-volatile merge log (4253) in FIG. 4b). After a sudden power loss and when the system restarts, the method (900) may further include the step of scanning the P2L address mapping table of the metadata block and the merge log. And in response to the decision that the merge log is updated, the P2L address mapping table of the metadata block and the L2P address mapping table are reconstructed according to the merge log. And also, in response to the decision that the merge log is not updated, the L2P address mapping table is restored according to the P2L address mapping table of the metadata block. This operation can be implemented by a recovery module (423) as shown in FIG. 4b.

[0062] FIG. 10 illustrates a flowchart of an exemplary method for operating a host according to some aspects of the present disclosure. The host may be any suitable host disclosed herein. The method (1000) may be partially or wholly implemented by the host (108) as in FIG. 5. The operations illustrated in the method (1000) may not be comprehensive, and it is understood that other operations may be performed before, after, or in between any of the illustrated operations. Additionally, some of the operations may be performed in a different order or simultaneously than those illustrated in FIG. 10.

[0063] Referring to FIG. 10, the method (1000) begins with an operation (1002) in which a merge LBA command is executed to rearrange an LBA segment of a file (e.g., a file (129) as in FIG. 5) stored in a host memory (e.g., host memory (110) of FIG. 5) into a merged LBA segment. In some implementations, the merge LBA command may cause a host processor (e.g., host processor (112) of FIG. 5) to initiate a merge LBA module (e.g., merge LBA module (123) of FIG. 5). In some implementations, rearranging an LBA segment of a file into a merged LBA segment involves rewriting an LBA segment of a file having logical addresses in a discontinuous or discrete order into a merged LBA segment having logical addresses in a continuous and sequential order. In some implementations, rearranging the LBA segments of a file into merged LBA segments involves sequentially reading the logical addresses of the LBA segments of the file before writing so that the logical addresses of the merged LBA segments become the merged LBA segments having each and all LBA segments of the file.

[0064] The method (1000) proceeds to an operation (1004) in which a mapping update command is transmitted to a memory controller (e.g., memory controller (106) of FIG. 4a) to cause the controller processor of the memory controller (e.g., controller processor (408) of FIG. 4a) to update the L2P address mapping table (e.g., volatile L2P address mapping table (4271) of FIG. 4b) according to the merged LBA segment, as illustrated in FIG. 10. In some implementations, updating the L2P address mapping table involves rewriting the contiguous logical addresses of the merged LBA segments of the file to the L2P address mapping table.

[0065] The method (1000) proceeds to an operation (1006) in which a command acknowledging that the L2P address mapping table has been updated is received from the controller processor, as illustrated in FIG. 10. In some implementations, after receiving the command, an index node update module (e.g., an index node update module (121)) is started.

[0066] The method (1000) proceeds to an operation (1008) in which the index node of a file is updated after confirming that the L2P address mapping table has been updated, as exemplified in FIG. 10.

[0067] The foregoing description of a particular implementation may be easily modified and / or adapted for various applications. Accordingly, such adaptation and modification are intended to be within the meaning and scope of equivalents of the disclosed implementation, based on the teachings and guidance set forth in this specification.

[0068] The breadth and scope of the present disclosure shall not be limited by any of the exemplary embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A system comprising a host and a storage device, wherein the host is configured to obtain a fragmented first address of a logical block address (LBA) segment of a file and to merge the fragmented first address into a contiguous first address of a merged LBA segment of the file, and the storage device stores a mapping table corresponding to the file, and the storage device is configured to respond to a first command received from the host to update a mapping relationship indicated by the mapping table from an original mapping relationship corresponding to the fragmented first address to a new mapping relationship corresponding to the contiguous first address, and to send a command to the host indicating that the mapping relationship indicated by the mapping table has been updated. Claim 2 A system according to claim 1, wherein the original mapping relationship corresponding to the fragmented first address includes a mapping relationship between the second address of the file and the fragmented first address, and the new mapping relationship corresponding to the continuous first address includes a mapping relationship between the second address of the file and the continuous first address. Claim 3 A system according to paragraph 2, wherein the first address includes a logical address and the second address includes a physical address. Claim 4 In paragraph 3, the storage device further comprises a memory device; and a memory controller coupled to the memory device and the host, a system. Claim 5 In paragraph 4, the system further comprises an interface configured such that the memory controller receives the first command from the host and transmits the instruction to the host. Claim 6 In paragraph 5, the memory device is configured to store a merge log that records a new mapping relationship between the contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file, and the updated rate of the merged log is faster than the mapping table in the memory device, in a system. Claim 7 In claim 6, the memory controller further comprises a controller processor coupled to the interface, and the controller processor is configured to rebuild the mapping table according to the merge log after the system is restarted in response to a sudden power loss. Claim 8 In paragraph 4, the system further comprises a controller memory configured to store a mapping table corresponding to the file, wherein the mapping table includes a logical-to-physical (L2P) address mapping table. Claim 9 A system according to claim 1, wherein the host obtains a consecutive first address of the merged LBA segment of the file before transmitting the first command. Claim 10 A system according to claim 1, wherein in response to a second command, the host merges the fragmented first address into a contiguous first address of the merged LBA segment of the file. Claim 11 A system according to claim 1, wherein the host is also configured to update the index node of the file by pointing to a new LBA segment having a contiguous first address of the merged LBA segment of the file after receiving the instruction. Claim 12 In claim 1, the storage device comprises a general-purpose flash storage (UFS) device, in a system. Claim 13 A storage device comprising: a memory device including a physical data block; and a memory controller, wherein the memory controller comprises: a controller memory for storing a mapping table corresponding to a file; and a controller processor coupled to the controller memory, wherein the controller processor receives a contiguous first address of a merged LBA segment of the file obtained by merging a fragmented first address of a logical block address (LBA) segment of the file in response to a command; updates a mapping relationship indicated by the mapping table from an original mapping relationship corresponding to the fragmented first address to a new mapping relationship corresponding to the contiguous first address; and is configured to transmit a command indicating that the mapping relationship indicated by the mapping table has been updated. Claim 14 A storage device according to claim 13, wherein the original mapping relationship corresponding to the fragmented first address includes a mapping relationship between the second address of the file and the fragmented first address, and the new mapping relationship corresponding to the continuous first address includes a mapping relationship between the second address of the file and the continuous first address. Claim 15 A storage device according to claim 14, wherein the first address includes a logical address and the second address includes a physical address. Claim 16 In paragraph 15, the physical data block is configured to store a merge log that records a new mapping relationship between the contiguous logical address of the merged LBA segment of the file and the physical address of the file, and the update rate of the merge log is faster than the mapping table in the memory device, the storage device. Claim 17 In paragraph 16, the storage device is also configured such that, in response to a sudden power loss, the controller processor rebuilds the mapping table according to the merge log after the storage device is restarted. Claim 18 A method for operating a host, comprising: a step of obtaining a fragmented logical address of a logical block address (LBA) segment of a file by the host; a step of merging the fragmented logical address into a continuous logical address of a merged LBA segment of the file by the host in response to a first command; and a step of transmitting a second command instructing the host to update a mapping relationship indicated by a mapping table from an original mapping relationship corresponding to the fragmented logical address to a new mapping relationship corresponding to the continuous logical address. Claim 19 A method for operating a host according to claim 18, wherein the original mapping relationship corresponding to the fragmented logical address includes a mapping relationship between the physical address of the file and the fragmented logical address, and the new mapping relationship corresponding to the contiguous logical address includes a mapping relationship between the physical address of the file and the contiguous logical address. Claim 20 A method for operating a system comprising a host and a storage device coupled to the host, comprising: a step of obtaining a fragmented logical address of a logical block address (LBA) segment of a file by the host; a step of merging the fragmented logical address into a continuous logical address of a merged LBA segment of the file by the host; a step of transmitting a command to the storage device by the host; a step of updating a mapping relationship indicated by a mapping table by the storage device in response to the command from an original mapping relationship corresponding to the fragmented logical address to a new mapping relationship corresponding to the continuous logical address by the storage device; and a step of transmitting a command to the host by the storage device indicating that the mapping relationship indicated by the mapping table has been updated.

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