Light emitting display apparatus and multi screen display apparatus using the same

Abstract

A light-emitting display device according to some embodiments of the present specification comprises a substrate having a display portion, a circuit layer disposed on the display portion, a flattening layer disposed on the circuit layer, a dam disposed on the circuit layer along an edge portion of the substrate, a device separation portion including a device separation line disposed on the circuit layer and surrounding the dam, and a light-emitting element layer having a self-luminous element disposed on the flattening layer, the dam, and the device separation portion, wherein the device separation line has a protruding tip protruding from the circuit layer toward the dam, and the self-luminous element can be separated from the device separation portion by the protruding tip of the device separation line.

Description

Technology Field

[0001] This specification relates to a light-emitting display device and a multi-screen light-emitting display device using the same. Background Technology

[0002] Emissive displays are self-emissive types that, unlike liquid crystal displays, do not require a separate light source, allowing them to be manufactured in lightweight and thin forms. Furthermore, emissive displays are gaining attention as next-generation devices because they offer advantages in terms of power consumption due to low-voltage driving, as well as superior color reproduction, response speed, viewing angle, and contrast ratio.

[0003] A light-emitting display device displays an image through the light emission of a light-emitting element layer comprising a light-emitting element interposed between two electrodes. At this time, light generated by the light emission of the light-emitting element is emitted to the outside through the electrodes and the substrate.

[0004] The light-emitting display device includes a display panel implemented to display an image. The display panel may include a display area having a plurality of pixels for displaying an image, and a bezel area surrounding the display area.

[0005] Conventional light-emitting display devices require a bezel (or structure) to cover the bezel area placed at the border (or edge portion) of the display panel, and the bezel width may increase due to the width of the bezel. Furthermore, if the bezel width of the light-emitting display device is reduced to an extreme degree, the reliability of the display panel may be compromised due to the degradation of the light-emitting element caused by moisture penetration.

[0006] Recently, multi-screen light-emitting display devices that realize a large screen by arranging light-emitting display devices in a grid shape are being commercialized.

[0007] However, in conventional multi-screen light-emitting display devices, a boundary area called a seam exists between adjacent light-emitting displays due to the bezel area of ​​each of the multiple light-emitting displays or the bezels. When displaying a single image across the entire screen of the multi-screen light-emitting display device, this boundary area reduces immersion by causing a sense of discontinuity in the image. The problem to be solved

[0008] The present specification has the technical objective of providing a light-emitting display device having a zero bezel width while preventing a decrease in the reliability of the light-emitting display panel due to moisture permeability, and a multi-screen light-emitting display device including the same.

[0009] The problems to be solved according to the examples of this specification are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art to which the technical concept of this specification belongs from the description below. means of solving the problem

[0010] A light-emitting display device according to some embodiments of the present specification comprises a substrate having a display portion, a circuit layer disposed on the display portion, a flattening layer disposed on the circuit layer, a dam disposed on the circuit layer along an edge portion of the substrate, a device separation portion including a device separation line disposed on the circuit layer and surrounding the dam, and a light-emitting element layer having a self-luminous element disposed on the flattening layer, the dam, and the device separation portion, wherein the device separation line has a protruding tip protruding from the circuit layer toward the dam, and the self-luminous element can be separated from the device separation portion by the protruding tip of the device separation line.

[0011] A multi-screen display device according to some embodiments of the present specification comprises a plurality of display modules arranged along at least one of a first direction and a second direction crossing the first direction, each of the plurality of display modules comprising a light-emitting display device, the light-emitting display device comprising a substrate having a display portion, a circuit layer disposed on the display portion, a flattening layer disposed on the circuit layer, a dam disposed on the circuit layer along an edge portion of the substrate, a device separation portion comprising a device separation line disposed on the circuit layer and surrounding the dam, and a light-emitting element layer having a self-luminous element disposed on the flattening layer, the dam, and the device separation portion, wherein the device separation line has a protruding tip protruding from the circuit layer toward the dam, and the self-luminous element can be separated from the device separation portion by the protruding tip of the device separation line.

[0012] Specific details according to various examples of this specification, other than the means for solving the problem mentioned above, are included in the description and drawings below. Effects of the invention

[0013] One embodiment of the present specification can provide a light-emitting display device having a thin bezel width while preventing a decrease in reliability due to moisture permeability, and a multi-screen light-emitting display device including the same.

[0014] One embodiment of the present specification may provide a light-emitting display device having an air-bezel or no bezel, and a multi-screen light-emitting display device including the same, while preventing a decrease in reliability due to moisture penetration.

[0015] One embodiment of the present specification may provide a multi-screen light-emitting display device capable of displaying images without interruption.

[0016] Since the problem to be solved, the means for solving the problem, and the effects mentioned above do not specify the essential features of the claim scope, the scope of rights of the claim is not limited by the matters described in the content of the invention. Brief explanation of the drawing

[0017] FIG. 1 is a plan view showing a light-emitting display device according to one embodiment of the present specification. FIG. 2a is a drawing showing a single pixel according to an embodiment illustrated in FIG. 1. FIG. 2b is a drawing showing a single pixel according to another embodiment illustrated in FIG. 1. FIG. 2c is a drawing showing a single pixel according to another embodiment shown in FIG. 1. Figure 3 is an enlarged view of part 'A' shown in Figure 1. Figure 4 is an equivalent circuit diagram for a single pixel shown in Figures 1 and 3. Figure 5 is a diagram showing the gate driving circuit illustrated in Figures 1 and 3. FIG. 6 is a rear perspective view showing a light-emitting display device according to one embodiment of the present specification. FIG. 7 is a rear perspective view showing a light-emitting display device according to another embodiment of the present specification. Figure 8 is a cross-sectional view of line I-I' shown in Figure 7. Figure 9 is a cross-sectional view of line II-II' shown in Figure 7. FIG. 10 is a cross-sectional view of line III-III' shown in FIG. 7. Figure 11 is an enlarged view of part 'B' shown in Figure 8. Figure 12 is an enlarged view of part 'C' shown in Figure 8. Figure 13 is an enlarged view of part 'D' shown in Figure 10. Fig. 14 is an enlarged view of part 'E' shown in Fig. 11. Figure 15 is another cross-sectional view of line I-I' shown in Figure 7. Fig. 16 is an enlarged view of the 'F' portion shown in Fig. 15. FIG. 17 is a drawing showing a multi-screen display device according to one embodiment of the present specification. FIG. 18 is a cross-sectional view of line IV-IV' shown in FIG. 17. Specific details for implementing the invention

[0018] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0019] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0020] In interpreting the components, even if there is no separate explicit description of the error range, it is interpreted as including the error range.

[0021] In the case of a description of a positional relationship, for example, when the positional relationship between two parts is described using terms such as "on," "on the upper," "on the lower," or "next to," for example, unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0022] In the case of an explanation of temporal relationships, when the temporal order is explained using "after," "followed," "next," "before," etc., cases that are not continuous may also be included unless "immediately" or "directly" is used.

[0023] The terms first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0024] In describing the components of this specification, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by the terms. Where it is stated that a component is "connected," "coupled," or "joined" to another component, it should be understood that the component may be directly connected or joined to the other component, but that other components may be "interposed" between each component that may be indirectly connected or joined unless specifically stated otherwise.

[0025] "At least one" should be understood to include all combinations of one or more associated components. For example, the meaning of "at least one of the first, second, and third components" may be said to include not only the first, second, or third components, but also all combinations of two or more of the first, second, and third components.

[0026] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0027] The embodiments of this specification are described below through the attached drawings and examples. For the convenience of explanation, the scale of the components shown in the drawings may differ from the actual scale and is therefore not limited to the scale shown in the drawings.

[0028] FIG. 1 is a plan view showing a light-emitting display device according to one embodiment of the present specification.

[0029] Referring to FIG. 1, a light-emitting display device (or display panel) (10) according to one embodiment of the present specification may include a substrate (100) having a display portion (AA), a plurality of pixels (P), a dam (104), and an element separation portion (102) on the display portion (AA) of the substrate (100).

[0030] The substrate (100) may be represented as a first substrate, a base substrate, or a pixel array substrate. For example, the substrate (100) may be a glass substrate, a thin glass substrate that can be bent or curved, or a plastic substrate.

[0031] The display portion (AA) is an area where an image is displayed, and may be expressed as an active portion, an active area, or a display area. The size of the display portion (AA) may be the same as the size of the substrate (or light-emitting display device) (10). For example, the size of the display portion (AA) may be the same as the entire size of the first surface of the substrate (100). Accordingly, the display portion (AA) is implemented (or placed) over the entire front surface of the substrate (100), so that the substrate (100) does not include an opaque non-display area provided along the edge portion of the first surface to surround the entire display portion (AA). Therefore, the entire front surface of the light-emitting display device can implement the display portion (AA).

[0032] The end (or outermost edge) of the display portion (AA) may overlap with the outer surface (OS) of the substrate (100) or be aligned with the outer surface (OS) of the substrate (100). For example, with respect to the thickness direction (Z) of the light-emitting display device, the side of the display portion (AA) may be aligned with a vertical extension line extending vertically from the outer surface (OS) of the substrate (100). The side of the display portion (AA) may be surrounded only by air without being surrounded by a separate structure. That is, all sides of the display portion (AA) may be structured to be in direct contact with air without being surrounded by a separate structure. Accordingly, by having the outer surface (OS) of the substrate (100) corresponding to the end of the display portion (AA) surrounded only by air, the light-emitting display device according to the present specification may have an air-bezel structure or a bezel-less (or zeroed-bezel) structure in which the end (or side) of the display portion (AA) is surrounded by air rather than an opaque non-display area.

[0033] A plurality of pixels (P) may be arranged (or positioned) on a display portion (AA) of a substrate (100) to have a first spacing (D1) along each of a first direction (X) and a second direction (Y). The first direction (X) may be a horizontal direction or a horizontal direction, or a first length direction (e.g., horizontal length direction) of the substrate (100) or the light-emitting display device. The second direction (Y) may be a vertical direction or a vertical direction, or a second length direction (e.g., vertical length direction) of the substrate (100) or the light-emitting display device.

[0034] Each of the plurality of pixels (P) may be implemented on a plurality of pixel regions defined on a display portion (AA) of the substrate (100). Each of the plurality of pixel regions may have a first length (L1) parallel to a first direction (X) and a second length (L2) parallel to a second direction (Y). The first length (L1) may be the same as the second length (L2) or the same as a first interval (D1). The first length (L1) and the second length (L2) may be the same as the first interval (D1). Accordingly, the plurality of pixels (or pixel regions) (P) may all have the same size.

[0035] Two adjacent pixels (P) along each of the first direction (X) and the second direction (Y) may have the same first interval (D1) within the error range of the manufacturing process. The first interval (D1) may be the pitch (or pixel pitch) between two adjacent pixels (P). For example, the first interval (or pixel pitch) (D1) may be the shortest distance (or shortest length) between the centers of each of two adjacent pixels (P).

[0036] Each of the plurality of pixels (P) according to one embodiment may include a circuit layer comprising a pixel circuit implemented in a pixel area on a substrate (100), and a light-emitting element layer disposed on the circuit layer and connected to the pixel circuit. The pixel circuit outputs a data current corresponding to the data signal in response to a data signal and a scan signal supplied from pixel driving lines disposed in the pixel area. The light-emitting element layer may include a self-luminous element that emits light by the data current supplied from the pixel circuit. These pixel driving lines, pixel circuit, and light-emitting element layer will be described later.

[0037] Multiple pixels (P) can be divided into outermost pixels (Po) and inner pixels (Pi).

[0038] The outermost pixels (Po) may be the pixels among the plurality of pixels (P) that are closest to the outer surface (OS) of the substrate (100).

[0039] The second gap (D2) between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100) may be half or less than half of the first gap (D1). For example, the second gap (D2) may be the shortest distance (or shortest length) between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100).

[0040] When the second gap (D2) exceeds half of the first gap (D1), the substrate (100) must have a size larger than the display portion (AA) by the difference between half of the first gap (D1) and the second gap (D2), and thus the area between the end of the outermost pixel (Po) and the outer surface (OS) of the substrate (100) can be configured as a non-display area surrounding the entire display portion (AA). For example, when the second gap (D2) exceeds half of the first gap (D1), the substrate (100) inevitably includes a bezel area corresponding to the non-display area surrounding the entire display portion (AA). In contrast, when the second interval (D2) is half or less than half of the first interval (D1), the end of the outermost pixel (Po) may be aligned with the outer surface (OS) of the substrate (100) or the end (AAa) of the display portion (AA) may be aligned with the outer surface (OS) of the substrate (100), and as a result, the display portion (AA) may be implemented (or placed) over the entire front surface of the substrate (100).

[0041] The inner pixels (Pi) may be the remaining pixels among the plurality of pixels (P) excluding the outermost pixels (Po), or pixels among the plurality of pixels (P) that are surrounded by the outermost pixels (Po). These inner pixels (Pi) may be implemented with a different configuration or structure from the outermost pixels (Po).

[0042] The dam (104) may be implemented on the edge portion of the substrate (100) or on the edge portion of the outermost pixels (Po) placed on the display portion (AA). For example, the dam (104) may be positioned to have a closed-loop line shape (or closed-loop shape) between the center of each of the outermost pixels (Po) and the outer surface (OS) of the substrate (100). By doing so, the outermost pixel (Po) may be implemented with a different configuration or structure from the inner pixel (Pi) that does not include the dam (104) by including the dam (104).

[0043] A dam (104) according to one embodiment may serve to block the spreading or overflow of an organic encapsulation layer among the encapsulation layers disposed on the light-emitting element layer at the edge portion of the outermost pixels (Po). Additionally, the dam (104) may block the lateral moisture penetration path by separating (or disconnecting) at least some layers of the light-emitting element layer at the edge portion of the outermost pixels (Po), thereby preventing or minimizing the degradation of the reliability of the light-emitting element layer due to lateral moisture penetration. Such a dam (104) may include the function of physically separating at least some layers of the light-emitting element layer at the edge portion of the substrate (100) or the outermost pixels (Po), the function of blocking the spreading or overflow of the organic encapsulation layer, and the function of preventing moisture penetration from the lateral direction of the substrate (100).

[0044] The device separation portion (102) may be positioned at the edge portion of the substrate (100) or the outermost pixels (Po) to form a closed-loop line shape surrounding the dam (104). For example, the device separation portion (102) may be positioned in a closed-loop line shape between the outer surface (OS) of the substrate (100) and the dam (104). By doing so, the outermost pixel (Po) may be implemented with a different configuration or structure from the inner pixel (Pi) that does not include the dam (104) and the device separation portion (102) by including the dam (104) and the device separation portion (102).

[0045] A device separation unit (102) according to one embodiment may be implemented to include a protruding tip structure protruding from the circuit layer toward the dam (104). This device separation unit (102) primarily blocks the lateral moisture penetration path by separating (or severing) at least some layer of the light-emitting device layer in the outer region of the dam (104), thereby preventing or minimizing the degradation of the reliability of the light-emitting device layer due to lateral moisture penetration. For example, at least some layer of the light-emitting device layer disposed on the device separation unit (102) may be further separated by the protruding tip structure of the device separation unit (102).

[0046] A light-emitting display device (or display panel) (10) according to one embodiment of the present specification may further include a groove line (105).

[0047] The groove line (105) may be positioned to be surrounded by the dam (104). For example, the groove line (105) may be positioned in a groove area (or ditch area) defined in the inner area of ​​the dam (104).

[0048] According to one embodiment, the groove line (105) may be arranged to have a closed-loop line shape between the side of the flattening layer (103) and the dam (104). For example, the groove line (105) may be formed or implemented by removing all structures and / or stepped portions that were placed in the groove area of ​​the inner region of the dam (104). For example, the groove line (105) may be implemented so that the circuit layer placed between the side of the flattening layer (103) and the dam (104) is exposed. Additionally, the groove line (105) may be implemented to separate at least some layers of the light-emitting element layer placed in the inner region of the dam (104).

[0049] A light-emitting display device (or display panel) (10) according to one embodiment of the present specification may further include a pad portion (110).

[0050] The pad portion (110) may be a first pad portion or a front pad portion. The pad portion (110) may include a plurality of pads for receiving data signals, gate control signals, pixel driving power, reference voltage, and pixel common voltage, etc. from a driving circuit portion.

[0051] The pad portion (110) may be included in the outermost pixels (Po) positioned in the first edge portion of the first surface of the substrate (100) parallel to the first direction (X). That is, the outermost pixels (Po) positioned in the first edge portion of the substrate (100) may include at least one of a plurality of pads. Accordingly, the plurality of pads are positioned or included within the display portion (AA), so that a non-display area (or bezel area) according to the pad portion (110) is not formed or does not exist on the substrate (100). Therefore, the outermost pixel (Po) may be implemented with a different configuration or structure from the internal pixel (Pi) that does not include the pad portion (110) by including the pad portion (110).

[0052] For example, when the pad portion (110) is not formed inside the outermost pixels (Po) but is positioned between the outermost pixels (Po) and the outer surface (OS) of the substrate (100), the substrate (100) has a non-display area corresponding to the area where the pad portion (110) is formed, and due to this non-display area, the second gap (D2) between the outermost pixels (Po) and the outer surface (OS) of the substrate (100) exceeds half of the first gap (D1), and the entire substrate (100) cannot be implemented as a display portion (AA), and a separate bezel is required to cover the non-display area. In contrast, the pad portion (110) according to the present specification is positioned between the outer surface (OS) of the substrate (100) and the outermost pixels (Po) and is included within the outermost pixels (Po), so that a non-display area (or bezel area) according to the pad portion (110) is not formed or does not exist between the outer surface (OS) of the substrate (100) and the outermost pixels (Po).

[0053] A light-emitting display device (or display panel) (10) according to one embodiment of the present specification may further include a gate driving circuit (150).

[0054] A gate driving circuit (150) is positioned within a display unit (AA) to supply a scan signal (or gate signal) to pixels (P) placed on a substrate (100). The gate driving circuit (150) can simultaneously supply a scan signal to pixels (P) placed in a horizontal line parallel to the first direction (X). For example, the gate driving circuit (150) can supply at least one scan signal to pixels (P) placed in a single horizontal line.

[0055] A gate driving circuit (150) according to one embodiment may be implemented as a shift register including a plurality of stage circuit sections. That is, the light-emitting display device according to the present example may include a shift register that is placed on a display section (AA) on a substrate (100) and supplies a scan signal to pixels (P).

[0056] Each of the plurality of stage circuits may include a plurality of branch circuits spaced apart along each horizontal line of the substrate (100) along the first direction (X). Each of the plurality of branch circuits includes at least one thin-film transistor (or branch thin-film transistor) and may be arranged one by one between at least one pixel (P) (or pixel area) within a horizontal line along the first direction (X). Each of these plurality of stage circuits may generate a scan signal by driving the plurality of branch circuits according to a gate control signal supplied through gate control lines scattered between the plurality of pixels (P) within the display unit (AA), and supply the scan signal to the pixels (P) arranged on the corresponding horizontal line.

[0057] FIG. 2a is a drawing showing one pixel according to one embodiment shown in FIG. 1, FIG. 2b is a drawing showing one pixel according to another embodiment shown in FIG. 1, and FIG. 2c is a drawing showing one pixel according to yet another embodiment shown in FIG. 1.

[0058] Referring to FIG. 1 and FIG. 2a, a pixel (or unit pixel) (P) according to one embodiment of the present specification may include first to fourth subpixels (SP1, SP2, SP3, SP4) arranged in a pixel area (PA).

[0059] The first subpixel (SP1) may be placed in the first subpixel area of ​​the pixel area (PA), the second subpixel (SP2) may be placed in the second subpixel area of ​​the pixel area (PA), the third subpixel (SP3) may be placed in the third subpixel area of ​​the pixel area (PA), and the fourth subpixel (SP4) may be placed in the fourth subpixel area of ​​the pixel area (PA).

[0060] Each of the first to fourth subpixels (SP1, SP2, SP3, SP4) according to one embodiment may be arranged in a 2x2 shape or a quad structure. Each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may include a light-emitting region (EA1, EA2, EA3, EA4) and a circuit region (CA1, CA2, CA3, CA4). For example, the light-emitting region (EA1, EA2, EA3, EA4) may be described as an aperture region, an aperture, or a light-emitting part.

[0061] Each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have a uniform quad structure having a square shape with equal size. According to one embodiment, the light-emitting regions (EA1, EA2, EA3, EA4) having the uniform quad structure may have a size smaller than a quarter size of the pixel (P) and may be positioned so as to be offset toward the center (CP) of the pixel (P) or concentrated at the center (CP) of the pixel (P) within the subpixel area. According to another embodiment, the light-emitting regions (EA1, EA2, EA3, EA4) having the uniform quad structure may have a size smaller than a quarter size of the pixel (P) and may be positioned at the center of the corresponding subpixel area.

[0062] Referring to FIG. 1 and FIG. 2b, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) according to another embodiment may be arranged in a non-uniform quad structure having different sizes. For example, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) light-emitting regions (EA1, EA2, EA3, EA4) may be arranged in a non-uniform quad structure having different sizes.

[0063] The size of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) having a non-uniform quad structure can be set according to resolution, luminous efficiency, or image quality, etc. According to one embodiment, when the light-emitting regions (EA1, EA2, EA3, EA4) have a non-uniform quad structure, among the light-emitting regions (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4), the light-emitting region (EA4) of the fourth subpixel (SP4) may have the smallest size, and the light-emitting region (EA3) of the third subpixel (SP3) may have the largest size. For example, the light-emitting regions (EA1, EA2, EA3, EA4) having a non-uniform quad structure may be arranged concentrated around the center (CP) of the pixel (P).

[0064] Referring to FIG. 1 and FIG. 2c, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) according to another embodiment may have a 1x4 shape or an even stripe structure. For example, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have a light-emitting region (EA1, EA2, EA3, EA4) in a 1x4 shape or an even stripe structure.

[0065] Each of the first to fourth subpixels (SP1, SP2, SP3, SP4) having a uniform stripe structure, the light-emitting region (EA1, EA2, EA3, EA4) may have a rectangular shape having a short side parallel to the first direction (X) and a long side parallel to the second direction (Y).

[0066] A light-emitting region (EA1, EA2, EA3, EA4) having a uniform stripe structure according to one embodiment may have a size smaller than the quarter size of a pixel (P) and may be positioned so as to be offset toward the center (CP) of the pixel (P) within the subpixel region or concentrated toward the center (CP) of the pixel (P).

[0067] A light-emitting region (EA1, EA2, EA3, EA4) having a uniform stripe structure according to another embodiment may be positioned at the center of the corresponding subpixel region while having a size smaller than the quarter size of the pixel (P).

[0068] A light-emitting region (EA1, EA2, EA3, EA4) having a uniform stripe structure according to another embodiment may be placed over the entire corresponding subpixel region while having a size equal to the quarter size of the pixel (P).

[0069] Alternatively, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have a non-uniform stripe structure having different sizes. According to one embodiment, when the light-emitting areas (EA1, EA2, EA3, EA4) have a non-uniform stripe structure, among the light-emitting areas (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4), the light-emitting area (EA4) of the fourth subpixel (SP4) may have the smallest size and the light-emitting area (EA3) of the third subpixel (SP3) may have the largest size, but is not limited thereto.

[0070] Referring to FIGS. 2a through 2c, the circuit regions (CA1, CA2, CA3, CA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be arranged around the corresponding light-emitting regions (EA1, EA2, EA3, EA4). The circuit regions (CA1, CA2, CA3, CA4) may include circuits and pixel driving lines for emitting light from the corresponding subpixels. For example, the circuit regions (CA1, CA2, CA3, CA4) may be described as non-light-emitting regions, non-aperture regions, non-light-emitting parts, non-aperture parts, or peripheral parts.

[0071] Additionally, in order to increase the aperture ratio of the subpixels (SP1, SP2, SP3, SP4) corresponding to the size of the light-emitting regions (EA1, EA2, EA3, EA4) or to reduce the pixel pitch (D1) according to the resolution of the pixel (P), the light-emitting regions (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be extended onto the circuit region (CA1, CA2, CA3, CA4) so ​​as to overlap with part or all of the circuit region (CA1, CA2, CA3, CA4). For example, since the light-emitting regions (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) have an upper light-emitting structure, they may be arranged to overlap with the corresponding circuit region (CA1, CA2, CA3, CA4). In this case, the light-emitting region (EA1, EA2, EA3, EA4) may have a size equal to or larger than the circuit region (CA1, CA2, CA3, CA4).

[0072] In FIGS. 2a to 2c, the first subpixel (SP1) may be implemented to emit light of a first color, the second subpixel (SP2) to emit light of a second color, the third subpixel (SP3) to emit light of a third color, and the fourth subpixel (SP4) to emit light of a fourth color, respectively. Each of the first to fourth colors may be different. In one embodiment, the first color may be red, the second color may be blue, the third color may be white, and the fourth color may be green. In another embodiment, some of the first to fourth colors may be the same. For example, the first color may be red, the second color may be first green, the third color may be second green, and the fourth color may be blue.

[0073] Optionally, among the first to fourth subpixels (SP1, SP2, SP3, SP4) having an even stripe structure or an uneven stripe structure, a white subpixel emitting white light may be omitted.

[0074] Figure 3 is an enlarged view of part 'A' shown in Figure 1, and Figure 4 is an equivalent circuit diagram for a single pixel shown in Figures 1 and 3.

[0075] Referring to FIGS. 1, 3, and 4, a substrate (100) according to one embodiment of the present specification may include pixel driving lines (DL, GL, PL, CVL, RL, GCL), a plurality of pixels (P), a common electrode (CE), a plurality of common electrode connection portions (CECP), a dam (104), an element separation portion (102), a groove line (105), and a pad portion (110).

[0076] Pixel driving lines (DL, GL, PL, CVL, RL, GCL) may include a plurality of data lines (DL), a plurality of gate lines (GL), a plurality of pixel driving power lines (PL), a plurality of pixel common voltage lines (CVL), a plurality of reference voltage lines (RL), and gate control lines (GCL).

[0077] Each of the plurality of data lines (DL) may be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) at a predetermined interval along the first direction (X). For example, among the plurality of data lines (DL), the odd-numbered data line (DLo) may be arranged at the first edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the second direction (Y), and the even-numbered data line (DLe) may be arranged at the second edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the second direction (Y), but is not limited thereto.

[0078] Each of the plurality of gate lines (GL) may be extended along the first direction (X) and arranged on the display portion (AA) of the substrate (100) with a predetermined spacing along the second direction (Y). For example, among the plurality of gate lines (GL), the odd-numbered gate line (GLo) may be arranged on the third edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the first direction (X), and the even-numbered gate line (GLe) may be arranged on the fourth edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the first direction (X), but is not limited thereto.

[0079] Each of the plurality of pixel driving power lines (PL) may be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) at a predetermined interval along the first direction (X). For example, among the plurality of pixel driving power lines (PL), the odd-numbered pixel driving power line (PL) may be arranged at the first edge portion of the odd-numbered pixel area (PA) with respect to the first direction (X), and the even-numbered pixel driving power line (PL) may be arranged at the second edge portion of the even-numbered pixel area (PA) with respect to the first direction (X), but is not limited thereto.

[0080] Among a plurality of pixel driving power lines (PL), two adjacent pixel driving power lines (PL) can be connected to each other through a plurality of power sharing lines (PSL) arranged in each pixel area (PA) along the second direction (Y). For example, the plurality of pixel driving power lines (PL) may have a ladder structure or a mesh structure by being electrically connected to each other by the plurality of power sharing lines (PSL). By having the plurality of pixel driving power lines (PL) have a ladder structure or a mesh structure, the voltage drop (IR drop) of the pixel driving power due to the line resistance of the pixel driving power lines (PL) can be prevented or minimized, and as a result, the light-emitting display device according to the present example can prevent or minimize image quality defects caused by deviations in the pixel driving power supplied to each pixel (P) arranged in the display unit (AA).

[0081] Each of the multiple power sharing lines (PSL) may be branched from an adjacent pixel driving power line (PL) so as to be parallel to the first direction (X) and placed in the middle area of ​​each pixel region (PA), but is not limited thereto.

[0082] Each of the plurality of pixel common voltage lines (CVL) may be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) with a predetermined spacing along the first direction (X). For example, each of the plurality of pixel common voltage lines (CVL) may be arranged at the first edge portion of an even-numbered pixel area (PA) with respect to the first direction (X), but is not limited thereto.

[0083] Each of the plurality of reference voltage lines (RL) may be arranged on the display portion (AA) of the substrate (100) such that it is extended along the second direction (Y) and has a predetermined spacing along the first direction (X). Each of the plurality of reference voltage lines (RL) may be arranged in the center area of ​​each pixel area (PA) arranged along the second direction (Y), but is not limited thereto.

[0084] Each of the plurality of reference voltage lines (RL) may be shared with two adjacent subpixels ((SP1, SP2)(SP3, SP4)) along a first direction (X) in each pixel area (PA). To this end, each of the plurality of reference voltage lines (RL) may include a reference branch line (RDL). The reference branch line (RDL) may branch (or protrude) toward two adjacent subpixels ((SP1, SP2)(SP3, SP4)) along a first direction (X) in each pixel area (PA) and may be electrically connected to the two adjacent subpixels ((SP1, SP2)(SP3, SP4)).

[0085] Each of the plurality of gate control lines (GCL) may be arranged on the display portion (AA) of the substrate (100) such that it extends along the second direction (Y) and has a predetermined spacing along the first direction (X). For example, each of the plurality of gate control lines (GCL) may be arranged at the boundary between a plurality of pixel regions (PA) or between two adjacent pixel regions (PA) with respect to the first direction (X).

[0086] Each of the plurality of pixels (P) may include at least three subpixels. For example, each of the plurality of pixels (P) may include first to fourth subpixels (SP1 to SP4).

[0087] Each of the first to fourth subpixels (SP1 to SP4) may include a pixel circuit (PC) and a light-emitting element layer.

[0088] A pixel circuit (PC) according to one embodiment may be placed in the circuit area of ​​a pixel area (PA) and connected to adjacent gate lines (GLo, GLe), data lines (DLo, DLe), and pixel driving power lines (PL). For example, a pixel circuit (PC) placed in a first subpixel (SP1) may be connected to an odd-numbered data line (DLo) and an odd-numbered gate line (GLo), a pixel circuit (PC) placed in a second subpixel (SP2) may be connected to an even-numbered data line (DLe) and an odd-numbered gate line (GLo), a pixel circuit (PC) placed in a third subpixel (SP3) may be connected to an odd-numbered data line (DLo) and an even-numbered gate line (GLe), and a pixel circuit (PC) placed in a fourth subpixel (SP4) may be connected to an even-numbered data line (DLe) and an even-numbered gate line (GLe).

[0089] Each pixel circuit (PC) of the first to fourth subpixels (SP1 to SP4) can sample a data signal supplied from a corresponding data line (DLo, DLe) in response to a scan signal supplied from a corresponding gate line (GLo, GLe) and control the current flowing from the pixel driving power line (PL) to the light-emitting element layer based on the sampled data signal.

[0090] A pixel circuit (PC) according to one embodiment may include, but is not limited to, a first switching thin film transistor (Tsw1), a second switching thin film transistor (Tsw2), a driving thin film transistor (Tdr), and a storage capacitor (Cst). In the following description, the thin film transistor will be referred to as "TFT".

[0091] The first switching TFT (Tsw1) may include a gate electrode connected to a gate line (GLo, GLe), a first source / drain electrode connected to a data line (DL), and a second source / drain electrode connected to a gate node (n1) of a driving TFT (Tdr). This first switching TFT (Tsw1) can supply a data voltage supplied from the data line (DL) to the gate node (n1) of the driving TFT (Tdr) according to a scan signal supplied to the corresponding gate line (GLo, GLe).

[0092] The second switching TFT (Tsw2) may include a gate node connected to gate lines (GLo, GLe), a first source / drain electrode connected to a source node (n2) of a driving TFT (Tdr), and a second source / drain electrode connected to a reference voltage line (RL). This second switching TFT (Tsw2) can supply a reference voltage supplied to the reference voltage line (RL) to the source node (n2) of the driving TFT (Tdr) according to a scan signal supplied to the corresponding gate lines (GLo, GLe).

[0093] A storage capacitor (Cst) may be formed between a gate node (n1) and a source node (n2) of a driving TFT (Tdr). A storage capacitor (Cst) according to one embodiment may include a first capacitor electrode connected to the gate node (n1) of the driving TFT (Tdr), a second capacitor electrode connected to the source node (n2) of the driving TFT (Tdr), and a dielectric layer formed in the overlapping region of the first capacitor electrode and the second capacitor electrode. After charging the differential voltage between the gate node (n1) and the source node (n2) of the driving TFT (Tdr), the storage capacitor (Cst) switches the driving TFT (Tdr) according to the charged voltage.

[0094] The driving thin-film transistor (Tdr) may include a gate electrode (or gate node (n1)) commonly connected to the second source / drain electrode of the first switching TFT (Tsw1) and the first capacitor electrode of the storage capacitor (Cst), a first source / drain electrode (or source node (n2)) commonly connected to the first source / drain electrode of the second switching TFT (Tsw2), the second capacitor electrode of the storage capacitor (Cst), and the pixel electrode (PE) of the light-emitting element layer, and a second source / drain electrode (or drain node) connected to the pixel driving power line (PL). This driving TFT (Tdr) can control the amount of current flowing from the pixel driving power line (PL) to the light-emitting element layer by being turned on by the voltage of the storage capacitor (Cst).

[0095] The light-emitting element layer may be disposed in the light-emitting region (EA) of the pixel region (PA) and electrically connected to the pixel circuit (PC). According to one embodiment, the light-emitting element layer may include a pixel electrode (PE) electrically connected to the pixel circuit (PC), a common electrode (CE) electrically connected to a pixel common voltage line (CVL), and a self-emissive element (ED) interposed between the pixel electrode (PE) and the common electrode (CE).

[0096] Each of the plurality of common electrode connection portions (CECP) electrically connects the common electrode (CE) to each of the plurality of pixel common voltage lines (CVL) between the plurality of pixels (P) that overlap with each of the plurality of pixel common voltage lines (CVL). Each of the plurality of common electrode connection portions (CECP) according to one embodiment is electrically connected to each of the plurality of pixel common voltage lines (CVL) at the boundary between the plurality of pixels (P) or between the plurality of pixels with respect to the second direction (Y), and can electrically connect the common electrode (CE) to each of the plurality of pixel common voltage lines (CVL) by being electrically connected to a part of the common electrode (CE).

[0097] Each of the plurality of common electrode connection portions (CECP) is arranged between each of the plurality of pixels (P) and electrically connects each of the plurality of pixel common voltage lines (CVL) to the common electrode (CE), thereby preventing or minimizing the voltage drop (IR drop) of the pixel common voltage due to the sheet resistance of the common electrode (CE). As a result, the light-emitting display device according to the present example can prevent or minimize image quality defects caused by deviations in the pixel common voltage supplied to each pixel (P) arranged in the display portion (AA).

[0098] According to one embodiment, each of a plurality of common electrode connection portions (CECP) may be formed together with a pixel electrode (PE) having at least a two-layer structure so as to be electrically connected to each of a plurality of pixel common voltage lines (CVL). Each of the plurality of common electrode connection portions (CECP) is " ( " or " < It can be electrically connected to a common electrode (CE) through a side contact structure having a cross-sectional structure of the shape. For example, when each of a plurality of common electrode connection parts (CECP) is composed of a first and a second metal layer, each of the plurality of common electrode connection parts (CECP) may have a side contact structure corresponding to an undercut structure or a tapered structure formed on the side of the first metal layer by the etching rate between the first and second metal layers. For example, when each of the plurality of common electrode connection parts (CECP) is composed of a first to third metal layer, each of the plurality of common electrode connection parts (CECP) may have a side contact structure corresponding to an undercut structure or a tapered structure formed on the side of the first metal layer by the etching rate between the first and second metal layers.

[0099] Each of the dam (104), the element separation part (102), and the groove line (105) is positioned or implemented on the edge portion of the substrate (100) or the outermost pixel (Po) so as to have a closed-loop line shape (or closed-loop shape), and since this is the same as described in FIG. 1, a redundant description thereof is omitted.

[0100] The pad portion (110) may be positioned at the first edge portion of the first surface of the substrate (100) parallel to the first direction (X). The pad portion (110) may be positioned at the third edge portion of the outermost pixel regions (PAo) positioned at the first edge portion of the substrate (100). With respect to the second direction (Y), the end of the pad portion (110) may overlap or be aligned with the end of the outermost pixel regions (PAo). Accordingly, the pad portion (110) is included (or positioned) within the outermost pixel regions (PAo) positioned at the first edge portion of the substrate (100), so that no non-display area (or bezel area) according to the pad portion (110) is formed or does not exist on the substrate (100).

[0101] The pad portion (110) may include a plurality of first pads arranged parallel to each other along a first direction (X) on a first edge portion of the substrate (100). The plurality of first pads may be divided (or classified) into first data pads (DP), first gate pads (GP), first pixel driving power pads (PPP), first reference voltage pads (RVP), and first pixel common voltage pads (CVP).

[0102] Each of the first data pads (DP) can be individually (or one-to-one) connected to one end of each of the plurality of data lines (DLo, DLe) disposed on the substrate (100).

[0103] Each of the first gate pads (GP) may be individually (or one-to-one) connected to one end of each of the gate control lines disposed on the substrate (100). According to one embodiment, a plurality of first gate pads (GP) may be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate driving power pad, and at least one first gate common power pad.

[0104] Each of the first pixel driving power pads (PPP) may be individually (or one-to-one) connected to one end of each of the plurality of pixel driving power lines (PL) disposed on the substrate (100). Each of the first reference voltage pads (RVP) may be individually (or one-to-one) connected to one end of each of the plurality of reference voltage lines (RL) disposed on the substrate (100). Each of the first pixel common voltage pads (CVP) may be individually (or one-to-one) connected to one end of each of the plurality of pixel common voltage lines (CVL) disposed on the substrate (100).

[0105] A pad portion (110) according to one embodiment may include a plurality of pad groups (PG) arranged in the order of a first pixel driving power pad (PPP), a first data pad (DP), a first reference power pad (RVP), a first data pad (DP), a first gate pad (GP), a first pixel common voltage pad (CVP), a first data pad (DP), a first reference power pad (RVP), a first data pad (DP), and a first pixel driving power pad (PPP) along a first direction (X). Each of the plurality of pad groups (PG) may be connected to two adjacent pixels (P) arranged along the first direction (X). For example, each of the plurality of pad groups (PG) may include a first pad group (PG1) comprising a first pixel driving power pad (PPP), a first data pad (DP), a first reference power pad (RVP), a first data pad (DP), and a first gate pad (GP) arranged continuously within an odd-numbered pixel area (PA) along a first direction (X), and a second pad group (PG2) comprising a first pixel common voltage pad (CVP), a first data pad (DP), a first reference power pad (RVP), a first data pad (DP), and a first pixel driving power pad (PPP) arranged continuously within an even-numbered pixel area (PA) along a first direction (X).

[0106] A substrate (100) according to one embodiment may further include a plurality of auxiliary voltage lines (SVL) and a plurality of auxiliary line connection parts (SLCP).

[0107] Each of the plurality of auxiliary voltage lines (SVL) may be extended along the second direction (Y) and arranged adjacent to each of the plurality of pixel common voltage lines (CVL). Each of the plurality of auxiliary voltage lines (SVL) may not be electrically connected to the first pixel common voltage pad (CVP) but may be electrically connected to an adjacent pixel common voltage line (CVL) to receive a pixel common voltage from the adjacent pixel common voltage line (CVL). To this end, the substrate (100) according to the present specification may further include a plurality of line connection patterns (LCP) that electrically connect the pixel common voltage lines (CVL) and auxiliary voltage lines (SVL) adjacent to each other.

[0108] Each of the plurality of line connection patterns (LCP) is arranged on a substrate (100) to intersect adjacent pixel common voltage lines (CVL) and auxiliary voltage lines (SVL), and the adjacent pixel common voltage lines (CVL) and auxiliary voltage lines (SVL) can be electrically connected through a line jumping structure. For example, one side of each of the plurality of line connection patterns (LCP) can be electrically connected to a part of the auxiliary voltage line (SVL) through a first line contact hole formed in an insulating layer on the auxiliary voltage line (SVL), and the other side of each of the plurality of line connection patterns (LCP) can be electrically connected to a part of the pixel common voltage line (CVL) through a second line contact hole formed in an insulating layer on the pixel common voltage line (CVL).

[0109] Each of the plurality of auxiliary line connection parts (SLCP) electrically connects a common electrode (CE) to each of the plurality of auxiliary voltage lines (SVL) between the plurality of pixels (P) that overlap with each of the plurality of auxiliary voltage lines (SVL). Each of the plurality of auxiliary line connection parts (SLCP) according to one embodiment is electrically connected to each of the plurality of auxiliary voltage lines (SVL) at the boundary between the plurality of pixels (P) or between the plurality of pixels with respect to the second direction (Y), and can electrically connect the common electrode (CE) to each of the plurality of auxiliary voltage lines (SVL) by being electrically connected to a part of the common electrode (CE). Accordingly, the common electrode (CE) can be additionally connected to each of the plurality of auxiliary voltage lines (SVL) through the plurality of auxiliary line connection parts (SLCP). As a result, the light-emitting display device according to the present example can further prevent or further minimize image quality defects caused by deviations in the pixel common voltage supplied to each pixel (P) arranged in the display part (AA). In addition, the light-emitting display device according to the present example can supply a pixel common voltage to each of the multiple auxiliary voltage lines (SVL) through each of the pixel common voltage line (CVL) and each of the multiple line connection patterns (LCP) without additionally arranging (or forming) a first pixel common voltage pad (CVP) connected to each of the multiple auxiliary voltage lines (SVL).

[0110] A substrate (100) according to one embodiment of the present specification may further include an encapsulation layer.

[0111] The encapsulation layer may be implemented to surround the light-emitting element layer. An encapsulation layer according to one embodiment may include a first inorganic encapsulation layer (or first encapsulation layer) disposed on the light-emitting element layer and the dam (104), a second inorganic encapsulation layer (or third encapsulation layer) disposed on the first inorganic encapsulation layer, and an organic encapsulation layer (or second encapsulation layer) interposed between the first encapsulation layer and the second encapsulation layer disposed on an encapsulation region defined by the dam (104).

[0112] The organic encapsulation layer may cover the front surface (or upper surface) of the light-emitting element layer and flow toward the end of the substrate (100), and the spreading (or flow) of the organic encapsulation layer may be blocked by a dam (104). The dam (104) may define or limit the placement area (or encapsulation area) of the organic encapsulation layer and further block or prevent the spreading or overflow of the organic encapsulation layer.

[0113] Figure 5 is a diagram showing the gate driving circuit illustrated in Figures 1 and 3.

[0114] Referring to FIGS. 1, FIGS. 3, and FIGS. 5, a gate driving circuit (150) according to one embodiment of the present specification may be implemented (or embedded) within a display portion (AA) of a substrate (100). The gate driving circuit (150) may generate a scan signal based on a gate control signal supplied through a pad portion (110) and gate control lines (GCL) and sequentially supply it to a plurality of gate lines (GL).

[0115] The gate control lines (GCL) may include a start signal line, a plurality of shift clock lines, at least one gate driving voltage line, and at least one gate common voltage line. The gate control lines (GCL) may be extended along a second direction (Y) and arranged on a display portion (AA) of the substrate (100) with a predetermined spacing along a first direction (X). For example, the gate control lines (GCL) may be arranged between at least one pixel (P) along the first direction (X).

[0116] A gate driving circuit (150) according to one embodiment may be implemented as a shift register including a plurality of stage circuit sections (1501 to 150m).

[0117] Each of the plurality of stage circuit sections (1501 to 150m) is individually arranged on each horizontal line on the first surface of the substrate (100) along the first direction (X) and can be connected dependently to each other along the second direction (Y). Each of the plurality of stage circuit sections (1501 to 150m) can generate a scan signal in a predetermined order in response to a gate control signal supplied through the pad section (110) and the gate control lines (GCL) and supply it to the corresponding gate line (GL).

[0118] Each of the plurality of stage circuit sections (1501 to 150m) according to one embodiment may include a plurality of branch circuits (1511 to 151n) and a branch network (153).

[0119] Each of the plurality of branch circuits (1511 to 151n) is selectively connected to gate control lines (GCL) through the branch network (153) and can be electrically connected to each other through the branch network (153). Each of these plurality of branch circuits (1511 to 151n) can generate a scan signal according to the gate control signal supplied through the gate control lines (GCL) and the voltage of the branch network (153) and supply it to the corresponding gate line (GL).

[0120] Each of the plurality of branch circuits (1511 to 151n) may include at least one TFT (or branch TFT) among the plurality of TFTs constituting one stage circuit section (1501 to 150m). Any one of the plurality of branch circuits (1511 to 151n) may include a pull-up TFT connected to a gate line (GL). Another of the plurality of branch circuits (1511 to 151n) may include a pull-down TFT connected to a gate line (GL).

[0121] Each of the plurality of branch circuits (1511 to 151n) according to one embodiment may be placed in a circuit area between two adjacent pixels (P) or in a circuit area between at least two adjacent pixels (P) in each horizontal line of the substrate (100), but is not limited thereto. For example, each of the plurality of branch circuits (1511 to 151n) may be placed in a circuit area (or boundary area) between at least one adjacent pixel (P) depending on the number of TFTs constituting one stage circuit section (1501 to 150m) and the number of pixels (P) placed in one horizontal line.

[0122] A branch network (153) is arranged on each horizontal line of the substrate (100) and can electrically connect a plurality of branch circuits (1511 to 151n) to each other. A branch network (153) according to one embodiment may include a plurality of control node lines and a plurality of network lines.

[0123] A plurality of control node lines are arranged on each horizontal line of the substrate (100) and can be optionally connected to a plurality of branch circuits (1511 to 151n) on one horizontal line. For example, a plurality of control node lines can be arranged on the upper edge region (or lower edge region) among the pixel regions arranged on each horizontal line of the substrate (100).

[0124] A plurality of network lines may be selectively connected to gate control lines (GCL) disposed on the substrate (100) and may be selectively connected to a plurality of branch circuits (1511 to 151n). For example, the plurality of network lines may supply gate control signals supplied from the gate control lines (GCL) to the corresponding branch circuits (1511 to 151n) and transmit signals between the plurality of branch circuits (1511 to 151n).

[0125] According to the present example, since the gate driving circuit (150) is positioned within the display portion (AA) of the substrate (100), the second gap (D2) between the center of the outermost pixel area (PAo) and the outer surfaces (OS) of the substrate (100) may be less than half of the first gap (or pixel pitch) (D1) between adjacent pixel areas (PA). For example, when the gate driving circuit (150) is not positioned within the display portion (AA) of the substrate (100) but is positioned at the edge portion of the substrate (100), the second gap (D2) may not be less than half of the first gap (D1). Accordingly, a light-emitting display device according to another embodiment of the present specification may have a second gap (D2) implemented to be less than half of the first gap (D1) by having a gate driving circuit (150) placed within the display portion (AA) of the substrate (100), and furthermore, may have an air bezel structure having no bezel area or a zeroed bezel.

[0126] FIG. 6 is a rear perspective view showing a light-emitting display device according to one embodiment of the present specification.

[0127] Referring to FIGS. 1, FIGS. 3, and FIGS. 6, a light-emitting display device according to one embodiment of the present specification may further include a second pad portion (210) disposed on the rear (or back) surface (100b) of a substrate (100).

[0128] The second pad portion (210) may be placed on one edge portion (or the first rear edge portion) of the rear surface (100b) of the substrate (100) that overlaps with the pad portion (110) placed on the front surface of the substrate (100). In the following description of FIG. 6, the pad portion (110) placed on the front surface of the substrate (100) will be referred to as the "first pad portion (110)."

[0129] The second pad section (210) may include a plurality of second pads that are arranged at regular intervals along the first direction (X) and overlap each of the pads of the pad section (110). In the following description of FIG. 6, the pad of the first pad section (110) will be referred to as the "first pad."

[0130] A plurality of second pads can be divided (or classified) into second pixel driving power pads that overlap with each of the first pixel driving power pads (PPP) among the first pads disposed in the first pad section (110), second data pads that overlap with each of the first data pads (DP), second reference voltage pads that overlap with each of the first reference voltage pads (RVP), second gate pads that overlap with each of the first gate pads (GP), and second pixel common voltage pads that overlap with each of the first pixel common voltage pads (CVP).

[0131] A light-emitting display device according to one embodiment of the present specification may further include at least one third pad portion (230) and a link line portion (250) disposed on the rear surface (100b) of a substrate (100).

[0132] At least one third pad portion (or input pad portion) (230) may be disposed on the rear surface (100b) of the substrate (100). For example, at least one third pad portion (230) may be disposed on an intermediate portion adjacent to one edge portion of the rear surface (100b) of the substrate (100). According to one embodiment, at least one third pad portion (230) may include a plurality of third pads (or input pads) spaced apart from each other to have a constant spacing. For example, the plurality of third pads may include third pixel driving power pads, third data pads, third reference voltage pads, third gate pads, and third pixel common voltage pads.

[0133] The link line section (250) may include a plurality of link lines disposed between the second pad section (210) and at least one third pad section (230).

[0134] A link line section (250) according to one embodiment may include pixel driving power link lines connecting the second pixel driving power pads and the third pixel driving power pads individually (or one-to-one), data link lines connecting the second data pads and the third data pads individually (or one-to-one), reference voltage link lines connecting the second reference voltage pads and the third reference voltage pads individually (or one-to-one), gate link lines connecting the second gate pads and the third gate pads individually (or one-to-one), and a pixel common voltage link line connecting the second pixel common voltage pads and the third pixel common voltage pads.

[0135] A pixel common voltage link line may include a first common link line (251) disposed between a second pad portion (210) and at least one third pad portion (230) and commonly connected to the second pixel common voltage pads, and a second common link line (253) commonly connected to the third pixel common voltage pads and electrically connected to the first common link line (251). The second common link line (253) may be disposed on a different layer from the first common link line (251) and electrically connected to the first common link line (251) through a via hole. The size of the second common link line (253) may gradually increase from at least one third pad portion (230) toward the edge portion of the substrate (100) in order to minimize the voltage drop of the pixel common voltage.

[0136] A light-emitting display device according to one embodiment of the present specification may further include a routing unit (400) disposed on one side (OS) of a substrate (100).

[0137] The routing portion (400) may be positioned to surround the first pad portion (110), the outer surface (OS), and the second pad portion (210) of the substrate (100).

[0138] A routing section (400) according to one embodiment may include a plurality of routing lines (410). Each of the plurality of routing lines (410) is arranged at regular intervals along a first direction (X) and is formed to surround the first pad section (110), the outer surface (OS), and the second pad section (210) of the substrate (100), and may be electrically connected one-to-one with the first pads of the first pad section (110) and the second pads of the second pad section (210). According to one embodiment, each of the plurality of routing lines (410) may be formed by a printing process using a conductive paste. According to another embodiment, each of the plurality of routing lines (410) may be formed by a transfer process in which a conductive paste pattern is transferred onto a transfer pad made of a flexible material. For example, the conductive paste may include silver (Ag) paste, but is not limited thereto.

[0139] A plurality of routing lines (410) according to one embodiment may be classified (or distinguished) into pixel power routing lines (411), data routing lines (413), reference voltage routing lines (415), gate routing lines (417), and pixel common voltage routing lines (419).

[0140] Each of the pixel power routing lines (411) is formed to wrap around the first pad portion (110), the outer surface (OS), and the second pad portion (210), and can be electrically connected one-to-one to the first pixel driving power pads (PPP) of the first pad portion (110) and the second pixel driving power pads of the second pad portion (210).

[0141] Each of the data routing lines (413) is formed to wrap around the first pad portion (110), the outer surface (OS), and the second pad portion (210), and can be electrically connected one-to-one to the first data pads (DP) of the first pad portion (110) and the second data pads of the second pad portion (210).

[0142] Each of the reference voltage routing lines (415) is formed to wrap around the first pad portion (110), the outer surface (OS), and the second pad portion (210), and can be electrically connected one-to-one to the first reference voltage pads (RVP) of the first pad portion (110) and the second reference voltage pads of the second pad portion (210).

[0143] Each of the gate routing lines (417) is formed to surround the first pad portion (110), the outer surface (OS), and the second pad portion (210), and can be electrically connected one-to-one to the first gate pads (GP) of the first pad portion (110) and the second gate pads of the second pad portion (210).

[0144] Each of the pixel common voltage routing lines (419) is formed to wrap around the first pad portion (110), the outer surface (OS), and the second pad portion (210), and can be electrically connected one-to-one to the first pixel common voltage pads (CVP) of the first pad portion (110) and the second pixel common voltage pads of the second pad portion (210).

[0145] A routing section (400) according to one embodiment may further include an edge coating layer.

[0146] The edge coating layer may be implemented to cover each of the plurality of routing lines (410). According to one embodiment, the edge coating layer may be implemented to cover not only the plurality of routing lines (410) but also the first edge portion and the entire outer surface (OS) of the substrate (100). Such an edge coating layer can prevent corrosion of each of the plurality of routing lines (410) made of a metal material or electrical short circuits between the plurality of routing lines (410). Additionally, the edge coating layer can prevent or minimize reflection of external light by the plurality of routing lines (410) and the first pads of the first pad portion (110). According to one embodiment, the edge coating layer may be made of a light-blocking material including black ink. For example, the edge coating layer may be formed to surround all outer surfaces (OS) of the substrate (100). For example, the edge coating layer may be an edge protection layer or an edge insulation layer.

[0147] A light-emitting display device according to one embodiment of the present specification may further include a driving circuit (500).

[0148] The driving circuit (500) can display an image corresponding to the image data on the display unit (AA) by driving (or emitting light) pixels (P) placed on the substrate (100) based on digital image data supplied from the display driving system and a synchronization signal. The driving circuit (500) is connected to at least one third pad unit (230) placed on the rear surface (100b) of the substrate (100), and can output a data signal, a gate control signal, and a driving power supply to at least one third pad unit (230) for driving (or emitting light) pixels (P) placed on the substrate (100).

[0149] A driving circuit section (500) according to one embodiment may include a flexible circuit film (510), a driving integrated circuit (530), a printed circuit board (550), a timing controller (570), and a power circuit section (590).

[0150] The flexible circuit film (510) can be connected to at least one third pad portion (230) disposed on the rear surface (100b) of the substrate (100).

[0151] The driving integrated circuit (530) is mounted on the flexible circuit film (510). The driving integrated circuit (530) receives subpixel data and a data control signal provided by the timing controller (570), and can convert the subpixel data into an analog data signal according to the data control signal and output it. The data signal can be supplied to third data pads placed on at least one third pad portion (230) through the flexible circuit film (510).

[0152] The driving integrated circuit (530) can sense the characteristic value of the driving TFT placed in each subpixel (SP) through each of the plurality of reference voltage lines (or pixel sensing lines) placed on the substrate (100), and generate sensing raw data for each subpixel corresponding to the sensing value for each subpixel and provide it to the timing controller (570).

[0153] The printed circuit board (550) can be connected to the other edge portion of the flexible circuit film (510). The printed circuit board (550) serves to transmit signals and power between the components of the driving circuit portion (500).

[0154] The timing controller (570) is mounted on the printed circuit board (550) and receives digital image data and timing synchronization signals provided from the display driving system through a user connector placed on the printed circuit board (550). Alternatively, the timing controller (570) may not be mounted on the printed circuit board (550) but may be implemented in the display driving system or mounted on a separate control board connected between the printed circuit board (550) and the display driving system.

[0155] The timing controller (570) generates pixel data by aligning digital image data to fit the pixel array structure placed on the display unit (AA) based on the timing synchronization signal, and provides the generated pixel data to the driving integrated circuit (530).

[0156] The timing controller (570) generates a data control signal and a gate control signal, respectively, based on a timing synchronization signal, and can control the driving timing of the driving integrated circuit (530) through the data control signal and control the driving timing of the gate driving circuit (150) through the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a main clock (or dot clock).

[0157] A data control signal according to one embodiment may include a source start pulse, a source shift clock, and a source output signal, etc. Such a data control signal may be supplied to a driving integrated circuit (530) via a flexible circuit film (510).

[0158] A gate control signal according to one embodiment may include a start signal (or gate start pulse), a plurality of shift clocks, a forward driving signal, and a reverse driving signal. In this case, the plurality of shift clocks may include a plurality of scan clocks in which the phase is sequentially shifted, and a plurality of carry clocks in which the phase is sequentially shifted. Additionally, a gate control signal according to one embodiment may further include an external sensing line selection signal, an external sensing reset signal, and an external sensing control signal for sensing a characteristic value of a driving TFT placed in a subpixel (SP). Such a gate control signal may be supplied to a gate driving circuit (150) via a flexible circuit film (510), at least one third pad portion (230), a link line portion (250), a second pad portion (210), a routing portion (400), a first pad portion (110), and gate control lines (GCL).

[0159] The timing controller (570) drives the driving integrated circuit (530) and the gate driving circuit (150) respectively in an external sensing mode during a preset external sensing interval, generates subpixel compensation data to compensate for changes in the characteristics of the driving TFT per subpixel based on the subpixel-specific sensing raw data provided from the driving integrated circuit (530), and modulates the pixel data per subpixel based on the subpixel-specific compensation data. For example, the timing controller (570) can drive the driving integrated circuit (530) and the gate driving circuit (150) respectively in an external sensing mode for each external sensing interval corresponding to the blanking interval (or vertical blanking interval) of the vertical synchronization signal. For example, the external sensing mode can be performed during the inspection process before product shipment of the light-emitting display device, during the initial driving of the light-emitting display device, when the power is turned on, when the power is turned off, when the power is turned off after a long period of driving of the light-emitting display device, or during the blanking period of a frame set in real time or periodically.

[0160] A timing controller (570) according to one embodiment stores the sensing raw data for each subpixel provided by the driving integrated circuit (530) in a storage circuit according to an external sensing mode. Then, in a display mode, the timing controller (570) can correct the pixel data to be supplied to each subpixel (SP) based on the sensing raw data for each subpixel stored in the storage circuit and provide it to the driving integrated circuit (530). Here, the sensing raw data for each subpixel may include information on the temporal change of each driving TFT and self-emissive element placed in the subpixel. Accordingly, in an external sensing mode, the timing controller (570) senses the characteristic value (e.g., threshold voltage or mobility) of the driving TFT placed in each subpixel and corrects the pixel data to be supplied to each subpixel based thereon, thereby minimizing or preventing image quality degradation due to deviations in the characteristic values ​​of the driving TFTs placed in the subpixels. Since such an external sensing mode of the light-emitting display device is a technology already known by the applicant of this specification, a detailed description thereof is omitted. For example, the light-emitting display device according to the present specification can sense the characteristic value of a driving TFT placed in each subpixel through the sensing mode disclosed in Korean Published Patent Application No. 10-2016-0093179, No. 10-2017-0054654, or No. 10-2018-0002099.

[0161] The power circuit section (590) is mounted on the printed circuit board (550) and generates various power voltages required to display an image on pixels (P) using an input power supplied from the outside, and provides them to the corresponding circuit. For example, the power circuit section (590) can generate and output a logic power voltage required for driving each of the timing controller (570) and the driving integrated circuit (530), a plurality of reference gamma voltages provided to the driving integrated circuit (530), at least one gate driving power and at least one gate common power required for driving the gate driving circuit (150). Additionally, the power circuit section (590) can generate and output a pixel driving power and a pixel common voltage, but is not limited thereto. For example, the driving integrated circuit (530) can generate and output a pixel driving power and a pixel common voltage, respectively, based on a plurality of reference gamma voltages.

[0162] FIG. 7 is a rear perspective view showing a light-emitting display device according to another embodiment of the present specification, which additionally comprises a wiring board in addition to the light-emitting display device shown in FIG. 1 to 6.

[0163] Referring to FIG. 7, a light-emitting display device according to another embodiment of the present specification may include a substrate (100), a second substrate (200), a coupling member (300), and a routing part (400).

[0164] The substrate (100) may be described as a display substrate, a pixel array substrate, an upper substrate, a front substrate, or a base substrate. The substrate (100) may be a glass substrate, a thin glass substrate that can be bent or curved, or a plastic substrate. In the following description of FIG. 7, the substrate (100) will be referred to as the "first substrate (100)."

[0165] Since the first substrate (100) is substantially the same as the substrate (100) of the light-emitting display device shown in FIGS. 1 to 6, the same reference numeral is given to it, and a redundant description thereof is omitted.

[0166] The second substrate (200) may be represented as a wiring substrate, a link substrate, a bottom substrate, a rear substrate, or a link glass. The second substrate (200) may be a glass substrate, a thin glass substrate that can be bent or curved, or a plastic substrate. For example, the second substrate (200) may be made of the same material as the first substrate (100). The second substrate (200) may have the same size as the first substrate (100), but is not limited thereto, and may have a smaller size than the first substrate (100). For example, it may be preferable for the second substrate (200) to have the same size as the first substrate (100) in order to maintain or secure the rigidity of the first substrate (100).

[0167] The second substrate (200) may include a second pad portion (210), at least one third pad portion (230), and a link line portion (250). Since each of the second pad portion (210), at least one third pad portion (230), and link line portion (250) is substantially identical to the second pad portion (210), at least one third pad portion (230), and link line portion (250) described in FIG. 6, except that they are placed on the rear (or back) (200b) of the second substrate (200), they are given the same reference numerals, and redundant descriptions thereof are omitted.

[0168] The second substrate (200) can be joined (or connected) to the second surface (or rear surface) of the first substrate (100) via a joining member (300). The joining member (300) is interposed between the first substrate (100) and the second substrate (200). Accordingly, the first substrate (100) and the second substrate (200) can be joined to each other via the joining member (300).

[0169] The routing section (400) may be described as a side routing section or a printing line section. The routing section (400) is arranged to surround the outer surface (OS1a) of the first substrate (100) and the outer surface (OS1b) of the second substrate (200). According to one embodiment, the routing section (400) may include a plurality of routing lines (410) arranged on each of the first outer surface (or one side) (OS1a) of the outer surface (OS) of the first substrate (100) and the first outer surface (or one side) (OS1b) of the outer surface (OS) of the second substrate (200). Since this routing section (400) is substantially the same as the routing section (400) described in FIG. 6, except that each of the plurality of routing lines (410) is arranged to surround the first pad section (110) and the first outer surface (OS1a) of the first substrate (100) and the second pad section (210) and the first outer surface (OS1b) of the second substrate (200), the same reference numerals are assigned to it, and a redundant description thereof is omitted.

[0170] A light-emitting display device according to another embodiment of the present specification may further include a driving circuit (500).

[0171] The driving circuit section (500) may include a flexible circuit film (510), a driving integrated circuit (530), a printed circuit board (550), a timing controller (570), and a power circuit section (590). Since this driving circuit section (500) is substantially the same as the driving circuit section (500) described in FIG. 6, except that the flexible circuit film (510) is connected to at least one third pad section (230) disposed on the rear surface (200b) of the second substrate (200), the same reference numerals are given to it, and a redundant description thereof is omitted.

[0172] FIG. 8 is a cross-sectional view of line I-I' shown in FIG. 7, FIG. 9 is a cross-sectional view of line II-II' shown in FIG. 7, FIG. 10 is a cross-sectional view of line III-III' shown in FIG. 7, and FIG. 11 is an enlarged view of part 'B' shown in FIG. 8. FIG. 8 is a cross-sectional view of line I-I' passing through the pad shown in FIG. 7, and FIG. 9 is a cross-sectional view of line II-II' passing between the pads shown in FIG. 7.

[0173] Referring to FIGS. 7 to 11, a light-emitting display device according to one embodiment of the present specification may further include a first substrate (100), a second substrate (200), a coupling member (300), and a routing part (400).

[0174] A first substrate (100) according to one embodiment may include a circuit layer (101), a passivation layer (PAS), a planarization layer (103), an emitting element layer (EDL), a bank (BK), a dam (104), a groove line (105), and an encapsulation layer (106).

[0175] The circuit layer (101) may be disposed on the first substrate (100). The circuit layer (101) may be represented as a pixel array layer or a TFT array layer.

[0176] A circuit layer (101) according to one embodiment may include a buffer layer (101a), a circuit array layer (101b), an interlayer insulation layer (ILD), and a passivation layer (PAS).

[0177] The buffer layer (101a) serves to block substances such as hydrogen contained in the first substrate (100) from diffusing into the circuit array layer (101b) during the high-temperature process in the manufacturing process of the TFT. Additionally, the buffer layer (101a) can also serve to prevent external moisture or humidity from penetrating into the light-emitting element layer (EDL). The buffer layer (101a) according to one embodiment may include a single-layer structure of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof, but is not necessarily limited thereto.

[0178] The circuit array layer (101b) may include a pixel circuit (PC) having a driving TFT (Tdr) disposed in each pixel area (PA) on the buffer layer (101a).

[0179] A driving TFT (Tdr) placed in the circuit area (CA) of each pixel area (PA) may include an active layer (ACT), a gate insulating film (GI), a gate electrode (GE), an interlayer insulating layer (ILD), a first source / drain electrode (SD1), and a second source / drain electrode (SD2).

[0180] An active layer (ACT) may be placed on a buffer layer (101a) on each pixel area (PA). The active layer (ACT) may include a channel area that overlaps with a gate electrode (GE), and a first source / drain area and a second source / drain area that are parallel to each other with the channel area in between. The active layer (ACT) can directly connect lines within a display area (AA) by being conductive through a conductive process. Additionally, the active layer (ACT) may be used as a bridge line of a jumping structure that electrically connects lines placed on different layers.

[0181] A gate insulating film (GI) can be placed on the channel region of an active layer (ACT). The gate insulating film (GI) can insulate the active layer (ACT) and the gate electrode (GE).

[0182] The gate electrode (GE) is placed on the gate insulating film (GI) and can be connected to the gate line (GL). The gate electrode (GE) can overlap with the channel region of the active layer (ACT) with the gate insulating film (GI) in between.

[0183] An interlayer insulating layer (ILD) may be disposed on a first substrate (100) to cover a gate electrode (GE) and an active layer (ACT). The interlayer insulating layer (ILD) may electrically insulate (or separate) the gate electrode (GE) and the source / drain electrodes (SD1, SD2). For example, the interlayer insulating layer (ILD) may be represented as an insulating layer or a first insulating layer.

[0184] The first source / drain electrode (SD1) is disposed on an interlayer insulating layer (ILD) that overlaps with the first source / drain region of the active layer (ACL), and can be electrically connected to the first source / drain region of the active layer (ACL) through a first source / drain contact hole disposed in the interlayer insulating layer (ILD). For example, the first source / drain electrode (SD1) is the source electrode of a driving TFT (Tdr), and the first source / drain region of the active layer (ACL) may be the source region.

[0185] The second source / drain electrode (SD2) is disposed on an interlayer insulating layer (ILD) that overlaps with the second source / drain region of the active layer (ACL), and can be electrically connected to the second source / drain region of the active layer (ACL) through a second source / drain contact hole disposed in the interlayer insulating layer (ILD). For example, the second source / drain electrode (SD2) is the drain electrode of the driving TFT (Tdr), and the second source / drain region of the active layer (ACL) may be the drain region.

[0186] Each of the first source / drain electrode (SD1) and the second source / drain electrode (SD1) may be formed with at least two layers, including a first source / drain metal layer and a second source / drain metal layer on the first source / drain metal layer.

[0187] According to one embodiment, the first source / drain metal layer may comprise at least one material selected from molybdenum (Mo), titanium (Ti), and molybdenum titanium alloy (MoTi). The first source / drain metal layer may comprise at least one material selected from aluminum (Al), silver (Ag), and copper (Cu). For example, the first source / drain electrode (SD1) and the second source / drain electrode (SD1) may each comprise a two-layer structure of MoTi / Cu, but are not limited thereto.

[0188] Each of the first source / drain electrode (SD1) and the second source / drain electrode (SD1) can be used as lines arranged in a direction parallel to the first direction (X) among the pixel driving lines (DL, GL, PL, CVL, RL, GCL) arranged on the first substrate (100). For example, each of the first source / drain electrode (SD1) and the second source / drain electrode (SD1) can be formed together with a gate line (GL), etc. arranged parallel to the second direction (Y) on the display portion (AA).

[0189] Each of the first and second switching TFTs (Tsw1, Tsw2) constituting the pixel circuit (PC) is formed together with the driving TFT (Tdr), so a description thereof is omitted.

[0190] A circuit layer (101) according to one embodiment may further include a lower metal layer (BML) disposed between a first substrate (100) and a buffer layer (101a).

[0191] The lower metal layer (BML) may include a light-blocking pattern (LSP) placed below the active layer (ACT) of the TFTs (Tdr, Tsw1, Tsw2) constituting the pixel circuit (PC).

[0192] The light-blocking pattern (LSP) can be arranged in an island shape between the first substrate (100) and the active layer (ACT). The light-blocking pattern (LSP) blocks light incident on the active layer (ACT) through the first substrate (100), thereby minimizing or preventing changes in the threshold voltage of the TFT caused by external light. Optionally, the light-blocking pattern (LSP) may be electrically connected to the first source / drain electrode (SD1) of the TFT to serve as the lower gate electrode of the corresponding TFT, in which case changes in the threshold voltage of the TFT due to bias voltage as well as changes in characteristics due to light can be minimized or prevented.

[0193] The lower metal layer (BML) can be used as lines arranged parallel to each other among the gate line (GL), data line (DL), pixel driving power line (PL), pixel common voltage line (CVL), and reference voltage line (RL). For example, the lower metal layer (BML) can be used as lines arranged parallel to the second direction (Y) among the pixel driving lines (DL, GL, PL, CVL, RL, GCL) arranged on the first substrate (100).

[0194] A passivation layer (PAS) may be placed on a first substrate (100) to cover a pixel circuit (PC) including a driving TFT (Tdr). The passivation layer (PAS) may cover a circuit layer (101) including a driving TFT (Tdr) placed in each pixel area (PA).

[0195] A passivation layer (PAS) according to one embodiment may be made of an inorganic material. For example, the passivation layer (PAS) may include a single-layer structure of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof. For example, the passivation layer (PAS) may be expressed using terms such as a protective layer, a circuit protective layer, a circuit insulating layer, an inorganic insulating layer, a first inorganic insulating layer, or a second insulating layer.

[0196] The flattening layer (103) may be disposed on a first substrate (100) disposed on a circuit layer (101) and may provide a flat surface on the circuit layer (101). For example, the flattening layer (103) may be disposed on a passivation layer (PAS) of the circuit layer (101) and may provide a flat surface on the passivation layer (PAS).

[0197] A planarization layer (103) according to one embodiment may be formed to cover the remaining circuit layer (101), excluding the circuit layer (101) disposed at the edge portion of the first substrate (100) or the outermost pixel (Po). For example, the planarization layer (103) may be disposed between the first substrate (100) and the light-emitting element layer (EDL) or disposed below the light-emitting element layer (EDL). A planarization layer (103) according to one embodiment may be formed of an organic material, but is not limited thereto. For example, the planarization layer (103) may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto.

[0198] A light-emitting element layer (EDL) may be disposed on a planarization layer (103). A light-emitting element layer (EDL) according to one embodiment may include a pixel electrode (PE), a self-emissive element (ED), and a common electrode (CE).

[0199] The pixel electrode (PE) may be represented as the anode electrode, reflective electrode, bottom electrode, or first electrode of the self-luminous element (ED).

[0200] A pixel electrode (PE) may be placed on a flattening layer (103) that overlaps with the light-emitting region (EA) of each subpixel (SP) on the first substrate (100). The pixel electrode (PE) may be patterned in an island shape and placed within each subpixel (SP), and may be electrically connected to the first source / drain electrode (SD1) of the driving TFT (Tdr) of the corresponding pixel circuit (PC). For example, one side of the pixel electrode (PE) may extend onto the first source / drain electrode (SD1) of the driving TFT (Tdr) and may be electrically connected to the first source / drain electrode (SD1) of the driving TFT (Tdr) through an electrode contact hole (ECH) provided in the flattening layer (103).

[0201] The pixel electrode (PE) may include a metal material having a low work function and excellent reflection efficiency, but is not limited thereto.

[0202] A pixel electrode (PE) according to one embodiment may have a two-layer structure comprising a first pixel electrode layer (PEL1) (or a first metal layer) and a second pixel electrode layer (PEL2) (or a second metal layer). The first and second pixel electrode layers (PEL1, PEL2) may be sequentially deposited on a planarization layer (103) and then simultaneously patterned.

[0203] The first pixel electrode layer (PEL1) may be placed on the planarization layer (103). The second pixel electrode layer (PEL2) may be placed (or laminated) on the first pixel electrode layer (PEL1). For example, the first pixel electrode layer (PEL1) may serve as an adhesive layer with the planarization layer (103) and as an auxiliary electrode for the self-emissive element (ED), and may be made of ITO or IZO material, but is not limited thereto. For example, the second pixel electrode layer (PEL2) may serve as a reflector and reduce the resistance of the pixel electrode (PE), and may be made of one of aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and molybdenum titanium alloy (MoTi), but is not limited thereto. For example, the pixel electrode (PE) may be made of a two-layer structure of ITO / MoTi or a two-layer structure of MoTi / ITO.

[0204] A pixel electrode (PE) according to another embodiment may have a three-layer structure comprising a first pixel electrode layer (PEL1), a second pixel electrode layer (PEL2) on the first pixel electrode layer (PEL1), and a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer (PEL2). The first and second pixel electrode layers (PEL1, PEL2) and the third pixel electrode layer may be sequentially deposited on a planarization layer (103) and then simultaneously patterned.

[0205] The third pixel electrode layer serves as an electrode for the self-emissive device (ED) and can be made of ITO or IZO material. In this case, the pixel electrode (PE) can be made of a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0206] A pixel electrode (PE) according to another embodiment may have a four-layer structure comprising a first pixel electrode layer (PEL1), a second pixel electrode layer (PEL2) on the first pixel electrode layer (PEL1), a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer (PEL2), and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer. The first to fourth pixel electrode layers may be sequentially deposited on a planarization layer (103) and then simultaneously patterned.

[0207] In a pixel electrode (PE) with a four-layer structure, the first pixel electrode layer can serve as an adhesive layer with the planarization layer (103) and as an auxiliary electrode for the self-luminous element (ED), and can be made of one of ITO, molybdenum (Mo), and molybdenum titanium alloy (MoTi). The second pixel electrode layer can serve to reduce the resistance of the pixel electrode (PE) and can be made of copper (Cu). The third pixel electrode layer can serve as a reflector and can be made of one of aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and molybdenum titanium alloy (MoTi). The fourth pixel electrode layer can serve as an electrode for the self-luminous element (ED) and can be made of ITO or IZO. For example, a pixel electrode (PE) according to another embodiment can be made of a four-layer structure of ITO / Cu / MoTi / ITO.

[0208] According to another example, the pixel electrode (PE) may be composed of a 5-layer structure including a first pixel electrode layer made of ITO, a second pixel electrode layer made of molybdenum titanium alloy (MoTi), a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of silver (Ag), and a fifth pixel electrode layer made of ITO.

[0209] A self-luminous element (ED) can be placed on a first substrate (100). The self-luminous element (ED) can be formed on a pixel electrode (PE) and can be in direct contact with the pixel electrode (PE). The pixel electrode (PE) can be placed between the planarization layer (103) and the self-luminous element (ED).

[0210] A self-luminous element (ED) according to one embodiment may be a common layer formed in common on each of a plurality of subpixels (SP) so as not to be distinguished by subpixel (SP). The self-luminous element (ED) may emit white light (or blue light) in response to a current flowing between a pixel electrode (PE) and a common electrode (CE). A self-luminous element (ED) according to one embodiment may include an organic light-emitting element, or may include a stacked or mixed structure of an organic light-emitting element and a quantum dot light-emitting element.

[0211] An organic light-emitting device according to one embodiment may include two or more organic light-emitting parts for emitting white light (or blue light). For example, the organic light-emitting device may include a first organic light-emitting part and a second organic light-emitting part for emitting white light by mixing a first light and a second light. Here, the first organic light-emitting part may include at least one of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting part may include at least one light-emitting layer among the blue light-emitting layer, the green light-emitting layer, the red light-emitting layer, the yellow light-emitting layer, and the yellow-green light-emitting layer for emitting a second light that can be mixed with the first light emitted from the first organic light-emitting part to produce white light.

[0212] An organic light-emitting device according to one embodiment may further include at least one functional layer to improve light emission efficiency and / or lifespan, etc. For example, the functional layer may be disposed on the upper and / or lower portions of the light-emitting layer, respectively.

[0213] A common electrode (CE) is placed on a display portion (AA) of a first substrate (100) and is electrically connected to each of the self-emissive elements (ED) of a plurality of pixels (P). For example, the common electrode (CE) may be placed on the remaining display portion (AA) excluding the edge portion of the first substrate (100).

[0214] The common electrode (CE) can be represented as a cathode electrode, a transparent electrode, an upper electrode, a negative electrode, or a second electrode. The common electrode (CE) is formed on a self-luminous element (ED) and can be in direct contact with or electrically in direct contact with the self-luminous element (ED). The common electrode (CE) may include a transparent conductive material so that light emitted from the self-luminous element (ED) can be transmitted.

[0215] A common electrode (CE) according to one embodiment may be composed of at least one single-layer or multi-layer structure of a transparent conductive material having a relatively high work function or graphene. For example, the common electrode (CE) may be composed of a metal oxide such as ITO or IZO, or a mixture of a metal and an oxide such as ZnO:Al or SnO2:Sb.

[0216] Additionally, the light-emitting element layer (EDL) may further include a capping layer disposed on the common electrode (CE). The capping layer is disposed on the common electrode (CE) and can improve the light emission efficiency by controlling the refractive index of the light emitted from the light-emitting element layer (EDL).

[0217] A bank (BK) may be placed on a planarization layer (103) and may define a pixel region on a first substrate (100). A bank (BK) may be placed on the planarization layer (103) to cover the edge portion of a pixel electrode (PE). A bank (BK) defines a light-emitting region (or aperture) (EA) of each of a plurality of subpixels (SP) and may electrically isolate a pixel electrode (PE) placed in an adjacent subpixel (SP). A bank (BK) may be formed to cover an electrode contact hole (ECH) placed in each pixel region (PA). A bank (BK) may be covered by a self-luminous element (ED) of a light-emitting element layer (EDL). For example, a self-luminous element (ED) may be placed on the bank (BK) as well as on the pixel electrode (PE) of each of the plurality of subpixels (SP).

[0218] A bank (BK) according to one embodiment may be a transparent bank made of a transparent material or a black bank containing a black pigment.

[0219] Referring to FIGS. 8 to 10, the dam (104) may be placed at the edge portion of the first substrate (100) or at the edge portion of the outermost pixel (Po). For example, the dam (104) is included as a component of the outermost pixels (Po) placed at the edge portion of the first substrate (100), thereby allowing the outermost pixels (Po) to have a structure different from the inner pixels.

[0220] The dam (104) may be placed on the circuit layer (101) at the edge portion of the first substrate (100) or the outermost pixel (Po) to form a closed-loop line shape. For example, the dam (104) may be placed on the circuit layer (101) to form a closed-loop line shape surrounding the display portion (AA) and may be supported by the buffer layer (101a) of the circuit layer (101). For example, the dam (104) may be implemented to isolate the self-luminescent element (ED) placed at the edge portion of the first substrate (100) or the outermost pixels (Po). Such a dam (104) will be described later.

[0221] The device isolation portion (102) may be disposed on a circuit layer (101) placed on the edge portion of the substrate (100) or the outermost pixels (Po) so as to have a closed-loop line shape surrounding the dam (104). One edge portion of the device isolation portion (102) according to one embodiment may be implemented to include a protruding tip structure protruding toward the dam (104). For example, the device isolation portion (102) may be interposed between an interlayer insulating layer (ILD) and a passivation layer (PAS). Such a device isolation portion (102) will be described later.

[0222] The groove line (105) may be placed in a groove area (or trench area) defined in the inner area of ​​the dam (104). According to one embodiment, the groove line (105) may be placed on the circuit layer (101) to form a closed-loop line shape between the end of the flattening layer (103) and the dam (104). For example, the groove line (105) may be formed or implemented by removing both the flattening layer (103) and the passivation layer (PAS) that were placed in the groove area of ​​the inner area of ​​the dam (104). For example, the groove line (105) may be implemented so that a portion of the buffer layer (101a) placed between the end of the flattening layer (103) and the dam (104) is exposed. Additionally, the groove line (105) may be implemented to separate the self-emissive element (ED) placed at the edge portion of the first substrate (100) or the outermost pixels (Po). Such groove line (105) will be described later.

[0223] The encapsulation layer (106) may be implemented to cover the light-emitting element layer (EDL) by being placed on the remaining portion of the first substrate (100) excluding the outermost edge portion. For example, the encapsulation layer (106) may be placed on the remaining portion of the first substrate (100) excluding the area between the outer surface (OS) of the first substrate (100) and the device isolation portion (102) to cover the light-emitting element layer (EDL) and the dam (104). For example, the encapsulation layer (106) may be implemented on the first substrate (100) to surround both the front surface and the lateral surfaces of the light-emitting element layer (EDL). For example, the encapsulation layer (106) is implemented to surround both the front surface and the lateral surfaces of the light-emitting element layer (EDL), thereby blocking oxygen or moisture from penetrating into the light-emitting element layer (EDL) and thereby improving the reliability of the light-emitting element layer (EDL) against oxygen or moisture.

[0224] A bag layer (106) according to one embodiment may include first to third bag layers (106a, 106b, 106c).

[0225] The first encapsulation layer (106a) can be implemented to block oxygen or moisture from penetrating into the light-emitting element layer (EDL). The first encapsulation layer (106a) can be placed on the common electrode (CE) and surround the light-emitting element layer (EDL). Accordingly, both the front surface and the lateral surfaces of the light-emitting element layer (EDL) can be surrounded by the first encapsulation layer (106a).

[0226] According to one embodiment, the first encapsulation layer (106a) may be disposed on the remaining portion of the first substrate (100), excluding the area between the outer surface (OS) of the first substrate (100) and the device separation portion (102), to cover the light-emitting element layer (EDL) and the dam (104). For example, the end of the first encapsulation layer (106a) may be disposed below the device separation portion (102).

[0227] According to one embodiment, the first encapsulation layer (106a) is disposed on the light-emitting element layer (EDL) and can surround or seal the light-emitting element layer (EDL) including the self-emissive element (ED) separated by the element separation portion (102), the dam (104), and the groove line (105) by being in direct contact with the uppermost surface (or surface) of the buffer layer (101a) at the edge portion of the first substrate (100) or the outermost pixel (Po). By doing so, the first encapsulation layer (106a) completely surrounds or seals the separation surface (or disconnection surface) of the separated self-emissive element (ED) and the common electrode (CE), thereby preventing lateral moisture penetration from the source (or completely).

[0228] According to one embodiment, the first encapsulation layer (106a) may be a first inorganic encapsulation layer comprising an inorganic insulating material. For example, the first encapsulation layer (106a) may include a single-layer structure of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof.

[0229] A second encapsulation layer (106b) may be implemented on the first encapsulation layer (106a) in an encapsulation area defined by the dam (104) so ​​as to have a thickness relatively thicker than that of the first encapsulation layer (106a). The second encapsulation layer (106b) may have a thickness sufficient to cover foreign substances (or unnecessary materials or unnecessary structures) that are present or may be present on the first encapsulation layer (106a). Due to its relatively thick thickness, this second encapsulation layer (106b) may spread to the edge portion of the substrate (100), but the spreading of the second encapsulation layer (106b) may be blocked by the dam (104).

[0230] According to one embodiment, the second encapsulation layer (106b) may include an organic material or a liquid organic material. For example, the second encapsulation layer (106b) may be made of an organic material such as silicon oxycarbon (SiOCz), acrylic, or epoxy-based resin. For example, the second encapsulation layer (106b) may be described as a foreign matter cover layer or an organic encapsulation layer.

[0231] According to one embodiment, the second bag layer (106b) can spread smoothly to the dam (104) through the groove line (105), thereby preventing the phenomenon of incomplete filling of the second bag layer (106b) occurring in the area adjacent to the inside of the dam (104). For example, the spreading of the second bag layer (106b) proceeds smoothly to the dam (104) through the groove line (105) without being obstructed by other structures, so that the second bag layer (106b) can be completely filled up to the area adjacent to the inside of the dam (104).

[0232] According to one embodiment, when an inner trench structure for separating the light-emitting element layer (EDL) is placed in the inner area of ​​the dam (104) instead of the groove line (105), the spreading of the second encapsulation layer (106b) is obstructed or blocked by the height and step difference of the inner trench structure and does not proceed to the dam (104), and as a result, an unfilled phenomenon of the second encapsulation layer (106b) may occur in the area adjacent to the inner side of the dam (104).

[0233] The third encapsulation layer (106c) may be implemented to primarily block oxygen or moisture from penetrating into the light-emitting diode layer (EDL). The third encapsulation layer (106c) may be implemented to surround both the second encapsulation layer (106b) disposed on the inside of the dam (104) and the first encapsulation layer (106a) disposed on the outside of the dam (104). According to one embodiment, the third encapsulation layer (106c) may include an inorganic material that is the same as or different from the first encapsulation layer (106a).

[0234] A light-emitting display device or a first substrate (100) according to one embodiment of the present specification may include a first margin region (MA1), a second margin region (MA2), and a third margin region (MA3).

[0235] A first margin area (MA1) may be positioned between the light-emitting area (EA) of the outermost pixel (P) and the dam (104). Based on the reliability margin of the light-emitting element layer (EDL) due to lateral moisture permeability, the first margin area (MA1) may have a first width between the end of the light-emitting area (EA) (or bank (BK)) of the outermost pixel (Po) and the dam (104). Accordingly, the dam (104) may be implemented to be spaced apart from the end of the light-emitting area (EA) by a first width of the first margin area (MA1) with respect to the first direction (X). For example, the first width may be set to 30 to 120 micrometers.

[0236] A second margin region (MA2) may be positioned between the outer surface (OS) of the first substrate (100) and the dam (104). The second margin region (MA2) may have a second width between the outer surface (OS) of the first substrate (100) and the dam (104), based on the reliability margin of the light-emitting element layer (EDL) due to lateral moisture permeability. Accordingly, the dam (104) may be implemented to be spaced apart from the outer surface (OS) of the first substrate (100) by a second margin region (MA2) of a second width with respect to the first direction (X). For example, the second margin region (MA2) may be an area including the first pad portion (110) and the element separation portion (102). For example, the second width may be set to 100 to 140 micrometers.

[0237] A third margin area (MA3) may be positioned between the first margin area (MA1) and the second margin area (MA2). The third margin area (MA3) may have a third width corresponding to the width of the lowest bottom surface (or lower surface) of the dam (104). For example, the third margin area (MA3) may be an area containing the dam (104). For example, the third width may be set to 40 to 60 micrometers.

[0238] Based on the first direction (X), the width of each of the first margin area (MA1), the second margin area (MA2), and the third margin area (MA3) can be implemented such that the second gap (D2) between the center of the outermost pixel (Po) and the outer surface (OS) of the first substrate (100) is less than or equal to half the pixel pitch.

[0239] In the second margin region (MA2), the edge portions of each of the self-luminous element (ED), common electrode (CE), first encapsulation layer (106a), and second encapsulation layer (106c) placed on the device separation portion (102) can be removed by a patterning process. For example, the edge portions of each of the self-luminous element (ED), common electrode (CE), first encapsulation layer (106a), and second encapsulation layer (106c) placed on the device separation portion (102) can be removed by a pad opening process. At this time, the separation pattern of each of the self-luminous element (ED) and common electrode (CE), which are separated by the device separation portion (102) and placed in an island shape on the buffer layer (101a) below the device separation portion (102), can be maintained in a state surrounded by the first encapsulation layer (106a).

[0240] Referring to FIG. 3 and FIG. 7 to 9, a first substrate (100) according to one embodiment may further include a first pad portion (110).

[0241] The first pad portion (110) is positioned on one edge portion of the first substrate (100) and can be electrically connected one-to-one with pixel driving lines (DL, GL, PL, CVL, RL, GCL).

[0242] A first pad portion (110) according to one embodiment may include a plurality of first pads (111) disposed inside a circuit layer (101).

[0243] A plurality of first pads (111) can be divided (or classified) into first data pads (DP), first gate pads (GP), first pixel driving power pads (PPP), first reference voltage pads (RVP), and first pixel common voltage pads (CVP).

[0244] Each of the plurality of first pads (111) is disposed on an interlayer insulating layer (ILD) and can be electrically connected to a corresponding line among the pixel driving lines (DL, GL, PL, CVL, RL, GCL) through a pad electrode contact hole (PEH) penetrating the interlayer insulating layer (ILD) and the buffer layer (101a). Each of the plurality of first pads (111) is made of the same material as the source / drain electrode of the TFT and can be formed together with the source / drain electrode of the TFT. These plurality of first pads (111) will be described later.

[0245] The first pad portion (110) according to one embodiment may further include a plurality of auxiliary pads (113).

[0246] Each of the plurality of auxiliary pads (113) may be disposed in the first pad portion (110) so as to be electrically connected one-to-one with each of the plurality of first pads (111). Each of the plurality of auxiliary pads (113) may be disposed on the passivation layer (PAS) of the first pad portion (110) to cover each of the plurality of first pads (111). Each of the plurality of auxiliary pads (113) may be disposed on the passivation layer (PAS) with each of the plurality of first pads (111) and may have a longer length than the first pad (111). One side of each of the plurality of auxiliary pads (113) may be electrically directly connected to the corresponding first pad (111).

[0247] According to one embodiment, a plurality of auxiliary pads (113) may be divided (or classified) into data auxiliary pads, gate auxiliary pads, pixel driving power auxiliary pads, reference voltage auxiliary pads, and pixel common voltage auxiliary pads.

[0248] Each of the plurality of auxiliary pads (113) according to one embodiment may have a line shape that is extended along the second direction (Y) and spaced apart from each other or electrically separated along the first direction (X). For example, each of the plurality of auxiliary pads (113) may extend from the outer surface (OS) of the first substrate (100) toward the inside of the display unit (AA) along the second direction (Y).

[0249] Each of the plurality of auxiliary pads (113) according to one embodiment may have a second length (or second width) that is relatively longer than the first length (or first width) of the corresponding first pad (111). Each of the plurality of auxiliary pads (113) may have a length of several tens of micrometers with respect to the length direction or the second direction (Y). For example, when each of the plurality of first pads (111) has a length of 5 to 50 micrometers or less with respect to the length direction or the second direction (Y), each of the plurality of auxiliary pads (113) may have a length of 50 to 150 micrometers. For example, each of the plurality of auxiliary pads (113) may have a length that is at least half as long as the corresponding first pad (111).

[0250] Each of the plurality of auxiliary pads (113) can be electrically directly connected to the corresponding pad (111) to extend the length of the corresponding first pad (111) to a length of tens of micrometers and / or increase the contact area between the first pad (111) and the routing unit (400). Accordingly, the auxiliary pad (113) can be described as an auxiliary pad electrode, an extension pad, a connecting pad, a pad extension electrode, a pad extension line, a pad connecting electrode, or a pad connecting line.

[0251] Referring to FIGS. 8 to 10, a light-emitting display device or a first substrate (100) according to one embodiment of the present specification may further include a wavelength conversion layer (107) disposed on an encapsulation layer (106).

[0252] The wavelength conversion layer (107) converts the wavelength of light incident from the light-emitting region (EA) of each pixel region (PA). For example, the wavelength conversion layer (107) may convert white light (or blue light) incident from the light-emitting region (EA) into color light corresponding to a subpixel (SP), or allow only color light corresponding to a subpixel (SP) to pass through. For example, the wavelength conversion layer (107) may include at least one of a wavelength conversion member and a color filter layer.

[0253] A wavelength conversion layer (107) according to one embodiment may include a plurality of wavelength conversion members (107a) and a protective layer (107b).

[0254] According to one embodiment, a plurality of wavelength conversion members (107a) may be disposed on an encapsulation layer (106) on a light-emitting region (EA) of each subpixel (SP). For example, the plurality of wavelength conversion members (107a) may have a size equal to or larger than the light-emitting region (EA) of each subpixel (SP).

[0255] A plurality of wavelength conversion members (107a) according to one embodiment may be divided (or classified) into a red color filter that converts white light into red light, a green color filter that converts white light into green light, and a blue color filter that converts white light into blue light. For example, the red color filter may be placed on the encapsulation layer (106) on the light-emitting region (EA) of a red subpixel (SP), the green color filter may be placed on the encapsulation layer (106) on the light-emitting region (EA) of a green subpixel (SP), and the blue color filter may be placed on the encapsulation layer (106) on the light-emitting region (EA) of a blue subpixel (SP).

[0256] According to another example, a plurality of wavelength conversion members (107a) may be disposed on the encapsulation layer (106) on each subpixel (SP). For example, each of the plurality of wavelength conversion members (107a) may be disposed on the encapsulation layer (106) so as to overlap with the entire area of ​​the corresponding subpixel (SP).

[0257] According to another example, a plurality of wavelength conversion members (107a) may overlap each other on an encapsulation layer (106) that overlaps with a circuit area (CA) (or non-luminous area) excluding the light-emitting area (EA) of each subpixel (SP). For example, two or more wavelength conversion members (107a) having different colors may be disposed on an encapsulation layer (106) that overlaps with a circuit area (CA) (or non-luminous area) excluding the light-emitting area (EA) of each subpixel (SP). The two or more wavelength conversion members (107a) disposed on an encapsulation layer (106) that overlaps with a circuit area (CA) (or non-luminous area) may serve as a light-blocking pattern that prevents color mixing between adjacent subpixels (SP) or adjacent pixels (P).

[0258] The protective layer (107b) may be implemented to cover the wavelength conversion members (107a) and provide a flat surface on the wavelength conversion members (107a). For example, the protective layer (107b) may be disposed to cover the wavelength conversion members (107a) and the encapsulation layer (106) on which the wavelength conversion members (107a) are not disposed. The protective layer (107b) according to one embodiment may comprise an organic material. Optionally, the protective layer (107b) may further comprise a getter material capable of adsorbing moisture and / or oxygen.

[0259] Optionally, the wavelength conversion layer (107) according to one embodiment may include two or more wavelength conversion members (107a) that are disposed on an encapsulation layer (106) overlapping with a circuit region (CA) (or non-luminous region) excluding a light-emitting region (EA) at each subpixel (SP) and serve as a light-blocking pattern.

[0260] Alternatively, the wavelength conversion layer (107) may be changed to a wavelength conversion sheet having a sheet form and disposed on the encapsulation layer (106). In this case, the wavelength conversion sheet (or quantum dot sheet) may include wavelength conversion members (107a) interposed between a pair of films. For example, when the wavelength conversion layer (107) includes quantum dots that re-emit color light set in the subpixel, the light-emitting element layer (EDL) of the subpixel (SP) may be implemented to emit white light or blue light.

[0261] A light-emitting display device or a first substrate (100) according to one embodiment of the present specification may further include a functional film (108).

[0262] A functional film (108) may be disposed on a wavelength conversion layer (107). For example, the functional film (108) may be bonded to the wavelength conversion layer (107) via a transparent adhesive member. A functional film (108) according to one embodiment may include at least one of an anti-reflection layer (or anti-reflection film), a barrier layer (or barrier film), a touch sensing layer, and a light path control layer (or light path control film).

[0263] The anti-reflection layer may include a circularly polarized layer (or circularly polarized film) that blocks reflected light that is reflected by TFT and / or pixel driving lines disposed on the first substrate (100) and travels outward again.

[0264] The barrier layer can primarily prevent moisture or oxygen penetration by being made of a material with low moisture permeability, for example, a polymer material.

[0265] The touch sensing layer includes a touch electrode layer based on mutual capacitance or magnetic capacitance, thereby enabling the output of touch data corresponding to a user touch through the touch electrode layer.

[0266] The light path control layer includes a structure in which a high-refractive index layer and a low-refractive index layer are alternately stacked, thereby changing the path of light incident from each pixel (P) and minimizing the color shift phenomenon according to the viewing angle.

[0267] A light-emitting display device or a first substrate (100) according to one embodiment of the present specification may further include a side sealing member (109).

[0268] A side sealing member (109) is formed between the first substrate (100) and the functional film (108) and can cover both sides of the circuit layer (101) and the wavelength conversion layer (107). For example, the side sealing member (109) can cover both sides of the circuit layer (101) and the wavelength conversion layer (107) that are exposed to the outside of the display device between the functional film (108) and the first substrate (100). Additionally, the side sealing member (109) can cover a portion of the routing portion (400) connected to the first pad portion (110) of the first substrate (100). This side sealing member (109) can serve to prevent side light leakage caused by light traveling toward the outer side within the wavelength conversion layer (107) among the light emitted from the self-emissive element (ED) of each subpixel (SP). In particular, the side sealing member (109) that overlaps with the first pad portion (110) of the first substrate (100) can serve to prevent or minimize the reflection of external light by the first pad (111) placed on the first pad portion (110).

[0269] Optionally, the side sealing member (109) may further include a getter material capable of adsorbing moisture and / or oxygen.

[0270] In a light-emitting display device according to one embodiment of the present specification, the first substrate (100) may further include a first chamfer (100c) formed in the corner portion between the first surface (100a) and the outer surface (OS). The first chamfer (100c) may serve to prevent the routing portion (400) from being severed along the corner portion of the first substrate (100) while minimizing damage to the corner portion of the first substrate (100) due to physical impact from the outside. For example, the first chamfer may have a 45-degree angle, but is not necessarily limited thereto. Such a first chamfer (100c) may be implemented by a cutting wheel, a grinding wheel, or a chamfering process using a laser. Accordingly, the outer surface of the pad electrodes (111) of the first pad portion (110) arranged to be in contact with the first chamfer (100c) may include an inclined surface inclined at an angle corresponding to the angle of the first chamfer (100c) by removing or grinding together with the corner portion of the first substrate (100) by a chamfering process. For example, when the first chamfer (100c) is formed at a 45-degree angle between the first surface (100a) and the outer surface (OS) of the first substrate (100), the outer surface (or one end) of the pad electrodes (111) of the first pad portion (110) may also be formed at a 45-degree angle.

[0271] Referring to FIGS. 7 to 10, a second substrate (200) according to one embodiment of the present specification may include a second pad portion (210), at least one third pad portion (230), and a link line portion (250) as described in FIG. 7, so a redundant description thereof is omitted or brief.

[0272] The link line section (250) may include a plurality of routing lines (410) disposed on each of the first outer surface (or one side) (OS1a) of the outer surface (OS) of the first substrate (100) and the first outer surface (or one side) (OS1b) of the outer surface (OS) of the second substrate (200).

[0273] Each of the plurality of routing lines (410) can be electrically connected one-to-one to the first pad section (110) and the second pad section (210). For example, each of the plurality of routing lines (410) can be electrically connected one-to-one to each of the auxiliary pads (113) of the first pad section (110) and each of the second pads (211) of the second pad section (210).

[0274] According to one embodiment, in each of the plurality of routing lines (410), one end covers the auxiliary pad (113) and the first chamfer (100c) of the first pad portion (110) disposed on the first edge portion of the first substrate (100), the other end covers the second pad (211) and the second chamfer (200c) of the second pad portion (210) disposed on the first edge portion of the second substrate (200), and the intermediate portion between the one end and the other end can cover the first outer surface (OS1a) of the first substrate (100) and the first outer surface (OS1b) of the second substrate (200), respectively. For example, one end of each of the plurality of routing lines (410) can be in direct contact with both the top surface and the side of the auxiliary pad (113), and the other end of each of the plurality of routing lines (410) can be in direct contact with both the rear surface and the side of the second pad (211). For example, in the data routing line (410), one end is implemented to wrap around the data auxiliary pad and the first chamfer (100c) of the first pad portion (110) placed at the first edge portion of the first substrate (100), and the other end is implemented to wrap around the second data pad and the second chamfer (200c) of the second pad portion (210) placed at the first edge portion of the second substrate (200), and the middle portion between the one end and the other end can be implemented to wrap around the first outer surface (OS1a) of the first substrate (100) and the first outer surface (OS1b) of the second substrate (200), respectively.

[0275] A second substrate (200) according to one embodiment may include a metal pattern layer disposed on the rear surface (200b) and an insulating layer insulating the metal pattern layer.

[0276] A metal pattern layer (or conductive pattern layer) may include a plurality of metal layers. A metal pattern layer according to one embodiment may include a first metal layer (201), a second metal layer (203), and a third metal layer (205). An insulating layer may include a plurality of insulating layers. For example, a rear insulating layer may include a first insulating layer (202), a second insulating layer (204), and a third insulating layer (206). An insulating layer may be described as a rear insulating layer or a pattern insulating layer.

[0277] The first metal layer (201) may be implemented on the back surface (200b) of the second substrate (200). The first metal layer (201) according to one embodiment may include a first metal pattern. For example, the first metal layer (201) may be represented as a first link layer or a link line layer.

[0278] According to one embodiment, the first metal pattern may be composed of a two-layer structure (Cu / MoTi) of copper (Cu) and molybdenum titanium alloy (MoTi). Since this first metal pattern can be used as link lines of the link line section (250), a redundant description thereof is omitted.

[0279] The first insulating layer (202) may be implemented on the back surface (200b) of the second substrate (200) to cover the first metal layer (201). According to one embodiment, the first insulating layer (202) may be made of an inorganic material.

[0280] The second metal layer (203) may be implemented on the first insulating layer (202). According to one embodiment, the second metal layer (203) may include a second metal pattern. For example, the second metal layer (203) may be represented as a second link layer, a jumping line layer, or a bridge line layer.

[0281] According to one embodiment, the second metal pattern may be composed of a two-layer structure (Cu / MoTi) of copper (Cu) and molybdenum titanium alloy (MoTi). This second metal pattern may be used as gate link lines among the link lines of the link line section (250), but is not necessarily limited thereto. For example, the second metal layer (203) may be used as a jumping line (or bridge line) to electrically connect link lines made of different layers or different metal materials in the link line section (250).

[0282] Optionally, the link lines (e.g., a plurality of first link lines) disposed in the second metal layer (203) may be disposed in the first metal layer (201), and the link lines (e.g., a plurality of second link lines) disposed in the first metal layer (201) may be changed to be disposed in the second metal layer (203).

[0283] The second insulating layer (204) may be implemented on the back surface (200b) of the second substrate (200) to cover the second metal layer (203). According to one embodiment, the second insulating layer (204) may be made of an inorganic material.

[0284] The third metal layer (205) may be implemented on the second insulating layer (204). According to one embodiment, the third metal layer (205) may include a third metal pattern. For example, the third metal layer (205) may be represented as a third link layer or a pad electrode layer.

[0285] According to one embodiment, the third metal pattern may be composed of at least two stacked structures of ITO (or IZO), molybdenum (Mo), titanium (Ti), and molybdenum titanium alloy (MoTi). For example, the third metal pattern may be composed of a three-layer structure of any one of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO, and IZO / MoTi / ITO. Such a third metal pattern may be used as pads of the second pad portion (210). For example, the pads of the second pad portion (210) composed of the third metal layer (205) may be electrically connected to the first metal layer (201) through pad contact holes formed in the first and second insulating layers (202, 204).

[0286] A third insulating layer (206) may be implemented on the rear surface (200b) of the second substrate (200) to cover the third metal layer (205). According to one embodiment, the third insulating layer (206) may be made of an organic material. For example, the third insulating layer (206) may be made of an insulating material such as photoacrylic. This third insulating layer (206) can prevent external exposure of the third metal layer (205) by covering the third metal layer (205). The third insulating layer (206) may also be described as an organic insulating layer, a protective layer, a rear protective layer, an organic protective layer, a rear coating layer, or a rear cover layer.

[0287] Each of the plurality of second pads disposed in the second pad portion (210) can be electrically connected to a link line of a link line portion (250) consisting of a first metal layer (201) or a second metal layer (203) disposed on the rear surface (200b) of the second substrate (200) through a second pad contact hole disposed in the first and second insulating layers (202, 204). For example, the second data pad can be electrically connected to one end of the data link line through the second pad contact hole disposed in the first and second insulating layers (202, 204).

[0288] A bonding member (300) according to one embodiment of the present specification is interposed between a first substrate (100) and a second substrate (200). The first substrate (100) and the second substrate (200) can be bonded to each other through the bonding member (300). The bonding member (300) according to one embodiment may be a transparent adhesive member comprising an optically clear adhesive (OCA) or an optically clear resin (OCR), or a double-sided tape. The bonding member (300) according to another example may include glass fibers.

[0289] A coupling member (300) according to one embodiment may be disposed in the entire space between the first substrate (100) and the second substrate (200). For example, the entire second surface (100b) of the first substrate (100) may be coupled to the entire one surface of the coupling member (300), and the entire front surface (200a) of the second substrate (200) may be coupled to the entire other surface of the coupling member (300).

[0290] According to another example, the coupling member (300) may be arranged in a pattern structure between the first substrate (100) and the second substrate (200). For example, the coupling member (300) may have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include a vent portion through which bubbles generated between the first substrate (100) and the second substrate (200) during the bonding of the first substrate (100) and the second substrate (200) can be discharged to the outside.

[0291] A routing unit (400) according to one embodiment of the present specification includes a plurality of routing lines (410) that electrically connect the first pads (111) of the first pad unit (110) and the second pads of the second pad unit (210) in a one-to-one manner. Since this is identical to the plurality of routing lines (410) described in FIG. 7, a redundant description thereof is omitted.

[0292] A light-emitting display device or routing unit (400) according to one embodiment of the present specification may further include an edge coating layer (430).

[0293] The edge coating layer (430) can be implemented to cover the routing portion (400). The edge coating layer (430) can be implemented to cover a plurality of routing lines (410). For example, the edge coating layer may be an edge protection layer or an edge insulation layer.

[0294] According to one embodiment, the edge coating layer (430) may be implemented to cover not only the plurality of routing lines (410) but also the entire first edge portion and first outer surface (OS1a) of the first substrate (100) and the first edge portion and first outer surface (OS1b) of the second substrate (200). The edge coating layer (430) can prevent corrosion of each of the plurality of routing lines (410) made of a metal material or electrical short circuits between the plurality of routing lines (410). In addition, the edge coating layer (430) can prevent or minimize reflection of external light by the plurality of routing lines (410) and the first pads (111) of the first pad portion (110). As an embodiment, the edge coating layer (430) may be made of a light-blocking material including black ink. As another example, since the edge coating layer (430) forms (or constitutes) the outermost side (or sidewall) of the display device (or display panel), it may include a shock-absorbing material (or material) or a soft material to prevent damage to the outer surface (OS) of the first and second substrates (100, 200) due to external impact. As yet another example, the edge coating layer (430) may include a mixture of a light-blocking material and a shock-absorbing material.

[0295] According to one embodiment, the edge coating layer (430) may be formed to surround one outer surface (OS) of each of the first and second substrates (100, 200) on which the routing portion (400) is disposed.

[0296] According to another embodiment, the edge coating layer (430) may be formed to surround not only one outer surface (OS) of each of the first and second substrates (100, 200) on which the routing portion (400) is disposed, as shown in FIG. 7, 9, and 11, but also all of the other outer surfaces (OS). For example, it may be formed to surround all outer surfaces (OS) of each of the first and second substrates (100, 200). In this case, one outer surface (OS) (or the first outer surface) of each of the first and second substrates (100, 200) may be surrounded by a plurality of routing lines (410) and the edge coating layer (430). The remaining outer surfaces (OS) (or the second to fourth outer surfaces) excluding one outer surface (OS) of each of the first and second substrates (100, 200) may be surrounded only by an edge coating layer (430). For example, the first outer surface of each of the first and second substrates (100, 200) may include a plurality of routing lines (410) and an edge coating layer (430), and the remaining second to fourth outer surfaces excluding the first outer surface of each of the first and second substrates (100, 200) may include only the edge coating layer (430).

[0297] According to one embodiment, when a plurality of routing lines (410) and an edge coating layer (430) disposed on a first outer surface are referred to as a first sidewall structure, and an edge coating layer (430) disposed on second to fourth outer surfaces is referred to as a second sidewall structure, the first sidewall structure and the second sidewall structure may have different thicknesses (or widths). For example, the thickness (or width) of the second sidewall structure may be thinner or narrower than the thickness (or width) of the first sidewall structure by the thickness of the plurality of routing lines (410).

[0298] FIG. 12 is an enlarged view of section 'C' shown in FIG. 8, FIG. 13 is an enlarged view of section 'D' shown in FIG. 10, and FIG. 14 is an enlarged view of section 'E' shown in FIG. 11, which is a drawing for explaining the first pad section, dam, element separation line, and groove line shown in FIG. 8.

[0299] Referring to FIG. 8 and FIG. 12, a first pad portion (110) according to one embodiment of the present specification may be disposed on one edge portion of a first substrate (100) or on the edge portion of an outermost pixel (Po) disposed on one edge portion of the first substrate (100).

[0300] The first pad portion (110) may include a plurality of first pads (111). Each of the plurality of first pads (111) according to one embodiment may include a pad electrode layer (111a) and a pad cover layer (111b).

[0301] The pad electrode layer (111a) may be disposed on an interlayer insulating layer (ILD) disposed on a pad area of ​​the first substrate (100). The pad electrode layer (111a) may have a length of 5 to 50 micrometers or less with respect to the longitudinal direction or the second direction (Y). This pad electrode layer (111a) may be electrically connected to a corresponding line among the pixel driving lines (DL, GL, PL, CVL, RL, GCL) through a pad electrode contact hole (PEH) penetrating the interlayer insulating layer (ILD) and the buffer layer (101a). For example, the pad electrode layer (111a) may be electrically connected to a first pixel driving power line (PL) through the pad electrode contact hole (PEH).

[0302] According to one embodiment, the pad electrode layer (111a) is made of the same material as the source / drain electrode of the TFT and can be formed together with the source / drain electrode of the TFT.

[0303] A pad electrode layer (111a) according to one embodiment may include a first pad metal layer (MLa) and a second pad metal layer (MLb) laminated on the first pad metal layer (MLa). For example, the first pad metal layer (MLa) may include at least one material selected from molybdenum (Mo), titanium (Ti), and molybdenum titanium alloy (MoTi). The second pad metal layer (MLb) may include at least one material selected from aluminum (Al), silver (Ag), and copper (Cu). For example, the pad electrode layer (111a) may include a two-layer structure of MoTi / Cu, but is not limited thereto.

[0304] The pad cover layer (111b) may be disposed on an interlayer insulating layer (ILD) to surround the pad electrode layer (111a). For example, the pad cover layer (111b) may function to prevent corrosion of the pad electrode layer (111a). The pad cover layer (111b) according to one embodiment may include a transparent conductive metal material. For example, the pad cover layer (111b) may be made of ITO material or IZO material, but is not limited thereto.

[0305] Each of the plurality of such first pads (111) can be covered by a passivation layer (PAS).

[0306] A first pad portion (110) according to one embodiment of the present specification may further include a plurality of auxiliary pads (113) electrically connected to each of a plurality of first pads (111).

[0307] Each of the plurality of auxiliary pads (113) is placed on a passivation layer (PAS) so as to overlap with each of the plurality of first pads (111), and can be individually connected to each of the plurality of first pads (111) through a pad contact hole (PCH) penetrating the passivation layer (PAS).

[0308] Each of the plurality of auxiliary pads (113) according to one embodiment is made of the same material as the pixel electrode (PE) and may be formed together with the pixel electrode (PE), but is not limited thereto. For example, each of the plurality of auxiliary pads (113) may be formed by a separate metal deposition process and a patterning process and may include a single-layer structure comprising at least one of molybdenum (Mo), titanium (Ti), molybdenum titanium alloy (MoTi), copper (Cu), and silver (Ag).

[0309] Each of the plurality of auxiliary pads (113) according to one embodiment may have a second length (or second width) that is relatively longer than the first length (or first width) of the corresponding first pad (111). Each of the plurality of auxiliary pads (113) may have a length of several tens of micrometers with respect to the length direction or the second direction (Y). For example, when each of the plurality of first pads (111) has a length of 5 to 50 micrometers or less with respect to the length direction or the second direction (Y), each of the plurality of auxiliary pads (113) may have a length of 50 to 150 micrometers. For example, each of the plurality of auxiliary pads (113) may have a length that is at least half as long as the corresponding first pad (111). Accordingly, each of the plurality of auxiliary pads (113) can have the function of extending the length of each of the plurality of first pads (111) to a length of tens of micrometers and / or increasing the contact area between the first pad (111) and the routing part (400).

[0310] Referring to FIGS. 8, 10, and 12, a dam (104) according to one embodiment of the present specification may be positioned or formed to have a closed-loop line shape in a third margin area (MA3) of a first substrate (100) or an outermost pixel (Po). Such a dam (104) may form or implement the other side of a groove line (105) by surrounding a groove line (105).

[0311] A dam (104) according to one embodiment may be placed on a buffer layer (101a) of a third margin region (MA3) of a first substrate (100) or an outermost pixel (Po). For example, the dam (104) may be formed or implemented by a patterning process of an interlayer insulating layer (ILD), a passivation layer (PAS), a planarization layer (103), a pixel electrode material layer, and a bank (BK) respectively placed on the buffer layer (101a). Such a dam (104) may serve to block the spreading or overflow of the second encapsulation layer (106b) (or organic encapsulation layer) of the encapsulation layer (106), and together with this, may serve to separate (or disconnect) some layers of the light-emitting element layer (EDL).

[0312] A dam (104) according to one embodiment of the present specification may include a first dam pattern (104a), a second dam pattern (104b), a third dam pattern (104c), and a fourth dam pattern (104d).

[0313] The first dam pattern (104a) can be implemented by an interlayer insulation layer (ILD) and a passivation layer (PAS). For example, the first dam pattern (104a) can be represented as a base trench structure or a multilayer trench structure, etc.

[0314] According to one embodiment, the first dam pattern (104a) may have a two-layer structure of an interlayer insulating layer (ILD) and a passivation layer (PAS). For example, the first dam pattern (104a) may be formed or realized by a portion (or non-patterned area) of the interlayer insulating layer (ILD) and the passivation layer (PAS) that remains intact on the buffer layer (101a) without being patterned (or removed) by the patterning process of the interlayer insulating layer (ILD) and the passivation layer (PAS) disposed on the buffer layer (101a) of the third margin region (MA3) of the first substrate (100). Accordingly, the first dam pattern (104a) may have the same height (or thickness) as the total height of the interlayer insulating layer (ILD) and the passivation layer (PAS) disposed on the buffer layer (101a).

[0315] According to one embodiment, the side of the first dam pattern (104a) may be implemented as a slanted structure or a regular taper structure. The bottom surface of the first dam pattern (104a) may be in direct contact with the top surface (or surface) of the buffer layer (101a), and the top surface of the first dam pattern (104a) may be positioned on the bottom surface of the first dam pattern (104a) and may have a width narrower than that of the bottom surface. The side of the first dam pattern (104a) may be formed at an angle between the top surface and the bottom surface. In the first dam pattern (104a), the angle between the bottom surface and the side may be acute, and the angle between the top surface and the side may be obtuse. For example, the cross-section of the first dam pattern (104a) cut along the width direction may have a trapezoidal cross-sectional structure in which the top side is narrower than the bottom side.

[0316] The second dam pattern (104b) can be placed on the first dam pattern (104a).

[0317] According to one embodiment, the second dam pattern (104b) may be made of an organic insulating material. For example, the second dam pattern (104b) may be made of the same material as the flattening layer (103). For example, the second dam pattern (104b) may have the same height (or thickness) as the flattening layer (103) or may have a higher height than the flattening layer (103). For example, the height (or thickness) of the second dam pattern (104b) may be twice the height (or thickness) of the flattening layer (103). Such a second dam pattern (104b) may be formed or realized by a part (or non-patterned area) of the flattening layer (103) that remains intact without being patterned (or removed) by the patterning process of the flattening layer (103).

[0318] According to one embodiment, the second dam pattern (104b) may have a width wider than the upper surface of the first dam pattern (104a). The second dam pattern (104b) may have a width equal to or wider than the lower surface of the first dam pattern (104a). The side of the second dam pattern (104b) may be implemented as a slanted structure or a regular taper structure. For example, the second dam pattern (104b) cut along the width direction may have a trapezoidal cross-sectional structure identical to that of the first dam pattern (104a). Based on the width direction, one edge portion and the other edge portion of the second dam pattern (104b) may each protrude outside the side of the first dam pattern (104a). For example, the distance between the side end of the second dam pattern (104b) and the side of the first dam pattern (104a) may be greater than the combined thickness of the self-luminescent element (ED) and the common electrode (CE).

[0319] According to one embodiment, the side of the first dam pattern (104a) may have an undercut structure with respect to the second dam pattern (104b). For example, the dam (104) may include an undercut region (UCA) located at the boundary between the first dam pattern (104a) and the second dam pattern (104b) or on the upper side of the first dam pattern (104a). The undercut region (UCA) between the first dam pattern (104a) and the second dam pattern (104b) may be a structure for separating (or disconnecting) each of the self-luminous element (ED) and the common electrode (CE) placed on the dam (104). For example, the undercut region (UCA) between the first dam pattern (104a) and the second dam pattern (104b) can be formed or realized by an over-etching process of the interlayer insulating layer (ILD) and the passivation layer (PAS), respectively. This second dam pattern (104b) can cover the side of the first dam pattern (104a) by protruding outward from the side of the first dam pattern (104a) due to the undercut structure of the first dam pattern (104a). By doing so, the second dam pattern (104b) can have an eaves structure with respect to the first dam pattern (104a).

[0320] The third dam pattern (104c) may be positioned to wrap around the second dam pattern (104b). For example, the third dam pattern (104c) may wrap around the upper surface and side of the second dam pattern (104b) by being positioned on the upper surface and side of the second dam pattern (104b).

[0321] The third dam pattern (104c) may include a metallic material. According to one embodiment, the third dam pattern (104c) may include a metallic layer having at least two layers identical to the pixel electrode (PE). For example, the third dam pattern (104c) may include a first metallic layer formed together with the first pixel electrode layer of the pixel electrode (PE) and in direct contact with the upper surface of the second dam pattern (104b), and a second metallic layer formed together with the second pixel electrode layer of the pixel electrode (PE) and formed (or laminated) on the first metallic layer. Such a third dam pattern (104c) may be formed or realized by a portion of the pixel electrode material (or a non-patterned area) that remains intact on the upper surface and side of the second dam pattern (104b) without being patterned (or removed) by the patterning process of the pixel electrode (PE).

[0322] The fourth dam pattern (104d) can be laminated on the third dam pattern (104c). The fourth dam pattern (104d) may have a width equal to or smaller than the top surface of the third dam pattern (104c). The sides of the fourth dam pattern (104d) may be implemented as a slanted structure or a regular taper structure. For example, the fourth dam pattern (104d) cut along the width direction may have a trapezoidal cross-sectional structure identical to that of the second dam pattern (104b).

[0323] According to one embodiment, the fourth dam pattern (104d) may include an organic insulating material or an inorganic insulating material. For example, the fourth dam pattern (104d) may be laminated on the upper surface of the third dam pattern (104c) with the same material as the bank (BK). This fourth dam pattern (104d) may be formed or realized by a part of the bank (BK) (or a non-patterned area) that remains on the third dam pattern (104c) without being patterned (or removed) by the patterning process of the bank (BK).

[0324] Referring to FIGS. 8, 10, and 12, a device isolation unit (102) according to one embodiment of the present specification may be arranged in a closed-loop line shape in a second margin area (MA2) of a first substrate (100) or an outermost pixel (Po) and may surround a dam (104). For example, the device isolation unit (102) may be arranged in a closed-loop line shape between an outer surface (OS) of the first substrate (100) and a dam (104). For example, the device isolation unit (102) arranged on one edge portion of the first substrate (100) may be arranged between a first pad portion (110) and a dam (104) and may overlap with at least a portion of the first pad portion (110). And, the element separation part (102) disposed on the remaining edge portion excluding one edge portion of the first substrate (100) can be disposed between the outer surface (OS) of the first substrate (100) and the dam (104).

[0325] A device separation unit (102) according to one embodiment may include a device separation line (102a) and an undercut structure (102b).

[0326] The device separation line (102a) may include a protruding tip (102t) protruding from the circuit layer (101) toward the dam (104).

[0327] A device isolation line (102a) according to one embodiment may be interposed between an interlayer insulating layer (ILD) and a passivation layer (PAS) of a circuit layer (101).

[0328] The device isolation line (102a) may be implemented as any one of the metal layers disposed in the circuit layer (101). The device isolation line (102a) according to one embodiment may include a transparent conductive metal material. For example, the device isolation line (102a) may be made of an ITO material or an IZO material, but is not limited thereto. This device isolation line (102a) may be made of the same material as the pad cover layer (111b) of the first pad portion (110) and may be formed together with the pad cover layer (111b). Accordingly, the device isolation line (102a) and the first pads (111) may be disposed together on the same layer.

[0329] The undercut structure (102b) can be formed by removing the interlayer insulating layer (ILD) placed below the device isolation line (102a). The undercut structure (102b) can be implemented by a structure in which the side of the interlayer insulating layer (ILD) placed below the device isolation line (102a) is inclined or has a regular taper structure. For example, the undercut structure (102b) can be primarily formed by a patterning process of the interlayer insulating layer (ILD) and the passivation layer (PAS) placed between the device isolation line (102a) and the dam (104). The undercut structure (102b) can be formed by further patterning the interlayer insulating layer (ILD) placed below the device isolation line (102a) by an over-etching process of the interlayer insulating layer (ILD) using the device isolation line (102a) as a mask. Accordingly, the protruding tip (102t) of the element separation line (102a) can have an eaves structure with respect to the undercut structure (102b).

[0330] According to one embodiment, the protruding tip (102t) of the device isolation line (102a) may be exposed on the buffer layer (101a) between the device isolation line (102a) and the dam (104) as the interlayer insulating layer (ILD) and the passivation layer (PAS) disposed between the device isolation line (102a) and the dam (104) are removed by the formation process of the first dam pattern (104a) of the dam (104). By doing so, the protruding tip (102t) of the device isolation line (102a) may protrude toward the dam (104) from the side (102c) and the undercut structure (102b) of the passivation layer (PAS) covering the device isolation line (102a), respectively. The protruding tip (102t) of the device separation line (102a) may be a structure for separating (or disconnecting) each of the self-luminous device (ED) and the common electrode (CE) placed on the device separation section (102).

[0331] According to one embodiment, a device separation line (102a) disposed on one edge portion of a first substrate (100) can be spaced apart from each of the first pads (111) of the first pad portion (110), as shown in FIG. 12, and can be electrically (or spatially) separated from each of the first pads (111). For example, if the device separation line (102a) and the first pads (111) are electrically connected, there is a problem that each of the first pads (111) is not electrically separated but is electrically connected to each other by the device separation line (102a) having a closed-loop line shape.

[0332] At least a portion of the device separation line (102a) disposed on one edge portion of the first substrate (100) may overlap with the auxiliary pads (113) of the first pad portion (110). For example, the device separation line (102a) may be disposed on the end of the auxiliary pads (113) and the dam (104) without overlapping with the auxiliary pads (113). In this case, as the distance between the dam (104) and the outer surface (OS) of the first substrate (100) increases, the second distance (D2) between the center of the outermost pixel (Po) and the outer surface (OS) of the first substrate (100) cannot be implemented as less than half of the first gap (or pixel pitch) (D1). Accordingly, at least a portion of the element separation line (102a) overlaps with the auxiliary pads (113) of the first pad portion (110), so that the second distance (D2) between the center of the outermost pixel (Po) and the outer surface (OS) of the first substrate (100) cannot be implemented as less than half of the first gap (or pixel pitch) (D1).

[0333] Additionally, the passivation layer (PAS) disposed between the device separation line (102a) and the auxiliary pads (113) may be formed with an undercut structure for the ends of the auxiliary pads (113). For example, the side (102c) of the passivation layer (PAS) disposed below the ends of the auxiliary pads (113) may be over-etched by the formation process of the first dam pattern (104a) of the dam (104) to have an undercut structure for the auxiliary pads (113). Accordingly, the device separation section (102) may include a lower undercut region formed by an undercut structure (102b) disposed below the device separation line (102a), and an upper undercut region formed by the undercut structure of the passivation layer (PAS) between the device separation line (102a) and the auxiliary pads (113). Each of the lower undercut region and the upper undercut region of the device separation section (102) may be a structure for separating (or disconnecting) the self-luminous element (ED) and the common electrode (CE) respectively placed on the device separation section (102).

[0334] According to one embodiment, a device separation line (102a) disposed on one edge portion of the first substrate (100) and disposed between the first pads (111) may include a protruding tip (102t) having an eaves structure for an undercut structure (102b), which is disposed between the outer surface (OS) of the first substrate (100) and the dam (104) as shown in FIG. 13, so as not to overlap with the first pads (111) and auxiliary pads (113).

[0335] According to one embodiment, the element separation line (102a) disposed on the remaining edge portion excluding one edge portion of the first substrate (100) may include a protruding tip (102t) having an eaves structure for the undercut structure (102b), which is disposed between the outer surface (OS) of the first substrate (100) and the dam (104) as shown in FIG. 14 and does not overlap with the first pads (111) and auxiliary pads (113).

[0336] Referring to FIGS. 8, FIGS. 10, and FIGS. 12 through 14, a groove line (105) according to one embodiment of the present specification may be arranged or formed to have a closed-loop line shape in a first margin area (MA1) of a first substrate (100) or an outermost pixel (Po).

[0337] According to one embodiment, the groove line (105) may correspond to an area where all structures on the spreading path of the encapsulation layer (106) spreading to the dam (104) have been removed. The groove line (105) may be an area where all single structures or multilayer structures, such as a passivation layer (PAS), a flattening layer (103), a pixel electrode material layer, and a bank (BK), which are disposed on the interlayer insulation layer (ILD) around the inner region of the dam (104), have been removed. For example, the groove line (105) may be formed or implemented by patterning (or removal) of the flattening layer (103) and the passivation layer (PAS) disposed on the first margin region (MA1) of the first substrate (100) or the outermost pixel (Po). Accordingly, the groove line (105) can define the side (103s) of the flattening layer (103) and have a closed loop line shape surrounding the side (103s) of the flattening layer (103).

[0338] According to one embodiment, the groove line (105) may expose the top surface (or surface) of the buffer layer (101a) as the interlayer insulating layer (ILD), passivation layer (PAS), and planarization layer (103) on the buffer layer (101a) are patterned (or removed). For example, the groove line (105) may include a primary groove line formed on the buffer layer (101a) by a patterning process of the interlayer insulating layer (ILD) to form source / drain contact holes of the TFT, and a secondary groove line formed on the buffer layer (101a) by a patterning process of the planarization layer (103) and passivation layer (PAS) to form electrode contact holes (ECH) of the TFT. The buffer layer (101a) can be exposed between the end (103e) of the flattening layer (103) and the dam (104) by the groove line (105) to form the bottom surface of the groove line (105). For example, the groove line (105) may have a width equal to or wider than the width of the dam (104).

[0339] One side of the groove line (105) can define the side (103s) of the flattening layer (103) and the side (PASs) of the passivation layer (PAS) and the side (ILDs) of the interlayer insulation layer (ILD) placed on the first substrate (100) or the display part (AA). For example, each of the side (103s) of the flattening layer (103), the side (PASs) of the passivation layer (PAS), and the side (ILDs) of the interlayer insulation layer (ILD) can be exposed to the groove line (105) to form one side wall of the groove line (105).

[0340] According to one embodiment, the side end (103e) of the flattening layer (103) may protrude from the side (PASs) of the passivation layer (PAS) toward the center of the groove line (105) (or the dam (104)). For example, the distance between the side end (103e) of the flattening layer (103) and the dam (104) may be smaller than the distance between the side (PASs) of the passivation layer (PAS) and the dam (104). The distance between the side end (103e) of the flattening layer (103) and the side (PASs) of the passivation layer (PAS) may be greater than the combined thickness of the self-luminescent element (ED) and the common electrode (CE). Accordingly, the edge portion of the flattening layer (103), including the side (103s) and side end (103e) of the flattening layer (103), covers the side (PASs) of the passivation layer (PAS) and the side (ILDs) of the interlayer insulation layer (ILD), respectively, and can face directly the upper surface of the buffer layer (101a). Thus, the edge portion of the flattening layer (103) can have an eaves structure with respect to the side (PASs) of the passivation layer (PAS).

[0341] According to one embodiment, the side (PASs) of the passivation layer (PAS) and the side (ILDs) of the interlayer insulation layer (ILD) can each be implemented with a slanted structure or a regular taper structure. Accordingly, the side (PASs) of the passivation layer (PAS) and the side (ILDs) of the interlayer insulation layer (ILD) can each have an undercut structure with respect to the edge portion of the flattening layer (103). For example, the boundary portion between the flattening layer (103) and the passivation layer (PAS) located on one side of the groove line (105), or the upper side portion of the passivation layer (PAS), can have an undercut structure with respect to the flattening layer (103). Due to this undercut structure, an undercut region (UCA) may be formed between the side (PASs) of the passivation layer (PAS) and the planarization layer (103), and the undercut region (UCA) may be a structure for separating (or disconnecting) the self-emissive element (ED) and the common electrode (CE) placed on the edge portion of the planarization layer (103) and the groove line (105). For example, the undercut region (UCA) may be formed or formed by an over-etching process of the passivation layer (PAS) and the interlayer insulating layer (ILD), respectively.

[0342] Each of the dam (104), the device separation part (102), and the groove line (105) according to one embodiment of the present specification may be formed or implemented after the bank (104) formation process and before the self-luminous device (ED) formation process, and may separate (or disconnect) the self-luminous device (ED) during the formation (or deposition) process of the self-luminous device (ED).

[0343] According to one embodiment, the material layer of the self-luminescent element (ED) disposed on the edge portion of the planarization layer (103) and the groove line (105) can be automatically separated (or severed) during the deposition process by an undercut area (UCA) (or eaves structure) between the side end (103e) of the planarization layer (103) and the side (PASs) of the passivation layer (PAS). For example, since the deposition material of the self-luminous element (ED) has straightness, it cannot be deposited on the side (PASs) of the passivation layer (PAS) which is covered by the side end (103e) of the planarization layer (103), but is deposited on the side (PASs) of the planarization layer (103) and the buffer layer (101a) on the groove line (105), thereby being separated (or severed) from the undercut region (UCA) between the side end (103e) of the planarization layer (103) and the side (PASs) of the passivation layer (PAS). Therefore, the self-luminous element (ED) can be automatically separated (or severed) from the groove line (105) during the deposition process.

[0344] According to one embodiment, a material layer of a self-luminous element (ED) placed on a dam (104) can be automatically separated (or severed) during the deposition process by an undercut region (UCA) (or eaves structure) between a first dam pattern (104a) and a second dam pattern (104b). For example, since the deposition material of the self-luminous element (ED) has a linearity, it cannot be deposited on the side of the first dam pattern (104a) which is obscured by the second dam pattern (104b), but can be separated (or severed) at the undercut region (UCA) between the first dam pattern (104a) and the second dam pattern (104b) by being deposited on the upper surface and side of the dam (105) and on the buffer layer (101a) around the dam (105). Thus, the self-luminous element (ED) can be automatically separated (or severed) from the dam (104) during the deposition process.

[0345] According to one embodiment, a material layer of a self-luminous element (ED) disposed on a device separation section (102) can be automatically separated (or severed) during the deposition process by a protruding tip (102t) of a device separation line (102a). For example, since the deposition material of the self-luminous element (ED) has straightness, it cannot be deposited on the side of the undercut structure (102b) that is covered by the protruding tip (102t) of the device separation line (102a), and can be separated (or severed) in the undercut area between the protruding tip (102t) of the device separation line (102a) and the undercut structure (102b) by being deposited on the upper surface and side of the protruding tip (102t) of the device separation line (102a) and the buffer layer (101a) below the protruding tip (102t) of the device separation line (102a). Accordingly, the self-luminous element (ED) can be automatically separated (or disconnected) from the protruding tip (102t) of the element separation line (102a) of the element separation section (102) during the deposition process.

[0346] According to one embodiment, a self-emissive element (ED) disposed at the edge portion of the first substrate (100) or the outermost pixel (Po) may be separated (or disconnected) at least three times by each of the element separation portion (102), the dam (104), and the groove line (105), and the separated self-emissive element (EDi) may be formed in an island shape on the upper surface (or surface) of the buffer layer (101a) on the groove line (105) and may be formed in an island shape on the upper surface (or surface) of the buffer layer (101a) between the dam (104) and the element separation portion (102).

[0347] According to one embodiment, a self-luminous element (ED) placed at the edge portion of the first substrate (100) or the outermost pixel (Po) is automatically separated (or cut off) by each of the element separation portion (102), the dam (104), and the groove line (105) during the deposition process, and as a result, a separate patterning process for separating (or cutting off) the self-luminous element (ED) placed at the edge portion of the first substrate (100) to prevent lateral moisture penetration may be omitted.

[0348] According to one embodiment, the lateral moisture penetration path of the first substrate (100) can be blocked by the undercut area of ​​each of the element separation part (102), the dam (104), and the groove line (105). In particular, as the self-luminous element (ED) placed at the edge portion of the first substrate (100) or the outermost pixel (Po) is separated by the element separation part (102), the distance between the dam (104) and the outer surface (OS) of the first substrate (100) can be reduced to the maximum extent, and thereby the light-emitting display device according to the present specification can have an air bezel structure having a bezel area that is either non-existent or zeroed out, while preventing the deterioration of the reliability of the self-luminous element (ED) due to lateral moisture penetration.

[0349] According to one embodiment, a common electrode (CE) disposed on a self-luminous element (ED) can be separated by an undercut area of ​​each of the element separation part (102), the dam (104), and the groove line (105), just like the self-luminous element (ED). At this time, since the electrode material of the common electrode (CE) has weaker linearity than the material layer of the self-luminous element (ED), it can penetrate toward the undercut area of ​​each of the element separation part (102), the dam (104), and the groove line (105), thereby covering the end (or separation surface) of the self-luminous element (ED) separated by the undercut area of ​​each of the element separation part (102), the dam (104), and the groove line (105). For example, the electrode material of the common electrode (CE) can penetrate into the undercut region (UCA) between the side end (103e) of the planarization layer (103) and the side (PASs) of the passivation layer (PAS), and can also be deposited on the lower surface of the side end (103e) of the planarization layer (103) to cover the end (or separation surface) of the separated self-luminous element (ED). Additionally, the electrode material of the common electrode (CE) placed on the dam (104) can penetrate into the undercut region (UCA) between the first dam pattern (104a) and the second dam pattern (104b), and can also be deposited on the lower surface of the second dam pattern (104b) to cover the end (or separation surface) of the separated self-luminous element (ED). And, the electrode material of the common electrode (CE) placed on the device separation section (102) can penetrate into the undercut area between the protruding tip (102t) of the device separation line (102a) and the undercut structure (102b) and be deposited on the lower surface of the protruding tip (102t) of the device separation line (102a), thereby covering the end (or separation surface) of the separated self-luminous device (ED).

[0350] According to one embodiment, the separation pattern (CEi) of a common electrode (CE) separated into an island shape by each of the element separation part (102), the dam (104), and the groove line (105) may come into direct contact with the uppermost surface (or surface) of the buffer layer (101a) to surround the separation pattern (EDi) of a self-luminous element (ED) separated into an island shape by each of the element separation part (102), the dam (104), and the groove line (105). For example, the separation pattern (CEi) of the common electrode (CE) can seal the boundary between each separation pattern (EDi) of the self-luminous element (ED) and the buffer layer (101a) by directly contacting the uppermost surface (or surface) of the buffer layer (101a) at each of the device separation part (102) and the dam (104) and the groove line (105), thereby preventing or blocking lateral moisture penetration through the boundary between the separation pattern (EDi) of the self-luminous element (ED) and the buffer layer (101a).

[0351] According to one embodiment, the light-emitting element layer (EDL), the element isolation portion (102), the dam (104), and the groove line (105) may be surrounded by the first encapsulation layer (106a) of the encapsulation layer (106). For example, the first encapsulation layer (106a) may be deposited with a uniform thickness over the entire first substrate (100) excluding the first pad portion (110) of the first substrate (100), thereby covering the light-emitting element layer (EDL) placed on the planarization layer (103) and covering the separation pattern (CEi) of the common electrode (CE) placed on the element isolation portion (102), the dam (104), and the groove line (105), respectively. In particular, the first encapsulation layer (106a) can penetrate deeply into the undercut area of ​​each of the device separation part (102), the dam (104), and the groove line (105) and surround the undercut area of ​​each of the device separation part (102), the dam (104), and the groove line (105).

[0352] According to one embodiment, a second encapsulation layer (106b) (or organic encapsulation layer) disposed on a first encapsulation layer (106a) may be disposed in an encapsulation area on a display portion (AA) defined by a dam (104). The second encapsulation layer (106b) may spread toward a groove line (105) surrounding the side (103s) of the flattening layer (103) and may completely surround the light-emitting element layer (EDL) disposed on the upper surface and side of the flattening layer (103). The spreading of the second encapsulation layer (106b) may proceed smoothly through the groove line (105) to the dam (104), thereby allowing the second encapsulation layer (106b) to completely fill up to an area adjacent to the inside of the dam (104). Additionally, the spreading of the second encapsulation layer (106b) can be finally blocked by the second to fourth dam patterns (104b, 104c, 104d) of the dam (104), thereby allowing the dam (104) to block or prevent the overflow of the second encapsulation layer (106b). Accordingly, the dam (104) according to one embodiment of the present specification may include a function of physically separating the light-emitting element layer, a function of blocking the spreading or overflow of the organic encapsulation layer (106b), and a function of preventing moisture penetration from the lateral direction of the first substrate (100).

[0353] According to one embodiment, a third bag layer (106c) disposed on the second bag layer (106b) may be implemented to surround both the second bag layer (106b) disposed inside the dam (104) and the first bag layer (106a) disposed outside the dam (104).

[0354] According to one embodiment, at least a portion of the auxiliary pads (113) disposed on the first pad portion (110) may be exposed on the first substrate (100). For example, at least a portion of the auxiliary pads (113) may be realized by a pad opening process performed after the formation process of the third encapsulation layer (106c). By this, the auxiliary pads (113) exposed on the first substrate (100) may be electrically connected to the routing line (410) of the routing portion (400).

[0355] According to one embodiment, the edge portions of each of the self-emissive element (ED), common electrode (CE), first encapsulation layer (106a), and second encapsulation layer (106c) disposed on the element separation portion (102) can be removed by a pad opening process. Accordingly, the encapsulation layer (106) can be disposed on the remaining part of the first substrate (100), excluding the area between the outer surface (OS) of the first substrate (100) and the element separation portion (102), to cover the light-emitting element layer (EDL) and the dam (104).

[0356] For example, the edge portions of each of the self-luminescent element (ED), common electrode (CE), first encapsulation layer (106a), and second encapsulation layer (106c) placed on the device separation section (102) can be removed by a pad opening process. At this time, the end (106ae) of the first encapsulation layer (106a) can be placed below the protruding tip (102t) of the device separation line (102) and can be in direct contact with the buffer layer (101a). And, the separation pattern (CEi) of the common electrode (CE) directly deposited on the lower surface of the protruding tip (103t) of the device separation line (102) is not removed by the pad opening process and remains in a state deposited on the lower surface of the protruding tip (102t) of the device separation line (102), and can be spaced apart from the separation pattern (CEi) of the common electrode (CE) placed below the protruding tip (102t) of the device separation line (102). Accordingly, the separation pattern (CEi) of each self-emissive element (ED) and common electrode (CE), which are separated by the element separation unit (102) and arranged in an island shape on the buffer layer (101a) below the element separation unit (102), can be maintained in a state surrounded by the first encapsulation layer (106a). Additionally, the end (106e) of the third encapsulation layer (106c) placed in the element separation unit (102) can be maintained in a state of physical contact with the first encapsulation layer (106a) placed in the element separation unit (102).

[0357] In a light-emitting display device according to one embodiment of the present specification, a dam (104) disposed at the edge portion of a first substrate (100) (or outermost pixel) can prevent a decrease in the reliability of the self-luminous element (ED) due to lateral moisture penetration by having a separation function of the self-luminous element (ED), a function to block spreading or overflow of the organic encapsulation layer, and a function to prevent moisture penetration. In addition, in a light-emitting display device according to one embodiment of the present specification, as the self-luminous element (ED) disposed at the edge portion of the first substrate (100) or outermost pixel (Po) is separated by an element separation part (102), the distance between the dam (104) and the outer surface (OS) of the first substrate (100) can be reduced, and as the element separation part (102) and the dam (104) are disposed at the edge portion of the outermost pixels, the decrease in the reliability of the self-luminous element (ED) due to lateral moisture penetration can be prevented, and the device can have an air bezel structure having a bezel area that is either non-existent or zeroed out. In addition, the light-emitting display device according to one embodiment of the present specification allows the spreading of the second sealing layer (106b) to proceed smoothly to the dam (104) through a groove line (GEV) disposed between the end of the flattening layer (103) and the dam (104), thereby preventing or minimizing the phenomenon of incomplete filling of the second sealing layer (106b) occurring in an area adjacent to the inside of the dam (104).

[0358] FIG. 15 is another cross-sectional view of line I-I' shown in FIG. 7, and FIG. 16 is an enlarged view of section 'F' shown in FIG. 15, which is a modified version of the dam structure described in FIG. 7 to FIG. 14. Accordingly, in the following description, redundant descriptions of components other than the dam and related components are omitted or brief.

[0359] Referring to FIGS. 7, 15, and 16, a dam (104) according to another embodiment of the present specification may include a first dam pattern (104a), a second dam pattern (104b), a third dam pattern (104c), and a fourth dam pattern (104d).

[0360] The first dam pattern (104a) is implemented by an interlayer insulation layer (ILD) and a passivation layer (PAS), which is the same as described above, so a redundant description thereof is omitted.

[0361] The second dam pattern (104b) is placed on the first dam pattern (104a), and since this is the same as previously described, a redundant description thereof is omitted.

[0362] The third dam pattern (104c) may be placed on the second dam pattern (104b) so as to be electrically connected to at least one pixel common voltage line (CVL).

[0363] The third dam pattern (104c) may include a metallic material. According to one embodiment, the third dam pattern (104c) may include a metallic layer having at least two layers, identical to the pixel electrode (PE). This third dam pattern (104c) may wrap around the upper and side surfaces of the second dam pattern (104b) and may be electrically connected to at least one pixel common voltage line (CVL) through via holes (VH) formed in the second dam pattern (104b), the first dam pattern (104a), and the buffer layer (101a). For example, the via holes (VH) may be formed to sequentially penetrate the second dam pattern (104b), the first dam pattern (104a), and the buffer layer (101a), which are positioned at the intersection of the third dam pattern (104c), which has a closed-loop line shape, and the pixel common voltage line (CVL). Accordingly, the third dam pattern (104c) can be electrically connected to at least one pixel common voltage line (CVL) through a via hole (VH). Thus, the third dam pattern (104c) forms an equipotential with each of the plurality of pixel common voltage lines (CVL) and can prevent defects caused by static electricity by primarily blocking static electricity flowing from the outside into the inside of the display unit (AA). For example, the third dam pattern (104c) can prevent defects caused by static electricity by discharging static electricity flowing from the outside into the pixel common voltage line (CVL).

[0364] The fourth dam pattern (104d) can be laminated on the third dam pattern (104c). The fourth dam pattern (104d) may have a width equal to or smaller than the top surface of the third dam pattern (104c). The sides of the fourth dam pattern (104d) may be implemented as a slanted structure or a regular taper structure. For example, the fourth dam pattern (104d) cut along the width direction may have a trapezoidal cross-sectional structure identical to that of the second dam pattern (104b).

[0365] According to one embodiment, the fourth dam pattern (104d) may include an organic insulating material or an inorganic insulating material. For example, the fourth dam pattern (104d) may be laminated on the upper surface of the third dam pattern (104c) with the same material as the bank (BK). This fourth dam pattern (104d) may be formed or realized by a part of the bank (BK) (or a non-patterned area) that remains on the third dam pattern (104c) without being patterned (or removed) by the patterning process of the bank (BK).

[0366] A light-emitting display device including a dam (104) according to another embodiment of the present specification, such as this, has the same effect as the light-emitting display device shown in FIGS. 7 to 14, and a third dam pattern (104c) of the dam (104) having a closed-loop line shape is electrically connected to pixel common voltage lines (CVL), thereby preventing or minimizing defects caused by static electricity introduced from the outside.

[0367] FIG. 17 is a drawing showing a multi-screen display device according to one embodiment of the present specification, and FIG. 18 is a cross-sectional view along line IV-IV' shown in FIG. 17, which shows a multi-screen display device implemented by tiling the light-emitting display devices according to the embodiments of the present specification shown in FIG. 1 to FIG. 16.

[0368] Referring to FIGS. 17 and 18, a multi-screen display device (or tiling light-emitting display device) according to one embodiment of the present specification may include a plurality of display modules (DM1, DM2, DM3, DM4).

[0369] Each of the plurality of display modules (DM1, DM2, DM3, DM4) can display individual images or divide and display a single image. Each of these plurality of display modules (DM1, DM2, DM3, DM4) includes a light-emitting display device according to the embodiment of the present specification shown in FIGS. 1 to 16, and a redundant description thereof may be omitted.

[0370] Each of the multiple display modules (DM1, DM2, DM3, DM4) can be tiled on a separate tiling frame so that their sides are in contact with each other. For example, each of the multiple display modules (DM1, DM2, DM3, DM4) can be tiled to have an N×M shape to implement a large-screen multi-screen display device. For example, N can be a positive integer greater than or equal to 1, and M can be a positive integer greater than or equal to 2. For example, N can be a positive integer greater than or equal to 2, and M can be a positive integer greater than or equal to 1.

[0371] Each of the plurality of display modules (DM1, DM2, DM3, DM4) does not include a bezel area (or non-display area) surrounding the entire display portion (AA) where an image is displayed, and has an air-bezel structure in which the display portion (AA) is surrounded by air. That is, for each of the plurality of display modules (DM1, DM2, DM3, DM4), the entire first surface of the first substrate (100) can be implemented as the display portion (AA).

[0372] According to the present example, in each of the plurality of display modules (DM1, DM2, DM3, DM4), the second gap (D2) between the center (CP) of the outermost pixel (Po) and the outermost outer surface (VL) of the first substrate (100) is implemented to be less than half of the first gap (D1) (or pixel pitch) between adjacent pixels. Accordingly, in two adjacent display modules (DM1, DM2, DM3, DM4) that are connected (or in contact) side by side along the first direction (X) and the second direction (Y) according to the side coupling method, the gap (D2+D2) between adjacent outermost pixels (Po) becomes equal to or smaller than the first gap (D1) between two adjacent pixels. For example, in FIG. 18, in a first display module (DM1) and a third display module (DM3) that are connected (or in contact) side by side along a second direction (Y), the gap (D2+D2) between the center (CP) of the outermost pixel (Po) of the first display module (DM1) and the center (CP) of the outermost pixel (Po) of the third display module (DM3) may be equal to or smaller than the first gap (D1) (or pixel pitch) between two adjacent pixels placed in each of the first display module (DM1) and the third display module (DM3).

[0373] Accordingly, since the gap (D2+D2) between the center (CP) of the outermost pixel (Po) of each of two adjacent display modules (DM1, DM2, DM3, DM4) that are connected (or in contact) side by side along the first direction (X) and the second direction (Y) is equal to or smaller than the first gap (D1) between two adjacent pixels placed in each display module (DM1, DM2, DM3, DM4), there is no boundary or seam between two adjacent display modules (DM1, DM2, DM3, DM4), and as a result, there is no dark area caused by the boundary provided between multiple display modules (DM1, DM2, DM3, DM4). Consequently, an image displayed on a multi-screen display device in which each of the multiple display modules (DM1, DM2, DM3, DM4) is tiled in an N×M shape can be displayed continuously without a sense of discontinuity (or break) at the boundary between the multiple display modules (DM1, DM2, DM3, DM4).

[0374] FIGS. 17 and 18 show a plurality of display modules (DM1, DM2, DM3, DM4) tiled in a 2×2 shape, but are not limited thereto, and the plurality of display modules (DM1, DM2, DM3, DM4) may be tiled in an x×1 shape, a 1×y shape, or an x×y shape. Here, x and y may be two or more natural numbers that are equal to or different from each other.

[0375] The multi-screen display device according to the present specification can display a single image on a single screen using a display portion (AA) of each of the plurality of display modules (DM1, DM2, DM3, DM4), and can display a continuously connected image without being interrupted at the boundary portion between the plurality of display modules (DM1, DM2, DM3, DM4), thereby improving the immersion of the viewer watching the image displayed on the multi-screen display device.

[0376] A light-emitting display device according to the present specification may be described as follows.

[0377] A light-emitting display device according to some embodiments of the present specification comprises a substrate having a display portion, a circuit layer disposed on the display portion, a flattening layer disposed on the circuit layer, a dam disposed on the circuit layer along an edge portion of the substrate, a device separation portion including a device separation line disposed on the circuit layer and surrounding the dam, and a light-emitting element layer having a self-luminous element disposed on the flattening layer, the dam, and the device separation portion, wherein the device separation line has a protruding tip protruding from the circuit layer toward the dam, and the self-luminous element can be separated from the device separation portion by the protruding tip of the device separation line.

[0378] According to some embodiments of the present specification, the circuit layer comprises a buffer layer disposed on a substrate, an interlayer insulating layer disposed on the buffer layer, and a passivation layer disposed on the interlayer insulating layer, and a device isolation line disposed between the interlayer insulating layer and the passivation layer, and the protruding tip of the device isolation line may protrude from the side of the interlayer insulating layer toward the dam.

[0379] According to some embodiments of the present specification, the circuit layer includes an insulating layer disposed between a substrate and a device isolation line, the device isolation section further includes an undercut structure formed in the insulating layer below the device isolation line, and the protruding tip of the device isolation line may have an eaves structure with respect to the undercut structure.

[0380] According to some embodiments of the present specification, the device isolation line may be made of a transparent conductive metal material.

[0381] A light-emitting display device according to some embodiments of the present specification further includes a pad portion disposed at one edge portion of a substrate, the pad portion includes a pad disposed on the same layer as a device isolation line, and the device isolation line disposed at one edge portion of the substrate may be spaced apart from the pad and electrically isolated.

[0382] According to some embodiments of the present specification, the circuit layer comprises a buffer layer disposed on a substrate, an interlayer insulating layer disposed on the buffer layer, and a passivation layer disposed on the interlayer insulating layer, and the pad comprises a pad electrode layer disposed on the interlayer insulating layer and a pad cover layer surrounding the pad electrode layer, and each of the pad cover layer and the device isolation line may be made of a transparent conductive metal material.

[0383] According to some embodiments of the present specification, the pad portion further includes an auxiliary pad disposed on a circuit layer and electrically connected to the pad, and at least a portion of a device isolation line disposed on one edge portion of the substrate may overlap with the auxiliary pad.

[0384] According to some embodiments of the present specification, the self-luminous element may be further separated by a dam.

[0385] According to some embodiments of the present specification, the dam comprises a first dam pattern implemented in a circuit layer, a second dam pattern disposed on the first dam pattern, a third dam pattern disposed on the second dam pattern, a fourth dam pattern disposed on the third dam pattern, and an undercut region formed between the first dam pattern and the second dam pattern, and a self-luminous element disposed on the dam may be separated by the undercut region.

[0386] According to some embodiments of the present specification, the first dam pattern is made of an inorganic insulating material, the second dam pattern is made of an organic insulating material, the third dam pattern is made of a metallic material, and the third dam pattern may be made of an organic insulating material or an inorganic insulating material.

[0387] A light-emitting display device according to some embodiments of the present specification further includes a pixel common voltage line disposed in a display portion, and the light-emitting element layer further includes a common electrode disposed on a self-luminous element and electrically connected to the pixel common voltage line, and the third dam pattern is made of a metallic material and can be electrically connected to the pixel common voltage line through a second dam pattern, a first dam pattern and via holes formed in a circuit layer.

[0388] A light-emitting display device according to some embodiments of the present specification further includes a groove line disposed between the side of a flattening layer and a dam and surrounded by the dam, and an undercut region between the side of the flattening layer and a circuit layer, and the self-luminous element may be further separated in the undercut region.

[0389] According to some embodiments of the present specification, the circuit layer comprises a buffer layer disposed on a substrate, an interlayer insulating layer disposed on the buffer layer, and a passivation layer disposed on the interlayer insulating layer, and the groove line is formed by removing the interlayer insulating layer, the passivation layer, and the planarization layer disposed on the buffer layer, and the upper surface of the buffer layer may be the bottom surface of the groove line.

[0390] A light-emitting display device according to some embodiments of the present specification may further include a light-emitting element layer disposed on the remaining portion of the first substrate excluding the area between the outer surface of the first substrate and the element separation portion, and an encapsulation layer covering the dam.

[0391] According to some embodiments of the present specification, the light-emitting display device may include an encapsulation layer comprising a first encapsulation layer covering a dam and a light-emitting element layer disposed on the first substrate excluding the area between the outer surface of the first substrate and the element separation portion, a second encapsulation layer disposed on the first encapsulation layer in an encapsulation region defined by the dam, and a third encapsulation layer covering the first encapsulation layer disposed on the outer side of the second encapsulation layer and the dam.

[0392] According to some embodiments of the present specification, the end of the first encapsulation layer may be positioned below the protruding tip of the device isolation line.

[0393] A light-emitting display device according to some embodiments of the present specification may further include a wiring board comprising a first pad portion having a plurality of first pads disposed on one edge portion of a substrate, a second pad portion having a plurality of second pads that overlap each of the plurality of first pads, a coupling member interposed between the substrate and the wiring board, and a routing portion having a plurality of routing lines disposed on one side of each of the substrate and the wiring board and connecting the plurality of first pads and the plurality of second pads in a one-to-one manner.

[0394] According to some embodiments of the present specification, the display unit includes a plurality of pixels arranged along a first direction and a second direction crossing the first direction on a substrate, and the distance between the center of the outermost pixels among the plurality of pixels and the outer surface of the substrate is less than or equal to half of the pixel pitch, and the pixel pitch may be the distance between the centers of two adjacent pixels.

[0395] A multi-screen display device according to some embodiments of the present specification comprises a plurality of display modules arranged along at least one of a first direction and a second direction crossing the first direction, each of the plurality of display modules comprising a light-emitting display device, the light-emitting display device comprising a substrate having a display portion, a circuit layer disposed on the display portion, a flattening layer disposed on the circuit layer, a dam disposed on the circuit layer along an edge portion of the substrate, a device separation portion comprising a device separation line disposed on the circuit layer and surrounding the dam, and a light-emitting element layer having a self-luminous element disposed on the flattening layer, the dam, and the device separation portion, wherein the device separation line has a protruding tip protruding from the circuit layer toward the dam, and the self-luminous element can be separated from the device separation portion by the protruding tip of the device separation line.

[0396] According to some embodiments of the present specification, in a light-emitting display device for each of a plurality of display modules, the display unit comprises a plurality of pixels arranged along a first direction and a second direction crossing the first direction on a substrate, and in a first display module and a second display module adjacent along the first direction and the second direction, the distance between the center of the outermost pixel of the first display module and the center of the outermost pixel of the second display module is equal to or smaller than the pixel pitch, and the pixel pitch may be the distance between the centers of two adjacent pixels.

[0397] A light-emitting display device according to the examples of the present specification may be applied to any electronic device including a display panel. For example, a light-emitting display device according to the present specification may be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic notebooks, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, in-vehicle navigation systems, in-vehicle display devices, televisions, wallpaper display devices, signage devices, game devices, laptops, monitors, cameras, camcorders, and home appliances, etc.

[0398] Features, structures, effects, etc. described in the various examples of this specification described above are included in at least one example of this specification and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. exemplified in at least one example of this specification may be combined or modified and implemented in other examples by a person with ordinary knowledge in the field to which the technical concept of this specification belongs. Accordingly, contents related to such combinations and modifications should be interpreted as being included within the technical scope or scope of rights of this specification.

[0399] It will be obvious to those skilled in the art to which this specification belongs that the above-described specification is not limited to the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of this specification. Therefore, the scope of this specification is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of this specification. Explanation of the symbols

[0400] 10: Light-emitting display device 100: First substrate 101: Circuit layer 102: Component isolation section 102a: Component isolation line 102b: Undercut structure 102t: Extrusion tip 103: Flattening layer 104: Dam 104a: 1st Dam Pattern 104b: 2nd Dam Pattern 104c: 3rd Dam Pattern 104d: 4th Dam Pattern 105: Groove Line 106: Bag layer 106a: First bag layer 106b: Second bag layer 106c: Third bag layer 110: 1st pad section 150: Gate driving circuit 200: Second substrate 300: Connecting member 400: Routing section 500: Driving circuit section

Claims

Claim 1 A light-emitting display device comprising: a substrate having a display portion; a circuit layer disposed on the display portion; a flattening layer disposed on the circuit layer; a dam disposed on the circuit layer along an edge portion of the substrate; a device isolation portion disposed on the circuit layer and surrounding the dam; and a light-emitting element layer having a self-luminous element disposed on the flattening layer, the dam, and the circuit layer, wherein the device isolation portion is disposed on the circuit layer to surround the dam and includes a device isolation line having a protruding tip for severing at least one portion of the light-emitting element layer, wherein the protruding tip protrudes toward the dam, and a separation pattern of the light-emitting element layer severed by the protruding tip is disposed below the protruding tip. Claim 2 A light-emitting display device according to claim 1, wherein the circuit layer comprises a buffer layer disposed on the substrate; an interlayer insulating layer disposed on the buffer layer; and a passivation layer disposed on the interlayer insulating layer, wherein the device isolation line is disposed between the interlayer insulating layer and the passivation layer, and the protruding tip of the device isolation line protrudes from the side of the interlayer insulating layer toward the dam. Claim 3 A light-emitting display device according to claim 1, wherein the circuit layer comprises an insulating layer disposed between the substrate and the element separation line, the element separation portion further comprises an undercut structure formed in the insulating layer below the element separation line, and the protruding tip of the element separation line has an eaves structure with respect to the undercut structure. Claim 4 In claim 1, the element separation line is made of a transparent conductive metal material, forming a light-emitting display device. Claim 5 A light-emitting display device according to claim 1, further comprising a pad portion disposed on one edge portion of the substrate, wherein the pad portion comprises a pad disposed on the same layer as the element isolation line, and the element isolation line disposed on one edge portion of the substrate is spaced apart from the pad and electrically isolated. Claim 6 In claim 5, the circuit layer comprises a buffer layer disposed on the substrate; an interlayer insulating layer disposed on the buffer layer; and a passivation layer disposed on the interlayer insulating layer, and the pad comprises a pad electrode layer disposed on the interlayer insulating layer; and a pad cover layer surrounding the pad electrode layer, wherein the pad cover layer and the element isolation line are each made of a transparent conductive metal material, a light-emitting display device. Claim 7 In claim 5, the pad portion further comprises an auxiliary pad disposed on the circuit layer and electrically connected to the pad, and at least a portion of the element isolation line disposed on one edge portion of the substrate overlaps with the auxiliary pad, a light-emitting display device. Claim 8 In claim 1, the self-luminous element is a light-emitting display device further disconnected by the dam. Claim 9 In claim 8, the dam comprises: a first dam pattern implemented in the circuit layer; a second dam pattern disposed on the first dam pattern; a third dam pattern disposed on the second dam pattern; a fourth dam pattern disposed on the third dam pattern; and an undercut region formed between the first dam pattern and the second dam pattern, wherein the self-luminous element disposed on the dam is separated by the undercut region, a light-emitting display device. Claim 10 A light-emitting display device according to claim 9, wherein the first dam pattern is made of an inorganic insulating material, the second dam pattern is made of an organic insulating material, the third dam pattern is made of a metallic material, and the third dam pattern is made of an organic insulating material or an inorganic insulating material. Claim 11 A light-emitting display device according to claim 9, further comprising a pixel common voltage line disposed in the display portion, wherein the light-emitting element layer further comprises a common electrode disposed on the self-luminous element and electrically connected to the pixel common voltage line, and wherein the third dam pattern is made of a metallic material and is electrically connected to the pixel common voltage line through the second dam pattern, the first dam pattern and via holes formed in the circuit layer. Claim 12 A light-emitting display device according to claim 1, further comprising: a groove line disposed between the side of the flattening layer and the dam and surrounded by the dam; and an undercut region between the side of the flattening layer and the circuit layer, wherein the self-luminous element is further disconnected in the undercut region. Claim 13 A light-emitting display device according to claim 12, wherein the circuit layer comprises a buffer layer disposed on the substrate; an interlayer insulating layer disposed on the buffer layer; and a passivation layer disposed on the interlayer insulating layer, wherein the groove line is formed by removing the interlayer insulating layer disposed on the buffer layer, the passivation layer, and the planarization layer, and the upper surface of the buffer layer is the bottom surface of the groove line. Claim 14 A light-emitting display device according to claim 1, further comprising the light-emitting element layer disposed on the remaining substrate excluding the space between the outer surface of the substrate and the element separation portion, and the encapsulation layer covering the dam. Claim 15 A light-emitting display device according to claim 14, wherein the encapsulation layer comprises: a first encapsulation layer covering the light-emitting element layer and the dam disposed on the remaining substrate excluding the area between the outer surface of the substrate and the element isolation portion; a second encapsulation layer disposed on the first encapsulation layer in an encapsulation region defined by the dam; and a third encapsulation layer covering the first encapsulation layer disposed on the outer side of the second encapsulation layer and the dam. Claim 16 In claim 15, the end of the first encapsulation layer is positioned below the protruding tip of the element separation line, a light-emitting display device. Claim 17 A light-emitting display device according to claim 1, further comprising: a first pad portion having a plurality of first pads disposed on one edge portion of the substrate; a second pad portion having a plurality of second pads overlapping with each of the plurality of first pads; a coupling member interposed between the substrate and the wiring substrate; and a routing portion having a plurality of routing lines disposed on one side of each of the substrate and the wiring substrate and connecting the plurality of first pads and the plurality of second pads in a one-to-one manner. Claim 18 A light-emitting display device according to any one of claims 1 to 17, wherein the display portion comprises a plurality of pixels arranged on the substrate along a first direction and a second direction crossing the first direction, and the distance between the center of the outermost pixels among the plurality of pixels and the outer surface of the substrate is less than or equal to half of the pixel pitch, and the pixel pitch is the distance between the centers of two adjacent pixels. Claim 19 A multi-screen display device comprising a plurality of display modules arranged along at least one of a first direction and a second direction crossing the first direction, wherein each of the plurality of display modules includes a light-emitting display device according to any one of claims 1 to 17. Claim 20 In claim 19, in each of the plurality of display modules, the display unit comprises a plurality of pixels arranged along the first direction and the second direction on the substrate, and in the first display module and the second display module adjacent along the first direction and the second direction, the distance between the center of the outermost pixel of the first display module and the center of the outermost pixel of the second display module is equal to or smaller than the pixel pitch, and the pixel pitch is the distance between the centers of two adjacent pixels.

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