Three-dimensional memory devices having through stair contacts and methods for forming the same

Abstract

An embodiment of a three-dimensional (3D) memory device having a through-step contact (TSC) and a method for forming the same are disclosed. In the example, a method for forming the 3D memory device is disclosed. A dielectric stack comprising a plurality of interleaved dielectric layers and a sacrificial layer is formed on a substrate. A step structure is formed on one side of the dielectric stack. A dummy hole is formed that extends vertically through the step structure to reach the substrate. A spacer having a hollow core is formed in the dummy hole. The TSC in contact with the substrate is formed by depositing a conductor layer on the hollow core of the spacer. The TSC extends vertically through the step structure.

Description

Technology Field

[0001] Embodiments of the present disclosure relate to a three-dimensional (3D) memory device and a method for manufacturing the same. Background Technology

[0002] Planar memory cells are scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar process and manufacturing technologies become difficult and costly. Consequently, the memory density of planar memory cells reaches an upper limit.

[0003] 3D memory architecture can overcome the density limitations of planar memory cells. 3D memory architecture includes a memory array and peripheral devices for controlling signals with the memory array.

[0004] An example of a 3D memory device and a method for manufacturing the same is disclosed herein.

[0005] In one example, a method for forming a 3D memory device is provided. A dielectric stack comprising a plurality of interleaved dielectric layers and a sacrificial layer is formed on a substrate. A step structure is formed on one side of the dielectric stack. A dummy hole is formed extending vertically through the step structure to reach the substrate. A spacer having a hollow core is formed in the dummy hole. A TSC in contact with the substrate is formed by depositing a conductor layer on the hollow core of the spacer. The TSC extends vertically through the step structure.

[0006] In another example, a method for forming a 3D memory device is provided. A dielectric stack comprising a plurality of interleaved dielectric layers and a sacrificial layer is formed on a substrate. A step structure is formed on one side of the dielectric stack. A dummy channel structure reaching the substrate is formed. The dummy channel structure extends vertically through the step structure. A spacer is formed by removing a portion of the dummy channel structure. The spacer has a hollow core. A TSC in contact with the substrate is formed by depositing a conductor layer on the hollow core of the spacer. The TSC extends vertically through the step structure.

[0007] In another example, a 3D memory device is provided. The 3D memory device comprises a substrate, a memory stack on the substrate comprising a plurality of interleaved conductor layers and dielectric layers, a step structure on one side of the memory stack, and a TSC extending vertically through the step structure of the memory stack. The TSC is in contact with the substrate. Brief explanation of the drawing

[0008] The attached drawings incorporated into and forming part of this specification illustrate embodiments of the present disclosure, explain the principles of the present disclosure together with the description, and enable a person skilled in the art to make and use the present disclosure. FIG. 1 illustrates a cross-section of an exemplary 3D memory device according to some embodiments of the present disclosure. FIGS. 2a-2c illustrates an exemplary manufacturing process for forming a channel structure and a step structure of a 3D memory device according to some embodiments of the present disclosure. FIGS. 3a-3e illustrate exemplary manufacturing processes for forming a TSC, peripheral contact, and word line contact of a 3D memory device according to various embodiments of the present disclosure. FIGS. 4a-4d illustrate other exemplary manufacturing processes for forming the TSC, peripheral contacts, and word line contacts of a 3D memory device according to some embodiments of the present disclosure. FIGS. 5a-5c is a flowchart of an exemplary method for forming a 3D memory device according to some embodiments. Figure 6 illustrates a related technology that uses different patterns to form dummy channel structures and TSCs in separate manufacturing steps. Embodiments of the present invention will be described with reference to the attached drawings. Specific details for implementing the invention

[0009] It should be understood that while specific configurations and arrangements have been discussed, they are done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure may be used in various other applications.

[0010] References in the specification to "examples," "one example," "exemplary examples," "some examples," etc., indicate that the described examples contain specific features, structures, or characteristics; however, not all examples may necessarily include specific features, structures, or characteristics. Furthermore, such wording does not necessarily refer to the same example. Additionally, when specific features, structures, or characteristics are described in relation to an example, achieving such features, structures, or characteristics in relation to other examples, regardless of whether they are explicitly described, would be within the knowledge of those skilled in the art.

[0011] Generally, terms may be understood at least partially from their use in context. For example, the term “one or more” as used herein may, depending at least partially on the context, be used to describe any feature, structure, or feature in a singular sense, or to describe a combination of features, structures, or features in a plural sense. Likewise, terms such as “a,” “an,” “or,” and “the” may be understood, depending on the context, to convey a singular usage or a plural usage, at least partially. Additionally, the term “used” may be understood, depending on the context, to allow for the existence of additional factors that are not explicitly described, at least partially, rather than being intended to convey an exclusive set of factors.

[0012] It should be readily understood that in the present invention, the meanings of "above," "above," and "on" should be interpreted in the broadest possible way, such that "on" means not only "immediately above" something but also includes the meaning of "above" something that has intermediate features or layers in between, and "above" or "on" means not only "above above" or "on" but also the meaning of "above above" or "on" something that does not have intermediate features or layers in between (i.e., directly on top of something).

[0013] Additionally, spatially relative terms, such as “below,” “below,” and “lower,” “above,” and “above,” may be used to indicate the relationship of one component or feature to other component(s) or feature(s) as depicted in the drawings for ease of explanation. Spatially relative terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and spatially relative descriptors used herein may be interpreted similarly accordingly.

[0014] As used herein, the term “substrate” refers to a material to which a subsequent layer of material is added. The substrate itself may be patterned. The material added to the substrate may remain patterned or unpatterned. Furthermore, the substrate may comprise various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of an electrically nonconductive material such as glass, plastic, or a sapphire wafer.

[0015] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure, or between any pair of horizontal planes in between. A layer may extend along a lateral, vertical, and / or tapered surface. A substrate may be a layer and may contain one or more layers within it and / or have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, an interconnect layer may comprise one or more conductor and contact layers (on which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0016] As used herein, the term “nominal” refers to the desired or target value of a characteristic or parameter for a component or process operation set during the design phase of a product or process, together with the desired value range described above and / or below. The range of values ​​may result from slight variations in the manufacturing process or tolerances. As used herein, the term “about” indicates a given amount of value that may vary based on a specific technical node associated with the target photomask structure. Depending on the specific technical node, the term “about” may indicate a given quantity of value that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0017] As used herein, the term “3D memory device” refers to a semiconductor device having a string of memory cell transistors (referred herein to as a “memory string,” such as a NAND memory string) oriented vertically on a laterally oriented substrate. The memory string extends in a direction perpendicular to the substrate. As used herein, the term “vertical / vertically” means nominally perpendicular to the side of the substrate.

[0018] In some 3D memory devices, through stair contacts (TSCs) are used to provide vertical interconnections between the memory device and peripheral devices. Additionally, dummy channel structures are used to provide structural support for the memory device. In conventional manufacturing processes, TSCs and dummy channel structures are formed in separate steps using different patterns. Since each pattern occupies its own spatial share on the die, the available area on the die for different patterns is limited.

[0019] FIG. 6 illustrates a related technique using different patterns to form a dummy channel structure and a TSC in separate manufacturing steps. As illustrated in FIG. 6, a memory device (600) includes a memory stack (604) on a substrate (602). The memory stack (604) may include an array of memory strings (606) and may include a step structure (642). An array of dummy channel structures (602) may first be formed by etching the array. Dummy holes are created using a dummy pattern, and then the dummy holes are filled with a dielectric layer to form the dummy channel structure (602). After forming the dummy channel structure (602), a sacrificial layer (610) initially formed as part of the dielectric stack includes an interleaved dielectric layer (612), and the sacrificial layer (610) may be replaced with a conductor layer to form a word line. After the word line is formed, an array of TSC holes can be etched using a TSC pattern and then filled with a conductor layer to form an ATSC (608). The manufacturing process described above utilizes different patterns (dummy channel structure pattern and TSC pattern) to form the dummy channel structure (602) and the TSC (608), respectively, in separate manufacturing steps.

[0020] Various embodiments according to the present invention provide a 3D memory device having a TSC that shares the same pattern to form a dummy channel structure, which improves the efficiency of die utilization. For example, two individual patterns can be combined into a single pattern to increase the usable area on the die and allow for the placement of additional patterns. Furthermore, various embodiments of the method for forming a 3D memory device disclosed herein allow the TSC to be formed in the same manufacturing process(s) as for making other structures (e.g., peripheral contacts), thereby further simplifying the manufacturing flow and reducing process costs.

[0021] FIG. 1 illustrates a cross-sectional view of an exemplary 3D memory device (100) according to some embodiments of the present disclosure. The 3D memory device (100) may include a substrate (102) which may comprise silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate (102) is a thin substrate (e.g., a semiconductor layer) that has been thinned from a normal thickness by grinding, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof.

[0022] A 3D memory device (100) may include a memory stack (104) on a substrate (102). The memory stack (104) may be a stacked storage structure in which a memory string (e.g., a NAND memory string (106)) is formed. In some embodiments, the memory stack (104) includes a plurality of conductor / dielectric layer pairs stacked vertically on the substrate (102). Each conductor / dielectric layer pair may include a conductor layer (110) and a dielectric layer (112). That is, the memory stack (104) may include vertically stacked interleaved conductor layers (110) and dielectric layers (112). As illustrated in FIG. 1, each NAND memory string (106) extends vertically through the interleaved conductor layers (110) and dielectric layers (112) of the memory stack (104). In some embodiments, the 3D memory device (100) is a NAND flash memory device in which memory cells are provided at the intersection of a NAND memory string (106) and a conductor layer (110) (functioning as a word line) of the 3D memory device (100). The number of conductor / dielectric layer pairs (e.g., 32, 64, 96, or 128) of the memory stack (104) can set the number of memory cells of the 3D memory device (100).

[0023] The conductor layers (110) may each have the same thickness or different thicknesses. Similarly, the dielectric layers (112) may each have the same thickness or different thicknesses. The conductor layers (110) may include a conductive material comprising, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layers (112) may include a dielectric material comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layers (110) include a metal such as W, and the dielectric layers (112) include silicon oxide. It is understood that a silicon oxide film (not shown), such as in-situ steam generation (ISSG) silicon oxide, may be formed between the substrate (102) (e.g., a silicon substrate) and the memory stack (104) according to some embodiments.

[0024] To further describe the spatial relationships of the components of the 3D memory device (100), x, y, and z axes are added to FIG. 1 (the y direction indicates the page). The x-, y-, and z- directions are perpendicular to each other. The substrate (102) includes two sides (e.g., an upper surface and a lower surface) that extend laterally in the x- direction and the y- direction (transverse direction) in the xy plane. As used herein, whether one component (e.g., a layer or device) is "above," "above," or "below" another component (e.g., a layer or device) of the semiconductor device (e.g., the 3D memory device (100)) is determined with respect to the substrate of the semiconductor device (e.g., the substrate (102)) in the z- direction (vertical direction) when the substrate is located at the lowest plane of the semiconductor device in the z- direction. The same concept for describing spatial relationships applies throughout this specification.

[0025] In some embodiments, the 3D memory device (100) is part of a monolithic 3D memory device, wherein the components of the monolithic 3D memory device (e.g., memory cells and peripheral devices) are formed on a single substrate (e.g., substrate (102)). Any suitable peripheral device (111), such as digital, analog and / or mixed-signal peripheral circuits used to facilitate the operation of the 3D memory device (100), may be formed on the substrate (102) outside the memory stack (104). The peripheral device (111) may be formed "on" the substrate (102), wherein all or part of the peripheral device (111) is formed within the substrate (102) (e.g., below the upper surface of the substrate (102)) and / or directly on the substrate (102). Peripheral devices (111) may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, a charge pump, a current or voltage reference, or active or passive components of a circuit (e.g., a transistor, a diode, a resistor, or a capacitor). Isolation regions (e.g., shallow trench isolations (STI)) and doped regions (e.g., source and drain regions of a transistor) may also be formed within a substrate (102) outside the memory stack (104). In some embodiments, it is understood that peripheral devices (111) are formed above or below the NAND memory string (106) as opposed to the side of the NAND memory string (106) as illustrated in FIG. 1. Also, in some embodiments, it is understood that the 3D memory device (100) is part of a non-monolithic 3D memory device, wherein the components are formed individually on different substrates and then joined in a face-to-face manner, a face-to-back manner, or a back-to-face manner.Peripheral device (111) can be formed on a separate substrate different from the substrate (102).

[0026] As illustrated in FIG. 1, the memory stack (104) may include an inner region (116) (also referred to as the “core array region”) and an outer region (118) (also referred to as the “staircase region”). In some embodiments, the inner region (116) is the central region of the memory stack, where an array of NAND memory strings (106) is formed through conductor / dielectric layer pairs, and the outer region (118) is the remaining region of the memory stack (104) surrounding the inner region (116) (including sides and edges) without NAND memory strings (106).

[0027] As illustrated in FIG. 1, each NAND memory string (106) may include a channel structure (108) extending vertically through a pair of conductor / dielectric layers in an internal region (116) of a memory stack (104). The channel structure (108) may include channel holes filled with a semiconductor material (e.g., forming a semiconductor channel) and a dielectric material (e.g., forming a memory film). In some embodiments, the semiconductor channel comprises silicon such as amorphous silicon, polysilicon, or single-crystal silicon. In some embodiments, the memory film is a composite layer comprising a tunneling layer, a storage layer (also known as a "charge trap / storage layer"), and a blocking layer. Each NAND memory string (106) may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and blocking layer are arranged in this order along a direction from the center toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may comprise silicon oxide, silicon oxynitride, a high-dielectric constant (high-k) dielectric, or any combination thereof.

[0028] In some embodiments, the NAND memory string (106) includes a plurality of control gates for the NAND memory string (106) (each being part of a word line / conductor layer (110)). The conductor layer (110) of each pair of conductor / dielectric layers can function as a control gate for a memory cell of the NAND memory string (106). The conductor layer (110) may include a plurality of control gates for a plurality of NAND memory strings (106) and may extend laterally as a word line ending in an outer region (118) of the memory stack (104).

[0029] In some embodiments, the NAND memory string (106) includes two plugs (117 and 119) at each end in the vertical direction. Each plug (117 or 119) may contact each end of the channel structure (108). The plug (117) may comprise a semiconductor material, such as silicon, that is epitaxially grown from the substrate (102). The plug (117) may function as a channel controlled by source selection. The plug (117) may be at the bottom of the NAND memory string (106) and may contact the channel structure (108) (e.g., at the bottom of the channel structure (108)). As used herein, the “upper end” of a component (e.g., NAND memory string 106) is the end that is further away from the substrate (102) in the z-direction, and the “bottom end” of a component (e.g., NAND memory string 106) is the end that is closer to the substrate (102) in the z-direction when the substrate (102) is located on the lowest plane of the 3D memory device (100).

[0030] The plug (119) may comprise a semiconductor material (e.g., polysilicon) or a conductor material (e.g., metal). In some embodiments, the plug (119) comprises an opening filled with titanium / titanium nitride (Ti / TiN as a barrier layer) and tungsten (as a conductor). By covering the top of the channel structure (108) during the manufacture of the 3D memory device (100), the plug (119) may function as an etching stop layer to prevent etching of the dielectric material filled in the channel structure (108), such as silicon oxide and silicon nitride. In some embodiments, the plug (119) functions as a drain of the NAND memory string (106).

[0031] As illustrated in FIG. 1, in at least one aspect of the lateral direction (e.g., x-direction), the outer region (118) of the memory stack (104) may include a step structure (142). In some embodiments, another step structure (not shown) is positioned on the opposite side of the memory stack (104) in the x-direction. Each "level" of the step structure (142) may include one or more pairs of conductor / dielectric layers, each comprising a conductor layer (110) and a dielectric layer (112). The upper layer of each level of the step structure (142) may be a conductor layer (110) for vertical interconnection. In some embodiments, each of two adjacent levels of the step structure (142) is offset by a nominally equal distance in the vertical direction and a nominally equal distance in the lateral direction. For each of the two adjacent levels of the step structure (142), the first level (and the conductor layer and dielectric layer within it) closer to the substrate (102) may be extended laterally further than the second level (and the conductor layer and dielectric layer within it), thereby forming a "landing area" of the first level for vertical interconnection.

[0032] The step structure (142) can be used for landing word line contacts (144). The bottom of each word line contact (144) contacts the upper conductor layer (110) (word line) at each level of the step structure (142) to individually address the corresponding word line of the 3D memory device (100). The word line contact (144) may include an opening (e.g., a via hole or trench) that extends vertically through one or more dielectric layers and is filled with a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or a combination thereof.

[0033] As illustrated in FIG. 1, the 3D memory device (100) further comprises a TSC (136) that extends vertically through each pair of conductor / dielectric layers of a step structure (142). Each TSC (136) may extend vertically through an interleaved conductor layer (110) and a dielectric layer (112). In some embodiments, the TSC (136) may extend through the entire thickness of the step structure (142) (e.g., all pairs of conductor / dielectric layers in the vertical direction at a lateral position of the step structure (142)) to reach the substrate (102). In some embodiments, the TSC (136) further extends through at least a portion of the substrate (102). The TSC (136) may shorten interconnect routing to transmit electrical signals from and / or to the 3D memory device (100), such as a portion of a power bus. In some embodiments, the TSC (136) may provide an electrical connection between the 3D memory device (100) and the peripheral device (111) and / or between a BEOL (back-end-of-line) interconnect (not shown) and the peripheral device (111). The TSC (136) may also provide mechanical support to the stepped structure (142).

[0034] The TSC (136) can be formed by filling a vertical opening with material through the steps (142). In some embodiments, the TSC (136) includes a conductor layer (140) surrounded by spacers (138). For example, the sidewalls of the TSC (136) may be in contact with the spacers (138). The conductor layer (140) may include a conductive material comprising, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The spacers (138) may electrically insulate the conductor layer (140) of the TSC (136) from the surrounding conductor layer (110) in the step structure (142). In some embodiments, the TSC (136) has a substantially circular shape in the top view, and the conductor layer (140) and the spacers (138) are arranged radially in this order from the center of the TSC (136). The spacer (138) may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0035] As illustrated in FIG. 1, the 3D memory device (100) may further include a peripheral contact (148) that extends vertically through one or more dielectric layers and contacts a peripheral device (111) outside the memory stack (104). The peripheral contact (148) may provide an electrical connection with the peripheral device (111). The peripheral contact (148) is formed by filling a vertical opening with material. In some embodiments, similar to the TSC (136), the peripheral contact (148) may include a conductor layer (152) surrounded by a spacer (150). The conductor layer (152) may include a conductive material comprising, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or a combination thereof. In some embodiments, the peripheral contact (148) has a substantially circular shape in a plan view, and the conductor layer (152) and spacer (150) are arranged radially in this order from the center of the peripheral contact (148). The spacer (150) may comprise a dielectric material comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the spacer (150) and the spacer (138) have nominally the same thickness in the lateral direction (e.g., radial direction). In some embodiments, both the spacer (150) and the spacer (138) comprise silicon oxide. It is understood that the peripheral device (111) may not be formed on the substrate (102), and the peripheral contact (148) may be in a different configuration in some embodiments where, for example, the 3D memory device (100) is a non-monolithic 3D memory device.

[0036] It is understood that the 3D memory device (100) may include additional components and structures not shown in FIG. 1. It is understood that FIG. 1 includes, but is not limited to, other local contacts and interconnects in one or more BEOL interconnect layers on top of the memory stack (104) and / or under the substrate (102).

[0037] FIGS. 2a-2c illustrate an exemplary manufacturing process for forming a channel structure and a step structure of a 3D memory device according to some embodiments of the present disclosure. FIGS. 3a-3e illustrate an exemplary manufacturing process for forming a TSC, peripheral contacts, and word line contacts of a 3D memory device according to various embodiments of the present disclosure. FIGS. 4a-4d illustrate other exemplary manufacturing processes for forming a TSC, peripheral contacts, and word line contacts of a 3D memory device according to some embodiments of the present disclosure. FIGS. 5a-5c is a flowchart of an exemplary method (500, 500', 500") for forming a 3D memory device according to some embodiments. An example of a 3D memory device illustrated in FIGS. 2-5 includes the 3D memory device (100) illustrated in FIG. 1. FIGS. 2-5 is described together. It is understood that the operations illustrated in the method (500, 500', and 500") are not complete and that other operations may be performed before, after, or between the illustrated operations. Additionally, some operations may be performed simultaneously and may be performed in a different order than that illustrated in FIGS. 5a-5c.

[0038] As illustrated in FIG. 5a, the method (500) begins with an operation (502) in which a dielectric stack comprising a plurality of interleaved dielectric layers and a sacrificial layer is formed on a substrate. The substrate may be a silicon substrate. The method (500) proceeds to an operation (504) as illustrated in FIG. 5a, in which a channel structure extending vertically through the dielectric stack is formed. The method (500) proceeds to an operation (506) in which a step structure is formed on one side of the dielectric stack.

[0039] As illustrated in FIG. 2a, a dielectric deck (204) comprising a plurality of interleaved dielectric layers and a sacrificial layer is formed on a silicon substrate (202). In some embodiments, the sacrificial layer (206) and the dielectric layer (208) are deposited alternately by one or more thin film deposition processes including physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof, but are not limited thereto. In some embodiments, the sacrificial layer (206) comprises silicon nitride, and the dielectric layer (208) comprises silicon oxide. It is understood that the order in which the sacrificial layer (206) and the dielectric layer (208) are deposited is not limited. The deposition may start with the sacrificial layer (206) or the dielectric layer (208) and may end with the sacrificial layer (206) or the dielectric layer (208).

[0040] As illustrated in FIG. 2b, an array of channel structures (210) is formed, each of which extends vertically through an interleaved sacrificial layer (206) and a dielectric layer (208) of a dielectric deck (204). In some embodiments, the manufacturing process for forming the channel structures (210) includes the step of forming channel holes through the interleaved sacrificial layer (206) and the dielectric layer (208) in the dielectric deck (204) by using a wet etching process, such as dry etching / and / or wet etching (DRIE), and then using a thin film deposition process to fill the channel holes with a plurality of layers, such as a dielectric layer and a semiconductor layer. In some embodiments, the dielectric layer is a composite dielectric layer, such as a combination of multiple dielectric layers, including but not limited to a tunneling layer, a storage layer, and a blocking layer. The tunneling layer may include a dielectric material including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The storage layer may include a material for storing charge for memory operation. The storage layer material may include, but is not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride. The blocking layer may include a dielectric material including, but not limited to, silicon oxide or a combination of silicon oxide / silicon oxynitride / silicon oxide (ONO). The blocking layer may further include a high dielectric constant dielectric layer, such as an aluminum oxide (Al2O3) layer. The semiconductor layer may include polysilicon acting as a semiconductor channel. The semiconductor layer and the dielectric layer may be formed by a process such as ALD, CVD, PVD, or any combination thereof.

[0041] In some embodiments, a dielectric stack (204) may be joined by other dielectric stacks to form a multi-stack structure through a joint layer (212). As illustrated in FIG. 2b, the joint layer (212) may be formed on the dielectric deck (204) by depositing a dielectric layer, such as a silicon oxide layer, using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof. An array of inter-deck plugs (214) may be formed on the joint layer (212) and may each come into contact with an array of channel structures (210). The inter-deck plugs (214) may be formed by patterning and etching openings through the joint layer (212) and then depositing a semiconductor material, such as polysilicon, using a thin film deposition process such as ALD, CVD, PVD, or any combination thereof. In the following, embodiments of the present disclosure are described for a single-stack structure for brevity and simplicity. It should be understood that the technical solution disclosed herein is also applicable to a multi-stack structure.

[0042] As illustrated in FIG. 2c, a step structure (224) is formed on the side of the dielectric stack (218). The step structure (224) can be formed by a so-called "trim-etch" process, which trims the patterned photoresist layer in each cycle (e.g., often etching progressively and internally from all directions), and then uses the trimmed photoresist layer as an etching mask to etch the exposed portion of the dielectric / sacrificial layer pair to form a step of the step structure (224).

[0043] The method (500) proceeds to operation (508) as illustrated in FIG. 5a, and a dummy channel structure extending vertically through a step structure is formed. In some embodiments, the dummy channel structure is formed as an intermediate structure that is later replaced by a TSC. As illustrated in FIG. 3b, an array of dummy channel structures (302) is formed through a step structure (342) of a dielectric stack (304). The dielectric stack (304) includes an interleaved dielectric layer (312) and a sacrificial layer (310).

[0044] The dummy channel structure (302) may extend vertically through the step structure (342) and may have a vertical opening filled with the same material as in the channel structure (108). Unlike the channel structure (108), according to some embodiments, no contact is formed on the dummy channel structure (302) for electrical connection with other components of a 3D memory device, such as a 3D memory device (100). In some embodiments, the dummy channel structure (302) is completely filled with a dielectric material comprising, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0045] The dummy channel structure (302) can be used to balance the load during specific processes (e.g., etching and chemical mechanical polishing (CMP)) during manufacturing and to provide mechanical support to the memory array structure, e.g., the step structure (342). The present disclosure can form a TSC from the dummy channel structure, and accordingly, both the dummy channel structure and the TSC can be formed using the same pattern. The resulting TSC can provide balancing and support functions for the dummy channel structure.

[0046] As illustrated in FIG. 3a, the dummy channel structure (302) may be formed by first etching a dummy hole (322) through one or more dielectric layers within the step structure (342) using wet etching and / or dry etching, such as DRIE. In some embodiments, the dummy hole (322) may extend vertically through all dielectric layers within the step structure (342) and expose a portion of the silicon substrate (202) (e.g., the dummy hole (322) may extend into the silicon substrate (202)). In some embodiments, the dummy hole (322) may extend into the silicon substrate (202) (e.g., a portion of the silicon substrate (202) may be etched during the etching process).

[0047] In some embodiments, a dummy hole (324) outside the dielectric stack (304) may be formed simultaneously with the formation of the dummy hole (322) (e.g., in the same manufacturing step). The dummy hole (324) may be used to form peripheral contacts that provide interconnection to peripheral devices (311). In some embodiments, the dummy holes (322 and 324) may have a nominally circular shape in a plan view, as shown in FIG. 3a. In some embodiments, the sizes of the dummy holes (322 and 324) may be nominally the same.

[0048] Referring again to FIG. 3b, the dummy hole (322) shown in FIG. 3a may be filled (deposited) with a dielectric layer (352), such as a silicon oxide layer, to form a dummy channel structure (302) using one or more thin film deposition processes, such as ALD, CVD, PVD, or any combination thereof. In some embodiments, the dummy channel structure (302) is formed simultaneously with the channel structure (210) in the same manufacturing step, so that the dummy hole (322) is filled with at least a portion of the material filling the channel structure (210).

[0049] In some embodiments, a dummy channel structure (303) outside the dielectric stack (304) is formed simultaneously with forming a dummy channel structure (302) by depositing a dielectric layer (354) in the dummy hole (324) (e.g., in the same manufacturing step). The dielectric layer (354) may have the same material as the dielectric layer (352).

[0050] In some embodiments, the dummy holes (322 / 324) may each be completely filled with a dielectric layer (352 / 354). In other embodiments, the dummy holes (322 or 324) may be partially filled as shown in FIG. 3b. In such cases, the resulting dummy channel structure (302 / 303) may have top, bottom, and sidewall portions deposited with a dielectric layer (352 / 354). The central region may not be completely filled.

[0051] The method (500) proceeds to operation (510) as illustrated in FIG. 5, wherein a sacrificial layer of a dielectric stack is replaced with a conductor layer to form a plurality of word lines. As illustrated in FIG. 3c, the sacrificial layer (310) is replaced with a conductor layer (309) (functioning as a word line). Replacing the sacrificial layer (310) with the conductor layer (309) can be accomplished by wet-etching the sacrificial layer (310) (e.g., silicon nitride) selectively with respect to the dielectric layer (304) (e.g., silicon nitride) and filling the structure with the conductor layer (309) (e.g., W). The conductor layer (309) can be deposited by PVD, CVD, ALD, electrochemical deposition, or any combination thereof. The conductor layer (309) may comprise a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. As a result, after the gate replacement process, the dielectric stack (304) of FIG. 3a-3b becomes a memory stack (305) comprising a conductor / dielectric layer pair on a silicon substrate (202), namely an interleaved conductor layer (309) and a dielectric layer (312).

[0052] The method (500) proceeds to the operation (512) in which an opening extending vertically through the central portion of a dummy channel structure is etched to form a spacer. Referring to FIG. 3d, the opening (372) (TSC hole) is etched through the dummy channel structure (302) (shown in FIG. 3b-3c) to form a spacer (362). In some embodiments, the opening (372) / spacer (362) may extend vertically through the interleaved dielectric layer (312) and conductor layer (309) in the step structure (242) to reach the silicon substrate (202). In some embodiments, a second opening (374) (peripheral contact hole) may be simultaneously formed from the dummy channel structure (303) (shown in FIG. 3b-3c). The openings (372 / 374) may be etched using a wet etching and / or dry etching process such as DRIE. For example, the central portion of the dummy channel structure (302 / 303) may be removed by etching to form a spacer (362 / 364) having a hollow core as shown in FIG. 3d. In some embodiments, the sidewalls of the spacers (362 and 364) may have nominally the same thickness. The depths of the vertical TSC hole (372) and the peripheral contact hole (374) may be nominally the same. The lateral dimensions of the TSC hole (372) and the peripheral contact hole (374), such as the diameter, may be nominally the same or different in various embodiments. For example, the diameter of the TSC hole (372) may be larger than the diameter of the peripheral contact hole (374) according to some embodiments.

[0053] As illustrated in FIG. 3d, the TSC hole (372) and the peripheral contact hole (374) may reach the silicon substrate (202), and the bottom of the peripheral contact hole (374) may contact a peripheral device (311) formed on the silicon substrate (202). In some embodiments, the peripheral device (311) includes a transistor, which may be formed by a plurality of processes including, but not limited to, photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, a doped region is formed on the silicon substrate (202) by ion implantation and / or thermal diffusion, for example, functioning as the source region and / or drain region of the transistor. In some embodiments, an insulating region (e.g., STI) is also formed on the silicon substrate (202) by wet etching and / or dry etching and thin film deposition processes. The manufacturing process for forming the peripheral device (311) may occur at any manufacturing stage prior to the etching of the peripheral contact hole (374).

[0054] Since the opening (372 / 374) is etched from the dummy channel structure (302 / 303) by removing a portion of the dielectric layer deposited thereon, the remaining portion including the sidewall of the dummy channel structure (302 / 303) after the opening (372 / 274) is formed and becomes a spacer (362 / 364). The spacer (362 / 264) can provide mechanical support to a memory stack (305) containing a stepped structure (342) similar to the dummy channel structure (302 / 303). Additionally, the spacer (362 / 364) can function as an insulating layer surrounding the conductor layer deposited at the opening (372 / 374) to form a TSC / peripheral contact.

[0055] In some embodiments, the opening (372 / 374) (defined by the inner wall of the spacer (362 / 364)) may have a nominally circular shape in the plan view as shown in FIG. 3d. In some embodiments, the side walls of the spacers (362 and 364) may have nominally the same thickness. In some embodiments, the spacers (362 and 364) may have the same or different sizes. For example, the diameter of the spacer (364) (e.g., measured from the inner or outer side wall) may be smaller than the diameter of the spacer (362).

[0056] The method (500) proceeds to operation (514) as illustrated in FIG. 5, where a word line contact and a TSC are formed simultaneously. In some embodiments, a conductor layer is deposited in the opening to form the TSC. In some embodiments, the conductor layer is a composite layer comprising an adhesive / barrier layer and a conductor. As illustrated in FIG. 3e, a conductor layer (382) is deposited in the opening (372) (as illustrated in FIG. 3d) to fill the remaining space of the opening (372), thereby forming a TSC (336) that extends vertically through the step structure (342). In some embodiments, the conductor may be formed in the remaining space of the opening (372) by depositing a metal such as tungsten using one or more thin film deposition processes such as ALD, CVD, PVD, electrochemical deposition, or any combination thereof. A conductor layer (384) can be simultaneously formed in an opening (374) (shown in FIG. 3d) using the same deposition process to form a peripheral contact (348) that contacts a peripheral device (311). In some embodiments, the conductor layers (382 and 384) may use the same material (e.g., tungsten (W)). After deposition, the excess conductor layer can be removed by CMP.

[0057] Word line contacts (344) can be formed simultaneously with the TSC (e.g., in the same manufacturing step). Each word line contact (344) contacts each of the conductor layer (309) of the conductor / dielectric layer pair in the step structure (342). The word line contacts (344) are formed through one or more dielectric layers by first etching a vertical opening (e.g. by wet etching and / or dry etching) and then filling the opening with a conductive material using ALD, CVD, PVD, electrochemical deposition, or any combination thereof. In some embodiments, another conductive material is filled within the opening to function as an adhesion / barrier layer. The etching of the dielectric layer to form the opening of the word line contacts (344) can be controlled by stopping the etching in different materials. For example, the etching of the dielectric layer can be stopped when reaching the conductor layer (309) in the step structure (342).

[0058] In some embodiments, the TSC (336), word line contact (344), and peripheral contact (348) may have a nominally circular shape in a plan view as shown in FIG. 3e. The TSC (336), word line contact (344), and peripheral contact (348) may have the same or different sizes. For example, the TSC (336) and peripheral contact (348) may have a diameter larger than the diameter of the word line contact (344) according to some embodiments.

[0059] FIG. 5b is a flowchart of another exemplary method (500') for forming a 3D memory device according to some embodiments of the present disclosure. Operations 502', 504', 506', and 508' are similar to operations 502, 504, 506, and 508, respectively, and are therefore not repeated. The method (500') proceeds to operation (520) as illustrated in FIG. 5b, where an opening extending vertically through the central portion of a dummy channel structure is etched to form a spacer. Step 520 is similar to step 512, but differs in that the etching of the opening in step 520 is performed before forming the word line. As illustrated in FIG. 4a, the opening (372 / 374) is etched before the sacrificial layer (310) is replaced by the conductor layer (309).

[0060] Method (500') proceeds to operation 522 as illustrated in FIG. 5b, where the TSC is formed by extending vertically through a step structure by depositing a conductor layer at the opening. Operation 522 is similar to 514 in terms of forming the TSC. Unlike operation 514, which forms a word line contact simultaneously with the TSC, operation 522 does not form a word line contact because a word line has not yet been formed prior to operation 522. Referring to FIG. 4b, the TSC (336) is formed before the sacrificial layer (310) is replaced by the conductor layer (309).

[0061] Method (500') proceeds to operation 524 as illustrated in FIG. 5b, wherein a word line is formed by replacing the sacrificial layer of the dielectric stack with a conductor layer. Operation 524 is similar to operation 510. Referring to FIG. 4c, the word line (309) is formed by replacing the sacrificial layer (310) with the conductor layer (309). Note that in FIG. 4c, the TSC (336) and peripheral contact (348) are formed.

[0062] Method (500') proceeds to operation 526 as illustrated in FIG. 5b, where a word line contact is formed. Operation 526 is similar to operation 514 in that it forms a word line. As illustrated in FIG. 4d, the word line contact (344) is formed after the TSC (336) and peripheral contact (348) are formed.

[0063] FIG. 5c is a flowchart of another exemplary method (500) for forming a 3D memory device according to some embodiment of the present disclosure. Operations 502", 504", and 506" are similar to operations 502, 504, and 506, respectively, and are therefore not repeated. The method (500) proceeds to operation 530 as illustrated in FIG. 5c, wherein a dummy hole extending vertically through a step structure is formed. As illustrated in FIG. 3a, the dummy hole (322) may be formed through one or more dielectric layers within the step structure (342) using wet etching and / or dry etching, such as DRIE. In some embodiments, the dummy hole (322) may extend vertically through all dielectric layers within the step structure (342) and reach the silicon substrate (202). In some embodiments, the dummy hole (322) may extend into the silicon substrate (202) (e.g., a portion of the silicon substrate (202) may be etched during the etching process).

[0064] In some embodiments, a dummy hole (324) outside the dielectric stack (304) may be formed simultaneously with the formation of the dummy hole (322) (e.g., in the same manufacturing step). The dummy hole (324) may be used to form peripheral contacts that provide interconnects to peripheral devices. In some embodiments, the dummy holes (322 and 324) may have a nominally circular shape in a plan view, as shown in FIG. 3a. In some embodiments, the sizes of the dummy holes (322 and 324) may be nominally the same.

[0065] The method (500) proceeds to operation (532) as illustrated in FIG. 5c, wherein a spacer having a hollow core is formed in a dummy hole. As illustrated in FIG. 3b-3d, the spacer (362) may be formed by depositing a dielectric layer (352) into a dummy hole (322) and then removing a portion of the dielectric layer (352) to form the spacer (362). In some embodiments, the spacer may be formed directly by depositing the dielectric layer (352) into the dummy hole (322) without additional etching operations to remove a portion of the dielectric material deposited to form the spacer (362). The spacer (364) may be formed in a similar manner.

[0066] The method (500) proceeds to operation 534 as illustrated in FIG. 5c, wherein a TSC extending vertically through a stepped structure is formed by depositing a conductor layer on the hollow core of the spacer. Operation 534 is similar to operation 522.

[0067] Method (500) proceeds to operation (536) as illustrated in FIG. 5c, wherein a word line is formed by replacing the sacrificial layer of the dielectric stack with a conductor layer. Operation 536 is similar to operation 524. Referring to FIG. 4c, the word line (309) is formed by replacing the sacrificial layer (310) with the conductor layer (309). Note that in FIG. 4c, the TSC (336) and the peripheral contact (348) are formed.

[0068] Method (500) proceeds to operation 538 as illustrated in FIG. 5c, where a word line contact is formed. Operation 538 is similar to operation 526. Referring to FIG. 4d, the word line contact (344) is formed after the TSC (336) and peripheral contact (348) are formed.

[0069] According to one aspect of the present disclosure, a method for forming a 3D memory device is provided. A dielectric stack comprising a plurality of interleaved dielectric layers and a sacrificial layer is formed on a substrate. A step structure is formed on one side of the dielectric stack. A dummy hole is formed extending vertically through the step structure to reach the substrate. A spacer having a hollow core is formed in the dummy hole. A TSC in contact with the substrate is formed by depositing a conductor layer on the hollow core of the spacer. The TSC extends vertically through the step structure.

[0070] In some embodiments, a plurality of word lines are formed by replacing the sacrificial layer of the dielectric stack with a conductor layer before forming the spacer.

[0071] In some embodiments, a plurality of word line contacts, each contacting a word line, are formed simultaneously with forming the TSC.

[0072] In some embodiments, after forming the TSC, a plurality of word lines are formed by replacing the sacrificial layer of the dielectric stack with a conductor layer.

[0073] In some embodiments, a plurality of word line contacts are formed, each contacting a respective word line.

[0074] In some embodiments, a dielectric layer is formed in a dummy hole to form a spacer.

[0075] In some embodiments, the dielectric layer comprises silicon oxide.

[0076] In some embodiments, the dielectric layer forms a spacer.

[0077] In some embodiments, to form a spacer, the hollow core is etched through a dielectric layer deposited in a dummy hole.

[0078] In some embodiments, a second dummy hole outside the genome stack is formed simultaneously with the dummy hole.

[0079] In some embodiments, a peripheral contact is formed by depositing a second conductor layer in a second dummy hole simultaneously with forming a TSC. The peripheral contact contacts the substrate.

[0080] In some embodiments, the first and second conductor layers comprise the same material.

[0081] In some embodiments, the TSC has a nominally circular shape in the plan view.

[0082] In some embodiments, the conductor layer includes tungsten (W).

[0083] In some embodiments, the sacrificial layer of the interleaved dielectric layer and the dielectric layer comprise silicon oxide, and the sacrificial layer of the interleaved dielectric layer and the sacrificial layer comprise silicon nitride.

[0084] According to another aspect of the present disclosure, a method for forming a 3D memory device is provided. A dielectric stack comprising a plurality of interleaved dielectric layers and a sacrificial layer is formed on a substrate. A step structure is formed on one side of the dielectric stack. A dummy channel structure reaching to the substrate is formed. The dummy channel structure extends vertically through the step structure. A spacer is formed by removing a portion of the dummy channel structure. The spacer has a hollow core. A TSC in contact with the substrate is formed by depositing a conductor layer on the hollow core of the spacer. The TSC extends vertically through the step structure.

[0085] In some embodiments, a plurality of word lines are formed by replacing the sacrificial layer of the dielectric stack with a conductor layer before forming the spacer.

[0086] In some embodiments, a plurality of word line contacts, each contacting a word line, are formed simultaneously with forming the TSC.

[0087] In some embodiments, after forming the TSC, a plurality of word lines are formed by replacing the sacrificial layer of the dielectric stack with a conductor layer.

[0088] In some embodiments, a plurality of word line contacts are formed, each contacting a respective word line.

[0089] In some embodiments, before forming the dummy channel structure, a dummy hole is formed that extends vertically through a step structure and exposes a portion of the substrate.

[0090] In some embodiments, a dielectric layer is deposited in a dummy hole to form a dummy channel structure.

[0091] In some embodiments, the dielectric layer comprises silicon oxide.

[0092] In some embodiments, to form a spacer, an opening is etched through a dielectric layer deposited in a dummy hole.

[0093] In some embodiments, to form a spacer, a portion of the dielectric layer deposited in the dummy hole is removed.

[0094] In some embodiments, a second spacer outside the genome stack is formed simultaneously with the spacer.

[0095] In some embodiments, a peripheral contact is formed by depositing a second conductor layer on the second spacer simultaneously with forming the TSC. The peripheral contact contacts the substrate.

[0096] In some embodiments, the first and second conductor layers comprise the same material.

[0097] In some embodiments, the spacer and the second space have the same thickness.

[0098] In some embodiments, the conductor layer includes tungsten (W).

[0099] In some embodiments, the sacrificial layer of the interleaved dielectric layer and the dielectric layer comprise silicon oxide, and the sacrificial layer of the interleaved dielectric layer and the sacrificial layer comprise silicon nitride.

[0100] According to another aspect of the present disclosure, a 3D memory device is provided. The 3D memory device comprises a substrate, a memory stack on the substrate comprising a plurality of interleaved conductive layers and dielectric layers, a step structure on one side of the memory stack, and a TSC extending vertically through the step structure of the memory stack. The TSC is in contact with the substrate.

[0101] In some embodiments, the 3D memory device further includes peripheral contacts outside the memory stack. The peripheral contacts contact a substrate.

[0102] In some embodiments, the peripheral contact and the TSC contain the same material.

[0103] In some embodiments, the sidewalls of the TSC and the surrounding contact, respectively, are surrounded by spacers having nominally the same thickness.

[0104] In some embodiments, the spacer comprises silicon oxide.

[0105] In some embodiments, the 3D memory device further includes a plurality of word line contacts that contact each conductor layer in a stepped structure.

[0106] The foregoing description of specific embodiments will reveal the general nature of the present disclosure, which allows others to easily modify and / or adapt various applications, such as specific embodiments, by applying their knowledge of the art, without excessive experimentation and without departing from the general concept of the present disclosure. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments based on the teachings and guidance set forth in this specification. It should be understood that the language or terminology of this specification is for illustrative purposes only and not for limitation, and that the language or terminology of this specification should be interpreted by a person skilled in the art in the context of the teachings and guidance.

[0107] Embodiments of the present disclosure have been described above with the help of functional building blocks that exemplify the implementation of specific functions and their relationships. The boundaries of these functional building blocks are defined arbitrarily herein for convenience of explanation. Alternative boundaries may be defined as long as the specified functions and their relationships are appropriately performed.

[0108] The summary and summary sections may present one or more exemplary embodiments of the present disclosure as considered by the inventor(s), and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0109] The breadth and scope of the present disclosure shall not be limited by any of the exemplary embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A method for forming a memory device comprising: forming a dielectric stack on a substrate including a plurality of interleaved dielectric layers and a sacrificial layer; forming a step structure on at least one side of the dielectric stack; forming a first dummy hole extending through the step structure and simultaneously forming a second dummy hole outside the dielectric stack while forming the first dummy hole; forming a first spacer having a hollow core in the first dummy hole; depositing a first conductor layer on the hollow core of the first spacer to form a through step contact (TSC) in contact with the substrate - the TSC extending through the step structure -; forming a second spacer in the second dummy hole; and depositing a second conductor layer in the second dummy hole to form a peripheral contact in contact with the substrate. Claim 2 A method for forming a memory device according to claim 1, further comprising the steps of: forming a dummy channel structure extending through the step structure; and removing a portion of the dummy channel structure to form the first spacer. Claim 3 A method for forming a memory device according to claim 1, wherein the step of forming the peripheral contact includes the step of depositing a second conductor layer in the second dummy hole simultaneously with forming the TSC. Claim 4 A method for forming a memory device according to claim 3, wherein the first conductor layer and the second conductor layer are composed of the same material. Claim 5 A method for forming a memory device according to claim 1, further comprising the step of forming a plurality of word lines by replacing the sacrificial layer of the dielectric stack with a conductive layer before forming the TSC or the first spacer. Claim 6 A method for forming a memory device according to claim 1, further comprising the step of forming a plurality of word lines by replacing the sacrificial layer of the dielectric stack with a conductive layer after forming the TSC. Claim 7 A method for forming a memory device according to claim 1, wherein the first spacer comprises silicon oxide. Claim 8 A method for forming a memory device according to claim 1, wherein the dielectric layer in the interleaved dielectric layer and the sacrificial layer comprises silicon oxide; and the sacrificial layer in the interleaved dielectric layer and the sacrificial layer comprises silicon nitride. Claim 9 A memory device comprising: a memory stack on a substrate, wherein the memory stack comprises interleaved conductive layers and dielectric layers and comprises steps in a step region; a through step contact (TSC) extending through the memory stack in the step region, wherein the TSC comprises a first conductive layer surrounded by a first spacer; and a peripheral contact located outside the memory stack, wherein the peripheral contact comprises a second conductive layer surrounded by a second spacer, wherein the peripheral contact contact is in contact with the substrate. Claim 10 A memory device according to claim 9, further comprising a word line contact in contact with one of the conductive layers of the memory stack in the step region, wherein the word line contact and the first conductive layer of the TSC comprise the same conductive material. Claim 11 In claim 9, the memory device, wherein the first spacer comprises a dielectric material. Claim 12 A memory device according to claim 9, further comprising a channel structure extending through the memory stack in a core array region adjacent to the staircase region. Claim 13 In claim 12, the above TSC is a memory device extending through a conductive layer and a dielectric layer of the memory stack, which is fewer than the number of channel structures. Claim 14 A memory device according to claim 9, wherein the second conductor layer and the first conductor layer of the TSC comprise the same conductive material. Claim 15 In claim 9, the above TSC is a memory device in contact with the substrate. Claim 16 delete Claim 17 delete

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