Printed circuit board and method of manufacturing the same

Abstract

The present invention relates to a printed circuit board and a method for manufacturing the same. A printed circuit board according to the present invention comprises: a substrate having a first layer to an n-th layer that is stacked in layers; a via hole formed to penetrate the first layer or the n-th layer along the stacking direction; a plating layer formed inside and outside the via hole; and a pad formed by separating the plating layer formed at the end of the via hole from the surroundings. Accordingly, by forming a via on one side of the pad along the stacking direction, the component density can be improved, thereby allowing the size of the substrate to be reduced.

Description

Technology Field

[0001] The present invention relates to a printed circuit board and a method for manufacturing the same. Background Technology

[0002] As is well known, a printed circuit board (PCB) has a structure in which conductors and insulators are laminated, and various components such as semiconductors, capacitors, and resistors are mounted on it.

[0003] These printed circuit boards are also referred to as single-sided, double-sided, 4-layer, 6-layer, or (n*2) layer PCBs depending on the number of circuit layers.

[0004] Typically, computer motherboards use 6-layer PCBs, graphics cards use 8-layer or 10-layer PCBs, and network equipment uses PCBs with dozens of layers.

[0005] A printed circuit board is composed of an insulator for the substrate excluding the conductors (circuits), and such a substrate is typically constructed by stacking multiple layers of glass fiber and epoxy plastic bonded resin (PREPREG, PP).

[0006] Meanwhile, a through-via is provided to electrically connect circuits (layers) of different layers stacked with an insulator (110I) in between.

[0007] The above-mentioned through-via is configured to have a via hole formed by penetrating different layers spaced apart (layered arrangement) with an insulator, and a plating layer having a conductor plated on the inner surface and both end surfaces of the via hole.

[0008] As a result, the circuit layers on both sides of the insulator are electrically connected.

[0009] However, in such conventional printed circuit boards and methods for manufacturing the same, when a through-via is formed on the lower side of a component pad, an insulating material (PSR) is applied to the lower and upper surfaces of the laminated board, and after the PCB cleaning process, a cleaning solution (acidic solution) remains inside the via hole, which can cause cracks in the PCB caused by corrosion.

[0010] In addition, when a through-via is formed on the lower side of a component pad, the opposite side of the pad (e.g., the bottom surface) is coated with an insulating material (PSR), and there is a problem that during surface mounting (SMT), the air inside the via hole expands at a high temperature (e.g., 245°C), which can cause cold soldering defects.

[0011] In addition, when a through-via is formed on the lower side of a component pad, if the opposite side of the pad (e.g., the bottom side) is open, there is a problem that solder may leak out to the lower side of the via hole at high temperatures during surface mounting (SMT).

[0012] Considering these problems, in a conventional printed circuit board and a method for manufacturing the same, a through-via is formed on one side spaced apart along the plate surface direction from the lower side of a component pad.

[0013] However, in a printed circuit board and a method for manufacturing the same in which a throughvia is formed at a point spaced apart along the plate plane direction from the lower side of such component pads, there is a problem that the component density per unit area of ​​the PCB is reduced because each throughvia must be formed at a point spaced apart along the plate plane direction from the component pads.

[0014] As a result, there is a problem in that the size of the PCB increases by that amount.

[0015] In addition, since a throughvia is formed at a point spaced apart from the component pad along the plate plane direction, the signal input to the component pad must be moved to the throughvia spaced apart along the plate plane direction, which causes a problem in that the signal transmission path (length) increases accordingly.

[0016] Consequently, there is a problem in that the signal processing speed decreases as the signal transmission path (length) increases, thereby limiting the improvement of product performance.

[0017] Considering these problems, in some printed circuit boards and manufacturing methods thereof, a method of forming laser vias on the lower side of component pads using a laser is used.

[0018] However, in the case of a printed circuit board equipped with such conventional laser vias and a method for manufacturing the same, there is a problem that the manufacturing cost increases significantly when manufacturing the printed circuit board because expensive laser equipment is required. The problem to be solved

[0019] Accordingly, the present invention aims to provide a printed circuit board and a method for manufacturing the same, wherein vias are formed on one side of a pad along the stacking direction to reduce the size of the substrate.

[0020] In addition, another objective of the present invention is to provide a printed circuit board capable of shortening the signal transmission path and increasing the signal processing speed, and a method for manufacturing the same.

[0021] In addition, another objective of the present invention is to provide a printed circuit board capable of increasing component density at a low cost and a method for manufacturing the same. means of solving the problem

[0022] A printed circuit board according to the present invention for solving the problem described above is characterized by having vias formed on one side of a pad along the stacking direction.

[0023] Specifically, a via hole is provided that penetrates the lowest first layer or the uppermost n-th layer of a substrate having a plurality of layers stacked in layers, a plating layer made of a conductor is formed inside and outside the via hole, and a pad is formed to separate the plating layer exposed on the outer surface from the surroundings among the plating layers, thereby reducing the size of the printed circuit board.

[0024] In addition, the signal input from the pad is transmitted through the plating layer of the via hole, thereby shortening the signal transmission path.

[0025] In addition, signal processing speed can be improved.

[0026] Here, the via hole is formed by drilling.

[0027] By doing so, the increase in manufacturing costs can be suppressed.

[0028] A printed circuit board according to one embodiment of the present invention comprises: a substrate having a first layer disposed at the bottom side along the stacking direction and an n-th layer disposed at the top side, which are stacked in layers; a via hole formed to penetrate the first layer or the n-th layer along the stacking direction; a plating layer formed inside and outside the via hole; and a pad formed by separating the plating layer formed at the end of the via hole from the surroundings.

[0029] Accordingly, the component density can be improved by providing vias on one side of the pad along the stacking direction.

[0030] By doing so, the size of the printed circuit board can be reduced.

[0031] In addition, the signal transmission path between pads and vias can be shortened, and the signal processing speed can be improved.

[0032] In one embodiment of the present invention, the via hole includes an n_n-1 via hole formed by penetrating the n-th layer and the n-1-th layer.

[0033] The plating layer comprises: an n_n-1 inner surface plating layer formed on the inner surface of the n_n-1 via hole; and an n_n-1 end plating layer formed at each of the two ends of the n_n-1 via hole.

[0034] The above pad is formed on the n_n-1st stage plating layer of the n_n-1st stage plating layer of the above n-th via hole that is exposed to the outside.

[0035] Here, an n_n-1 filling portion is provided, which is formed by filling an insulating material into the n_n-1 inner surface plating layer and the n_n-1 end plating layer of the n_n-1 via hole.

[0036] Accordingly, the air layer inside the n_n-1 via hole is reduced (removed), so that cold soldering defects caused by air expansion during surface mounting can be suppressed.

[0037] In addition, since the n_n-1 via hole is blocked during surface mounting, the occurrence of solder leakage through the n_n-1 via hole can be suppressed.

[0038] In one embodiment of the present invention, the via hole includes a second_1 via hole formed by penetrating the second layer and the first layer.

[0039] The plating layer comprises: a second_1 inner surface plating layer formed on the inner surface of the second_1 via hole; and second_1 end plating layers formed at each of the two ends of the second_1 via hole.

[0040] The above pad is formed on the second_1 plating layer exposed to the outside among the second_1 plating layers of the second_1 via hole.

[0041] Here, a 2_1 filling portion is provided, which is formed by filling an insulating material into the 2_1 inner surface plating layer and the 2_1 end plating layer of the 2_1 via hole.

[0042] Accordingly, the air layer inside the 2_1 via hole is reduced (removed), so that cold soldering defects caused by air expansion during surface mounting can be suppressed.

[0043] In addition, since the 2_1 via hole is blocked during surface mounting, the occurrence of solder leakage through the 2_1 via hole can be suppressed.

[0044] In one embodiment of the present invention, the via hole includes a second_1 via hole formed by penetrating the second layer and the first layer, and an n_n-1 via hole formed by penetrating the n-th layer and the n-1-th layer.

[0045] The plating layer comprises: a second_1 inner surface plating layer formed on the inner surface of the second_1 via hole; a second_1 end plating layer formed at each of the two ends of the second_1 via hole; an n_n-1 inner surface plating layer formed on the inner surface of the n_n-1 via hole; and an n_n-1 end plating layer formed at each of the two ends of the n_n-1 via hole.

[0046] The above pad is formed on the 2_1 stage plating layer exposed to the outside among the 2_1 stage plating layers of the 2_1 via hole and on the 9_n-1 stage plating layer exposed to the outside among the 9_n-1 stage plating layers of the 9_n-1 via hole, respectively.

[0047] Herein, a 2_1 filling portion formed by filling an insulating material into the interior of the 2_1 inner plating layer and the 2_1 end plating layer of the 2_1 via hole; and

[0048] An n_n-1 filling portion is provided, which is formed by filling an insulating material into the interior of the n_n-1 inner surface plating layer and the n_n-1 end plating layer of the n_n-1 via hole.

[0049] Accordingly, the air layer inside each of the 2_1 via hole and the n_n-1 via hole is reduced (removed), thereby suppressing the occurrence of cold soldering defects caused by air expansion during surface mounting.

[0050] In addition, when surface mounting, the 2_1 via hole and the n_n-1 via hole are each blocked, so the occurrence of solder leakage through the 2_1 via hole and the n_n-1 via hole can be suppressed.

[0051] In one embodiment of the present invention, the via hole includes a through-via hole formed by penetrating the first layer to the nth layer.

[0052] The plating layer comprises an inner plating layer formed on the inner surface of the throughvia hole and end plating layers formed at each of the two ends of the throughvia hole.

[0053] The above pads are each formed on the end plating layers formed at each of the two ends of the above-mentioned through-hole.

[0054] Here, a filling portion is provided that is formed by filling the interior plating layer and the end plating layer of the above-mentioned through-hole with an insulating material.

[0055] Accordingly, the air layer inside the throughvia hole is reduced (removed), so that cold soldering defects caused by air expansion inside the throughvia hole can be suppressed during surface mounting.

[0056] In addition, when surface-mounted, the throughvia hole is blocked, so solder leakage through the throughvia hole can be suppressed.

[0057] In one embodiment of the present invention, a plate-shaped insulator is provided between each of the first to nth layers, and the via holes are formed by drilling.

[0058] By doing so, the use of expensive laser equipment can be excluded, thereby suppressing the increase in costs when manufacturing the via hole.

[0059] In one embodiment of the present invention, the via hole further includes an intermediate via hole formed by penetrating two or more layers among the second layer to the n-1st layer.

[0060] The plating layer comprises an inner plating layer formed on the inner surface of the intermediate via hole and end plating layers formed at each of the two ends of the intermediate via hole.

[0061] Here, a filling portion is provided, which is formed by filling the interior plating layer and the end plating layer of the intermediate via hole with an insulating material.

[0062] Accordingly, the air inside the intermediate via hole is reduced (removed), so that the occurrence of defects caused by the expansion of air inside the intermediate via hole during surface mounting can be suppressed.

[0063] Meanwhile, according to another aspect of the present invention, a plurality of layers are formed in a layered arrangement with an insulator in between;

[0064] A step of forming a via hole that penetrates through the nth layer positioned at the uppermost side along the stacking direction, or penetrates through the first layer at the lowest side;

[0065] A step of forming a plating layer on the inside and outside of the above via hole; and

[0066] A method for manufacturing a printed circuit board is provided, comprising the step of forming a pad by separating the plating layer exposed to the outside among the plating layers of the via hole from the surroundings.

[0067] By doing so, the integration density of components on the printed circuit board can be increased, and the size of the printed circuit board can be reduced.

[0068] In addition, the signal transmission path can be shortened and the signal processing speed can be improved.

[0069] In one embodiment of the present invention, the step of forming the plating layer is,

[0070] A step of forming an inner plating layer formed on the inner surface of the above via hole; and

[0071] The method includes the step of forming end plating layers formed at each of the two ends of the via hole.

[0072] In one embodiment of the present invention, prior to the step of forming the end plating layer,

[0073] The method further includes the step of forming a filled portion by filling the interior of the inner plating layer with an insulating material.

[0074] As a result, the air inside the via hole can be reduced (excluded), so that defects caused by air expansion inside the via hole during surface mounting can be suppressed.

[0075] In one embodiment of the present invention, prior to the step of forming the via hole,

[0076] The method includes the step of providing a drill capable of penetrating the plurality of layers.

[0077] By doing so, the use of expensive equipment such as lasers can be eliminated, thereby suppressing the increase in manufacturing costs caused by via hole formation.

[0078] In one embodiment of the present invention, the step of forming the via hole comprises the step of forming a second_1 via hole penetrating the second layer and the first layer.

[0079] In one embodiment of the present invention, the step of forming the via hole is,

[0080] The method includes the step of forming an n_n-1 via hole penetrating the n-th layer and the n-1-th layer.

[0081] In one embodiment of the present invention, before the step of forming the pad,

[0082] Step of stacking the above plurality of layers in a layered manner; and

[0083] It further includes the step of insulating the surface of the plurality of layers stacked in layers.

[0084] Meanwhile, according to another aspect of the present invention, a plurality of layers are each formed in a layered arrangement with an insulator in between;

[0085] A step of stacking the plurality of layers such that a first layer is placed at the bottom side along the stacking direction and an n-th layer is placed at the top side;

[0086] A step of forming a via hole including a through-via hole penetrating the nth layer to the first layer;

[0087] A step of forming a plating layer on the inside and outside of the via hole including the above-mentioned through-via hole; and

[0088] A method for manufacturing a printed circuit board is provided, comprising the step of forming a pad by separating the plating layer exposed to the outside among the plating layers of the above-mentioned throughvia hole from the surroundings.

[0089] By doing so, the integration density of components on the printed circuit board can be increased, and the size of the printed circuit board can be reduced.

[0090] In addition, the signal transmission path can be shortened and the signal processing speed can be improved.

[0091] In one embodiment of the present invention, the step of forming a plating layer on the inside and outside of a via hole including the through-via hole comprises: the step of forming an inner plating layer on the inner surface of the through-via hole; and the step of forming an end plating layer on both ends of the through-via hole.

[0092] Herein, prior to the step of forming the end plating layer of the throughvia hole, the method further includes the step of forming a filled portion by filling the interior of the inner plating layer of the throughvia hole with an insulating material.

[0093] The step of forming a via hole including the above-mentioned through-via hole is,

[0094] The method further includes the step of forming an intermediate via hole that is formed by penetrating two or more consecutive layers among the first to nth layers and is not exposed to the outside.

[0095] The step of forming a plating layer on the inside and outside of the via hole including the through-via hole; comprises the step of forming an inner plating layer on the inner surface of the intermediate via hole; and the step of forming an end plating layer on the end of the intermediate via hole.

[0096] The method further includes the step of forming a filled portion by filling an insulating material into the inner plating layer of the intermediate via hole before the step of forming the end plating layer of the intermediate via hole. Effects of the invention

[0097] As described above, according to one embodiment of the present invention, by providing a via hole formed to penetrate a first layer or an n-th layer along the stacking direction, a plating layer formed inside and outside the via hole, and a pad formed by separating the plating layer formed at the end of the via hole from the surroundings, the component density can be improved and the size of the substrate can be reduced. In addition, the signal transmission path can be shortened and the signal processing speed can be improved.

[0098] In addition, by filling the interior of the n_n-1 via hole penetrating the n-th layer and the n-1-th layer with an insulating material to form the n_n-1 filling portion, the air inside the n_n-1 via hole can be reduced. As a result, the occurrence of defects (cold soldering) caused by the expansion of air inside the n_n-1 via hole can be suppressed. Furthermore, the occurrence of solder leakage through the n_n-1 via hole can be suppressed.

[0099] In addition, by filling the interior of the 2_1 via hole penetrating the 2nd layer and the 1st layer with an insulating material to form the 2_1 filling portion, the air inside the 2_1 via hole is reduced, thereby suppressing the occurrence of cold soldering defects caused by air expansion.

[0100] In addition, by filling the inside of the n_n-1 via hole and the 2_1 via hole with an insulating material to provide the n_n-1 filling portion and the 2_1 filling portion, respectively, the air inside each via hole can be reduced (removed). As a result, the occurrence of cold soldering defects caused by the expansion of air inside each via hole due to high temperature during surface mounting can be suppressed.

[0101] In addition, by configuring each via hole to be penetrated by a drill, the use of expensive laser equipment can be eliminated. This allows for suppressing the increase in manufacturing costs associated with the formation of via holes. Brief explanation of the drawing

[0102] FIG. 1 is a cross-sectional view of a key part of a printed circuit board according to one embodiment of the present invention, FIG. 2 is a drawing for explaining a method for manufacturing a printed circuit board according to an embodiment of the present invention, FIGS. 3a to 3i are drawings for explaining the manufacturing process of the printed circuit board of FIG. 1. FIG. 4 is a cross-sectional view of a key part of a printed circuit board according to another embodiment of the present invention, FIGS. 5a to 5i are drawings for explaining the manufacturing process of the printed circuit board of FIG. 4. FIG. 6 is a cross-sectional view of a key part of a printed circuit board according to another embodiment of the present invention, FIG. 7 is a drawing for explaining a method for manufacturing a printed circuit board according to another embodiment of the present invention, FIGS. 8a to 8h are drawings for explaining the manufacturing process of the printed circuit board of FIG. 6. Specific details for implementing the invention

[0103] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. In this specification, identical or similar reference numbers are assigned to identical or similar components even if they are different embodiments, and the description thereof is replaced by the first description. Singular expressions used in this specification include plural expressions unless the context clearly indicates otherwise. Furthermore, in describing the embodiments disclosed in this specification, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may obscure the essence of the embodiments disclosed in this specification. Additionally, it should be noted that the attached drawings are intended only to facilitate understanding of the embodiments disclosed in this specification, and should not be interpreted as limiting the technical concept disclosed in this specification.

[0104] FIG. 1 is a cross-sectional view of a key part of a printed circuit board according to one embodiment of the present invention. As shown in FIG. 1, the printed circuit board (100) of the present embodiment comprises a substrate (110), a via hole (210), a plating layer (230a), and a pad (270).

[0105] The above substrate (110) has a plurality of layers (110L) that are stacked in a layered manner.

[0106] In this embodiment, the stacking direction of the plurality of layers (110L) refers to the vertical direction of the drawing.

[0107] In this embodiment, the plurality of layers (110L) may be composed of circuit layers made of a conductor (e.g., copper (Cu)).

[0108] The above plurality of layers (110L) have a first layer (110L1) to an nth layer (110Ln) along the stacking direction.

[0109] The above plurality of layers (110L) are spaced apart from each other along the stacking direction.

[0110] A plate-shaped insulator (110I) is provided between each of the above plurality of layers (110L).

[0111] By this, the plurality of layers (110L) (circuit layers (110L)) can be insulated from each other.

[0112] The above plurality of layers (110L) are implemented as a first layer (110L1) to a fourth layer (110L4).

[0113] An insulator (110I) is provided between the first layer (110L1) to the fourth layer (110L4).

[0114] The insulator (110I) is implemented in a plate shape as a composite material called prepreg, which is formed by impregnating a liquid synthetic resin, such as epoxy resin, into a fiber reinforcing agent, such as glass fiber or carbon fiber.

[0115] In this embodiment, the plurality of layers (110L) may be provided on one or both sides of the plate-shaped insulator (110I).

[0116] In this embodiment, the plurality of layers (110L) are implemented as a first layer (110L1) to a fourth layer (110L4).

[0117] In this embodiment, the insulator (110I) comprises a first insulator (110I1) to a third insulator (110I3).

[0118] Specifically, for example, the first layer (110L1) may be formed on the bottom surface of the first insulator (110I1), and the second layer (110L2) may be formed on the bottom surface of the second insulator (110I2). The third layer (110L3) may be formed on the bottom surface of the third insulator (110I3), and the nth layer (110Ln) (the fourth layer (110L4)) may be provided on the top surface of the third insulator (110I3).

[0119] In this embodiment, the plurality of layers (110L) are exemplified as being implemented as a first layer (110L1) to a fourth layer (110L4), but this is merely an example and is not limited thereto. That is, the plurality of layers (110L) may be implemented to have 6 layers, 8 layers, or 10 layers.

[0120] An insulating layer (150) may be formed on both side surfaces (bottom surface and top surface) along the stacking direction of the substrate (110).

[0121] The insulating layer (150) is formed, for example, by coating the outer surface of a plated (copper foil) circuit layer (in this embodiment, the first layer (110L1) and the fourth layer (110L4)) with permanent ink.

[0122] The above insulating layer (150) comprises, for example, a lower insulating layer (1501) coated on the outer surface of the first layer (110L1) and an upper insulating layer (1502) coated on the outer surface of the nth layer (110Ln) (fourth layer (110L4)).

[0123] The above substrate (110) is provided with a via hole (210) formed through the uppermost layer, the n-th layer (110Ln) (in this embodiment, the fourth layer (110L4)).

[0124] In this embodiment, the via hole (210) comprises an n_n-1 via hole (2101) formed by penetrating the n-th layer (110Ln) and the n-1-th layer (110Ln-1). In this embodiment, since the uppermost layer, the n-th layer (110Ln), is the fourth layer (110L4), the n_n-1 via hole (2101) may be referred to as the 4_3 via hole (2101).

[0125] In this embodiment, the via hole (210) can be formed by a drill (220).

[0126] Specifically, the via hole (210) (the n-1st via hole (2101)) can be formed by drilling through the nth layer (110Ln), the third insulator (110I3), and the n-1st layer (110Ln-1) by a drill (220).

[0127] The above via hole (210) can be implemented, for example, with an inner diameter of 0.6 mm.

[0128] In this embodiment, the inner diameter of the via hole (210) is 0.6 mm, but this is merely an example and the size can be adjusted.

[0129] A plating layer (230) can be formed in the above via hole (210) (n_n-1 via hole (2101)).

[0130] In this embodiment, the plating layer (230) comprises an n_n-1 inner surface plating layer (2301) formed on the inner surface of the n_n-1 via hole (2101) and an n_n-1 end surface plating layer (2302) formed on the end of the n_n-1 via hole (2101).

[0131] Here, the plating layer (230) (the n_n-1 inner surface plating layer (2301), the n_n-1 end plating layer (2302)) can be implemented, for example, by copper (Cu) plating.

[0132] Accordingly, the n-th layer (110Ln) (4th layer (110L4)) and the n-1st layer (110Ln-1) (3rd layer (110L3)) can be electrically connected. Additionally, a signal transmission path can be formed between the n-th layer (110Ln) and the n-1st layer (110Ln-1).

[0133] The above n_n-1 via hole (2101), n_n-1 inner surface plating layer (2301), and n_n-1 end plating layer (2302) may be referred to as vias.

[0134] In this embodiment, the via may include the n_n-1 via hole (2101), the n_n-1 inner surface plating layer (2301), and the n_n-1 end plating layer (2302).

[0135] In this embodiment, the first layer (110L1) to the nth layer (110Ln) and the plating layer (230) are depicted differently (distinguished) for convenience of the drawing description, but in reality, they can be formed of the same material (e.g., copper (Cu)).

[0136] The interior of the plating layer (230) is provided with a filling portion (250) formed by filling with an insulating material.

[0137] Specifically, the n_n-1 filling portion (2501) is provided inside the n_n-1 via hole (2101).

[0138] By doing so, the air inside the n_n-1 via hole (2101) can be reduced (removed).

[0139] According to this configuration, when surface mounted, the occurrence of air expansion inside the n_n-1 via hole (2101) due to high temperature can be suppressed.

[0140] By doing so, the occurrence of cold soldering defects caused by air expansion of the solder (290) coupled to the pad (270) described later can be suppressed.

[0141] In this embodiment, the plating layer (230) (the n_n-1th plating layer (2302)) among the plating layers (230) that is exposed to the outside may be provided with a pad (270) formed separately from the surroundings.

[0142] The pad (270) can be formed to be larger than the via hole (210), for example.

[0143] In this embodiment, the pad (270) may be configured to include the n_n-1 inner surface plating layer (2301), the end of the n_n-1 end plating layer (2302), and a part of the n-th layer (110Ln).

[0144] The above pad (270) can be implemented in a circular shape, for example.

[0145] In this embodiment, the pad (270) is exemplified as being implemented in a circular shape, but this is merely an example, and it may be implemented in a polygonal shape such as a square, pentagon, hexagon, octagon, or ellipse.

[0146] A component (300) can be attached (mounted) to the above pad (270) by solder (290).

[0147] FIG. 2 is a drawing for explaining a method for manufacturing a printed circuit board according to an embodiment of the present invention, and FIGS. 3a to 3i are drawings for explaining the manufacturing process of a printed circuit board of FIG. 1. As illustrated in FIG. 2, a method for manufacturing a printed circuit board (100) according to one embodiment of the present invention comprises the steps of: forming a plurality of layers (110L) arranged in layers with an insulator (110I) in between (S110); forming a via hole (210) that is penetrated by including an n-th layer (110Ln) arranged at the uppermost side along the stacking direction or by including a first layer (110L1) at the lowermost side (S130); forming a plating layer (230) inside and outside the via hole (210) (S140); and forming a pad (270) by separating the plating layer (230) exposed to the outside from the surroundings among the plating layers (230) of the via hole (210) (S180).

[0148] As illustrated in FIG. 3a, a plurality of layers (110L) comprises a first layer (110L1) to an nth layer (110Ln) spaced apart in the stacking direction. In this embodiment, a plurality of layers (110L) is exemplified as being composed of a first layer (110L1) to a fourth layer (110L4), but this is merely an example and is not limited thereto.

[0149] Multiple layers (110L) may be circuit layers formed of copper (Cu).

[0150] Multiple layers (110L) are provided on one or both sides of the insulator (110I).

[0151] In this embodiment, the insulator (110I) is composed of a first insulator (110I1) to a third insulator (110I3).

[0152] Specifically, the first layer (110L1) is provided on the bottom surface of the first insulator (110I1).

[0153] The second layer (110L2) is provided on the bottom surface of the second insulator (110I2).

[0154] The third layer (110L3) is provided on the bottom surface of the third insulator (110I3), and the fourth layer (110L4) is provided on the top surface of the third insulator (110I3).

[0155] Before the step (S130) of forming the via hole (210), a step (S120) of providing a drill (220) is provided.

[0156] As shown in FIG. 3b, the via hole (210) (the n_n-1 via hole (2101)) is formed by drilling (220).

[0157] In this embodiment, the via hole (210) includes an n_n-1 via hole (2101) formed by penetrating the n-th layer (110Ln) and the n-1-th layer (110Ln-1).

[0158] Specifically, the n_n-1 via hole (2101) is formed by penetrating the n-th layer (110Ln), the third insulator (110I3), and the n-1 layer (110Ln-1). In this embodiment, since the n-th layer (110Ln) is the fourth layer (110L4), the n_n-1 via hole (2101) refers to the fourth_3 via hole (2101).

[0159] The step (S140) of forming a plating layer (230) on the inside and outside of the via hole (210) comprises the step (S145) of forming an inner plating layer (2301) on the inner surface of the via hole (210) and the step (S155) of forming end plating layers (2302) formed at each end of the via hole (210).

[0160] As illustrated in FIG. 3c, an inner plating layer (2301) (the n_n-1 inner plating layer (2301)) is formed on the inner surface of the via hole (210) (the n_n-1 via hole (2101)) by copper (Cu) plating. The n_n-1 inner plating layer (2301) is formed on the n-th layer (110Ln), the third insulator (110I3), and the n-1 layer (110Ln-1), respectively.

[0161] Before the step (S155) of forming the end plating layer (2302), the method further comprises the step (S150) of forming a filling portion (250) by filling the interior of the inner plating layer (2301) with an insulating material (resin).

[0162] As shown in FIG. 3d, an insulating material (resin) is filled inside the inner plating layer (2301) (the n_n-1 inner plating layer (2301)) to form a filling portion (250) (the n_n-1 filling portion (2501)).

[0163] As illustrated in FIG. 3e, end plating layers (2302) (n_n-1 end plating layers (2302)) are formed at both ends of the via hole (210) (n_n-1 via hole (2101)) along the stacking direction. Here, the end plating layers (2302) are configured to be planar with the n-th layer (110Ln) and the n-1-th layer (110Ln-1).

[0164] After the step (S155) of forming the end plating layer (2302), the method further comprises the step (S160) of stacking the plurality of layers (110L).

[0165] When a plating layer (230) is formed (S140) on the inside and outside of the via hole (210), a plurality of layers (110L) are stacked as shown in FIG. 3f.

[0166] After the step (S160) of stacking the plurality of layers (110L), the step (S170) of joining the plurality of layers (110L) is further provided.

[0167] As shown in Fig. 3g, a plurality of stacked layers (110L) are joined (heat bonded, hot press).

[0168] After the step (S170) of joining the above plurality of layers (110L), the end plating layer (2302) that is exposed to the outside among the end plating layers (2302) is separated from the surroundings to form a pad (270).

[0169] As shown in FIG. 3h, the n_n-1st stage plating layer (2302) that is exposed to the outside among the n_n-1st stage plating layers (2302) is separated from the surroundings to form a pad (270).

[0170] The pad (270) may be formed to be larger than the diameter of the via hole (210) (the n-1st via hole (2101)), for example.

[0171] The above pad (270) may be configured to include a portion of the n-th layer (110Ln).

[0172] The above pad (270) may be configured in a circular shape, for example, and a cut portion (280) is provided around the pad (270) such that a part of the n-th layer (110Ln) is cut away so that the pad (270) is spaced apart from the n-th layer (110Ln).

[0173] After the step (S180) of forming the pad (270), a step (S190) of insulating the surface of the lowest layer (first layer (110L1)) and the uppermost layer (n-th layer (11OLn)) of the plurality of layers (110L) is further provided.

[0174] As shown in FIG. 3i, an insulating layer (150) is formed on the outer surface (bottom surface) of the first layer (110L1) and on the outer surface (top surface) of the nth layer (110Ln).

[0175] Here, the insulating layer (150) can be formed, for example, by coating the outer surface of the first layer (110L1) and the nth layer (110Ln) (the fourth layer (110L4)) with permanent ink.

[0176] After the step (S190) of insulating the plurality of layers (110L) above, a step (S200) of mounting a component (300) by interposing solder (290) on the pad (270) is further provided.

[0177] Referring again to FIG. 1, a component (300) is mounted on the upper surface of the pad (270) with solder (290) interposed therebetween.

[0178] With this configuration, the signal input from the component (300) is transmitted to the third layer (110L3) via the solder (290) and pad (270) and via the inner plating layer (2301) (the n_n-1 inner plating layer (2301)).

[0179] FIG. 4 is a cross-sectional view of a key part of a printed circuit board according to another embodiment of the present invention, and FIGS. 5a to 5i are drawings for explaining the manufacturing process of the printed circuit board of FIG. 4.

[0180] As shown in FIG. 4, the printed circuit board (100a) of the present embodiment comprises a substrate (110), via holes (210a), a plating layer (230a), and a pad (270a).

[0181] The above substrate (110) has a plurality of layers (110L) that are stacked in a layered manner.

[0182] In this embodiment, each of the plurality of layers (110L) may be composed of a circuit layer formed of copper (Cu).

[0183] The above plurality of layers (110L) comprises a first layer (110L1) to an nth layer (110Ln) that are stacked from the bottom along the stacking direction.

[0184] Between the above plurality of layers (110L), a plate-shaped insulator (110I) (e.g., prepreg) is provided.

[0185] Accordingly, the plurality of layers (110L) can be insulated from one another by the insulator (110I). In this embodiment, the plurality of layers (110L) comprises a first layer (110L1) to a fourth layer (110L4).

[0186] In this embodiment, the plurality of layers (110L) is exemplified as having a first layer (110L1) to a fourth layer (110L4), but this is merely an example and is not limited thereto.

[0187] The plurality of layers (110L) may be provided on one or both sides of the insulator (110I).

[0188] The above insulator (110I) is composed of a first insulator (110I1) to a third insulator (110I3) spaced apart in layers.

[0189] Specifically, in this embodiment, the first layer (110L1) is provided on the bottom surface of the first insulator (110I1), and the second layer (110L2) is provided on the top surface of the first insulator (110I1).

[0190] The third layer (110L3) is provided on the bottom surface of the third insulator (110I3), and the nth layer (110Ln) (fourth layer (110L4)) is provided on the top surface of the third insulator (110I3).

[0191] A second insulator (110I2) is inserted and disposed between the second layer (110L2) and the third layer (110L3).

[0192] The second insulator (110I2) is placed between the second layer (110L2) and the third layer (110L3).

[0193] By doing so, the second layer (110L2) and the third layer (110L3) can be insulated from each other.

[0194] The above via hole (210a) is provided with, for example, an n_n-1 via hole (210a1) that penetrates the n-th layer (110Ln) and the n-1-th layer (110Ln-1).

[0195] The above via hole (210a) is configured, for example, by having a second_1 via hole (210a2) formed by penetrating the second layer (110L2) and the first layer (110L1).

[0196] The above via hole (210a) can be implemented with a diameter of, for example, 0.6 mm.

[0197] The above via hole (210a) can be formed by a drill (220).

[0198] By doing so, the increase in cost during the manufacture of the via hole (210a) can be suppressed.

[0199] The above plating layers (230a) are each formed by copper (Cu) plating.

[0200] The plating layer (230a) comprises, for example, an n_n-1 inner surface plating layer (230a1) formed on the inner surface of the n_n-1 via hole (210a1) and n_n-1 end plating layers (230a2) formed on both ends of the n_n-1 via hole (210a1).

[0201] By this, the n-th layer (110Ln) and the n-1-th layer (110Ln-1) can be electrically connected to each other.

[0202] The plating layer (230a) includes, for example, a second_1 inner surface plating layer (230a3) formed on the inner surface of the second_1 via hole (210a2) and a second_1 end surface plating layer (230a4) formed on both ends of the second_1 via hole (210a2).

[0203] By this, the first layer (110L1) and the second layer (110L2) can be electrically connected to each other.

[0204] Here, the n_n-1 via hole (210a1), the n_n-1 inner surface plating layer (230a1), and the n_n-1 end plating layer (230a2) may be referred to, for example, as upper vias.

[0205] Additionally, the second_1 via hole (210a2), the second_1 inner plating layer (230a3), and the second_1 terminal plating layer (230a4) may be referred to, for example, as lower vias.

[0206] In this embodiment, the first layer (110L1) to the nth layer (110Ln) and each plating layer (230a) are depicted as distinct from one another for convenience of description, but in reality, they are all formed from the same material (copper (Cu)).

[0207] Meanwhile, the interior of the plating layer (230a) is provided with a filling portion (250a) filled with an insulating material (e.g., resin).

[0208] Specifically, the n_n-1 inner plating layer (230a1) and the n_n-1 end plating layer (230a2) are provided with an n_n-1 filling portion (250a1) inside.

[0209] By doing so, the air inside the n_n-1 via hole (210a1) is reduced (removed), and the occurrence of cold soldering defects caused by air expansion during surface mounting can be suppressed.

[0210] The interior of the above-mentioned second_1 inner plating layer (230a3) and second_1 terminal plating layer (230a4) is provided with a second_1 filling portion (250a2) filled with an insulating material (e.g., resin).

[0211] By doing so, the air inside the 21st via hole (210a2) is reduced, and the occurrence of cold soldering defects caused by air expansion during surface mounting can be suppressed.

[0212] In this embodiment, among the plating layers (230a), the plating layer (230a) exposed to the outside is formed with a pad (270a) that is separated from the surroundings (circuit layer of the n-th layer (110Ln) and the first layer (110L1)). A cut-out portion (280a) is formed around the perimeter of the pad (270a) to separate it from the circuit layer.

[0213] Specifically, an upper pad (270a2) is formed on the n_n-1st plating layer (230a2) that is exposed to the outside among the n_n-1st plating layers (230a2). An upper cut-out portion (280a2) is formed around the upper pad (270a2) in which a part of the n_n-1st layer is cut out.

[0214] Additionally, a lower pad (270a1) is formed on the second_1st stage plating layer (230a4) that is exposed to the outside among the second_1st stage plating layers (230a4). A lower cut-out portion (280a1) is formed around the perimeter of the lower pad (270a1), in which a part of the first layer (110L1) is cut out.

[0215] A component (300a) is mounted on each of the above pads (270a) (upper pad (270a2), lower pad (270a1)) by interposing solder (290a).

[0216] Specifically, a lower component (300a1) is mounted on the lower pad (270a1) via a lower solder (290a1), and an upper component (300a2) is mounted on the upper pad (270a2) via an upper solder (290a2).

[0217] Hereinafter, the manufacturing process of a printed circuit board (100a) will be described with reference to FIGS. 5a to 5i.

[0218] As illustrated in FIG. 5a, a plurality of layers (110L) comprises a first layer (110L1) to an nth layer (110Ln) spaced apart from each other along the stacking direction. In this embodiment, the plurality of layers (110L) comprises a first layer (110L1) to a fourth layer (110L4).

[0219] The above plurality of layers (110L) are each provided on the surface of an insulator (110I) (e.g., prepreg).

[0220] The above insulator (110I) comprises a first insulator (110I1) to a third insulator (110I3) spaced apart along the stacking direction.

[0221] Specifically, the first layer (110L1) and the second layer (110L2) are respectively provided on the bottom surface and the top surface of the first insulator (110I1). The third layer (110L3) and the fourth layer (110L4) are respectively provided on the bottom surface and the top surface of the third insulator (110I3). The second insulator (110I2) is inserted between the second layer (110L2) and the third layer (110L3). By doing so, the second layer (110L2) and the third layer (110L3) can be insulated from each other.

[0222] As shown in FIG. 5b, the n-th layer (110Ln), the third insulator (110I3) and the n-1st layer (110Ln-1), and the second layer (110L2), the first insulator (110I1) and the first layer (110L1) are each penetrated by a drill (220) to form via holes (210a) (n_n-1st via hole (210a1) and 2_1st via hole (210a2)).

[0223] In the interior of each of the above via holes (210a) (the n_n-1 via hole (210a1) and the 2_1 via hole (210a2)), an inner plating layer (230a1, 230a3) is formed, respectively, as shown in FIG. 5C. In the interior of the n_n-1 via hole (210a1), the n_n-1 inner plating layer (230a1) is formed by copper (Cu) plating. In the interior of the 2_1 via hole (210a2), the 2_1 inner plating layer (230a3) is formed by copper (Cu) plating.

[0224] Meanwhile, as shown in FIG. 5d, an insulating material (e.g., resin) is filled into the interior of each of the above inner plating layers (230a1, 230a3) to form a filling portion (250a) in each. An n_n-1 filling portion (250a1) is formed inside the n_n-1 inner plating layer (230a1). A second_1 filling portion (250a2) is formed inside the second_1 inner plating layer (230a3).

[0225] As shown in FIG. 5e, end plating layers (230a2, 230a4) are formed at both ends of each via hole (210a) (n_n-1 via hole (210a1), 2_1 via hole (210a2)) by copper (Cu) plating.

[0226] An n_n-1 end plating layer (230a2) is formed at each end of the n_n-1 via hole (210a1).

[0227] A second-first plating layer (230a4) is formed at each end of the second-first via hole (210a2).

[0228] When end plating layers (230a2, 230a4) are formed at each end of each of the above via holes, the plurality of layers (110L) are arranged in layers along the stacking direction as shown in FIG. 5f.

[0229] As illustrated in Fig. 5g, a plurality of layers (110L) arranged in a layered manner are joined together (e.g., heat-bonded (hot press)).

[0230] When the above plurality of layers (110L) are joined, the end plating layers (230a2, 230a4) exposed to the outside among the plating layers (230a) are cut away from the surroundings to form a pad (270a) of a preset shape.

[0231] As shown in FIG. 5h, the perimeter of the n_n-1 plating layer (230a2) exposed to the outside among the n_n-1 plating layer (230a2) and the 2_1 plating layer (230a4) exposed to the outside among the 2_1 plating layer (230a4) are cut to be separated from the surroundings to form an upper pad (270a2) and a lower pad (270a1), respectively.

[0232] An upper cut-out section (280a2) is formed around the perimeter of the upper pad (270a2) in which a portion of the n-th layer (110Ln) (4th layer (110L4)) is removed.

[0233] In addition, a lower cut-out portion (280a1) is formed around the perimeter of the lower pad (270a1) in which a portion of the first layer (110L1) is removed.

[0234] When the above pads (270a) are each formed, the outer surfaces of the first layer (110L1) and the n-th layer (110Ln) are coated with an insulating material to form an insulating layer (150) for each.

[0235] The insulating layer (150) comprises a lower insulating layer (1501) coated on the outer surface of the first layer (110L1) and an upper insulating layer (1502) coated on the outer surface of the nth layer (110Ln).

[0236] The insulating material forming the insulating layer (150) may be, for example, permanent ink.

[0237] When an insulating layer (150) is formed on the surface of the n-th layer (110Ln) and the surface of the first layer (110L1), a component (300a) is mounted on each pad (270a) by means of solder (290a) (see FIG. 4). Specifically, a lower component (300a1) is mounted on the lower pad (270a1) by means of lower solder (290a1), and an upper component (300a2) is mounted on the upper pad (270a2) by means of upper solder (290a2).

[0238] With this configuration, a signal input from the upper component (300a2) of the substrate (110) is transmitted to the third layer (110L3) via the upper solder (290a2) and upper pad (270a2) and via the inner plating layer (230a) (the n_n-1 inner plating layer (230a1)).

[0239] Additionally, a signal input from the lower component (300a1) of the substrate (110) is transmitted to the second layer (110L2) via the lower solder (290a1) and lower pad (270a1), and via the inner plating layer (230a) (the second_1 inner plating layer (230a3)).

[0240] FIG. 6 is a cross-sectional view of a key part of a printed circuit board according to another embodiment of the present invention.

[0241] As shown in FIG. 6, the printed circuit board (100b) of the present embodiment comprises a substrate (110), via holes (210b), a plating layer (230b), and a pad (270b).

[0242] The above substrate (110) has a plurality of layers (110L) that are stacked in a layered manner.

[0243] In this embodiment, the plurality of layers (110L) are circuit layers formed of, for example, a conductor (copper (Cu)).

[0244] The plurality of layers (110L) comprises a first layer (110L1) to an nth layer (110Ln) along the stacking direction. In this embodiment, the plurality of layers (110L) is exemplified as comprising a first layer (110L1) to a fourth layer (110L4), but is not limited thereto.

[0245] Between the plurality of layers (110L) above, a plate-shaped insulator (110I) (e.g., prepreg) is provided.

[0246] The above insulator (110I) comprises, for example, a first insulator (110I1) to a third insulator (110I3) spaced apart along the thickness direction.

[0247] The plurality of layers (110L) may be provided, for example, on one or both sides of the insulator (110I).

[0248] Specifically, for example, the first layer (110L1) may be provided on the bottom surface of the first insulator (110I1).

[0249] The second layer (110L2) may be provided on the bottom surface of the second insulator (110I2).

[0250] The third layer (110L3) may be provided on the bottom surface of the third insulator (110I3), and the fourth layer (110L4) may be provided on the top surface of the third insulator (110I3).

[0251] An insulating layer (150) is provided on both surfaces along the stacking direction of the substrate (110).

[0252] The insulating layer (150) is formed by coating the surface of the first layer (110L1) and the surface of the nth layer (110Ln) with, for example, indelible ink.

[0253] The insulating layer (150) comprises a lower insulating layer (1501) coated on the surface of the first layer (110L1) and an upper insulating layer (1502) coated on the surface of the nth layer (110Ln).

[0254] The above substrate (110) is provided with a via hole (210b) that penetrates at least two layers.

[0255] The above via hole (210b) can be formed by penetrating, for example, with a drill (220).

[0256] By doing so, the use of expensive equipment can be excluded when forming the via hole (210b), thereby preventing a significant increase in manufacturing costs.

[0257] The above via hole (210b) can be formed with a diameter of, for example, 0.6 mm.

[0258] Specifically, the via hole (210b) is provided with a through-via hole (210b1) formed by penetrating the nth layer (110Ln) to the first layer (110L1).

[0259] The above through-hole (210b1) can be formed by sequentially penetrating the n-th layer (110Ln) (4th layer (110L4)), the third insulator (110I3), the third layer (110L3), the second insulator (110I2), the second layer (110L2), the first insulator (110I1), and the first layer (110L1).

[0260] The above via hole (210b) is formed by penetrating two consecutive layers among the first layer (110L1) to the nth layer (110Ln), and has an intermediate via hole (210b2) that is not exposed to the outside.

[0261] The above intermediate via hole (210b2) can be formed by sequentially penetrating the n-th layer (110Ln) (4th layer (110L4)), the third insulator (110I3), the third layer (110L3), the second insulator (110I2), the second layer (110L2), the first insulator (110I1), and the first layer (110L1).

[0262] In this embodiment, the intermediate via hole (210b2) is exemplified as being formed by penetrating the first layer (110L1) from the nth layer (110Ln), but this is merely an example and is not limited thereto.

[0263] A plating layer (230b) is formed on the inside and outside of the via hole (210b). The plating layer (230b) is formed, for example, by copper (Cu) plating.

[0264] Specifically, an inner plating layer (230b1) is formed on the inner surface of the above-mentioned through-hole (210b1).

[0265] End plating layers (230b2) are formed at both ends of the above-mentioned through-hole (210b1) along the stacking direction.

[0266] An inner plating layer (230b3) is formed on the inner surface of the above intermediate via hole (210b2).

[0267] End plating layers (230b4) are formed at each end of the intermediate via hole (210b2) along the stacking direction.

[0268] In this embodiment, the plating layers (230b4) at both ends of the intermediate via hole (210b2) are placed inside the insulating layer (150) and are therefore not exposed to the outside.

[0269] Here, the end plating layers (230b2) on both sides of the above-mentioned through-hole (210b1) are exposed to the outside.

[0270] The interior of the plating layer (230b) is provided with a filling portion (250b) formed by filling with an insulating material.

[0271] The above filling portion (250b) comprises a first filling portion (250b1) formed on the inner side of the through-via hole (210b1) and a second filling portion (250b2) formed on the inner side of the intermediate via hole (210b2).

[0272] Specifically, the end plating layers (230b2) on both sides of the throughvia hole (210b1) are cut away from the surroundings (the nth layer (110Ln) and the first layer (110L1)) to form pads (270b) respectively. The pads (270b) formed on both sides of the throughvia hole (210b1) include a lower pad (270b1) formed on the lower part of the substrate (110) and an upper pad (270b2) formed on the upper part of the substrate (110).

[0273] The pad (270b) is formed with a size larger than the via hole (210b).

[0274] Accordingly, a portion of the conductor around the inner plating layer (230b1, 230b3) is formed as a pad (270b).

[0275] A cut-out section (280b) in which a portion is cut out is formed around the perimeter of the pad (270b). Specifically, a lower cut-out section (280b1) is formed around the perimeter of the lower pad (270b1), and an upper cut-out section (280b2) is formed around the perimeter of the upper pad (270b2).

[0276] A component (300b) is mounted on each of the pads (270b1, 270b2) on both sides of the above-mentioned through-hole (210b1) by interposing solder (290b).

[0277] Specifically, a lower component (300b1) is mounted on the lower pad (270b1) via a lower solder (290b1), and an upper component (300b2) is mounted on the upper pad (270b2) via an upper solder (290b2).

[0278] FIG. 7 is a drawing for explaining a method for manufacturing a printed circuit board according to another embodiment of the present invention, and FIGS. 8a to 8h are drawings for explaining the manufacturing process of the printed circuit board of FIG. 6.

[0279] As illustrated in FIG. 7, a method for manufacturing a printed circuit board (100b) according to an embodiment of the present invention comprises: a step (S310) of forming a first layer (110L1) to an n-th layer (110Ln) respectively arranged in layers with an insulator (110I) in between; a step (S320) of stacking the first layer (110L1) to the n-th layer (110Ln) such that the first layer (110L1) is arranged at the bottom side along the stacking direction and the n-th layer (110Ln) is arranged at the top side; and a step (S350) of forming a via hole (210b) including a through-via hole (210b1) penetrating the first layer (110L1) from the n-th layer (110Ln). The method comprises the step (S360) of forming a plating layer (230b) on the inside and outside of a via hole (210b) including the above-mentioned through-via hole (210b1); and the step (S380) of forming a pad (270b) by separating the plating layer (230b) exposed to the outside from the surroundings among the plating layers (230b) of the above-mentioned through-via hole (210b1).

[0280] As illustrated in FIG. 8a, a plurality of layers (110L) of a substrate (110) comprises a first layer (110L1) to an nth layer (110Ln) spaced apart in the stacking direction. In this embodiment, the plurality of first layers (110L1) to nth layers (110Ln) are exemplified as being implemented as a first layer (110L1) to a fourth layer (110L4), but are not limited thereto.

[0281] The first layer (110L1) to the nth layer (110Ln) are spaced apart along the stacking direction, and an insulator (110I) is provided between each of the first layer (110L1) to the nth layer (110Ln). By doing so, the plurality of first layers (110L1) to the nth layer (110Ln) can be insulated from each other.

[0282] The above plurality of first layers (110L1) to nth layers (110Ln) are circuit layers formed of a conductor (e.g., copper (Cu)).

[0283] The insulator (110I) can be implemented, for example, as prepreg.

[0284] The above insulator (110I) comprises a first insulator (110I1) to a third insulator (110I3) implemented in a plate shape.

[0285] In this embodiment, the first layer (110L1) is provided on the bottom surface of the first insulator (110I1), and the second layer (110L2) is provided on the bottom surface of the second insulator (110I2). The third layer (110L3) is provided on the bottom surface of the third insulator (110I3), and the fourth layer (110L4) is provided on the top surface of the third insulator (110I3).

[0286] After the stacking step (S320) of the plurality of layers, the method further comprises a step (S330) of joining the plurality of layers (110L).

[0287] The plurality of first layers (110L1) to nth layers (110Ln) are laminated and then bonded, as shown in FIG. 8b. Here, the plurality of first layers (110L1) to nth layers (110Ln) can be bonded together, for example, by being compressed in a high-temperature vacuum.

[0288] A via hole (210b) is formed in the bonded substrate (110).

[0289] Before the step (S350) of forming the via hole (210b), a step (S340) of preparing a drill (220) is provided.

[0290] In the mutually bonded substrate (110), a via hole (210b) is formed by the drill (220) as shown in FIG. 8c.

[0291] The above via hole (210b) is provided with a through via hole (210b1) formed to pass through sequentially from the nth layer (110Ln) to the first layer (110L1).

[0292] On one side of the above through-via hole (210b1), an intermediate via hole (210b2) is provided that penetrates two consecutive layers among the first layer (110L1) to the nth layer (110Ln) and is not exposed to the outside.

[0293] In this embodiment, the intermediate via hole (210b2) is configured to be formed by penetrating the first layer (110L1) from the nth layer (110Ln), but this is merely an example and is not limited thereto.

[0294] A plating layer (230b) is formed on the inside and outside of the above via hole (210b) (through via hole (210b1), intermediate via hole (210b2)) by copper (Cu) plating.

[0295] The step (S360) of forming a plating layer (230b) on the inside and outside of a via hole (210b) including the above-mentioned through-via hole (210b1) comprises the step (S365) of forming an inner plating layer (230b) on the inner surface of the above-mentioned via hole (210b) and the step (S375) of forming end plating layers (230b) on both ends of the above-mentioned via hole (210b).

[0296] In this embodiment, the step (S365) of forming the inner plating layer (230b) includes the step of forming an inner plating layer (230b1) on the inner surface of the through-via hole (210b1) and the step of forming an inner plating layer (230b3) on the inner surface of the intermediate via hole (210b2).

[0297] The step (S375) of forming end plating layers (230b) at both ends of the via hole (210b) comprises the step of forming end plating layers (230b2) at both ends of the through via hole (210b1) and the step of forming end plating layers (230b4) at both ends of the intermediate via hole (210b2).

[0298] As shown in FIG. 8d, an inner plating layer (230b) is formed on the inner surface of the through-via hole (210b1) and the intermediate via hole (210b2) by copper (Cu) plating.

[0299] Meanwhile, prior to the step (S375) of forming the end plating layer (230b) of the via hole (210b), the method further comprises the step (S370) of forming a filled portion (250b) by filling the interior of the via hole (210b) with an insulating material (resin).

[0300] As shown in FIG. 8e, the insulating material (resin) is filled into the interior of the through-via hole (210b1) and the interior of the intermediate via hole (210b2) to form a filled portion (250b) respectively.

[0301] The above filling portion (250b) comprises a first filling portion (250b1) filled inside the through-via hole (210b1) and a second filling portion (250b2) filled inside the intermediate via hole (210b2).

[0302] As shown in FIG. 8f, end plating layers (230b) are formed by copper plating on both sides of the through-via hole (210b1) and the intermediate via hole (210b2) along the stacking direction of the substrate (110).

[0303] Accordingly, the n-th layer (110Ln) (4th layer (110L4)), n-1st layer (110Ln-1) (3rd layer (110L3)), 2nd layer (110L2) and 1st layer (110L1) can be electrically connected to each other.

[0304] Meanwhile, as shown in FIG. 8g, the end plating layers (230b2) on both sides of the throughvia hole (210b1) along the stacking direction of the substrate (110) can be cut away from the surroundings to form a pad (270b).

[0305] In this embodiment, the pad (270b) may be configured to be separated from the n-th layer (110Ln) and the first layer (110L1), respectively. A cut-out portion (280b) is provided around the perimeter of the pad (270b), in which the n-th layer (110Ln) and the first layer (110L1) are respectively cut out to form a cut-out portion.

[0306] The pad (270b) can be implemented with a size larger than the diameter of the through-hole (210b1), for example.

[0307] The above pad (270b) comprises an upper pad (270b2) positioned on the upper side along the thickness direction (upward and downward direction in the drawing) of the substrate (110) and a lower pad (270b1) positioned on the lower side.

[0308] The upper pad (270b2) may be configured to include, for example, a part of the n-th layer (110Ln) (4th layer (110L4)).

[0309] An upper cut-out section (280b2) is provided around the perimeter of the upper pad (270b2), in which a portion of the n-th layer (110Ln) (4th layer (110L4)) is cut off.

[0310] The lower pad (270b1) may be formed, for example, by including a part of the first layer (110L1).

[0311] A lower cut-out section (280b1) is provided around the perimeter of the lower pad (270b1), in which a portion of the first layer (110L1) is cut (removed).

[0312] Meanwhile, after the step (S380) of forming a pad (270b) by separating the plating layer (230b) exposed to the outside from the surroundings among the plating layers (230b) of the above-mentioned through-via hole (210b1), an additional step (S390) of insulating treatment is provided so that an insulating layer (150) is formed on both sides along the thickness direction of the substrate (110).

[0313] Along the thickness direction of the substrate (110), both sides (bottom surface and top surface) may be coated with indeterminate ink to form an insulating layer (150). The insulating layer (150) comprises a lower insulating layer (1501) coated on the outer surface of the first layer (110L1) and an upper insulating layer (1502) coated on the outer surface of the nth layer (110Ln).

[0314] The upper pad (270b2) and lower pad (270b1) are exposed to the outside.

[0315] The plating layers (230b4) on both ends of the intermediate via hole (210b2) are not exposed to the outside as both ends are coated by the insulating layer (150).

[0316] After the step (S390) of insulating the substrate (110) so that an insulating layer (150) is formed on both sides along the thickness direction, a step (S400) of mounting a component by interposing solder (290b) on the pad (270b) is further provided.

[0317] A lower component (300b1) is mounted on the lower pad (270b1) via a lower solder (290b1), and an upper component (300b2) is mounted on the upper pad (270b2) via an upper solder (290b2).

[0318] With this configuration, a signal input from the upper component (300b2) of the substrate (110) can be input to the inner plating layer (230b1) via the upper solder (290b2) and the upper pad (270b2). Additionally, a signal input from the lower component (300b2) can be input to the inner plating layer (230b1) via the lower solder (290b1) and the lower pad (270b1).

[0319] The signal input to the inner plating layer (230b1) of the above-mentioned through-hole (210b1) can be transmitted to the third layer (110L3) and / or the second layer (110L2), respectively.

[0320] Specific embodiments of the present invention have been illustrated and described above. However, since the present invention may be implemented in various forms without departing from its spirit or essential features, the embodiments described above should not be limited by specific details for implementing the invention.

[0321] In addition, even embodiments not listed individually in the detailed description above should be broadly interpreted within the scope of the technical concept defined in the appended claims. Furthermore, all modifications and variations included within the technical scope of the claims and their equivalents should be encompassed by the appended claims.

Claims

Claim 1 A substrate having a first layer to an nth layer stacked in layers; a via hole formed to penetrate the first layer or the nth layer along the stacking direction; a plating layer formed inside and outside the via hole; and a pad formed by separating the plating layer formed at the end of the via hole from the surroundings. A printed circuit board comprising a plating layer and a filling portion formed by filling with an insulating material inside the plating layer, wherein the via hole includes an n_n-1 via hole formed by penetrating the n-th layer and the n-1-th layer, wherein the plating layer comprises an n_n-1 inner surface plating layer formed on the inner surface of the n_n-1 via hole and an n_n-1 end surface plating layer formed at each end of the n_n-1 via hole, wherein the filling portion includes an n_n-1 filling portion formed inside surrounded by the n_n-1 inner surface plating layer and the n_n-1 end surface plating layer, and wherein the n_n-1 end surface plating layer is configured to be planar with the n-th layer and the n-1-th layer. Claim 2 In claim 1, the pad is a printed circuit board formed on the n_n-1 terminal plating layer of the n_n-1 terminal plating layer of the n_n-1 via hole that is exposed to the outside. Claim 3 delete Claim 4 In claim 1, the via hole comprises a second_1 via hole formed by penetrating a second layer and a first layer, and the plating layer comprises a second_1 inner surface plating layer formed on the inner surface of the second_1 via hole; and second_1 end plating layers formed at each of the two ends of the second_1 via hole; and the pad is a printed circuit board formed on the second_1 end plating layer of the second_1 via hole that is exposed to the outside. Claim 5 A printed circuit board further comprising, in claim 4, a 2_1 filling portion formed by filling an insulating material inside the 2_1 inner surface plating layer and the 2_1 terminal plating layer of the 2_1 via hole. Claim 6 In claim 1, the via hole comprises a 2_1 via hole formed by penetrating the second layer and the first layer, and an n_n-1 via hole formed by penetrating the n-th layer and the n-1-th layer, and the plating layer comprises: a 2_1 inner surface plating layer formed on the inner surface of the 2_1 via hole; a 2_1 end plating layer formed at each of the two ends of the 2_1 via hole; and an n_n-1 inner surface plating layer formed on the inner surface of the n_n-1 via hole. and an n_n-1 end plating layer formed at each end of the n_n-1 via hole; wherein the pad is formed on the n_n-1 end plating layer of the 2_1 via hole that is exposed to the outside and on the n_n-1 end plating layer of the n_n-1 via hole that is exposed to the outside, respectively. Claim 7 A printed circuit board further comprising, in claim 6, a 2_1 filling portion formed by filling an insulating material inside the 2_1 inner surface plating layer and the 2_1 terminal plating layer of the 2_1 via hole; and an n_n-1 filling portion formed by filling an insulating material inside the n_n-1 inner surface plating layer and the n_n-1 terminal plating layer of the n_n-1 via hole. Claim 8 In claim 1, the via hole comprises a through-via hole formed by penetrating the first layer to the nth layer, the plating layer comprises an inner plating layer formed on the inner surface of the through-via hole and end plating layers formed at each of the two ends of the through-via hole, and the pad is a printed circuit board formed at each of the end plating layers formed at each of the two ends of the through-via hole. Claim 9 A printed circuit board further comprising, in claim 8, a filling portion formed by filling the interior plating layer and the end plating layer of the above-mentioned throughvia hole with an insulating material. Claim 10 A printed circuit board according to any one of claims 1, 2, 4 to 9, wherein a plate-shaped insulator is provided between each of the first to nth layers, and the via holes are formed by drilling. Claim 11 A printed circuit board according to claim 10, wherein the via hole further comprises an intermediate via hole formed by penetrating two or more consecutive layers among the first layer to the nth layer and not exposed to the outside, and the plating layer comprises an inner plating layer formed on the inner surface of the intermediate via hole and end plating layers formed at each of the two ends of the intermediate via hole; and further comprises a filling portion formed by filling the interior of the inner plating layer and the end plating layer of the intermediate via hole with an insulating material. Claim 12 The method comprises: a step of forming a plurality of layers arranged in a layered manner with an insulator in between; a step of forming a via hole that is penetrated by including an n-th layer arranged at the uppermost side along the stacking direction or by including a first layer at the lowest side; a step of forming a plating layer on the inside and outside of the via hole; and a step of forming a pad by separating the plating layer exposed to the outside among the plating layers of the via hole from the surroundings; wherein the step of forming the plating layer includes the step of forming an inner plating layer formed on the inner surface of the via hole. A method for manufacturing a printed circuit board comprising: a step of forming end plating layers formed at each of the ends of the via hole; further comprising, prior to the step of forming the end plating layers, a step of forming a filling portion by filling an insulating material inside the inner plating layer; wherein the step of forming the via hole comprises a step of forming an n_n-1 via hole penetrating the n-th layer and the n-1-th layer; wherein the inner plating layer comprises an n_n-1 inner plating layer formed on the inner surface of the n_n-1 via hole, and the end plating layer comprises an n_n-1 end plating layer formed at each of the ends of the n_n-1 via hole, and the filling portion comprises an n_n-1 filling portion formed inside surrounded by the n_n-1 inner plating layer and the n_n-1 end plating layer, and wherein the n_n-1 end plating layer is configured to be planar with the n-th layer and the n-1-th layer. Claim 13 delete Claim 14 delete Claim 15 A method for manufacturing a printed circuit board according to claim 12, further comprising the step of providing a drill capable of penetrating the plurality of layers before the step of forming the via hole. Claim 16 In claim 12, the step of forming the via hole comprises the step of forming a second_1 via hole penetrating the second layer and the first layer; a method for manufacturing a printed circuit board. Claim 17 delete Claim 18 A method for manufacturing a printed circuit board according to any one of claims 12, 15 to 16, further comprising: a step of laminating the plurality of layers in layers before the step of forming the pad; and a step of insulating the surface of the plurality of layers laminated in layers. Claim 19 A step of forming a first layer to an n-th layer, each arranged in layers with an insulator in between; a step of stacking the first layer to the n-th layer such that the first layer is arranged at the bottom side and the n-th layer is arranged at the top side along the stacking direction; a step of forming a via hole including a through-via hole penetrating the first layer from the n-th layer; and a step of forming a plating layer on the inside and outside of the via hole including the through-via hole. A method for manufacturing a printed circuit board comprising: a step of forming a pad by separating the plating layer exposed to the outside among the plating layers of the through-via hole from the surroundings; wherein the step of forming plating layers on the inside and outside of the via hole including the through-via hole comprises a step of forming an inner plating layer on the inner surface of the via hole and a step of forming end plating layers on both ends of the via hole; and further comprising, prior to the step of forming the end plating layers of the via hole, a step of forming a filling portion by filling an insulating material inside the via hole, wherein the filling portion is formed inside surrounded by the inner plating layer and the end plating layer, and the end plating layer is configured to be planar with the n-th layer and the first layer. Claim 20 In claim 19, the step of forming the via hole comprises the step of forming an intermediate via hole that is formed by penetrating two or more consecutive layers among the first layer to the nth layer and is not exposed to the outside; a method for manufacturing a printed circuit board.

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