Semiconductor package

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and having a first surface facing the lower substrate and having connection pads electrically connected to the lower wiring layer disposed thereon, and a second surface located opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip and having a lower surface having support members protruding toward the second surface of the semiconductor chip and having an upper wiring layer disposed thereon; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer; a sealing material filling the space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure; adhesive members disposed on the second surface of the semiconductor chip corresponding to each of the support members and contacting the second surface and the support members, respectively; and connection bumps disposed below the lower substrate and electrically connected to the lower wiring layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0003] In line with the recent trend toward higher performance and miniaturization of electronic devices, package-on-package (POP) technology is being developed in the semiconductor packaging field. In package-on-package technology, since two or more semiconductor packages are stacked vertically, the development of technology to ensure thickness uniformity of the semiconductor packages is required. The problem to be solved

[0005] One of the problems that the present invention aims to solve is to provide a semiconductor package with improved thickness uniformity. means of solving the problem

[0007] As a means of solving the aforementioned problem, one embodiment of the present invention provides a semiconductor package comprising: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and having a first surface on which connection pads electrically connected to the lower wiring layer are disposed facing the lower substrate and a second surface located opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip and having a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed and which includes an upper wiring layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer; a sealing material filling the space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure; adhesive members disposed on the second surface of the semiconductor chip corresponding to each of the support members and contacting the second surface and the support members, respectively; and connection bumps disposed below the lower substrate and electrically connected to the lower wiring layer.

[0009] Additionally, the semiconductor package comprises: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and having a first surface having connection pads disposed facing the lower substrate and electrically connected to the lower wiring layer, and a second surface located opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip and having a lower surface having support members disposed protruding toward the second surface of the semiconductor chip and having an upper wiring layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer; and adhesive members disposed on the second surface of the semiconductor chip corresponding to each of the support members and having protrusions extending outwardly beyond the width of the support members in a direction parallel to the second surface, wherein the protrusions of each of the adhesive members contact at least a portion of the side surface of the support members.

[0011] Additionally, the present invention provides a semiconductor package comprising: a lower substrate; a semiconductor chip disposed on the lower substrate and having a first surface facing the lower substrate and a second surface located opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip and having a lower surface having support members disposed thereon that protrude toward the second surface of the semiconductor chip; adhesive members disposed between the second surface of the semiconductor chip and the support members corresponding to each of the support members; and a sealant disposed between the lower substrate and the upper substrate and covering at least a portion of each of the semiconductor chip, the support members, and the adhesive members. Effects of the invention

[0013] According to embodiments of the present invention, by introducing adhesive members connecting the support members of an upper substrate and the inactive surface of a semiconductor chip, a semiconductor package with improved thickness uniformity can be provided. Brief explanation of the drawing

[0015] FIG. 1a is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention, and FIG. 1b is a plan view illustrating a cross-sectional view along line II' of FIG. 1a. FIG. 2 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIGS. 6a and 6b are cross-sectional views illustrating, exemplarily, the manufacturing process of an upper substrate applicable to embodiments of the present invention. FIGS. 7a to 7c are cross-sectional views illustrating the bonding process between an upper substrate and a semiconductor chip. Specific details for implementing the invention

[0016] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0018] FIG. 1a is a cross-sectional view illustrating a semiconductor package (100A) according to one embodiment of the present invention, and FIG. 1b is a plan view illustrating a cross-sectional view along line II' of FIG. 1a.

[0020] Referring to FIGS. 1a and 1b, a semiconductor package (100A) of one embodiment may include a lower substrate (110), a semiconductor chip (120), an upper substrate (130), and a connection structure (140). Additionally, the semiconductor package (100A) may further include a sealing material (150), a connection bump (160), and / or a passive element (170).

[0021] The present invention can improve warpage occurring during the manufacturing process by introducing a plurality of support members (134) on the lower surface (LS) of the upper substrate (130) of a semiconductor package (100A), thereby maintaining the joint pitch between the inactive surface (hereinafter, the second surface (BS)) of the semiconductor chip (120) and the lower surface (LS) of the upper substrate (130). In addition, by introducing adhesive members (125) that bond the support members (134) and the second surface (BS) on the second surface (BS) of the semiconductor chip (120), the occurrence of a void between the support members (134) and the second surface (BS) of the semiconductor chip (120) can be prevented, and interfacial delamination and warpage imbalance caused by the void can be improved. Each component will be described in detail below with reference to the drawings.

[0023] The lower substrate (110) is a support substrate on which a semiconductor chip (120) is mounted, and may be a substrate for a package including a lower wiring layer (112) for rewiring the semiconductor chip (120). The substrate for the package may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, etc. For example, the lower substrate (110) may include an insulating layer (111), a lower wiring layer (112), and a lower wiring via (113).

[0024] The insulating layer (111) may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which an inorganic filler or / and glass fiber (glass fiber, glass cloth, glass fabric) is impregnated into these resins, for example, a photosensitive resin such as prepreg, ABF, FR-4, BT, or PID (Photo-Imageable Dielectric). The insulating layer (111) may include a plurality of insulating layers (111) stacked in a vertical direction (Z-axis direction). Depending on the process, the boundaries between the plurality of insulating layers (111) may be indistinct. Also, for convenience of explanation, only five insulating layers (111) are shown in the drawings, but embodiments of the present invention are not limited thereto. Depending on the embodiment, fewer or more insulating layers (111) may be formed than shown in the drawings. For example, the core insulating layer (111) located in the middle among the plurality of insulating layers (111) may be thicker than the insulating layers (111) stacked above and below it. The core insulating layer (111) can improve the rigidity of the substrate and suppress bending of the substrate. The core insulating layer (111) may be formed using, for example, a copper clad laminate (CCL), an unclad copper clad laminate (Unclad CCL), a glass substrate, or a ceramic substrate. According to the embodiment, the lower substrate (110) may not include the core insulating layer (111). The uppermost and / or lowermost insulating layer (111) among the plurality of insulating layers (111) may be a solder resist layer that protects the wiring layer (112) from external physical / chemical damage. The solder resist layer contains an insulating material and can be formed, for example, using photo solder resist (PSR).

[0025] The lower wiring layer (112) may include a metallic material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The lower wiring layer (112) may include, for example, a ground (GND) pattern, a power (PoWeR) pattern, and a signal (S) pattern. The signal (S) pattern may provide a path for transmitting and receiving various signals, such as data signals, excluding the ground (GND) pattern, power (PWR) pattern, etc. The lower wiring layer (112) may be provided as a plurality of lower wiring layers (112) each disposed below a plurality of insulating layers (111). The plurality of lower wiring layers (112) may be electrically connected to each other through wiring vias (113). The lower wiring layer (112) may include landing pads on which a semiconductor chip (120), a connection structure (140), a connection bump (160), and a passive component (170) are mounted. The landing pads may be formed to have different pitches depending on the object being mounted. In one example, the lowest lower wiring layer (112) in contact with the connection bump (160) may be formed to have a greater thickness than the upper lower wiring layers (112). The number of layers of the lower wiring layer (112) may be determined according to the number of layers of the insulating layer (111), and may include more or fewer layers than shown in the drawing.

[0026] The lower wiring via (113) is electrically connected to the lower wiring layer (112) and may include signal vias, ground vias, and power vias. The lower wiring via (113) may include a metallic material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The lower wiring via (113) may have the form of a filled via in which a metallic material is filled inside the via hole, or a conformal via in which a metallic material is formed along the inner wall of the via hole. The lower wiring via (113) may be integrated with the lower wiring layer (112), but embodiments of the present invention are not limited thereto.

[0028] A semiconductor chip (120) is placed on a lower substrate (110) and may have a first surface (FS) facing the lower substrate (110) and having connection pads (121) electrically connected to a lower wiring layer (112), and a second surface (BS) located opposite the first surface (FS). The semiconductor chip (120) may be mounted on the lower substrate (110) in a flip-chip manner. The semiconductor chip (120) may be connected to the lower wiring layer (112) through metal bumps in the form of balls or posts. For example, the semiconductor chip (120) may be electrically connected to the lower wiring layer (112) through a bump structure (122) combined with a solder ball and a copper (Cu) pillar, but is not limited thereto. According to an embodiment, the semiconductor chip (120) may be directly connected to the lower wiring layer (112) or the lower wiring via (113) without a separate bump. The semiconductor chip (120) may include silicon (Si), germanium (Ge), or gallium arsenide (GaAs) and may form various types of integrated circuits. The integrated circuit may be a processor chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, etc., but is not limited thereto, and may be a logic chip such as an analog-to-digital converter or an ASIC (application-specific IC), or a memory chip such as a volatile memory (e.g., DRAM) or a non-volatile memory (e.g., ROM and flash memory). According to an embodiment, an underfill member (123) may be disposed between the lower substrate (110) and the first surface (FS) of the semiconductor chip (120). The underfill member (123) may have a capillary underfill (CUF) structure that is separated from the suture material (150), but depending on the embodiment, it may have a moled underfill (MUF) structure formed integrally with the suture material (150).

[0030] The upper substrate (130) is a substrate disposed on the lower substrate (110) and the semiconductor chip (120) to provide a redistribution layer on the upper side of the semiconductor package (100A), and may be referred to as an interposer substrate located between the lower package and the upper package in a package-on-package structure. The upper substrate (130) has a lower surface (LS) on which support members (134) protruding toward the second surface (BS) of the semiconductor chip (120) are disposed, and may include an insulating layer (131), an upper wiring layer (132), and an upper wiring via (133). Since the insulating layer (131), the upper wiring layer (132), and the upper wiring via (133) have the same or similar features as the insulating layer (111), the lower wiring layer (112), and the lower wiring via (113) of the lower substrate (110) described above, a redundant description is omitted.

[0031] The present invention can improve interfacial delamination and warping imbalance occurring between the support members (134) and the second surface (BS) of the semiconductor chip (120) by introducing a plurality of support members (134) on the lower surface (LS) of the upper substrate (130) and adhesive members (125) that bond these to the second surface (BS) of the semiconductor chip (120). For example, if the height (134H) of the support members (134) in the direction perpendicular to the second surface (BS) (Z-axis direction) is in the range of about 15㎛ to about 25㎛, the spacing distance (H) between the second surface (BS) of the semiconductor chip (120) and the lower surface (LS) of the upper substrate (130) may be in the range of about 15㎛ to about 35㎛, about 20㎛ to about 35㎛, or about 20㎛ to about 30㎛. Here, the spacing distance (H) between the second surface (BS) and the lower surface (LS) may be varied according to the design, for example, according to the height (134H) of the support members (134), the amount of adhesive members (125) applied, etc., and is not limited to the numerical ranges described above.

[0032] Each support member (134) has a lower surface (134LS) facing the second surface (BS) of the semiconductor chip (120) and a side surface (134S) extending from the lower surface (134LS) to the lower surface (LS) of the upper substrate (130), and can be arranged to overlap the semiconductor chip (120) in a direction perpendicular to the second surface (BS) (Z-axis direction) from below the lower surface (LS) of the upper substrate (130). The support members (134) can control warping of the upper substrate (130). For example, if the upper substrate (130) warps during the manufacturing process of the semiconductor package (100A), the warping of the upper substrate (130) can be controlled by supporting the upper substrate (130) in contact with the second surface (BS) of the semiconductor chip (120). However, if the upper substrate (130) is excessively bent, at least some of the support members (134) may be separated from the second surface (BS), and a void may occur in which the sealing material (150) is not filled between them. On the other hand, the present invention can prevent the occurrence of a void by introducing adhesive members (125) that bond the support members (134) to the second surface (BS) of the semiconductor chip (120). For example, at least some of the support members (134) may be separated from the second surface (BS) of the semiconductor chip (120), and the adhesive members (125) may fill the gap between at least some of the support members (134) and the second surface (BS) of the semiconductor chip (120). In the drawing, all of the support members (134) are shown as being separated from the second surface (BS), but some of the support members (134) may be in contact with the second surface (BS). Support members (134) can be formed, for example, by patterning the PSR applied on the lower surface (LS) of the upper substrate (130). The number and pitch of the support members (134) can be varied according to the design.

[0033] Adhesive members (125) are disposed on a second surface (BS) of a semiconductor chip (120) corresponding to each of the support members (134) and may contact the second surface (BS) of the semiconductor chip (120) and the support members (134), respectively. For example, the adhesive members (125) have a protrusion (125P) that extends outwardly beyond the width of the support members (134) in a direction parallel to the second surface (BS) (e.g., X-axis direction), and the adhesive members (125) or each protrusion (125P) may contact at least a portion of the side (134S) of the corresponding support member among the support members (134). For example, the width of the protrusion (125P) in a direction parallel to the second surface (BS) (e.g., X-axis direction) may be greater than the height (134h) of the protrusion (125P) in contact with the side (134S) of the support members (134) in a direction perpendicular to the second surface (BS) (e.g., Z-axis direction). The adhesive members (125) or each protrusion (125P) may be spaced apart from each other, and the spaced-apart space between the adhesive members (125) may be filled with a sealant (150). At least some of the adhesive members (125) may be interposed between the second surface (BS) of the semiconductor chip (120) and the support members (134) to prevent voids from forming between the support members (134) and the semiconductor chip (120). Accordingly, the sealant (150) may cover at least a portion of each of the second surface (BS) of the semiconductor chip (120), the outer surface of the protrusion (125P), and the side (134S) of the support members (134) exposed from the protrusion (125P). The adhesive members (125) may comprise an insulating resin, for example, a thermosetting resin, a thermoplastic resin, or a resin mixed thereof, but the material constituting the adhesive members (125) is not particularly limited.

[0035] A connecting structure (140) is positioned between a lower substrate (110) and an upper substrate (130) and can provide a vertical connecting path that electrically connects a lower wiring layer (112) and an upper wiring layer (132). The connecting structure (140) may have a spherical or ball shape made of a low-melting point metal such as, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or an alloy containing these (e.g., Sn-Ag-Cu).

[0037] The sealing material (150) fills the space between the lower substrate (110) and the upper substrate (130) and can seal at least a portion of each of the semiconductor chip (120) and the connecting structure (140). The sealing material (150) may include, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a prepreg including an inorganic filler or / and glass fiber, ABF, FR-4, BT, EMC. According to the present invention, since the support members (134) and the second surface (BS) of the semiconductor chip (120) are bonded by the adhesive members (125), the sealing material (150) may not be interposed between the support members (134) and the second surface (BS) of the semiconductor chip (120). Accordingly, the sealant (150) can be formed to surround at least a portion of each of the semiconductor chip (120), the support members (134), and the adhesive members (125).

[0039] A connection bump (160) is positioned below the lower substrate (110) and can be electrically connected to the lower wiring layer (112). The connection bump (160) can physically and / or electrically connect the semiconductor package (100A) to an external device. The connection bump (160) includes a conductive material and may have the form of a ball, pin, or lead. For example, the connection bump (160) may be a solder ball. At least one passive component (170) may be positioned on the lower substrate (110). The passive component (170) may include, for example, a capacitor such as an MLCC (Multi Layer Ceramic Capacitor) or LICC (Low Inductance Chip Capacitor), an inductor, a bead, etc. For example, the passive component (170) may be a Land-Side Capacitor (LSC) placed on the lower surface of the lower substrate (110). However, it is not limited thereto, and depending on the embodiment, the passive component (170) may be a Die-Side Capacitor (DSC) mounted on the upper surface of the lower substrate (110) or an embedded type capacitor built inside the lower substrate (110).

[0041] FIG. 2 is a cross-sectional view illustrating a semiconductor package (100B) according to one embodiment of the present invention.

[0043] Referring to FIG. 2, a semiconductor package (100B) of one embodiment has the same or similar features as described with reference to FIG. 1a and 1b, except that it includes fillers dispersed within adhesive members, so redundant description is omitted. In this embodiment, the adhesive members (125) may include an insulating resin and fillers (FL) dispersed within the insulating resin. The fillers (FL) may be interposed between the support members (134) and the second surface (BS) of the semiconductor chip (120). The insulating resin may include a thermosetting resin, a thermoplastic resin, or a resin mixed therewith. The fillers (FL) may be added to the insulating resin to satisfy the mechanical properties, thermal properties, electrical properties, etc. required of the adhesive members (125). For example, the fillers (FL) can control the fluidity of the insulating resin to prevent overflow of the adhesive members (125) and secure a gap between the support members (134), or improve the adhesion of the adhesive members (125) to effectively suppress interfacial delamination between the semiconductor chip (120) and the support members (134). The fillers (FL) may include insulating fillers or conductive fillers. The insulating filler may include, for example, inorganic fillers such as boron nitride, alumina, silica, aluminum nitride, magnesium oxide, silicon oxide, aluminum hydroxide, and barium sulfate. The conductive filler may be, for example, conductive particles such as carbon fibers or metal balls, or may have a form in which a metallic material such as gold (Au), silver (Ag), nickel (Ni), or lead (Pd) is coated on the surface of the core particles.

[0045] FIG. 3 is a cross-sectional view illustrating a semiconductor package (100C) according to one embodiment of the present invention.

[0047] Referring to FIG. 3, a semiconductor package (100C) of one embodiment has the same or similar features as described with reference to FIG. 1a to 2, except that the first gap (h1) between some support members (134-1) and the semiconductor chip (120) is different from the second gap (h2) between other support members (134-2) and the semiconductor chip (120), so redundant descriptions are omitted. For example, the first gap (h1) between the first support member (134-1) and the semiconductor chip (120) may be smaller than the second gap (h2) between the second support member (134-2) and the semiconductor chip (120). The difference between the first gap (h1) and the second gap (h2) may be about 5 μm or less, for example, in the range of about 0.001 μm to about 5 μm, about 0.001 μm to about 3 μm, about 0.001 μm to about 2 μm, etc. Additionally, the first separation distance (H1) between the lower surface (LS) of the upper substrate (130) on which the first support member (134-1) is placed and the second surface (BS) of the semiconductor chip (120) may be smaller than the second separation distance (H2) between the lower surface (LS) of the upper substrate (130) on which the second support member (134-2) is placed and the second surface (BS) of the semiconductor chip (120). The first separation distance (H1) and the second separation distance (H2) may each be in the range of about 15 μm to about 35 μm, about 20 μm to about 35 μm, or about 20 μm to about 30 μm. Additionally, the height (134H1) of the first support member (134-1) and the height (134H2) of the second support member (134-2) are substantially the same, and the first support member (134-1) is positioned to overlap the outer part of the semiconductor chip (120) in the vertical direction (Z-axis direction), and the second support member (134-2) can be positioned to overlap the central part of the semiconductor chip (120) in the vertical direction (Z-axis direction).According to an embodiment, unlike what is shown in the drawing, the first separation distance (H1) between the lower surface (LS) of the upper substrate (130) on which the first support member (134-1) is placed and the second surface (BS) of the semiconductor chip (120) may be greater than the second separation distance (H2) between the lower surface (LS) of the upper substrate (130) on which the second support member (134-2) is placed and the second surface (BS) of the semiconductor chip (120), and the first gap (h1) may be greater than the second gap (h2). Here, "substantially identical" can be understood as a concept that includes process errors, etc., in which the heights of the first support member (134-1) and the second support member (134-2) are not intentionally formed differently during the design and manufacturing process. That is, the difference between the first gap (h1) and the second gap (h2) is caused by the bending of the upper substrate (130), and despite this gap difference, adhesive members (125) are filled under the first support member (134-1) and the second support member (134-2), thereby preventing the sealant (150) from being unfilled and voids from forming.

[0049] FIG. 4 is a cross-sectional view illustrating a semiconductor package (100D) according to one embodiment of the present invention.

[0051] Referring to FIG. 4, a semiconductor package (100D) of one embodiment has the same or similar features as described with reference to FIG. 1a through 3, except that the connection structure (140) includes a core (142) and a solder layer (141) covering the surface of the core (142), so a redundant description is omitted. In this embodiment, the connection structure (140) may have a core-ball structure including a core (142) formed in the center and a solder layer (141) covering the core (142). The core (142) may include a polymer material including a thermoplastic resin or a thermosetting resin, or a metallic material distinct from solder. The solder layer (141) may include tin (Sn) or an alloy containing tin (Sn). Such a core-ball structure can maintain a gap between the lower substrate (110) and the upper substrate (130) and prevent misalignment of the connection structure (140).

[0053] FIG. 5 is a cross-sectional view illustrating a semiconductor package (1000) according to one embodiment of the present invention.

[0055] Referring to FIG. 5, a semiconductor package (1000) of one embodiment may include a first package (100) and a second package (200). The first package (100) is illustrated identically to the semiconductor package (100A) shown in FIG. 1a, but it can be understood to have the same or similar features as the semiconductor packages (100A, 100B, 100C, 100D) described with reference to FIG. 1a through 4. Accordingly, the semiconductor package (1000) of the present embodiment can implement a package-on-package structure with improved thickness uniformity and yield.

[0056] The second package (200) may include a rewiring substrate (210), a second semiconductor chip (220), and a second sealing material (230). The rewiring substrate (210) may include a lower pad (211) and an upper pad (212) on the lower and upper surfaces, respectively, which can be electrically connected to the outside. Additionally, the rewiring substrate (210) may include a rewiring circuit (213) that electrically connects the lower pad (211) and the upper pad (212).

[0057] The second semiconductor chip (220) may be mounted on the redistribution board (210) by wire bonding or flip-chip bonding. For example, a plurality of second semiconductor chips (220) may be stacked vertically on the redistribution board (210) and electrically connected to the upper pad (212) of the redistribution board (210) by a bonding wire (WB). In one example, the second semiconductor chip (220) may include a memory chip, and the first semiconductor chip (120) may include an AP chip.

[0058] The second sealing material (230) may include a material identical or similar to the sealing material (150) of the first package (100). The second package (200) may be physically and electrically connected to the first package (100) by a metal bump (260). The metal bump (260) may be electrically connected to a redistribution circuit (213) inside the redistribution board (210) through a lower pad (211) of the redistribution board (210). The metal bump (260) may include a low-melting point metal, for example, tin (Sn) or an alloy containing tin (Sn).

[0060] FIGS. 6a and 6b are cross-sectional views illustrating, exemplarily, the manufacturing process of an upper substrate (130) applicable to embodiments of the present invention.

[0062] Referring to FIG. 6a, first, a preliminary upper substrate (130') is prepared having an insulating layer (131), an upper wiring layer (132), and an upper wiring via (133) formed thereon. Among the plurality of insulating layers (131), the core insulating layer (131C) may be formed, for example, using a copper clad laminate. The upper wiring layer (132) and the upper wiring via (133) may be formed on both sides of the core insulating layer (131C) using a photolithography process, a plating process, an etching process, etc. According to the embodiment, a greater number of insulating layers and upper wiring layers than shown in the drawing may be formed on both sides of the core insulating layer (131C). The uppermost and lowermost insulating layers (131) may be solder resist layers (131SR) formed by applying solder resist ink (e.g., PSR ink) and performing an exposure process and a development process. The preliminary upper substrate (130') may have a lower surface (LS) provided by a lower solder resist layer (134SR).

[0063] Subsequently, a patterned mask layer (MA) can be formed on the lower surface (LS) of the preliminary upper substrate (130'). The mask layer (MA) may include an etching pattern (EP) that exposes a portion of the solder resist layer (134SR). The mask layer (MA) may include a thermosetting resin, a UV-curing resin, or a composite curing resin. Subsequently, the support members (134) of FIG. 6b can be formed by filling the etching pattern (EP) of the mask layer (MA) with solder resist ink.

[0065] Referring to FIG. 6b, an upper substrate (130) having support members (134) formed can be manufactured by filling solder resist ink within an etching pattern ('EP' in FIG. 6a) and removing a mask layer ('MA' in FIG. 6a). The support members (134) can be formed by applying solder resist ink containing epoxy-based, melamine-based, or imidazole-based resins, etc. The support members (134) may have a shape protruding from the lower surface (LS) of the upper substrate (130). The support members (134) can secure a gap between the upper substrate (130) and the semiconductor chip ('120' in FIG. 7c) in a process described later.

[0067] FIGS. 7a to 7c are cross-sectional views illustrating the bonding process of an upper substrate (130) and a semiconductor chip (120). FIGS. 7b and 7c illustrate the bonding process of the upper substrate (130) of FIG. 6b and the lower substrate (110) on which the semiconductor chip (120) is mounted.

[0069] Referring to FIG. 7a, preliminary adhesive members (125p) can be formed on a semiconductor chip (120) mounted on a lower substrate (110). The preliminary adhesive members (125p) can be placed on a second surface (BS) of the semiconductor chip (120), for example, by a dotting tool (10). The preliminary adhesive members (125p) can be positioned to correspond to the support members ('134' in FIG. 7b) of the upper substrate (130) in a process described later. The dotting amount of the preliminary adhesive members (125p) can be adjusted according to the size and pitch of the support members ('134' in FIG. 7b) of the upper substrate (130). For example, the preliminary adhesive members (125p) can be formed to have a volume of about 20% to about 50% of the volume of the support members ('134' in FIG. 7b). If the dotting amount of the pre-adhesive members (125p) is less than about 20% of the volume of the support members ('134' in FIG. 7b), the adhesion between the support members ('134' in FIG. 7b) and the semiconductor chip (120) is reduced and voids may occur. If the dotting amount of the pre-adhesive members (125p) exceeds about 50% of the volume of the support members ('134' in FIG. 7b), the pre-adhesive members (125p) may overflow during the thermal compression process and move out of a designated position (a position corresponding to the support members). The semiconductor chip (120) may be supported and fixed on the lower substrate (110) by an underfill member (123). A first pre-connection structure (140p1) seated on the lower wiring layer (112) may be disposed on the lower substrate (110). The first preliminary connecting structure (140p1) may have a spherical or ball shape made of a low-melting point metal such as tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or an alloy containing these (e.g., Sn-Ag-Cu).

[0071] Referring to FIG. 7b, an upper substrate (130) on which a second pre-connecting structure (140p2) is seated can be prepared on the lower surface (LS). The second pre-connecting structure (140p2) is connected to the upper wiring layer (132) and may have a spherical or ball shape made of a low-melting point metal similar to the first pre-connecting structure (140p1). The upper substrate (130) may be aligned on the lower substrate (110) such that the second pre-connecting structure (140p2) and the support members (134) overlap in a vertical direction (Z-axis direction) with the first pre-connecting structure (140p1) and the pre-adhesive members (125p) of the lower substrate (110), respectively. A flux layer (not shown) may be coated on the surfaces of the first pre-connecting structure (140p1) and the second pre-connecting structure (140p2).

[0073] Referring to FIG. 7c, a thermal compression bonding process can be performed to form a connecting structure (140) and adhesive members (125). The first preliminary connecting structure (140p1) of FIG. 7b and the second preliminary connecting structure (140p2) of FIG. 7b can be reflowed and fused together. Additionally, the preliminary adhesive members (125p) of FIG. 7b can be raised along the side of the supporting members (134) by a thermal compression process. Thus, at least a portion of the adhesive members (125) can wrap around a portion of the side of the supporting members (134) and have a protrusion (125P) extending outward from the supporting members (134).

[0074] Afterward, a cleaning solution (e.g., purified water) can be introduced into the remaining space (SP) between the lower substrate (110) and the upper substrate (130) to remove flux residue, and a sealing material ('150' in FIG. 1a) can be filled. According to the present invention, since adhesive members (125) are filled between the support members (134) and the semiconductor chip (120), the sealing material ('150' in FIG. 1a) filled in the remaining space (SP) can be formed to surround the outer surface of the adhesive members (125) and the side of the support members (134) exposed from the adhesive members (125).

[0076] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

Claims

Claim 1 A lower substrate comprising a lower wiring layer; a semiconductor chip disposed on the lower substrate and having a first surface facing the lower substrate and having connection pads electrically connected to the lower wiring layer disposed thereon, and a second surface located opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip and having a lower surface having support members protruding toward the second surface of the semiconductor chip disposed thereon, and comprising an upper wiring layer; a connecting structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer; a sealing material filling the space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connecting structure; and adhesive members disposed on the second surface of the semiconductor chip corresponding to each of the support members and contacting the second surface and the support members, respectively. A semiconductor package comprising connection bumps disposed below the lower substrate and electrically connected to the lower wiring layer, wherein each of the support members comprises an upper surface in contact with the lower surface of the upper substrate, a lower surface spaced apart from the second surface of the semiconductor chip, and a side between the upper surface and the lower surface, and each of the adhesive members comprises an upper end in contact with the side of the corresponding support member among the support members, and the upper end of each of the adhesive members is located between the upper surface and the lower surface of the corresponding support member. Claim 2 delete Claim 3 In claim 1, the adhesive members fill the gap between the lower surface of the support members and the second surface of the semiconductor chip in a semiconductor package. Claim 4 A semiconductor package according to claim 1, wherein the adhesive members are spaced apart from each other, and the sealant fills the spaced-apart space between the adhesive members. Claim 5 In claim 1, the sealant surrounds at least a portion of each of the support members and the adhesive members in a semiconductor package. Claim 6 In claim 1, the adhesive members comprise an insulating resin and fillers dispersed within the insulating resin in a semiconductor package. Claim 7 In claim 6, the fillers comprise an insulating filler or a conductive filler in a semiconductor package. Claim 8 A lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate and having a first surface facing the lower substrate and having connection pads electrically connected to the lower wiring layer disposed thereon, and a second surface located opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip and having a lower surface having support members protruding toward the second surface of the semiconductor chip disposed thereon, and including an upper wiring layer; and a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer. A semiconductor package comprising adhesive members disposed on the second surface of the semiconductor chip corresponding to each of the support members and having a protrusion extending outwardly beyond the width of the support members in a direction parallel to the second surface, wherein the protrusion of each of the adhesive members contacts at least a portion of the side surface of the support members, and each of the support members includes an upper surface contacting the lower surface of the upper substrate, a lower surface spaced apart from the second surface of the semiconductor chip, and a side surface between the upper surface and the lower surface, wherein the protrusion of each of the adhesive members includes an upper end contacting the side surface of the corresponding support member, and the upper end of the protrusion is located between the upper surface and the lower surface of the corresponding support member. Claim 9 A semiconductor package according to claim 8, wherein the width of the protrusion in a direction parallel to the second surface is greater than the height of the protrusion in a direction perpendicular to the second surface that contacts the side of the support members. Claim 10 A semiconductor package comprising: a lower substrate; a semiconductor chip disposed on the lower substrate and having a first surface facing the lower substrate and a second surface located opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip and having a lower surface having support members disposed thereon that protrude toward the second surface of the semiconductor chip; adhesive members disposed between the second surface of the semiconductor chip and the support members corresponding to each of the support members; and a sealing material disposed between the lower substrate and the upper substrate and covering at least a portion of each of the semiconductor chip, the support members, and the adhesive members, wherein each of the support members includes an upper surface in contact with the lower surface of the upper substrate, a lower surface spaced apart from the second surface of the semiconductor chip, and a side between the upper surface and the lower surface, and each of the adhesive members includes a top end in contact with the side of a corresponding support member among the support members, and the top end of each of the adhesive members is located between the upper surface and the lower surface of the corresponding support member.

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