Display panels and display device

Abstract

The present application discloses a display panel and a display device, wherein the display panel comprises an array substrate, the array substrate comprises a substrate, a first conductive layer, an insulating layer, and a second conductive layer, the first conductive layer comprises a first signal line and a second signal line extending in a first direction, and the second conductive layer comprises a third signal line and a fourth signal line extending in a second direction, and the third signal line and the fourth signal line transmit the same signal; along a direction perpendicular to the substrate, the first signal line and the third signal line have a first overlapping region and are electrically connected in the first overlapping region, the second signal line and the fourth signal line have a fourth overlapping region and are electrically connected in the fourth overlapping region, the first signal line and the fourth signal line have a second overlapping region and are insulated, and / or, the second signal line and the third signal line have a third overlapping region and are insulated, and the orthographic projections of the second overlapping region and the third overlapping region in the substrate are both located outside the orthographic projection of a type of pixel aperture in the substrate. The display panel according to the present application can improve the color deviation of the display panel.

Description

Technology Field

[0001] This application relates to the field of display technology, and in particular to display panels and display devices. Background Technology

[0002] Flat display devices based on technologies such as Organic Light Emitting Diodes (OLEDs) and Light Emitting Diodes (LEDs) possess advantages such as high image quality, energy efficiency, thin bodies, and a wide range of applications. As a result, they are widely used in various consumer electronic products, including mobile phones, televisions, laptop computers, and desktop computers, and have established themselves as the mainstream display devices.

[0003] However, the performance of current OLED display products needs to be improved.

[0004] The embodiments of the present application provide a display panel and a display device capable of improving color deviation of the display panel and enhancing the performance of the display panel.

[0005] An embodiment of the first aspect of the embodiment of the present application provides a display panel, wherein the display panel is,

[0006] Includes an array substrate,

[0007] The array substrate comprises a substrate and a first conductive layer, an insulating layer, and a second conductive layer sequentially stacked on one side of the substrate, wherein the first conductive layer comprises a first signal line and a second signal line extending in a first direction, and the second conductive layer comprises a third signal line and a fourth signal line extending in a second direction, wherein the first direction and the second direction intersect, the first signal line and the second signal line are arranged along the second direction, the third signal line and the fourth signal line are arranged along the first direction, and the third signal line and the fourth signal line transmit the same signal;

[0008] Along a direction perpendicular to the above substrate, the first signal line and the third signal line have a first overlapping region, the first signal line and the fourth signal line have a second overlapping region, the second signal line and the third signal line have a third overlapping region, the second signal line and the fourth signal line have a fourth overlapping region, and the first signal line and the third signal line are electrically connected in the first overlapping region.

[0009] The first signal line and the fourth signal line are insulated in the second overlapping area, and / or, the second signal line and the third signal line are insulated in the third overlapping area,

[0010] The second signal line and the fourth signal line are electrically connected in the fourth overlapping region, and the orthographic projections of the first overlapping region and the fourth overlapping region in the substrate are both located outside the orthographic projection of a type of pixel opening in the substrate, and the orthographic projections of the second overlapping region and the third overlapping region in the substrate are both located at least partially within the orthographic projection of a type of pixel opening in the substrate, wherein the pixel opening is located on one side of the array substrate facing from the substrate toward the insulating layer.

[0011] According to an embodiment of the first aspect of the present invention, the pixel opening includes a first pixel opening, and the orthographic projections of the second overlapping region and the third overlapping region in the substrate are both located at least partially within the orthographic projection of the first pixel opening in the substrate;

[0012] Preferably, the orthographic projections of the first overlapping region and the fourth overlapping region in the substrate are both located outside the orthographic projection of the first pixel opening in the substrate, and the first pixel opening is used to accommodate a blue light-emitting unit.

[0013] According to any one of the aforementioned embodiments of the first aspect of the present invention, the pixel opening further comprises a second pixel opening, wherein the first pixel opening and the second pixel opening are alternately arranged along the second direction, and the first pixel opening and the second pixel opening are also alternately arranged along the first direction, and the first overlapping area and the fourth overlapping area are located between the first pixel opening and the second pixel opening adjacent in the second direction;

[0014] Preferably, the second pixel opening is used to accommodate a red light-emitting unit.

[0015] According to any one of the aforementioned embodiments of the first aspect of the present invention, a plurality of the first pixel openings and the second pixel openings are alternately arranged along a second direction to form a first pixel row, and the first overlapping area and the third overlapping area are located in the first pixel row of any two adjacent first pixel rows, and the second overlapping area and the fourth overlapping area are located in the other first pixel row.

[0016] According to any one of the aforementioned embodiments of the first aspect of the present invention, the pixel opening further comprises a third pixel opening, and a plurality of the third pixel openings are arranged along the second direction to form a second pixel row, and the first pixel row and the second pixel row are alternately arranged along the first direction.

[0017] According to any one of the aforementioned embodiments of the first aspect of the present invention, two first pixel openings and two second pixel openings are installed around the third pixel opening, and the two first pixel openings and two second pixel openings are alternately distributed around the third pixel opening.

[0018] According to any one of the aforementioned embodiments of the first aspect of the present invention, the orthographic projection of the first signal line in the substrate does not overlap with the orthographic projection of the second pixel opening and the third pixel opening in the substrate, and the orthographic projection of the first signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate in the first direction;

[0019] Preferably, the orthographic projection of the second signal line in the substrate does not overlap with the orthographic projection of the second pixel opening and the third pixel opening in the substrate, and the orthographic projection of the second signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate in the first direction;

[0020] Preferably, the orthographic projection of the third signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the third signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate and the orthographic projection of the second pixel opening in the substrate in the second direction;

[0021] Preferably, the orthographic projection of the fourth signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the fourth signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate and the orthographic projection of the second pixel opening in the substrate in the second direction.

[0022] According to any one of the aforementioned embodiments of the first aspect of the present invention, the first signal line and the fourth signal line are insulated in the second overlapping region, and the second signal line and the third signal line are insulated in the third overlapping region;

[0023] Alternatively, the first signal line and the fourth signal line are insulated in the second overlapping area, and the second signal line and the third signal line are electrically connected in the third overlapping area;

[0024] Alternatively, the first signal line and the fourth signal line are electrically connected in the second overlapping area, and the second signal line and the third signal line are insulated in the third overlapping area;

[0025] Alternatively, the first signal line and the fourth signal line are insulated in part of the second overlapping area and are electrically connected in part of the second overlapping area, and the second signal line and the third signal line are insulated in part of the third overlapping area and are electrically connected in part of the third overlapping area;

[0026] Preferably, the sum of the number of the second overlap area and the third overlap area is 1 / 2 or 1 / 4 of the sum of the number of the second overlap area and the third overlap area.

[0027] According to any one of the aforementioned embodiments of the first aspect of the present invention, the first conductive layer further comprises a fifth signal line and a sixth signal line extending in the first direction, and the second conductive layer further comprises a seventh signal line and an eighth signal line extending in the second direction, wherein the fifth signal line and the sixth signal line are arranged along the second direction, and the seventh signal line and the eighth signal line are arranged along the first direction, and the seventh signal line and the eighth signal line transmit the same signal.

[0028] According to any one of the aforementioned embodiments of the first aspect of the present invention, the third signal line and the fourth signal line are installed adjacent to each other along the first direction, and the seventh signal line and the eighth signal line are installed adjacent to each other along the first direction; the fifth signal line is located between the adjacent first signal line and the second signal line, and the sixth signal line is located between the adjacent first signal line and the second signal line, and the first signal line or the second signal line is installed between the fifth signal line and the sixth signal line.

[0029] According to any one of the aforementioned embodiments of the first aspect of the present invention, the pixel opening comprises a first pixel opening, a second pixel opening, and a third pixel opening, wherein the first pixel opening and the second pixel opening are alternately arranged along the second direction, and the first pixel opening and the second pixel opening are also alternately arranged along the first direction, and a plurality of the first pixel openings and the second pixel openings are alternately arranged along the second direction to form a first pixel row, and a plurality of the third pixel openings are alternately arranged in the second direction to form a second pixel row, and the first pixel row and the second pixel row are alternately arranged along the first direction, and the orthographic projection of the fifth signal line in the substrate does not overlap with the orthographic projection of the first pixel opening and the second pixel opening in the substrate, and the orthographic projection of the first signal line in the substrate passes through the orthographic projection of the third pixel opening in the substrate in the first direction;

[0030] Preferably, the orthographic projections of the second overlapping region and the third overlapping region in the substrate are both located at least partially within the orthographic projection of the first pixel opening in the substrate;

[0031] Preferably, the first overlapping region and the fourth overlapping region are located between the first pixel opening and the second pixel opening that are adjacent to each other along the second direction;

[0032] Preferably, the first overlapping region and the third overlapping region are located in the first pixel row of either of the two adjacent first pixel rows, and the second overlapping region and the fourth overlapping region are located in the other first pixel row;

[0033] Preferably, the orthographic projection of the sixth signal line in the substrate does not overlap with the orthographic projection of the first pixel opening and the second pixel opening in the substrate, and the orthographic projection of the sixth signal line in the substrate passes through the orthographic projection of the third pixel opening in the substrate in the first direction;

[0034] Preferably, the orthographic projection of the seventh signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the seventh signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate and the orthographic projection of the second pixel opening in the substrate in the second direction;

[0035] Preferably, the orthographic projection of the eighth signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the eighth signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate and the orthographic projection of the second pixel opening in the substrate in the second direction.

[0036] According to any one of the aforementioned embodiments of the first aspect of the present invention, the first signal line further comprises a first extension, the first extension is connected to the second overlapping area and is also arranged along the second overlapping area and the second direction, at least a portion of the orthographic projection of the first extension in the substrate is located outside the orthographic projection of the first pixel opening in the substrate, the first extension is electrically connected to the fourth signal line through a first through hole, and the orthographic projection of the first through hole in the substrate does not overlap with the orthographic projection of the first pixel opening in the substrate;

[0037] Preferably, the fifth signal line includes a first isolation region for accommodating the first extension, and at least a portion of the first extension is located in the first isolation region.

[0038] According to any one of the aforementioned embodiments of the first aspect of the present invention, the second signal line further comprises a second extension, the second extension is connected to the third overlapping area and is also arranged along the third overlapping area and the second direction, at least a portion of the orthographic projection of the second extension in the substrate is located outside the orthographic projection of the first pixel opening in the substrate, the second extension is electrically connected to the third signal line through a second through hole, and the orthographic projection of the second through hole in the substrate does not overlap with the orthographic projection of the first pixel opening in the substrate;

[0039] Preferably, the sixth signal line includes a second isolation region for accommodating the second extension, and at least a portion of the second extension is located in the second isolation region.

[0040] According to any one of the aforementioned embodiments of the first aspect of the present invention, the fifth signal line and the seventh signal line have a fifth overlapping region, the fifth signal line and the eighth signal line have a sixth overlapping region, the sixth signal line and the seventh signal line have a seventh overlapping region, the sixth signal line and the eighth signal line have an eighth overlapping region, the fifth signal line and the seventh signal line are electrically connected in the fifth overlapping region, the sixth signal line and the eighth signal line are electrically connected in the eighth overlapping region, and / or, the fifth signal line and the eighth signal line are electrically connected in the sixth overlapping region, and the sixth signal line and the seventh signal line are electrically connected in the seventh overlapping region.

[0041] According to any one of the aforementioned embodiments of the first aspect of the present invention, the third signal line has a first reset signal, and the seventh signal line has a second reset signal;

[0042] Preferably, the display panel further includes a plurality of driving circuits, and the driving circuits are electrically connected to at least one light-emitting unit, and the driving circuits include a first light-emitting control module, a first initialization module, and a second initialization module;

[0043] The control terminal of the second initialization module is electrically connected to the first scanning signal line, the first terminal of the second initialization module is electrically connected to the second reset signal line, and the second terminal of the second initialization module is electrically connected to the first terminal of the first light emission control module;

[0044] The control terminal of the first initialization module is electrically connected to the first scanning signal line, the first terminal of the first initialization module is electrically connected to the first reset signal line, and the second terminal of the first initialization module is electrically connected to the second terminal of the first light emission control module and the light emission unit.

[0045] According to any one of the aforementioned embodiments of the first aspect of the present invention, the display panel further comprises a first high-level signal line located in the second conductive layer, wherein the first high-level signal line extends along the second direction, and the portion located within the projection of the second pixel opening and the first pixel opening in the substrate in the orthographic projection of the first high-level signal line in the substrate is symmetrical with respect to a symmetry axis parallel to the second direction.

[0046] An embodiment of a second aspect of the present application further provides a display panel, wherein the display panel comprises an array substrate, the array substrate comprises a substrate and a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer stacked in a direction away from the substrate.

[0047] The array substrate comprises a first type transistor, a second type transistor, and a capacitor, wherein the first semiconductor layer is used to form a source region, a drain region, and a channel region of the first type transistor, the first metal layer is used to form a gate electrode of the first type transistor and a first electrode plate of the capacitor, the second metal layer is used to form a bottom-gate of the second type transistor, the second semiconductor layer is used to form a source region, a drain region, and a channel region of the second type transistor, the third metal layer is used to form a top-gate of the second type transistor, and the fourth metal layer is used to form the source electrode and drain electrode of the first type transistor and the second type transistor;

[0048] In one of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer, a first signal line and a second signal line extending in a first direction are formed, and the first signal line and the second signal line are arranged along the second direction; in the fourth metal layer, a third signal line and a fourth signal line extending in the second direction are formed, and the third signal line and the fourth signal line are arranged along the first direction, the first direction and the second direction intersect, and the third signal line and the fourth signal line transmit the same signal;

[0049] Along a direction perpendicular to the above substrate, the first signal line and the third signal line have a first overlapping region, the first signal line and the fourth signal line have a second overlapping region, the second signal line and the third signal line have a third overlapping region, the second signal line and the fourth signal line have a fourth overlapping region, and the first signal line and the third signal line are electrically connected in the first overlapping region.

[0050] The first signal line and the fourth signal line are insulated in the second overlapping area, and / or, the second signal line and the third signal line are insulated in the third overlapping area,

[0051] The second signal line and the fourth signal line are electrically connected in the fourth overlapping area, and the orthographic projections of the first overlapping area and the fourth overlapping area in the substrate are both located outside the orthographic projection of a type of pixel opening in the substrate, and the orthographic projections of the second overlapping area and the third overlapping area in the substrate are both located at least partially within the orthographic projection of a type of pixel opening in the substrate.

[0052] According to an embodiment of the second aspect of the present invention, a first insulating layer is formed between the first semiconductor layer and the first metal layer, a second insulating layer is formed between the first metal layer and the second metal layer, a third insulating layer is formed between the second metal layer and the second semiconductor layer, a fourth insulating layer is formed between the second semiconductor layer and the third metal layer, a fifth insulating layer is formed between the third metal layer and the fourth metal layer, and a sixth insulating layer is formed between the fourth metal layer and the fifth metal layer, and the third signal line and the fourth signal line are formed on the fourth metal layer;

[0053] The first signal line and the second signal line are formed in the first metal layer, the first signal line and the third signal line are electrically connected through the first via hole in the first overlapping area, the second signal line and the fourth signal line are electrically connected through the second via hole in the fourth overlapping area, and the first via hole and the second via hole penetrate the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer;

[0054] Alternatively, the first signal line and the second signal line are formed in the second metal layer, the first signal line and the third signal line are electrically connected through a first via hole in the first overlapping region, the second signal line and the fourth signal line are electrically connected through a second via hole in the fourth overlapping region, and the first via hole and the second via hole penetrate the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer;

[0055] Or the first signal line and the second signal line are formed in the fourth metal layer, the first signal line and the third signal line are electrically connected through a first via hole in the first overlapping area, the second signal line and the fourth signal line are electrically connected through a second via hole in the fourth overlapping area, and the first via hole and the second via hole penetrate the sixth insulating layer;

[0056] Alternatively, the first signal line and the second signal line are formed in the third metal layer, the first signal line and the third signal line are electrically connected through a first via hole in the first overlapping region, the second signal line and the fourth signal line are electrically connected through a second via hole in the fourth overlapping region, and the first via hole and the second via hole penetrate the fifth insulating layer and the sixth insulating layer;

[0057] Preferably, the material of the first semiconductor layer comprises a polysilicon semiconductor, and the material of the second semiconductor layer comprises a metal oxide semiconductor.

[0058] According to any one of the aforementioned embodiments of the second aspect of the present invention, the display panel further comprises a light-emitting layer and an isolation structure located on one side of the array substrate, wherein the light-emitting layer comprises a light-emitting unit, and the isolation structure comprises a main body portion and an isolation opening installed openly in the main body portion, and the orthographic projection of the light-emitting unit on the array substrate is located within the orthographic projection of the isolation opening on the array substrate;

[0059] Preferably, the main body comprises a first isolation portion and a second isolation portion, wherein the second isolation portion is located on one side of the first isolation portion facing away from the array substrate, and the orthographic projection of the second isolation portion on the array substrate covers the orthographic projection of the first isolation portion on the array substrate.

[0060] Preferably, the light-emitting unit comprises a first electrode, a light-emitting functional layer, and a second electrode that are stacked and installed in a direction away from the substrate, and the second electrode is electrically connected to the first isolation portion.

[0061] An embodiment of the second aspect of the present application also provides a display device, wherein the display device comprises a display panel according to any one of the first aspects of the present application.

[0062] In the display panel described above according to the present application, the signals within the first signal line and the third signal line are identical, and a first overlapping area is formed at a position where they intersect and is electrically connected so that the first signal line and the third signal line form a mesh structure. Since the orthographic projection of the first overlapping area on the substrate does not overlap with the orthographic projection of the pixel opening on the substrate, the first signal line and the third signal line can be electrically connected through a via hole in the first overlapping area, and since the via hole is not located within the pixel opening area, the presence of the via hole does not cause a display defect of the light-emitting unit corresponding to the pixel opening due to irregularities in the film layer above the via hole. The signals within the second signal line and the fourth signal line are identical, and a fourth overlapping area is formed at a position where they intersect and is electrically connected so that the second signal line and the fourth signal line form a mesh structure. The orthographic projection of the fourth overlapping area in the substrate does not overlap with the orthographic projection of the pixel opening in the substrate, that is, the second signal line and the fourth signal line implement an electrical connection through a via hole in the fourth overlapping area, and since the via hole is not located within the pixel opening area, the presence of the via hole does not cause a display defect of the light-emitting unit corresponding to the pixel opening due to irregularities in the film layer above the via hole. The first signal line and the fourth signal line have a second overlapping area, and the second signal line and the third signal line have a third overlapping area, and the first signal line and the fourth signal line are insulated from the second overlapping area, and the second signal line and the third signal line are insulated from the third overlapping area, and since both the second overlapping area and the third overlapping area in the substrate are located at least partially within the orthographic projection of a pixel opening in the substrate, there is no need to install a via hole at the location of the second overlapping area and the third overlapping area, so the display yield of the light-emitting unit corresponding to the pixel opening is not affected.The above-described display panel according to the present application can improve the display quality of the display panel by improving the problem of large color deviation caused by the presence of via holes, by ensuring that the orthographic projection of via holes required for electrical connection in the substrate is located outside the orthographic projection of the pixel opening in the substrate, based on the implementation that the first signal line and the third signal line are electrically connected and the second signal line and the fourth signal line are electrically connected. Brief explanation of the drawing

[0063] In order to more clearly explain the technical solution means of the embodiments of the present application, the drawings to be used in the embodiments of the present application will be briefly introduced below. It is evident that the drawings described below are merely some embodiments of the present application, and that those skilled in the art can obtain other drawings based on the attached drawings without creative effort. FIG. 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present application. Figure 2 is a cross-sectional view along P-P' of Figure 1. Figure 3 is a partial enlarged view of the Q region of Figure 1. Figure 4 is a partial enlarged view of the Q region of Figure 1. Figure 5 is a partial enlarged view of the Q region of Figure 1. Figure 6 is a partial enlarged view of the Q region of Figure 1. Figure 7 is a partial enlarged view of the Q region of Figure 1. Figure 8 is a partial enlarged view of the Q region of Figure 1. Figure 9 is a partial enlarged view of the Q region of Figure 1. Figure 10 is a partial enlarged view of the Q region of Figure 1. Figure 11 is a partial enlarged view of the Q region of Figure 1. Fig. 12 is a partial enlarged view of Fig. 11. Figure 13 is a partial enlarged view of the Q region of Figure 1. Fig. 14 is a partial enlarged view of Fig. 13. FIG. 15 is a circuit diagram of a driving circuit within a display panel according to an embodiment of the present application. FIG. 16 is a schematic diagram of the structure of a display panel according to an embodiment of the present application. FIG. 17 is a schematic diagram of the structure of a display device according to an embodiment of the present application. Specific details for implementing the invention

[0064] The features of each aspect of the present application and exemplary embodiments are described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced without some of these specific details. The description of the embodiments below is merely to provide a better understanding of the present application by illustrating examples of the application.

[0065] It must be explained that, in this disclosure, relational terms of the first and second types are used merely to distinguish one thing or action from another, and do not require or imply that any such actual relationship or order exists in these things or actions. Furthermore, the terms “include,” “include,” or any other similar terms are meant to cover non-exclusive inclusion, so that a process, method, article, or equipment comprising a series of components includes not only the components mentioned above but also additionally includes other components not explicitly listed, or additionally includes components inherent to such process, method, article, or equipment. Unless otherwise specified, the component defined by the expression “…includes” is not intended to exclude the existence of other identical components in the process, method, article, or equipment comprising said component.

[0066] To better understand the present application, the display panel and display device (2) of an embodiment of the present application will be described in detail below in conjunction with FIGS. 1 to 17.

[0067] Referring to FIGS. 1 to 3, an embodiment of the present application provides a display panel (1), wherein the display panel (1) comprises an array substrate (11), and the array substrate (11) comprises a substrate (110) and a first conductive layer (111), an insulating layer, and a second conductive layer (112) sequentially stacked on one side of the substrate (110); the first conductive layer (111) comprises a first signal line (1111) and a second signal line (1112) extending in a first direction (x); the second conductive layer comprises a third signal line (1121) and a fourth signal line (1122) extending in a second direction (y); the first direction (x) intersects the second direction (y); the first signal line (1111) and the second signal line (1112) are arranged along the second direction (y); and the third signal line (1121) and the fourth The signal line (1122) is arranged along the first direction (x), and the third signal line (1121) and the fourth signal line (1122) transmit the same signal.

[0068] Along a direction perpendicular to the substrate (110), the first signal line (1111) and the third signal line (1121) have a first overlapping area (12), the first signal line (1111) and the fourth signal line (1122) have a second overlapping area (13), the second signal line (1112) and the third signal line (1121) have a third overlapping area (14), the second signal line (1112) and the fourth signal line (1122) have a fourth overlapping area (15), the first signal line (1111) and the third signal line (1121) are electrically connected in the first overlapping area (12), the first signal line (1111) and the fourth signal line (1122) are insulated in the second overlapping area (13), and / or, the second signal line (1112) and the third signal line (1121) are the third The second signal line (1112) and the fourth signal line (1122) are insulated in the overlapping area (14), and are electrically connected in the fourth overlapping area (15).

[0069] The orthographic projections of the first overlapping area (12) and the fourth overlapping area (15) in the substrate (110) are both located outside the orthographic projection of the pixel opening (16) in the substrate (110), and the orthographic projections of the second overlapping area (13) and the third overlapping area (14) in the substrate (110) are both located at least partially within the orthographic projection of a type of pixel opening (16) in the substrate (110), where the pixel opening (16) is located on the side facing the insulating layer from the substrate (110) of the array substrate.

[0070] In the above-described embodiment, the second conductive layer (112) is located on one side of the first conductive layer (111), specifically, it may be located on the upper side of the first conductive layer (111) or on the lower side of the first conductive layer (111), and the present application does not particularly limit this.

[0071] In the above-described embodiment, the first overlapping area (12) is an area where the orthographic projections of the first signal line (1111) and the third signal line (1121) in the substrate (110) overlap each other. The second overlapping area (13) is an area where the orthographic projections of the first signal line (1111) and the third signal line (1121) in the substrate (110) overlap each other. The third overlapping area (14) is an area where the orthographic projections of the second signal line (1112) and the third signal line (1121) in the substrate (110) overlap each other. The fourth overlapping area (15) is an area where the orthographic projections of the second signal line (1112) and the fourth signal line (1122) in the substrate (110) overlap each other.

[0072] The pixel opening (16) is located on the side facing the insulating layer from the substrate (110) of the array substrate (11), that is, on one side of the second conductive layer (112) away from the substrate (110), and the pixel opening (16) is used to accommodate and limit a light-emitting unit.

[0073] In the display panel (1) described above according to the present application, the signals within the first signal line (1111) and the third signal line (1121) are identical, and a first overlapping area (12) is formed at a position where they intersect each other and is electrically connected so that the first signal line (1111) and the third signal line (1121) form a mesh structure. Since the orthographic projection of the first overlapping area (12) in the substrate (110) does not overlap with the orthographic projection of the pixel opening (16) in the substrate (110), the first signal line (1111) and the third signal line (1121) in the first overlapping area (12) can be electrically connected through a via hole, and since the via hole is not located within the pixel opening (16) area, the presence of the via hole does not cause a display defect of the light-emitting unit corresponding to the pixel opening (16) due to the irregularities of the film layer above the via hole.

[0074] The signals within the second signal line (1112) and the fourth signal line (1122) are identical, and a fourth overlapping area (15) is formed at a position where they intersect and is electrically connected, so that the second signal line (1112) and the fourth signal line (1122) form a mesh structure. The orthographic projection of the fourth overlapping area (15) on the substrate (110) does not overlap with the orthographic projection of the pixel opening (16) on the substrate (110), that is, in the fourth overlapping area, the second signal line (1112) and the fourth signal line (1122) are electrically connected through a via hole, and since the via hole is not located within the pixel opening (16) area, the presence of the via hole does not cause a display defect of the light-emitting unit corresponding to the pixel opening (16) due to the irregularities of the film layer above the via hole.

[0075] The first signal line (1111) and the fourth signal line (1122) have a second overlapping area (13), and the second signal line (1112) and the third signal line (1121) have a third overlapping area (14), and the first signal line (1111) and the fourth signal line (1122) are insulated from the second overlapping area (13), and / or, the second signal line (1112) and the third signal line (1121) are insulated from the third overlapping area (14), and the orthographic projections of the second overlapping area (13) and the third overlapping area (14) in the substrate (110) are all located at least partially within the orthographic projection of a type of pixel opening (16) in the substrate (110), so that there is no need to install via holes in the location of the second overlapping area (13) and / or the third overlapping area (14), thereby reducing the number of via holes and emitting light corresponding to the pixel opening (16). It can reduce the impact on the unit's display yield.

[0076] The display panel (1) described above according to the present application can improve the display quality of the display panel (1) by improving the problem of large color deviation caused by the presence of via holes affecting the flatness of the electrodes of the light-emitting unit within the pixel opening (16), thereby improving the display quality of the display panel (1), based on the fact that the third signal line (1121) and the fourth signal line (1122) transmit the same signal, the first signal line (1111) is electrically connected to the third signal line (1121), and the second signal line (1112) is electrically connected to the fourth signal line (1122), by positioning most or all of the orthographic projection of the via holes required for electrical connection in the substrate (110) outside the orthographic projection of the pixel opening (16) in the substrate (110).

[0077] In one executable embodiment, as illustrated in FIG. 4, the pixel opening (16) includes a first pixel opening (161), and the orthographic projections of the second overlapping area (13) and the third overlapping area (14) in the substrate (110) are both located at least partially within the orthographic projection of the first pixel opening (161) in the substrate (110).

[0078] Additionally, the orthographic projections of the first overlapping area (12) and the fourth overlapping area (15) in the substrate (110) are both located outside the orthographic projection of the first pixel opening (161) in the substrate (110).

[0079] In the above-described embodiment, the pixel opening (16) is used to define the light-emitting unit. The light-emitting unit may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit, among which the area of ​​the blue light-emitting unit is relatively large and its color deviation has the most severe effect on the yield of the display panel (1). The first pixel opening (161) may be used to accommodate the blue light-emitting unit.

[0080] By installing the orthographic projections of the second overlapping area (13) and the third overlapping area (14) in the substrate (110) so as to be at least partially located within the orthographic projection of the first pixel opening (161) in the substrate (110), there is no need to install via holes in the location of the second overlapping area (13) and / or the third overlapping area (14). On the one hand, the influence of the second overlapping area (13) and / or the third overlapping area (14) on the flattening of the upper film layer is reduced, thereby ensuring the yield of the blue light-emitting unit, and the problem of poor display of the blue light-emitting unit corresponding to the first pixel opening (161) due to the irregularities of the upper film layer caused by the via holes can be improved.

[0081] On the other hand, since the first pixel opening (161) is relatively large, the orthographic projections of the second overlapping area (13) and the third overlapping area (14) in the substrate (110) are all installed to be at least partially located within the orthographic projection of the first pixel opening (161) in the substrate (110), thereby simplifying the difficulty of wiring and securing wiring spacing. In one feasible embodiment, the display panel (1) may further include a pixel defining layer formed on one side of the conductive layer that is away from the substrate (110) among the first conductive layer (111) and the second conductive layer (112). This can be used to define the pixel opening (16).

[0082] In one executable embodiment, as illustrated in FIG. 4, the pixel opening (16) further includes a second pixel opening (162), the first pixel opening (161) and the second pixel opening (162) are alternately arranged along a second direction (y), the first pixel opening (161) and the second pixel opening (162) are also alternately arranged along a first direction (x), and the first overlapping area (12) and the fourth overlapping area (15) are located between the first pixel opening (161) and the second pixel opening (162) adjacent in the second direction (y). That is, by installing a via hole for implementing an electrical connection between the first signal line (1111) and the third signal line (1121) and a via hole for implementing an electrical connection between the second signal line (1112) and the fourth signal line (1122) between the first pixel opening (161) and the second pixel opening (162), the adverse effect on the light-emitting unit of a different color due to the irregularities of the upper film layer caused by the via hole can be reduced and the display effect can be improved.

[0083] Specifically, the second pixel opening (162) can be used to accommodate a red light-emitting unit.

[0084] In one executable embodiment, as illustrated in FIG. 4, a plurality of first pixel openings (161) and second pixel openings (162) are alternately arranged along a second direction (y) to form a first pixel row, and a first overlapping area (12) and a third overlapping area (14) are located in one of two adjacent first pixel rows, and a second overlapping area (13) and a fourth overlapping area (15) are located in the other first pixel row, thereby enabling the realization that one of the first overlapping area (12) and the fourth overlapping area (15) and one of the second overlapping area (13) or the third overlapping area (14) are all placed in each pixel row, and since electrical connections are realized in the first overlapping area (12) and the fourth overlapping area (15) and are insulated in the second overlapping area (13) and / or the third overlapping area (14), in the above-described embodiment, the first overlapping area (12) and the fourth overlapping area for realizing electrical connections The uniformity of the display panel (1) can be improved by alternately installing a second overlapping area (13) and / or a third overlapping area (14) that can be used for insulation and an area (15) along the first direction (x) and the second direction (y).

[0085] In one executable embodiment, as shown in FIG. 4, the pixel opening (16) further includes a third pixel opening (163), and a plurality of third pixel openings (163) are arranged along a second direction (y) to form a second pixel row, and the first pixel row and the second pixel row are arranged alternately along a first direction (x).

[0086] In the above-described embodiment, the third pixel opening (163) can be used to form a green light-emitting unit.

[0087] In one feasible embodiment, as shown in FIG. 4, two first pixel openings (161) and two second pixel openings (162) are installed around the third pixel opening (163), and the two first pixel openings (161) and two second pixel openings (162) are alternately distributed around the third pixel opening (163). The pixel arrangement method described above can obtain a superior light mixing effect.

[0088] Under the pixel arrangement method described above, the display panel (1) includes a plurality of virtual quadrilaterals (C), and the plurality of virtual quadrilaterals (C) are arranged in rows and columns, and in each virtual quadrilateral (C), two opposing vertices each coincide with the center of the first pixel opening (161), and the other two opposing vertices each coincide with the center of the second pixel opening (162).

[0089] Under the pixel arrangement described above, the orthographic projection of the first signal line (1111) in the substrate (110) does not overlap with the orthographic projection of the second pixel opening (162) and the third pixel opening (163) in the substrate (110), and the orthographic projection of the first signal line (1111) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) in the first direction (x).

[0090] The orthographic projection of the second signal line (1112) in the substrate (110) does not overlap with the orthographic projection of the second pixel opening (162) and the third pixel opening (163) in the substrate (110), and the orthographic projection of the second signal line (1112) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) in the first direction (x).

[0091] The orthographic projection of the third signal line (1121) in the substrate (110) does not overlap with the orthographic projection of the third pixel opening (163) in the substrate (110), and the orthographic projection of the third signal line (1121) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) and the orthographic projection of the second pixel opening (162) in the substrate (110) in the second direction (y).

[0092] The orthographic projection of the fourth signal line (1122) in the substrate (110) does not overlap with the orthographic projection of the third pixel opening (163) in the substrate (110), and the orthographic projection of the fourth signal line (1122) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) and the orthographic projection of the second pixel opening (162) in the substrate (110) in the second direction (y).

[0093] In the above-described embodiment, the orthographic projection of the first signal line (1111) in the substrate (110) does not overlap with the orthographic projection of the second pixel opening (162) and the third pixel opening (163) in the substrate (110), and the orthographic projection of the first signal line (1111) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) in the first direction (x). The orthographic projection of the third signal line (1121) in the substrate (110) does not overlap with the orthographic projection of the third pixel opening (163) in the substrate (110), and the orthographic projection of the third signal line (1121) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) and the orthographic projection of the second pixel opening (162) in the substrate (110) in the second direction (y).

[0094] The projection of one first signal line (1111) or second signal line (1112) in the substrate (110) can pass through the same virtual quadrilateral (C) in the substrate (110), and the projection of the first signal line (1111) in the substrate (110) does not overlap with the projection of the second pixel opening (162) and the third pixel opening (163) in the substrate (110), and the projection of the third signal line (1121) in the substrate (110) passes through the projection of the first pixel opening (161) in the substrate (110) and the projection of the second pixel opening (162) in the substrate (110) in the second direction (y), so that the first overlapping area (12) formed by the overlap between the first signal line (1111) and the third signal line (1121) is the second By positioning the second pixel opening (162) and the first pixel opening (161) along the direction (y), the orthographic projection of the first overlapping area (12) in the substrate (110) is not overlapped with the orthographic projection of the pixel opening (16) in the substrate (110), and by installing the first signal line (1111) and the third signal line (1121) to be electrically connected at the location of the first overlapping area (12), the flatness of the electrode of the light-emitting unit (36) corresponding to the pixel opening (16) is prevented, thereby improving color deviation.

[0095] In the above-described embodiment, the orthographic projection of the second signal line (1112) in the substrate (110) does not overlap with the orthographic projection of the second pixel opening (162) and the third pixel opening (163) in the substrate (110), and the orthographic projection of the second signal line (1112) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) in the first direction (x). The orthographic projection of the fourth signal line (1122) in the substrate (110) does not overlap with the orthographic projection of the third pixel opening (163) in the substrate (110), and the orthographic projection of the fourth signal line (1122) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) and the orthographic projection of the second pixel opening (162) in the substrate (110) in the second direction (y).

[0096] The projection of one first signal line (1111) or one second signal line (1112) in the substrate (110) can pass through the same virtual quadrilateral (C) in the substrate (110), and the projection of the second signal line (1112) in the substrate (110) does not overlap with the projection of the second pixel opening (162) and the third pixel opening (163) in the substrate (110), but overlaps only with the projection of the first pixel opening (161) in the substrate (110), so that the projection of the fourth signal line (1122) in the substrate (110) passes through the projection of the first pixel opening (161) and the second pixel opening (162) in the substrate (110) in the second direction (y) and then the second signal line (1112) and the fourth overlapping area (15) It can be formed such that the orthographic projection of the fourth overlapping area (15) in the substrate (110) is positioned between the orthographic projection of the second pixel opening (162) and the first pixel opening (161) in the substrate (110), so that the orthographic projection of the fourth overlapping area (15) in the substrate (110) does not overlap with the orthographic projection of the pixel opening (16) in the substrate (110), and by installing the second signal line (1112) and the fourth signal line (1122) to be electrically connected at the location of the second overlapping area (13), the flatness of the electrode of the light-emitting unit (36) corresponding to the pixel opening (16) is prevented, thereby improving color deviation.

[0097] In one feasible embodiment, as shown in FIG. 4, the first signal line (1111) and the fourth signal line (1122) are insulated in the second overlapping area (13), and the second signal line (1112) and the third signal line (1121) are insulated in the third overlapping area (14).

[0098] In the above-described embodiment, since the signal lines are insulated in both the second overlapping area (13) and the third overlapping area (14), in the display panel (1), the orthographic projection of the first overlapping area (12) and the fourth overlapping area (15) for electrical connection in the substrate (110) is located outside the pixel opening (16), and since the signal lines in the second overlapping area (13) and the third overlapping area (14), where the orthographic projection in the substrate (110) overlaps with the orthographic projection of the pixel opening (16) in the substrate (110), are all insulated, the via hole used for electrical connection can completely avoid the pixel opening (16) area, so the effect of the via hole used for electrical connection on the color deviation of the light-emitting unit within the pixel opening (16) can be minimized, thereby improving the display quality.

[0099] In another possible embodiment, as illustrated in FIG. 5, the first signal line (1111) and the fourth signal line (1122) are insulated in the second overlapping area (13), and the second signal line (1112) and the third signal line (1121) are electrically connected in the third overlapping area (14). By doing so, the location of the connection point between the second signal line (1112) and the third signal line (1121) can be increased, thereby further enhancing the electrical connection effect between the second signal line (1112) and the third signal line (1121).

[0100] In another possible embodiment, as illustrated in FIG. 6, the first signal line (1111) and the fourth signal line (1122) are electrically connected in the second overlapping area (13), and the second signal line (1112) and the third signal line (1121) are insulated in the third overlapping area (14). By doing so, the location of the connection point between the first signal line (1111) and the fourth signal line (1122) can be increased, thereby further enhancing the electrical connection effect between the first signal line (1111) and the fourth signal line (1122).

[0101] In another possible embodiment, as illustrated in FIGS. 7 and 8, the first signal line (1111) and the fourth signal line (1122) are insulated in part of the second overlapping area (13) and are electrically connected in part of the second overlapping area (13), and the second signal line (1112) and the third signal line (1121) are insulated in part of the third overlapping area (14) and are electrically connected in part of the third overlapping area (14). Thus, the location of the connection point between the first signal line (1111) and the fourth signal line (1122) and the location of the connection point between the second signal line (1112) and the third signal line (1121) can be increased, thereby further enhancing the electrical connection effect between the second signal line (1112) and the third signal line (1121) and further enhancing the electrical connection effect between the first signal line (1111) and the fourth signal line (1122).

[0102] In the above-described embodiment, as shown in FIG. 7, the sum of the number of some pre-set second overlapping areas (13) and some pre-set third overlapping areas (14) may be half the sum of the number of second overlapping areas (13) and third overlapping areas (14), or as shown in FIG. 8, the sum of the number of some pre-set second overlapping areas (13) and some pre-set third overlapping areas (14) may be one-fourth the sum of the number of second overlapping areas (13) and third overlapping areas (14). Accordingly, the number of connection points can be reduced by half or three-quarters, so the color deviation problem can be improved to some extent.

[0103] In one feasible embodiment, as illustrated in FIG. 9, the first conductive layer (111) further comprises a fifth signal line (1113) and a sixth signal line (1114) extending in a first direction (x), and the second conductive layer (112) further comprises a seventh signal line (1123) and an eighth signal line (1124) extending in a second direction (y), wherein the fifth signal line (1113) and the sixth signal line (1114) are arranged along the second direction (y), and the seventh signal line (1123) and the eighth signal line (1124) are arranged along the first direction (x), and the seventh signal line (1123) and the eighth signal line (1124) transmit the same signal.

[0104] In the above-described embodiment, the third signal line (1121) and the fourth signal line (1122) transmit the same signal and also form a network for transmitting one type of signal by crossing the first signal line (1111) and the second signal line (1112); and the seventh signal line (1123) and the eighth signal line (1124) transmit the same signal and also form a network for transmitting another type of signal by crossing the fifth signal line (1113) and the sixth signal line (1114).

[0105] In one executable embodiment, as illustrated in FIG. 9, the third signal line (1121) and the fourth signal line (1122) are installed adjacent to each other along the first direction (x), and the seventh signal line (1123) and the eighth signal line (1124) are installed adjacent to each other along the first direction (x); the fifth signal line (1113) is located between the adjacent first signal line (1111) and the second signal line (1112), and the sixth signal line (1114) is located between the adjacent first signal line (1101) and the second signal line (1112), and the first signal line (1111) or the second signal line (1112) is installed between the fifth signal line (1113) and the sixth signal line (1114).

[0106] In the above-described embodiment, by installing the third signal line (1121) and the fourth signal line (1122) adjacent to each other along the first direction (x), and installing the seventh signal line (1123) and the eighth signal line (1124) adjacent to each other along the first direction (x), insulation can be ensured at the location of the second overlapping area (13) and the third overlapping area (14), while ensuring that the third signal line (1121) and the fourth signal line (1122) are each formed in a mesh shape.

[0107] In one executable embodiment, as illustrated in FIG. 9, the orthographic projection of the fifth signal line (1113) in the substrate (110) does not overlap with the orthographic projection of the first pixel opening (161) and the second pixel opening (162) in the substrate (110), and the orthographic projection of the first signal line (1111) in the substrate (110) passes through the orthographic projection of the third pixel opening (163) in the substrate (110) in the first direction (x).

[0108] The orthographic projection of the sixth signal line (1114) in the substrate (110) does not overlap with the orthographic projection of the first pixel opening (161) and the second pixel opening (162) in the substrate (110), and the orthographic projection of the sixth signal line (1114) in the substrate (110) passes through the orthographic projection of the third pixel opening (163) in the substrate (110) in the first direction (x).

[0109] The orthographic projection of the seventh signal line (1123) in the substrate (110) does not overlap with the orthographic projection of the third pixel opening (163) in the substrate (110), and the orthographic projection of the seventh signal line (1123) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) and the orthographic projection of the second pixel opening (162) in the substrate (110) in the second direction (y).

[0110] The orthographic projection of the eighth signal line (1124) in the substrate (110) does not overlap with the orthographic projection of the third pixel opening (163) in the substrate (110), and the orthographic projection of the eighth signal line (1124) in the substrate (110) passes through the orthographic projection of the first pixel opening (161) in the substrate (110) and the orthographic projection of the second pixel opening (162) in the substrate (110) in the second direction (y).

[0111] In the above-described embodiment, since the fifth signal line (1113) and the sixth signal line (1114) do not pass through the first pixel opening (161) and the second pixel opening (162), the electrically connected positions of the fifth signal line (1113), the sixth signal line (1114), the seventh signal line (1123), and the eighth signal line (1124) can be installed between the first pixel opening (161) and the second pixel opening (162) arranged along the second direction (y), thereby preventing the light emission yield of the light-emitting unit (36) within the pixel opening (16) from being affected.

[0112] In one executable embodiment, as illustrated in FIG. 9, the fifth signal line (1113) and the seventh signal line (1123) have a fifth overlapping area (19), the fifth signal line (1113) and the eighth signal line (1124) have a sixth overlapping area (20), the sixth signal line (1114) and the seventh signal line (1123) have a seventh overlapping area (21), the sixth signal line and the eighth signal line (1124) have an eighth overlapping area (22), the fifth signal line (1113) and the seventh signal line (1123) are electrically connected in the fifth overlapping area (19), the sixth signal line (1114) and the eighth signal line (1124) are electrically connected in the eighth overlapping area (22), and / or, the fifth signal line (1113) and the eighth signal line (1124) are the sixth overlapping The sixth signal line (1114) and the seventh signal line (1123) are electrically connected in the region (20), and the seventh signal line (1123) are electrically connected in the seventh overlapping region (21).

[0113] In the above-described embodiment, as illustrated in FIG. 9, the fifth overlapping region (19), the sixth overlapping region (20), the seventh overlapping region (21), and the eighth overlapping region (22) may all be electrically connected overlapping regions. Alternatively, some may be electrically heated overlapping regions and some may be electrically connected overlapping regions, provided that the fifth signal line (1113), the eighth signal line (1124), the sixth signal line (1114), and the seventh signal line (1123) can be ensured to form a mesh shape, specifically, one mesh shape or two mesh shapes. Specifically, as illustrated in FIG. 10, the fifth signal line (1113) and the seventh signal line (1123) can be electrically connected in the fifth overlapping area (19), the fifth signal line (1113) and the eighth signal line (1124) can be insulated in the sixth overlapping area (20), the sixth signal line (1114) and the seventh signal line (1123) can be insulated in the seventh overlapping area (21), and the sixth signal line and the eighth signal line (1124) can be electrically connected.

[0114] In one executable embodiment, as illustrated in FIGS. 11 and 12, the first signal line (1111) further comprises a first extension (17), the first extension (17) is connected to a second overlapping area (13) and is aligned with the second overlapping area (13) in a second direction (y), at least a portion of the orthographic projection of the first extension (17) in the substrate (110) is located outside the orthographic projection of the first pixel opening (161) in the substrate (110), the first extension (17) is electrically connected to a fourth signal line (1114) through a first through hole, and the orthographic projection of the first through hole in the substrate (110) does not overlap with the orthographic projection of the first pixel opening (161) in the substrate (110).

[0115] In the above-described embodiment, an electrical connection between the first signal line (1111) and the fourth signal line (1122) can be realized by opening and installing a first through hole in the first extension part (17). Specifically, the first through hole is formed in the first extension part (17), and the first extension part (17) is connected to the second overlapping area (13) to increase the overlapping area of ​​the first signal line (1111) and the fourth signal line (1122). The first signal line (1111) and the fourth signal line (1122) can be overlapped through the first extension part (17), and the position where the first through hole is formed can be moved outside the orthographic projection of the pixel opening (16) in the substrate (110) to realize an electrical connection between the first signal line (1111) and the fourth signal line (1122), and the first through hole can be prevented from affecting the color deviation of the light-emitting unit (36) within the pixel opening (16).

[0116] In the above-described embodiment, the fifth signal line (1113) includes a first isolation area for accommodating the first extension (17), and at least a portion of the first extension (17) is located in the first isolation area.

[0117] Since the distance between the fifth signal line (1113) and the first signal line (1111) is short, a first isolation area is installed openly on the fifth signal line (1113) to accommodate the first extension (17), thereby providing a condition for installing a first through hole on the first extension (17).

[0118] In one executable embodiment, as illustrated in FIGS. 13 and 14, the second signal line (1112) further comprises a second extension (18), the second extension (18) is connected to a third overlapping area (14) and is aligned with the third overlapping area (14) in a second direction (y), at least a portion of the orthographic projection of the second extension (18) in the substrate (110) is located outside the orthographic projection of the first pixel opening (161) in the substrate (110), the second extension (18) is electrically connected to the third signal line (1121) through a second through hole, and the orthographic projection of the second through hole in the substrate (110) does not overlap with the orthographic projection of the first pixel opening (161) in the substrate (110).

[0119] In the above-described embodiment, an electrical connection between the second signal line (1112) and the third signal line (1121) can be realized by opening and installing a second through-hole in the second extension part (18). Specifically, the second through-hole is formed in the second extension part (18), and the second extension part (18) is connected to the third overlapping area (14) to increase the overlapping area of ​​the second signal line (1112) and the third signal line (1121). The second signal line (1112) and the third signal line (1121) can be overlapped through the second extension part (18), and the position where the second through-hole is formed can be moved outside the orthographic projection of the pixel opening (16) in the substrate (110) to realize an electrical connection between the second signal line (1112) and the third signal line (1121), and the second through-hole can be prevented from affecting the color deviation of the light-emitting unit (36) within the pixel opening (16).

[0120] In the above-described embodiment, the sixth signal line (1114) includes a second isolation area for accommodating the second extension (18), and at least a portion of the second extension (18) is located in the second isolation area.

[0121] Since the distance between the sixth signal line (1114) and the second signal line (1112) is short, a second isolation area is installed openly on the sixth signal line (1114) to accommodate the second extension (18), thereby providing a condition for installing a second through hole in the second extension (18).

[0122] In one executable embodiment, a first high-level signal line is further included in the second conductive layer (112), the first high-level signal line extends along the second direction (y), and the portion located within the projection of the first high-level signal line in the substrate (110) and the second pixel opening (162) and the first pixel opening (161) in the substrate (110) is symmetric with respect to a symmetry axis parallel to the second direction (y).

[0123] By doing so, the symmetry of the first electrode (361) of the light-emitting unit (36) can be further strengthened to improve the color deviation phenomenon and improve the display quality of the display panel (1).

[0124] In one feasible embodiment, the second conductive layer (112) is located on one side of the first conductive layer (111) facing away from the substrate (110).

[0125] In one executable embodiment, the signals in the first signal line (1111) and the fifth signal line (1113) are different.

[0126] Specifically, the first signal line (1111) has a first reset signal, that is, the first signal line (1111), the second signal line (1112), the third signal line (1121), and the fourth signal line (1122) are all the first reset signal line (Vref1), and the fifth signal line (1113) has a second reset signal, that is, the fifth signal line (1113), the sixth signal line (1114), the seventh signal line (1123), and the eighth signal line (1124) are all the second reset signal line (Vref2).

[0127] Specifically, as illustrated in FIG. 15, the driving circuit is electrically connected to at least one light-emitting unit (36), and the driving circuit includes a first light-emitting control module (500), a first initialization module (700), and a second initialization module (800). The control terminal of the second initialization module (800) is electrically connected to the first scanning signal line (S1), the first terminal of the second initialization module (800) is electrically connected to the second reset signal line (Vref2), and the second terminal of the second initialization module (800) is electrically connected to the first terminal of the first light-emitting control module (500). The control terminal of the first initialization module (700) is electrically connected to the first scanning signal line (S1), the first terminal of the first initialization module (700) is electrically connected to the first reset signal line (Vref1), and the second terminal of the first initialization module (700) is electrically connected to the second terminal of the first light emission control module (500) and the light emission unit (36). The control terminal of the first light emission control module (500) is electrically connected to the light emission control signal line (EM), the first terminal of the first light emission control module (500) is electrically connected to the second initialization module (800), and the second terminal of the first light emission control module (500) is electrically connected to the first initialization module (700) and the light emission unit (36).

[0128] The driving circuit further includes a driving module (100), a data writing module (200), a compensation module (300), a storage module (400), a second light emission control module (600), and a third initialization module (900), and the display panel (1) further includes a first high-level signal line (ELVDD), a first low-level signal line (ELVSS), a second scanning signal line (S2), a first scanning signal line (S1), a third scanning signal line (S3), a fourth scanning signal line (S4), a light emission control signal line (EM), a data signal line (Data), and a third reset signal line (Vref3), wherein,

[0129] The control terminal of the second light emission control module (600) is connected to the light emission control signal line (EM), the first terminal of the second light emission control module (600) is connected to the first high-level signal line (ELVDD) and the first terminal of the storage module (400), and the second terminal of the second light emission control module (600) is connected to the second terminal of the data writing module (200) and the first terminal of the driving module (100);

[0130] The first terminal of the storage module (400) is connected to the first high-level signal line (ELVDD) and the first terminal of the second light-emitting control module (600), and the second terminal of the storage module (400) is connected to the first terminal of the compensation module (300) and the control terminal of the driving module (100);

[0131] The control terminal of the data entry module (200) is electrically connected to the second scanning signal line (S2), the first terminal of the data entry module (200) is electrically connected to the data signal line (Data), and the second terminal of the data entry module (200) is connected to the first terminal of the driving module (100) and the second terminal of the second light emission control module (600);

[0132] The control terminal of the compensation module (300) is connected to the fourth scanning signal line (S4), the first terminal of the compensation module (300) is connected to the second terminal of the storage module (400) and the control terminal of the driving module (100), and the second terminal of the compensation module (300) is electrically connected to the first node (N);

[0133] The control terminal of the driving module (100) is electrically connected to the second terminal of the storage module (400) and the first terminal of the compensation module (300), the first terminal of the driving module (100) is connected to the second terminal of the data writing module (200) and the second terminal of the second light emission control module (600), and the second terminal of the driving module (100) is electrically connected to the first node (N);

[0134] The control terminal of the first light emission control module (500) is electrically connected to the light emission control signal line (EM), the first terminal of the first light emission control module (500) is electrically connected to the second initialization module (800) and the first node (N), and the second terminal of the first light emission control module (500) is electrically connected to the first initialization module (700) and the light emission unit (36);

[0135] The control terminal of the second initialization module (800) is electrically connected to the first scanning signal line (S1), the first terminal of the second initialization module (800) is electrically connected to the second reset signal line (Vref2), and the second terminal of the second initialization module (800) is electrically connected to the first terminal and the first node (N) of the first light emission control module (500);

[0136] The control terminal of the first initialization module (700) is electrically connected to the first scanning signal line (S1), the first terminal of the first initialization module (700) is electrically connected to the first reset signal line (Vref1), and the second terminal of the first initialization module (700) is electrically connected to the second terminal of the first light emission control module (500) and the light emission unit (36);

[0137] The control terminal of the third initialization module (900) is electrically connected to the third scanning signal line (S3), the first terminal of the third initialization module (900) is electrically connected to the third reset signal line (Vref3), and the second terminal of the third initialization module (900) is electrically connected to the second terminal of the second initialization module (800) and the first node (N);

[0138] The light-emitting unit (36) includes a first electrode (361) and a second electrode (363), the first electrode (361) is electrically connected to the second terminal of the first initialization module (700) and the second terminal of the first light-emitting control module (500), and the second electrode (363) is electrically connected to the first low-level signal line (ELVSS).

[0139] In the above-described embodiment, the first initialization module (700) is used to reset the first electrode (361) of the light-emitting unit (36), the second initialization module (800) is used to reset the second stage of the driving module (100), and the third initialization module (900) is used to reset the control stage of the driving module (100) to contribute to improving display quality.

[0140] The present application also provides a display panel (1), as illustrated in FIG. 16, wherein the display panel (1) comprises an array substrate (11), and the array substrate (11) comprises a first semiconductor layer (23), a first metal layer (24), a second metal layer (25), a second semiconductor layer (26), a third metal layer (27), a fourth metal layer (28) and a fifth metal layer (29) stacked along a direction away from the substrate (110), wherein,

[0141] The array substrate (11) includes a first type transistor, a second type transistor, and a capacitor, and the first semiconductor layer (23) is used to form the source region, drain region, and channel region of the first type transistor, the first metal layer (24) is used to form the gate electrode of the first type transistor and the first electrode plate of the capacitor, the second metal layer (25) is used to form the bottom-gate of the second type transistor, the second semiconductor layer (26) is used to form the source region, drain region, and channel region of the second type transistor, the third metal layer (27) is used to form the top-gate of the second type transistor, and the fourth metal layer (28) is used to form the source electrode and drain electrode of the first type transistor and the second type transistor.

[0142] Here, a first signal line (1111) and a second signal line (1112) extending in a first direction (x) are formed in one of the first metal layer (24), the second metal layer (25), the fourth metal layer (28), and the third metal layer (27), and the first signal line (1111) and the second signal line (1112) are arranged along a second direction (y), and a third signal line (1121) and a fourth signal line (1122) extending in a second direction (y) are formed in the fifth metal layer (29), and the third signal line (1121) and the fourth signal line (1122) are arranged along a first direction (x), the first direction (x) and the second direction (y) intersect each other, and the third signal line (1121) and the fourth signal line (1122) transmit the same signal.

[0143] Along a direction perpendicular to the substrate (110), the first signal line (1111) and the third signal line (1121) have a first overlapping area (12), the first signal line (1111) and the fourth signal line (1122) have a second overlapping area (13), the second signal line (1112) and the third signal line (1121) have a third overlapping area (14), the second signal line (1112) and the fourth signal line (1122) have a fourth overlapping area (15), the first signal line (1111) and the third signal line (1121) are electrically connected in the first overlapping area (12), the first signal line (1111) and the fourth signal line (1122) are insulated in the second overlapping area (13), and / or, the second signal line (1112) and the third signal line (1121) are the third The second signal line (1112) and the fourth signal line (1122) are insulated in the overlapping area (14), and the second signal line (1112) and the fourth signal line (1122) are electrically connected in the fourth overlapping area (15). The orthographic projections of the first overlapping area (12) and the fourth overlapping area (15) in the substrate (110) are both located outside the orthographic projection of the pixel opening (16) in the substrate (110), and the orthographic projections of the second overlapping area (13) and the third overlapping area (14) in the substrate (110) are both located at least partially within the orthographic projection of a type of pixel opening (16) in the substrate (110).

[0144] In the display panel (1) described above according to the present application, the signals within the first signal line (1111) and the third signal line (1121) are identical, and a first overlapping area (12) is formed at a position where they intersect each other and is electrically connected so that the first signal line (1111) and the third signal line (1121) form a mesh structure. Since the orthographic projection of the first overlapping area (12) in the substrate (110) does not overlap with the orthographic projection of the pixel opening (16) in the substrate (110), the first signal line (1111) and the third signal line (1121) in the first overlapping area (12) can be electrically connected through a via hole, and since the via hole is not located within the pixel opening (16) area, the presence of the via hole does not cause a display defect of the light-emitting unit (36) corresponding to the pixel opening (16) due to the irregularities of the film layer above the via hole.

[0145] The signals within the second signal line (1112) and the fourth signal line (1122) are identical, and a fourth overlapping area (15) is formed at a position where they intersect each other and is electrically connected so that the second signal line (1112) and the fourth signal line (1122) form a mesh structure. The orthographic projection of the fourth overlapping area (15) on the substrate (110) does not overlap with the orthographic projection of the pixel opening (16) on the substrate (110), that is, the second signal line (1112) and the fourth signal line (1122) are electrically connected through a via hole in the fourth overlapping area (15), and since the via hole is not located within the pixel opening (16) area, the presence of the via hole does not cause a display defect of the light-emitting unit corresponding to the pixel opening (16) due to the irregularities of the film layer above the via hole.

[0146] The first signal line (1111) and the fourth signal line (1122) have a second overlapping area (13), and the second signal line (1112) and the third signal line (1121) have a third overlapping area (14), and the first signal line (1111) and the fourth signal line (1122) are insulated from the second overlapping area (13), and / or, the second signal line (1112) and the third signal line (1121) are insulated from the third overlapping area (14), and the orthographic projections of the second overlapping area (13) and the third overlapping area (14) in the substrate (110) are all located at least partially within the orthographic projection of a type of pixel opening (16) in the substrate (110), so that there is no need to install via holes in the location of the second overlapping area (13) and / or the third overlapping area (14), thereby reducing the number of via holes and emitting light corresponding to the pixel opening (16). The effect on the display yield of the unit (36) can be reduced.

[0147] The display panel (1) described above according to the present application can improve the display quality of the display panel (1) by improving the problem of large color deviation caused by the presence of via holes affecting the flatness of the electrodes of the light-emitting unit (36) within the pixel opening (16), by implementing the third signal line (1121) and the fourth signal line (1122) transmitting the same signal, the first signal line (1111) being electrically connected to the third signal line (1121), and the second signal line (1112) being electrically connected to the fourth signal line (1122), by positioning most or all of the orthographic projection of via holes required for electrical connection in the substrate (110) outside the orthographic projection of the pixel opening (16) in the substrate (110).

[0148] Specifically, the material of the first semiconductor layer (23) includes a polysilicon semiconductor, and the material of the second semiconductor layer (26) includes a metal oxide semiconductor.

[0149] In the above-described embodiment, the second type transistor is an oxide semiconductor transistor, and the second type transistor may be a double gate transistor.

[0150] In the above-described embodiment, a first insulating layer (30) is formed between the first semiconductor layer (23) and the first metal layer (24), a second insulating layer (31) is formed between the first metal layer (24) and the second metal layer (25), a third insulating layer (32) is formed between the second metal layer (25) and the second semiconductor layer (26), a fourth insulating layer (33) is formed between the second semiconductor layer (26) and the third metal layer (27), a fifth insulating layer (34) is formed between the third metal layer (27) and the fourth metal layer (28), a sixth insulating layer (35) is formed between the fourth metal layer (28) and the fifth metal layer (29), and the third signal line (1121) and the fourth signal line (1122) are formed on the fifth metal layer (29).

[0151] In one executable embodiment, a first signal line (1111) and a second signal line (1112) are formed in a first metal layer (24), the first signal line (1111) and a third signal line (1121) are electrically connected through a first via hole in a first overlapping area (12), the second signal line (1112) and a fourth signal line (1122) are electrically connected through a second via hole in a fourth overlapping area (15), and the first via hole and the second via hole penetrate a second insulating layer (31), a third insulating layer (32), a fourth insulating layer (33), a fifth insulating layer (34), and a sixth insulating layer (35).

[0152] In another feasible embodiment, the first signal line (1111) and the second signal line (1112) are formed in the second metal layer (25), the first signal line (1111) and the third signal line (1121) are electrically connected through the first via hole in the first overlapping area (12), the second signal line (1112) and the fourth signal line (1122) are electrically connected through the second via hole in the fourth overlapping area (15), and the first via hole and the second via hole penetrate the third insulating layer (32), the fourth insulating layer (33), the fifth insulating layer (34), and the sixth insulating layer (35).

[0153] In another feasible embodiment, the first signal line (1111) and the second signal line (1112) are formed in the fourth metal layer (28), the first signal line (1111) and the third signal line (1121) are electrically connected through the first via hole in the first overlapping area (12), the second signal line (1112) and the fourth signal line (1122) are electrically connected through the second via hole in the fourth overlapping area (15), and the first via hole and the second via hole penetrate the sixth insulating layer (35).

[0154] In another feasible embodiment, the first signal line (1111) and the second signal line (1112) are formed in the third metal layer (27), the first signal line (1111) and the third signal line (1121) are electrically connected through the first via hole in the first overlapping area (12), the second signal line (1112) and the fourth signal line (1122) are electrically connected through the second via hole in the fourth overlapping area (15), and the first via hole and the second via hole penetrate the fifth insulating layer (34) and the sixth insulating layer (35).

[0155] In one executable embodiment, as shown in FIG. 16, the array substrate (11) further comprises a light-emitting layer and an isolation structure (37) located on one side thereof, wherein the light-emitting layer comprises a light-emitting unit (36), and the isolation structure (37) comprises a main body and an isolation opening (370) installed openly in the main body, and the orthographic projection of the light-emitting unit (36) on the array substrate (11) is located within the orthographic projection of the isolation opening (370) on the array substrate (11).

[0156] Specifically, the light-emitting unit (36) includes a first electrode (361), a light-emitting functional layer (362), and a second electrode (363) that are stacked and installed in a direction away from the substrate.

[0157] In the above-described embodiment, the isolation structure (37) can be used to isolate the second electrode (363) of the light-emitting unit (36) and the light-emitting functional layer (362), thereby enabling independence of different light-emitting units (36), improving crosstalk problems between adjacent light-emitting units (36), and helping to improve the display quality of the display panel (1). At the same time, by adopting the isolation structure (37), there is no need to use a mask plate in the manufacturing process of the light-emitting unit (36), which, on the one hand, can improve the aperture ratio by reducing the gap between the light-emitting units (36), and on the other hand, can reduce costs.

[0158] Specifically, the isolation structure (37) includes a first isolation section (371) and a second isolation section (372), the second isolation section (372) is located on one side of the first isolation section (371) facing away from the substrate (110), and the orthographic projection of the second isolation section (372) on the substrate (110) covers the orthographic projection of the first isolation section (371) on the substrate (110).

[0159] In the above-described embodiment, a step portion may be formed between the second isolation portion (372) and the first isolation portion (371) in the isolation structure (37), and the light-emitting functional layer (362) and the second electrode (363) may be separated at the step portion to realize independence between different light-emitting units (36). Additionally, optionally, the second electrode (363) is electrically connected to the first isolation portion (371), which helps to realize the transmission requirement of a power signal required within the second electrode (363).

[0160] Patent PCT / CN2023 / 134518, Patent 202310759370.2, Patent 202310740412.8, Patent 202310707209.0 and Patent 202311346196.5 describe related technical solutions for isolation structures, the contents of which are incorporated into this specification by reference.

[0161] The present application also provides a display device (2), which includes one of the display panels (1) according to the above-described embodiments of the present application, as shown in FIG. 17.

[0162] The above display device (2) helps to improve the color deviation problem and enhance the display quality, thereby further improving the user experience.

[0163] The display device (2) may be a mobile terminal such as a mobile phone or a laptop computer, or a fixed terminal such as a television or a computer monitor, or a wearable device such as a watch, etc., and the present application is not specifically limited.

[0164] According to the embodiments described above in this application, such embodiments are not detailed, nor is the invention limited to specific embodiments. Of course, many modifications and variations may be made in accordance with the description above. To better interpret the principles and practical applications of this application, these embodiments have been selected and described in detail in this specification, thereby enabling those skilled in the art to make good use of this application and modifications based on this application. This application is limited only by the claims and their entire scope and equivalents. Explanation of the symbols

[0165] 1-Display panel; 11-Array substrate; 110-Substrate; 111-First conductive layer; 1111-First signal line; 1112-Second signal line; 1113-Fifth signal line; 1114-Sixth signal line; 112-Second conductive layer; 1121-Third signal line; 1122-Fourth signal line; 1123-Seventh signal line; 1124-Eighth signal line; 12-First overlapping region; 13-Second overlapping region; 14-Third overlapping region; 15-Fourth overlapping region; 16-Pixel aperture; 161-First pixel aperture; 162-Second pixel aperture; 163-Third pixel aperture; 17-First extension; 18-Second extension; 19-Fifth overlapping region; 20-Sixth overlapping region; 21-7th overlapping region; 22-8th overlapping region; 23-1st semiconductor layer; 24-1st metal layer; 25-2nd metal layer; 26-2nd semiconductor layer; 27-3rd metal layer; 28-4th metal layer; 29-5th metal layer; 30-1st insulating layer; 31-2nd insulating layer; 32-3rd insulating layer; 33-4th insulating layer; 34-5th insulating layer; 35-6th insulating layer; 36- Light-emitting unit; 361-1st electrode; 362-Light-emitting functional layer; 363-2nd electrode; 37 Isolation structure; 371-1st isolation section; 372-2nd isolation section; 370-Isolation aperture; 100-Driving module; 200-Data writing module; 300-Compensation module; 400-Storage module; 500-1st light emission control module; 600-2nd light emission control module; 700-1st initialization module; 800-2nd initialization module; 900-3rd initialization module; Vref1-1st reset signal line; Vref2-2nd reset signal line; ELVDD-1st high level signal line; ELVSS-1st low level signal line; S1-1st scanning signal line; S2-2nd scanning signal line; S3-3rd scanning signal line; S4-4th scanning signal line; EM-light emission control signal line; Data-data signal line; Vref3-3rd reset signal line; 2-display device.

Claims

Claim 1 A display panel comprises an array substrate, wherein the array substrate comprises a substrate and a first conductive layer, an insulating layer, and a second conductive layer sequentially stacked on one side of the substrate, wherein the first conductive layer comprises a first signal line and a second signal line extending in a first direction, and the second conductive layer comprises a third signal line and a fourth signal line extending in a second direction, wherein the first direction and the second direction intersect, the first signal line and the second signal line are arranged along the second direction, the third signal line and the fourth signal line are arranged along the first direction, the third signal line and the fourth signal line transmit the same signal, and the first signal line, the second signal line, the third signal line, and the fourth signal line transmit a first reset signal;Along a direction perpendicular to the substrate, the first signal line and the third signal line have a first overlapping region, the first signal line and the fourth signal line have a second overlapping region, the second signal line and the third signal line have a third overlapping region, the second signal line and the fourth signal line have a fourth overlapping region, the first signal line and the third signal line are electrically connected in the first overlapping region, and the first signal line and the fourth signal line are insulated in the second overlapping region, and / or, the second signal line and the third signal line are insulated in the third overlapping region, and the second signal line and the fourth signal line are electrically connected in the fourth overlapping region, and the orthographic projections of the first overlapping region and the fourth overlapping region in the substrate are both located outside the orthographic projection of a certain pixel aperture in the substrate, and the orthographic projections of the second overlapping region and the third overlapping region in the substrate are both within the orthographic projection of a certain pixel aperture in the substrate A display panel characterized by being located at least partially, wherein the pixel opening is located on the side facing the insulating layer from the substrate of the array substrate. Claim 2 A display panel according to claim 1, wherein the pixel opening includes a first pixel opening, and the orthographic projections of the second overlapping area and the third overlapping area in the substrate are both located at least partially within the orthographic projection of the first pixel opening in the substrate; and the orthographic projections of the first overlapping area and the fourth overlapping area in the substrate are both located outside the orthographic projection of the first pixel opening in the substrate, and the first pixel opening is used to accommodate a blue light-emitting unit. Claim 3 A display panel according to claim 2, wherein the pixel opening further comprises a second pixel opening, the first pixel opening and the second pixel opening are alternately arranged along the second direction, the first pixel opening and the second pixel opening are also alternately arranged along the first direction, the first overlapping area and the fourth overlapping area are located between the first pixel opening and the second pixel opening adjacent in the second direction; and the second pixel opening is used to accommodate a red light-emitting unit. Claim 4 A display panel according to claim 3, wherein a plurality of the first pixel openings and the second pixel openings are alternately arranged along a second direction to form a first pixel row, the first overlapping area and the third overlapping area are located in one of the first pixel rows among two adjacent first pixel rows, and the second overlapping area and the fourth overlapping area are located in the other first pixel row. Claim 5 A display panel according to claim 4, wherein the pixel opening further includes a third pixel opening, a plurality of the third pixel openings are arranged along the second direction to form a second pixel row, and the first pixel row and the second pixel row are alternately arranged along the first direction. Claim 6 A display panel according to claim 5, characterized in that two first pixel openings and two second pixel openings are installed around the perimeter of the third pixel opening, and the two first pixel openings and two second pixel openings are alternately distributed around the perimeter of the third pixel opening. Claim 7 In paragraph 5, the orthographic projection of the first signal line in the substrate does not overlap with the orthographic projection of the second pixel opening and the third pixel opening in the substrate, and the orthographic projection of the first signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate in the first direction; the orthographic projection of the second signal line in the substrate does not overlap with the orthographic projection of the second pixel opening and the third pixel opening in the substrate, and the orthographic projection of the second signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate in the first direction; the orthographic projection of the third signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the third signal line in the substrate is the orthographic projection of the first pixel opening in the substrate and the second pixel opening in the substrate A display panel characterized by passing an orthographic projection in the second direction; wherein the orthographic projection of the fourth signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the fourth signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate and the orthographic projection of the second pixel opening in the substrate in the second direction. Claim 8 In claim 1, the first signal line and the fourth signal line are insulated in the second overlapping area, and the second signal line and the third signal line are insulated in the third overlapping area; or, the first signal line and the fourth signal line are insulated in the second overlapping area, and the second signal line and the third signal line are electrically connected in the third overlapping area; or, the first signal line and the fourth signal line are electrically connected in the second overlapping area, and the second signal line and the third signal line are insulated in the third overlapping area; or, the first signal line and the fourth signal line are insulated in a part of the second overlapping area and are electrically connected in a partially predetermined second overlapping area, and the second signal line and the third signal line are insulated in a part of the third overlapping area and are electrically connected in a partially predetermined third overlapping area; and the sum of the number of the partially predetermined second overlapping area and the partially predetermined third overlapping area is 1 / 2 of the sum of the number of the second overlapping area and the third overlapping area or A display panel characterized by being 1 / 4. Claim 9 A display panel according to claim 1, wherein the first conductive layer further comprises a fifth signal line and a sixth signal line extending in the first direction, and the second conductive layer further comprises a seventh signal line and an eighth signal line extending in the second direction, wherein the fifth signal line and the sixth signal line are arranged along the second direction, the seventh signal line and the eighth signal line are arranged along the first direction, and the seventh signal line and the eighth signal line transmit the same signal. Claim 10 A display panel according to claim 9, wherein the third signal line and the fourth signal line are installed adjacent to each other along the first direction, and the seventh signal line and the eighth signal line are installed adjacent to each other along the first direction; the fifth signal line is located between the adjacent first signal line and the second signal line, and the sixth signal line is located between the adjacent first signal line and the second signal line, and the first signal line or the second signal line is installed between the fifth signal line and the sixth signal line. Claim 11 In claim 10, the pixel opening comprises a first pixel opening, a second pixel opening, and a third pixel opening, wherein the first pixel opening and the second pixel opening are alternately arranged along the second direction, and the first pixel opening and the second pixel opening are also alternately arranged along the first direction, and a plurality of the first pixel openings and the second pixel openings are alternately arranged along the second direction to form a first pixel row, and a plurality of the third pixel openings are alternately arranged in the second direction to form a second pixel row, and the first pixel row and the second pixel row are alternately arranged along the first direction, and the orthographic projection of the fifth signal line in the substrate does not overlap with the orthographic projection of the first pixel opening and the second pixel opening in the substrate, and the orthographic projection of the first signal line in the substrate passes through the orthographic projection of the third pixel opening in the substrate in the first direction; and the second overlap in the substrate The orthographic projections of the region and the third overlapping region are all located at least partially within the orthographic projection of the first pixel opening in the substrate; the first overlapping region and the fourth overlapping region are located between the first pixel opening and the second pixel opening adjacent to each other along the second direction; the first overlapping region and the third overlapping region are located in the first pixel row of either of the two adjacent first pixel rows, and the second overlapping region and the fourth overlapping region are located in the other first pixel row; the orthographic projection of the sixth signal line in the substrate does not overlap with the orthographic projections of the first pixel opening and the second pixel opening in the substrate, and the orthographic projection of the sixth signal line in the substrate passes through the orthographic projection of the third pixel opening in the substrate in the first direction;A display panel characterized in that the orthographic projection of the seventh signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the seventh signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate and the orthographic projection of the second pixel opening in the substrate in the second direction; and the orthographic projection of the eighth signal line in the substrate does not overlap with the orthographic projection of the third pixel opening in the substrate, and the orthographic projection of the eighth signal line in the substrate passes through the orthographic projection of the first pixel opening in the substrate and the orthographic projection of the second pixel opening in the substrate in the second direction. Claim 12 A display panel according to claim 11, wherein the first signal line further comprises a first extension, the first extension is connected to the second overlapping area and is also arranged along the second overlapping area and the second direction, and at least a portion of the orthographic projection of the first extension in the substrate is located outside the orthographic projection of the first pixel opening in the substrate, and the first extension is electrically connected to the fourth signal line through a first through hole, and the orthographic projection of the first through hole in the substrate does not overlap with the orthographic projection of the first pixel opening in the substrate; and the fifth signal line comprises a first isolation area for accommodating the first extension, and at least a portion of the first extension is located in the first isolation area. Claim 13 A display panel according to claim 11, wherein the second signal line further comprises a second extension, the second extension is connected to the third overlapping area and is also arranged along the third overlapping area and the second direction, and at least a portion of the orthographic projection of the second extension in the substrate is located outside the orthographic projection of the first pixel opening in the substrate, and the second extension is electrically connected to the third signal line through a second through hole, and the orthographic projection of the second through hole in the substrate does not overlap with the orthographic projection of the first pixel opening in the substrate; and the sixth signal line comprises a second isolation area for accommodating the second extension, and at least a portion of the second extension is located in the second isolation area. Claim 14 A display panel according to claim 9, wherein the fifth signal line and the seventh signal line have a fifth overlapping region, the fifth signal line and the eighth signal line have a sixth overlapping region, the sixth signal line and the seventh signal line have a seventh overlapping region, the sixth signal line and the eighth signal line have an eighth overlapping region, the fifth signal line and the seventh signal line are electrically connected in the fifth overlapping region, the sixth signal line and the eighth signal line are electrically connected in the eighth overlapping region, and / or, the fifth signal line and the eighth signal line are electrically connected in the sixth overlapping region, and the sixth signal line and the seventh signal line are electrically connected in the seventh overlapping region. Claim 15 In claim 9, the display panel is characterized in that the seventh signal line has a second reset signal; the display panel further comprises a plurality of driving circuits, wherein the driving circuit is electrically connected to at least one light-emitting unit, and the driving circuit comprises a first light-emitting control module, a first initialization module, and a second initialization module; wherein the control terminal of the second initialization module is electrically connected to a first scanning signal line, the first terminal of the second initialization module is electrically connected to a second reset signal line, and the second terminal of the second initialization module is electrically connected to the first terminal of the first light-emitting control module; and wherein the control terminal of the first initialization module is electrically connected to the first scanning signal line, the first terminal of the first initialization module is electrically connected to a first reset signal line, and the second terminal of the first initialization module is electrically connected to the second terminal of the first light-emitting control module and the light-emitting unit. Claim 16 In paragraph 3, the display panel further comprises a first high-level signal line located in the second conductive layer, wherein the first high-level signal line extends along the second direction, and the portion located within the projection of the second pixel opening and the first pixel opening in the substrate during the projection of the first high-level signal line in the substrate is symmetrical with respect to a symmetry axis parallel to the second direction. Claim 17 In a display panel, the display panel comprises an array substrate, wherein the array substrate comprises a substrate and a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a fourth metal layer, and a fifth metal layer stacked in a direction away from the substrate, wherein the array substrate comprises a first type transistor, a second type transistor, and a capacitor, wherein the first semiconductor layer is used to form a source region, a drain region, and a channel region of the first type transistor, the first metal layer is used to form a gate electrode of the first type transistor and a first electrode plate of the capacitor, the second metal layer is used to form a lower gate of the second type transistor, the second semiconductor layer is used to form a source region, a drain region, and a channel region of the second type transistor, the third metal layer is used to form an upper gate of the second type transistor, and the fourth metal layer is used to form a source electrode and a drain electrode of the first type transistor and the second type transistor; wherein the first metal layer, the second metal layer, the third metal layer, and the One of the fourth metal layers has a first signal line and a second signal line formed extending in a first direction, and the first signal line and the second signal line are arranged along a second direction, and the fourth metal layer has a third signal line and a fourth signal line formed extending in a second direction, and the third signal line and the fourth signal line are arranged along the first direction, the first direction and the second direction intersect, and the third signal line and the fourth signal line transmit the same signal, and the first signal line, the second signal line, the third signal line, and the fourth signal line transmit a first reset signal;Along a direction perpendicular to the substrate, the first signal line and the third signal line have a first overlapping region, the first signal line and the fourth signal line have a second overlapping region, the second signal line and the third signal line have a third overlapping region, the second signal line and the fourth signal line have a fourth overlapping region, the first signal line and the third signal line are electrically connected in the first overlapping region, and the first signal line and the fourth signal line are insulated in the second overlapping region, and / or, the second signal line and the third signal line are insulated in the third overlapping region, and the second signal line and the fourth signal line are electrically connected in the fourth overlapping region, and the orthographic projections of the first overlapping region and the fourth overlapping region in the substrate are both located outside the orthographic projection of a certain pixel aperture in the substrate, and the orthographic projections of the second overlapping region and the third overlapping region in the substrate are both within the orthographic projection of a certain pixel aperture in the substrate A display panel characterized by being located at least partially.; Claim 18 In claim 17, a first insulating layer is formed between the first semiconductor layer and the first metal layer, a second insulating layer is formed between the first metal layer and the second metal layer, a third insulating layer is formed between the second metal layer and the second semiconductor layer, a fourth insulating layer is formed between the second semiconductor layer and the third metal layer, a fifth insulating layer is formed between the third metal layer and the fourth metal layer, and a sixth insulating layer is formed between the fourth metal layer and the fifth metal layer, and the third signal line and the fourth signal line are formed in the fifth metal layer; the first signal line and the second signal line are formed in the first metal layer, the first signal line and the third signal line are electrically connected through a first via hole in the first overlapping region, the second signal line and the fourth signal line are electrically connected through a second via hole in the fourth overlapping region, and the first via hole and the second via hole are the Penetrating the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer; or, the first signal line and the second signal line are formed in the second metal layer, and the first signal line and the third signal line are electrically connected through a first via hole in the first overlapping area, and the second signal line and the fourth signal line are electrically connected through a second via hole in the fourth overlapping area, and the first via hole and the second via hole penetrate the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer; or, the first signal line and the second signal line are formed in the fourth metal layer, and the first signal line and the third signal line are electrically connected through a first via hole in the first overlapping area, and the second signal line and the fourth signal line are electrically connected through a second via hole in the fourth overlapping area, and the first via hole and the second via hole are the Penetrating the 6th insulation layer;Alternatively, the first signal line and the second signal line are formed in the third metal layer, the first signal line and the third signal line are electrically connected through a first via hole in the first overlapping region, the second signal line and the fourth signal line are electrically connected through a second via hole in the fourth overlapping region, and the first via hole and the second via hole penetrate the fifth insulating layer and the sixth insulating layer; the material of the first semiconductor layer comprises a polysilicon semiconductor, and the material of the second semiconductor layer comprises a metal oxide semiconductor, characterized in that the display panel. Claim 19 In claim 17, the display panel further comprises a light-emitting layer and an isolation structure located on one side of the array substrate, wherein the light-emitting layer comprises a light-emitting unit, and the isolation structure comprises a main body portion and an isolation opening installed openly in the main body portion, and the orthographic projection of the light-emitting unit on the array substrate is located within the orthographic projection of the isolation opening on the array substrate; the main body portion comprises a first isolation portion and a second isolation portion, wherein the second isolation portion is located on one side of the first isolation portion facing away from the array substrate, and the orthographic projection of the second isolation portion on the array substrate covers the orthographic projection of the first isolation portion on the array substrate; and the light-emitting unit comprises a first electrode, a light-emitting functional layer, and a second electrode that are stacked and installed in a direction away from the substrate, and the second electrode is electrically connected to the first isolation portion. Claim 20 A display device characterized by including a display panel according to any one of claims 1 to 19.

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