Neuron circuit with one biristor and two-transistor, and devices having the samr

Abstract

A neuron circuit capable of reducing the magnitude and pulse width of an output voltage is disclosed. The neuron circuit includes a collector electrode that receives a constant input current output from a first synapse circuit and an emitter electrode connected to ground, a biristor that outputs a collector signal through the collector electrode, and a voltage divider that is enabled by the collector signal, divides the operating voltage using resistance values ​​included therein, and outputs an output voltage corresponding to the result of the voltage division to a second synapse circuit.

Description

Technology Field

[0001] An embodiment according to the concept of the present invention relates to a neuron circuit, and in particular to a neuron circuit comprising one biristor and two transistors, and devices comprising the same. Background Technology

[0002] With the advent of the Fourth Industrial Revolution, research on artificial intelligence systems is actively underway. Among them, neuromorphic computing systems, which deviate from the conventional von Neumann method that consumes massive amounts of energy, are receiving significant attention.

[0003] Neuromorphic computing is a method of implementing artificial intelligence operations by hardware-mimicking the human brain. Although the human brain performs very complex functions, it consumes only 20 watts (W) of energy. Neuromorphic computing mimics the structure of the human brain itself, enabling associative, reasoning, recognition, and data processing capabilities that are superior to conventional computing to be performed at ultra-low power.

[0004] In particular, Spiking Neural Networks (SNNs), which are referred to as third-generation artificial neural network models within neuromorphic computing, are neural network models based on the biological learning methods and signal transmission of the biological brain. Since they can significantly reduce energy consumption, related research is actively underway.

[0005] Among the hardware components for implementing a spiking neural network, the neuron circuit is composed of a leaky integrate-and-fire (LIF) neuron circuit that receives a current signal from the previous synaptic circuit and fires to transmit a voltage signal to the next synaptic circuit when the received current signal exceeds a certain level.

[0006] Complex circuits including capacitors, integrators, comparators, and reset circuits are used for neuron circuits that perform this LIF operation. However, since the actual human brain has 100 billion neurons, there is a need to improve the integration density of neuron circuits. The problem to be solved

[0007] The technical problem to be achieved by the present invention is to provide a neuron circuit composed of one biristor and two transistors capable of reducing the magnitude of an output voltage while simultaneously reducing the pulse width of the output voltage, and electronic devices including said neuron circuit. means of solving the problem

[0008] A neuron circuit according to an embodiment of the present invention includes a collector electrode that receives a constant input current output from a first synapse circuit and an emitter electrode connected to ground, a biristor that outputs a collector signal through the collector electrode, and a voltage divider that is enabled by the collector signal, divides the operating voltage using resistance values ​​included therein, and outputs an output voltage corresponding to the result of the voltage division to a second synapse circuit.

[0009] In a neural processing unit (NPU) including a neuromorphic circuit according to an embodiment of the present invention, the neuromorphic circuit includes a first synapse circuit, a second synapse circuit, and a neuron circuit connected between the first synapse circuit and the second synapse circuit. The neuron circuit includes a collector electrode that receives a constant input current output from the first synapse circuit and an emitter electrode connected to ground, a biristor that outputs a collector signal through the collector electrode, and a voltage divider that is enabled by the collector signal, divides the operating voltage using resistance values ​​included therein, and outputs an output voltage corresponding to the result of the voltage division to the second synapse circuit.

[0010] A data processing device comprising a Neural Processing Unit (NPU) including a neuromorphic circuit according to an embodiment of the present invention, wherein the neuromorphic circuit includes a first synapse circuit, a second synapse circuit, and a neuron circuit connected between the first synapse circuit and the second synapse circuit, and the neuron circuit includes a collector electrode that receives a constant input current output from the first synapse circuit and an emitter electrode connected to ground, a biristor that outputs a collector signal through the collector electrode, and a voltage divider that is enabled by the collector signal, divides the operating voltage using resistance values ​​included therein, and outputs an output voltage corresponding to the result of the voltage division to the second synapse circuit.

[0011] The above-mentioned viristor is a bipolar NPN transistor, and the base electrode of the bipolar NPN transistor is in a floating state.

[0012] The voltage divider comprises a first transistor including a first electrode connected to a voltage line supplying the operating voltage, a second electrode connected to an output node outputting the output voltage, and a first control terminal connected to the collector electrode, and a second transistor including a third electrode connected to the output node, a fourth electrode connected to ground, and a second control terminal, wherein the first transistor has a first value among the resistance values, and the second transistor has a second value among the resistance values. Effects of the invention

[0013] A neuron circuit according to an embodiment of the present invention is composed of one bistable resistor and two transistors that perform the role of a voltage divider, and has the effect of reducing the magnitude of the output voltage of the neuron circuit while simultaneously reducing the pulse width of the output voltage.

[0014] As the magnitude of the output voltage and the pulse width of the neuron circuit are reduced, there is an effect of reducing the energy consumption of the neuromorphic hardware including the neuron circuit. Brief explanation of the drawing

[0015] Detailed descriptions of each drawing are provided to help to more fully understand the drawings cited in the detailed description of the present invention. FIG. 1 is a block diagram of a neuromorphic circuit including synaptic circuits and neuron circuits according to an embodiment of the present invention. Figure 2 is a circuit diagram of the first neuron circuit shown in Figure 1, which includes one biristor and two transistors. Figure 3(a) is a waveform of the output signal over time of the first neuron circuit shown in Figure 2. Figure 3(b) is a waveform of the current flowing through two transistors connected in series as shown in Figure 2. Figure 4 is a scanning electron microscope image of the biristor shown in Figure 2. FIG. 5 is a block diagram of a data processing device including a Neural Processing Unit (NPU) including a neuromorphic circuit illustrated in FIG. 1. Specific details for implementing the invention

[0016] Neuromorphic engineering, also known as neuromorphic computing including neuronal circuits according to the present invention, can be applied to very-large-scale integration (VLSI) systems including electronic circuits to mimic neurobiological architectures existing in nervous systems.

[0017] A neuromorphic computer or neuromorphic chip comprising neuron circuits according to the present invention refers to any device that uses physical artificial neurons (e.g., physical artificial neurons are made of silicon (or semiconductor)) to perform computations. A neuromorphic circuit comprising neuron circuits according to the present invention refers to a circuit capable of efficiently processing a vast amount of data by mimicking nerve cells and synapses of the human brain.

[0018] FIG. 1 is a block diagram of a neuromorphic circuit including synaptic circuits and neuron circuits according to an embodiment of the present invention.

[0019] Referring to FIG. 1, a neuromorphic circuit (100) implemented as an integrated circuit (IC) includes a plurality of synapse circuits (110_1 to 110_n) and a plurality of neuron circuits (120_1 to 120_n). Here, n is a natural number greater than or equal to 3.

[0020] A neuromorphic circuit (100) means a neural network of circuits composed of artificial neurons or nodes.

[0021] Each synapse circuit (110_1 to 110_n) may be implemented as a volatile memory device or a non-volatile memory device, for example, each synapse circuit (110_1 to 110_n) may be implemented as a static random access memory (SRAM), a resistive random access memory (RRAM or ReRAM), a memory resistor (also called a memristor), a charge trap flash (CTF), a phase-change memory (PCM), or a ferroelectric random access memory (FeRAM).

[0022] Each neuron circuit (120_1~120_n) performs a leaky integrate-and-fire (LIF) function and is enabled according to a constant input current output from each synapse circuit (110_1~110_n). Since the operating voltage supplied to each neuron circuit (120_1~120_n) can be distributed using the resistance values ​​included therein, the magnitude of the output voltage and the pulse width of each neuron circuit (120_1~120_n) can be adjusted.

[0023] The LIF function refers to the ability to receive a current signal output from the previous synaptic circuit, and to fire and transmit a voltage signal to the next synaptic circuit if the received current signal is equal to or greater than a certain level. Therefore, each neuron circuit (120_1~120_n) is also called an LIF neuron.

[0024] Figure 2 is a circuit diagram of the first neuron circuit shown in Figure 1, which includes one biristor and two transistors.

[0025] Since the structure and operation of each neuron circuit (120_1 to 120_n) shown in Fig. 1 are identical, the structure and operation of the first neuron circuit (120-1) are described as representative.

[0026] Referring to FIGS. 1 and 2, the first neuron circuit (120_1) includes one bistable resistor (hereinafter referred to as 'biristor', 121) and two transistors (TR1 and TR2). The first neuron circuit (120_1) receives a constant input current (Iin1) from the first synapse circuit (110_1) and outputs a first output voltage (Vout1) with a controlled magnitude and pulse width to the second synapse circuit (110_2).

[0027] A biristor (121), also called a single-transistor neuron, can be implemented as a bipolar NPN transistor, the base electrode of the bipolar NPN transistor (121) remains in a floating state, a constant input current (Iin1) output from the first synapse circuit (110_1) is supplied to the collector electrode (ER1_1) of the bipolar NPN transistor (121), and the emitter electrode (ER1_2) of the bipolar NPN transistor (121) is connected to ground (Vss).

[0028] The symbol of the biristor (121) is represented by a bistable hysteric loop of current-voltage characteristics by the single-transistor latch (STL) phenomenon.

[0029] The first control electrode of the first transistor (TR1) is connected to the collector electrode (ER1_1) of the biristor (121), the first electrode (ER2_1) of the first transistor (TR1) is connected to a voltage line (125_1) that supplies an operating voltage (Vdd), and the second electrode (ER2_2) of the first transistor (TR2) is connected to an output terminal (125_2).

[0030] The second control voltage (Vg2) is supplied to the second control electrode of the second transistor (TR2), the first electrode (ER3_1) of the second transistor (TR2) is connected to the output terminal (125_2), and the second electrode (ER3_2) of the second transistor (TR2) is connected to ground (Vss).

[0031] According to embodiments, the first transistor (TR1) may be implemented as an n-type MOSFET (metal-oxide-semiconductor field-effect transistor), a p-type MOSFET, a bipolar NPN transistor, or a bipolar PNP transistor. Additionally, the second transistor (TR2) may be implemented as an n-type MOSFET, a p-type MOSFET, a bipolar NPN transistor, or a bipolar PNP transistor.

[0032] For example, when each transistor (TR1 and TR2) is a MOSFET, each first electrode (ER2_1 and ER3_1) is either a drain electrode or a source electrode, each second electrode (ER2_2 and ER3_2) is the other between the drain electrode and the source electrode, and each control electrode is a gate electrode.

[0033] For example, when each transistor (TR1 and TR2) is a bipolar transistor, each first electrode (ER2_1 and ER3_1) is either a collector electrode or an emitter electrode, each second electrode (ER2_2 and ER3_2) is the other between the collector electrode and the emitter electrode, and each control electrode is a base electrode.

[0034] The biristor (121) performs the function of enabling the first neuron circuit (120_1), and the transistors (TR1 and TR2) act as a voltage divider (125). The voltage divider (125) composed of the transistors (TR1 and TR2) can modulate the magnitude and pulse width of the first output signal (Vout1) to reduce power consumption and energy consumption of the first neuron circuit (120_1) and the second synapse circuit (110_2).

[0035] When a constant input current (Iin1) is supplied to the collector electrode (ER1_1) of the biristor (121), the collector signal (Vg1, e.g., voltage or current) of the collector electrode (ER1_1) is supplied to the first control electrode of the first transistor (TR1).

[0036] When the second transistor (TR2) is turned on according to a second control signal (e.g., a second control voltage (Vg2)) supplied to the second control electrode of the second transistor (TR2), the first output voltage (Vout1) of the output terminal (125_2) is equal to Equation 1 according to the voltage divider rule.

[0037] [Mathematical Formula 1]

[0038]

[0039] Here, R TR1 is the resistance value of the first transistor (TR1), and R TR2 is the resistance value of the second transistor (TR2).

[0040] Figure 3(a) is a waveform of the output signal over time of the first neuron circuit shown in Figure 2.

[0041] Figure 3(a) is a simulation result when the constant input current (Iin1) is 5nA, the threshold voltage of the first transistor (TR1) is 2V, the threshold voltage of the second transistor (TR2) is 0V, the operating voltage (Vdd) is 1V, and the second control signal (e.g., the second gate voltage (Vg2)) is 0.2V.

[0042] Referring to FIG. 3(a), when transistors (TR1 and TR2) are implemented in the first neuron circuit (120_1), the magnitude (Mag2) and pulse width (Tp2) of the first output voltage (Vout1) of the output terminal (125_2) are significantly reduced compared to the magnitude (Mag1) and pulse width (Tp1) of the voltage (Vg1) of the collector electrode (ER1_1) of the biristor (121) when transistors (TR1 and TR2) are not implemented in the first neuron circuit (120_1).

[0043] Figure 3(b) is a waveform of the current flowing through two transistors connected in series as shown in Figure 2.

[0044] In FIG. 3(b), under the same conditions as in FIG. 3(a), the current (I) flowing through the transistors (TR1 and TR2) 2T The waveform of ) is shown. Current (I 2T ) determines the energy consumption of the first neuron circuit (120_1).

[0045] A reduction in the magnitude (Mag2) and pulse width (Tp2) of the first output voltage (Vout1) of the first neuron circuit (120_1) can reduce the energy consumption of the second synapse circuit (110_2) connected to the first neuron circuit (120_1).

[0046] Figure 4 is a scanning electron microscope (SEM) image of the biristor shown in Figure 2.

[0047] Referring to FIG. 4, the first biristor (121) includes a substrate (121_1), a floating body layer (121_2), an emitter (121_3), a collector (121_4), and a base (121_5).

[0048] According to an embodiment, an emitter electrode (ER1_2) may be connected to the emitter (121_3), and a collector electrode (ER1_1) may be connected to the collector (121_4).

[0049] The substrate (121_1) can be implemented as a hole barrier material or an electron barrier material. For example, when the substrate (121_1) is formed of silicon-on-insulator (SOI), the first biristor (121) is an SOI transistor. For example, the substrate (121_1) is a surface state <100> It can be a p-type SOI wafer.

[0050] The substrate (121_1) can serve as a back gate that applies voltage bias, and a hole barrier material (or electron barrier material) and a floating body layer (121_2) can be sequentially formed on or above the substrate (121_1).

[0051] Hole barrier materials (or electron barrier materials) can be formed from buried oxide.

[0052] The floating body layer (121_2) is formed on top of the hole barrier material or electron barrier material (121_1), and holes (or electrons) generated by impact ionization accumulate in the floating body layer (121_2), thereby enabling neuron operation.

[0053] The emitter (121_3) and collector (121_4) are formed on both sides of the floating body layer (121_2).

[0054] Each of the emitter (121_3) and collector (121_4) can be formed from any one of an n-type semiconductor, a p-type semiconductor, and a metal silicide.

[0055] The types of the emitter (121_3) and the collector (121_4) may differ from the type of the floating body layer (120). For example, when the emitter (121_3) and the collector (121_4) are each p-type semiconductors, the floating body layer (120) may be an n-type semiconductor, and when the emitter (121_3) and the collector (121_4) are each n-type semiconductors, the floating body layer (120) may be a p-type semiconductor.

[0056] Each of the emitter (121_3) and the collector (121_4) can be formed by at least one of diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation, and subsequent heat treatment.

[0057] When a current signal output from the previous synapse circuit is input to the emitter (121_3) and the collector (121_4) respectively, a spike-shaped voltage signal can be output from the emitter (121_3) and the collector (121_4) respectively.

[0058] The base (121_5) may be formed from any one of n-type polysilicon, p-type polysilicon, and metal, and the metal may include aluminum (Al), molybdenum (Mo), chromium (Cr), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), tantalum (Ta), tungsten (W), silver (Ag), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. For example, the base width (W) may be 180 nm and the base length (L) may be 380 nm.

[0059] The first biristor (121) may further include an insulating film for insulating between a floating body layer (121_2) and a base (121_5), and the insulating film may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, hafnium zirconium oxide (HZO), or a combination thereof.

[0060] FIG. 5 is a block diagram of a data processing device including a Neural Processing Unit (NPU) including a neuromorphic circuit illustrated in FIG. 1.

[0061] Referring to FIG. 5, the data processing unit (200) includes a system bus (201), a processor (210), a neural processing unit (NPU; 220), a system memory (230), a non-volatile memory device (240), and a communication device (250). The communication device (250) is also called connectivity.

[0062] Examples of data processing devices (200) include artificial intelligence computing devices, mobile devices, Internet of Things (IoT) devices, and drones with cameras.

[0063] Examples of mobile devices include smartphones, tablet computers, laptop computers, Mobile Internet devices (MIDs), Personal digital assistants (PDAs), Handheld game consoles, Portable media players, digital cameras, and wearable computers.

[0064] Examples of wearable computers include smartwatches, head-mounted displays (HMDs), and smart glasses.

[0065] Each device (210, 220, 230, 240, and 250) exchanges information (or data) through the system bus (201). The processor (210) collectively represents at least one of a CPU, a GPU (Graphics Processing Unit), and a DPU (Data Processing Unit), and according to the embodiment, the processor (210) may mean an application processor.

[0066] The NPU (220) refers to a processor optimized for artificial intelligence learning and execution that processes data with a structure similar to a human brain neural network. The NPU (220) includes a neuromorphic circuit (100) described with reference to FIGS. 1 to 4.

[0067] System memory (230) may be composed of a physical memory device called RAM (Random Access Memory) or a virtual memory device. Data processed or to be processed by the processor (210) or NPU (220) may be stored in system memory (230).

[0068] Data processed or to be processed by the processor (210) or NPU (220) may be stored in a non-volatile memory device (240). Examples of non-volatile memory devices (240) may be implemented as RRAM (or ReRAM), memristor, CTF, PCM, or FeRAM.

[0069] The data processing device (200) can exchange signals (or information) with an external device through a communication device (250). The communication device (250) collectively refers to a Wi-Fi communication module, an NFC communication module, and a Bluetooth communication module, etc.

[0070] The present invention has been described with reference to embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0071] 100: Neuromorphic circuit 110_1~110_n: Synaptic circuits 120_1~120_n: Neuron circuits 121: Bilister 125: Voltage divider TR1: Second transistor TR2: Jet transistor 200: Data processing circuit 210: Processor 220: Neural Processing Unit (NPU)

Claims

Claim 1 A neuron circuit comprising: a biristor including a collector electrode receiving a constant input current output from a first synapse circuit and an emitter electrode connected to ground, and outputting a collector signal through the collector electrode; and a voltage divider enabled by the collector signal, voltage divides an operating voltage using resistance values ​​included therein, and outputs an output voltage corresponding to the result of the voltage division to a second synapse circuit. Claim 2 In claim 1, the viristor is a bipolar NPN transistor, and the base electrode of the bipolar NPN transistor is in a floating state, forming a neuron circuit. Claim 3 In claim 1, the voltage divider comprises: a first transistor including a first electrode connected to a voltage line supplying the operating voltage, a second electrode connected to an output node outputting the output voltage, and a first control terminal connected to the collector electrode; and a second transistor including a third electrode connected to the output node, a fourth electrode connected to ground, and a second control terminal, wherein the first transistor has a first value among the resistance values ​​and the second transistor has a second value among the resistance values. Claim 4 A neuron circuit according to paragraph 3, wherein the first transistor is an n-type MOSFET, a p-type MOSFET, a bipolar NPN transistor, or a bipolar PNP transistor, and the second transistor is an n-type MOSFET, a p-type MOSFET, a bipolar NPN transistor, or a bipolar PNP transistor. Claim 5 In paragraph 3, when the first transistor and the second transistor are each bipolar transistors, the first electrode and the third electrode are each one of a collector electrode and an emitter electrode, the second electrode and the fourth electrode are each the other one of the collector electrode and the emitter electrode, and the first control terminal and the second control terminal are each base electrodes, a neuron circuit. Claim 6 A neural processing unit (NPU) comprising a neuromorphic circuit, wherein the neuromorphic circuit comprises: a first synapse circuit; a second synapse circuit; and a neuron circuit connected between the first synapse circuit and the second synapse circuit, wherein the neuron circuit comprises a collector electrode receiving a constant input current output from the first synapse circuit and an emitter electrode connected to ground, and a biristor outputting a collector signal through the collector electrode; and a voltage divider enabled by the collector signal, voltage divides an operating voltage using resistance values ​​included therein, and outputs an output voltage corresponding to the result of the voltage division to the second synapse circuit. Claim 7 In paragraph 6, the first synapse circuit and the second synapse circuit are each a neural network processing unit that is a non-volatile memory device or a volatile memory device. Claim 8 In claim 6, the voltage divider comprises: a first transistor including a first electrode connected to a voltage line supplying the operating voltage, a second electrode connected to an output node outputting the output voltage, and a first control terminal connected to the collector electrode; and a second transistor including a third electrode connected to the output node, a fourth electrode connected to ground, and a second control terminal, wherein the first transistor has a first value among the resistance values ​​and the second transistor has a second value among the resistance values. Claim 9 A data processing device comprising a Neural Processing Unit (NPU) including a neuromorphic circuit, wherein the neuromorphic circuit comprises: a first synapse circuit; a second synapse circuit; and a neuron circuit connected between the first synapse circuit and the second synapse circuit, wherein the neuron circuit comprises a collector electrode receiving a constant input current output from the first synapse circuit and an emitter electrode connected to ground, and a biristor outputting a collector signal through the collector electrode; and a voltage divider enabled by the collector signal, voltage divides an operating voltage using resistance values ​​included therein, and outputs an output voltage corresponding to the result of the voltage division to the second synapse circuit. Claim 10 In claim 9, the voltage divider comprises: a first transistor including a first electrode connected to a voltage line supplying the operating voltage, a second electrode connected to an output node outputting the output voltage, and a first control terminal connected to the collector electrode; and a second transistor including a third electrode connected to the output node, a fourth electrode connected to ground, and a second control terminal, wherein the first transistor has a first value among the resistance values ​​and the second transistor has a second value among the resistance values.

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