Semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, comprises: a substrate including an active pattern; a channel pattern and a source / drain pattern on the active pattern, wherein the channel pattern is connected to the source / drain pattern; a gate electrode on the channel pattern; and an active contact electrically connected to the source / drain pattern. The active contact comprises a first barrier metal and a first filling metal on the first barrier metal, wherein the first barrier metal comprises a metal nitride film, and the first filling metal comprises at least one of molybdenum, tungsten, ruthenium, cobalt, and vanadium, and the first filling metal comprises a first crystal region having a body-centered cubic structure (BCC) and a second crystal region having a face-centered cubic structure (FCC), and the proportion of the first crystal region within the first filling metal is 60% to 99%.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a field-effect transistor and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics.

[0004] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device with improved electrical characteristics. means of solving the problem

[0005] A semiconductor device according to the concept of the present invention may include a substrate having an active pattern; a channel pattern and a source / drain pattern on the active pattern, wherein the channel pattern is connected to the source / drain pattern; a gate electrode on the channel pattern; and an active contact electrically connected to the source / drain pattern. The active contact may include a first barrier metal and a first filling metal on the first barrier metal, wherein the first barrier metal comprises a metal nitride film, the first filling metal comprises at least one of molybdenum, tungsten, ruthenium, cobalt, and vanadium, and the first filling metal comprises a first crystal region having a body-centered cubic structure (BCC) and a second crystal region having a face-centered cubic structure (FCC), and the proportion of the first crystal region within the first filling metal may be 60% to 99%.

[0006] According to another concept of the present invention, a semiconductor device may comprise: a substrate including an active pattern; a channel pattern and a source / drain pattern on the active pattern, wherein the channel pattern is connected to the source / drain pattern; a gate electrode on the channel pattern; an active contact connected to the source / drain pattern; and a metal layer on the active contact. The wiring within the metal layer is electrically connected to each other through the active contact and via, the active contact comprises a first barrier metal and a first filler metal on the first barrier metal, the via comprises a second barrier metal and a second filler metal on the second barrier metal, the first and second barrier metals comprise a metal nitride film, the first and second filler metals comprise at least one of molybdenum, tungsten, ruthenium, cobalt, and vanadium, and the ratio of the body-centered cubic structure (BCC) of the first filler metal may be greater than the ratio of the body-centered cubic structure (BCC) of the second filler metal.

[0007] According to another concept of the present invention, a semiconductor device comprises: a substrate including a PMOSFET region and an NMOSFET region; a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region; a first channel pattern and a first source / drain pattern on the first active pattern; a second channel pattern and a second source / drain pattern on the second active pattern; a gate electrode extending in the first direction across the first and second channel patterns; a gate insulating film interposed between the gate electrode and the first and second channel patterns; a gate spacer on the sidewall of the gate electrode; a gate capping pattern on the upper surface of the gate electrode; a gate cutting pattern penetrating the gate electrode; an interlayer insulating film on the gate capping pattern and the gate cutting pattern; an active contact electrically connected to the first and second source / drain patterns penetrating the interlayer insulating film; and metal-semiconductor compound layers interposed between the active contact and the first and second source / drain patterns, respectively. A gate contact electrically connected to the gate electrode by penetrating the interlayer insulating film and the gate capping pattern; a first metal layer on the interlayer insulating film, the first metal layer including power wiring vertically superimposed with the gate cutting pattern, and first wiring electrically connected to the active and gate contacts, respectively; and a second metal layer on the first metal layer. The second metal layer includes second wiring electrically connected to the first metal layer, the active contact includes a first barrier metal and a first filling metal on the first barrier metal, and the gate contact includes a second barrier metal and a second filling metal on the second barrier metal, and the ratio of the body-centered cubic structure (BCC) of the first filling metal may be greater than the ratio of the body-centered cubic structure (BCC) of the second filling metal.

[0008] According to another concept of the present invention, a method for manufacturing a semiconductor device may include: forming an active pattern on a substrate; forming a sacrificial pattern extending in a first direction on the active pattern; forming a source / drain pattern including a sacrificial layer on one side of the sacrificial pattern; forming an interlayer insulating film covering the sacrificial pattern and the source / drain pattern; replacing the sacrificial pattern with a gate electrode; forming a contact trench that penetrates the interlayer insulating film to expose the source / drain pattern; and forming an active contact within the contact trench. Forming the active contact may include: forming a barrier metal film within the contact trench; performing ion bombardment using plasma on the barrier metal film; and forming a filling metal film on the barrier metal film, wherein the ratio of a body-centered cubic (BCC) structure within the filling metal film may be 60% to 99%. Effects of the invention

[0009] The filling metal of the contact of the semiconductor device according to the present invention may have a relatively high proportion of a body-centered cubic (BCC) structure. When the proportion of the body-centered cubic (BCC) structure of the filling metal of the contact increases, the resistivity of the contact may decrease. Consequently, the electrical resistance between the transistors constituting the logic circuit and the first metal layer above them may be reduced, thereby improving the electrical characteristics of the semiconductor device according to the present invention. Brief explanation of the drawing

[0010] FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention. FIG. 4 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 5a to 5d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively. FIG. 6 is an enlarged view showing one embodiment of the M region of FIG. 5a. FIGS. 7a to 14d are cross-sectional views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 15 to 17 are enlarged views illustrating a method for forming an active contact in the M region of FIG. 14a. FIG. 18 is an enlarged view illustrating a method for forming an active contact in the M region of FIG. 14a according to a comparative example of the present invention. FIGS. 19a to 19d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively, for illustrating a semiconductor device according to an embodiment of the present invention. Specific details for implementing the invention

[0011] FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention.

[0012] Referring to FIG. 1, a Single Height Cell (SHC) may be provided. Specifically, a first power line (M1_R1) and a second power line (M1_R2) may be provided on a substrate (100). The first power line (M1_R1) may be a channel for providing a drain voltage (VDD), for example, a power voltage. The second power line (M1_R2) may be a channel for providing a source voltage (VSS), for example, a ground voltage.

[0013] A single height cell (SHC) may be defined between the first power line (M1_R1) and the second power line (M1_R2). The single height cell (SHC) may include one PMOSFET region (PR) and one NMOSFET region (NR). In other words, the single height cell (SHC) may have a CMOS structure provided between the first power line (M1_R1) and the second power line (M1_R2).

[0014] Each of the PMOSFET region (PR) and the NMOSFET region (NR) may have a first width (WI1) in a first direction (D1). The length of the single height cell (SHC) in the first direction (D1) may be defined as a first height (HE1). The first height (HE1) may be substantially equal to the distance (e.g., pitch) between the first power line (M1_R1) and the second power line (M1_R2).

[0015] A single height cell (SHC) can constitute a single logic cell. In this specification, a logic cell may refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic cell may include transistors for constituting a logic element and wirings connecting said transistors to each other.

[0016] Referring to FIG. 2, a double height cell (DHC) may be provided. Specifically, a first power line (M1_R1), a second power line (M1_R2), and a third power line (M1_R3) may be provided on a substrate (100). The first power line (M1_R1) may be positioned between the second power line (M1_R2) and the third power line (M1_R3). The third power line (M1_R3) may be a passage through which a drain voltage (VDD) is provided.

[0017] A double height cell (DHC) may be defined between the second power wiring (M1_R2) and the third power wiring (M1_R3). The double height cell (DHC) may include a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2).

[0018] The first NMOSFET region (NR1) may be adjacent to the second power line (M1_R2). The second NMOSFET region (NR2) may be adjacent to the third power line (M1_R3). The first and second PMOSFET regions (PR1, PR2) may be adjacent to the first power line (M1_R1). In a planar view, the first power line (M1_R1) may be positioned between the first and second PMOSFET regions (PR1, PR2).

[0019] The length of the double height cell (DHC) in the first direction (D1) can be defined as the second height (HE2). The second height (HE2) may be approximately twice the first height (HE1) of FIG. 1. The first and second PMOSFET regions (PR1, PR2) of the double height cell (DHC) can be combined to operate as a single PMOSFET region.

[0020] Accordingly, the channel size of the PMOS transistor of the double height cell (DHC) may be larger than the channel size of the PMOS transistor of the single height cell (SHC) shown in FIG. 1. For example, the channel size of the PMOS transistor of the double height cell (DHC) may be approximately twice the channel size of the PMOS transistor of the single height cell (SHC). Consequently, the double height cell (DHC) can operate at a higher speed than the single height cell (SHC). In the present invention, the double height cell (DHC) shown in FIG. 2 may be defined as a multi-height cell. Although not illustrated, the multi-height cell may include a triple height cell in which the cell height is approximately three times that of the single height cell (SHC).

[0021] Referring to FIG. 3, a first single height cell (SHC1), a second single height cell (SHC2), and a double height cell (DHC) may be arranged two-dimensionally on a substrate (100). The first single height cell (SHC1) may be placed between first and second power lines (M1_R1, M1_R2). The second single height cell (SHC2) may be placed between first and third power lines (M1_R1, M1_R3). The second single height cell (SHC2) may be adjacent to the first single height cell (SHC1) in a first direction (D1).

[0022] A double height cell (DHC) may be placed between the second and third power lines (M1_R2, M1_R3). The double height cell (DHC) may be adjacent to the first and second single height cells (SHC1, SHC2) in the second direction (D2).

[0023] A separation structure (DB) may be provided between the first single-height cell (SHC1) and the double-height cell (DHC), and between the second single-height cell (SHC2) and the double-height cell (DHC). By the separation structure (DB), the active region of the double-height cell (DHC) may be electrically separated from the active region of each of the first and second single-height cells (SHC1, SHC2).

[0025] FIG. 4 is a plan view illustrating a semiconductor device according to embodiments of the present invention. FIG. 5a to 5d are cross-sectional views along lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively. FIG. 6 is an enlarged view showing an embodiment of region M of FIG. 5a. The semiconductor device illustrated in FIG. 4 and FIG. 5a to 5d is an example showing the first and second single-height cells (SHC1, SHC2) of FIG. 3 in more detail.

[0026] Referring to FIGS. 4 and FIGS. 5a through 5d, first and second single-height cells (SHC1, SHC2) may be provided on a substrate (100). Logic transistors constituting a logic circuit may be disposed on each of the first and second single-height cells (SHC1, SHC2). The substrate (100) may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. As an example, the substrate (100) may be a silicon substrate.

[0027] The substrate (100) may have a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2). Each of the first PMOSFET region (PR1), the second PMOSFET region (PR2), the first NMOSFET region (NR1), and the second NMOSFET region (NR2) may extend in a second direction (D2). A first single height cell (SHC1) may include a first NMOSFET region (NR1) and a first PMOSFET region (PR1), and a second single height cell (SHC2) may include a second PMOSFET region (PR2) and a second NMOSFET region (NR2).

[0028] A first active pattern (AP1) and a second active pattern (AP2) can be defined by a trench (TR) formed on the upper surface of the substrate (100). The first active pattern (AP1) can be provided on each of the first and second PMOSFET regions (PR1, PR2). The second active pattern (AP2) can be provided on each of the first and second NMOSFET regions (NR1, NR2). The first and second active patterns (AP1, AP2) can be extended in a second direction (D2). The first and second active patterns (AP1, AP2) can be vertically protruding portions as part of the substrate (100).

[0029] The device isolation layer (ST) may fill the trench (TR). The device isolation layer (ST) may include a silicon oxide film. The device isolation layer (ST) may not cover the first and second channel patterns (CH1, CH2) to be described later.

[0030] A first channel pattern (CH1) may be provided on a first active pattern (AP1). A second channel pattern (CH2) may be provided on a second active pattern (AP2). Each of the first channel pattern (CH1) and the second channel pattern (CH2) may include a first semiconductor pattern (SP1), a second semiconductor pattern (SP2), and a third semiconductor pattern (SP3) that are sequentially stacked. The first to third semiconductor patterns (SP1, SP2, SP3) may be spaced apart from each other in a vertical direction (i.e., a third direction (D3)).

[0031] Each of the first to third semiconductor patterns (SP1, SP2, SP3) may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns (SP1, SP2, SP3) may include crystalline silicon.

[0032] A plurality of first source / drain patterns (SD1) may be provided on a first active pattern (AP1). A plurality of first recesses (RS1) may be formed on the upper portion of the first active pattern (AP1). Each of the first source / drain patterns (SD1) may be provided within the first recesses (RS1). The first source / drain patterns (SD1) may be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern (CH1) may be interposed between a pair of first source / drain patterns (SD1). In other words, stacked first to third semiconductor patterns (SP1, SP2, SP3) may connect a pair of first source / drain patterns (SD1) to each other.

[0033] A plurality of second source / drain patterns (SD2) may be provided on a second active pattern (AP2). A plurality of second recesses (RS2) may be formed on the upper portion of the second active pattern (AP2). The second source / drain patterns (SD2) may each be provided within the second recesses (RS2). The second source / drain patterns (SD2) may be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern (CH2) may be interposed between a pair of second source / drain patterns (SD2). In other words, stacked first to third semiconductor patterns (SP1, SP2, SP3) may connect a pair of second source / drain patterns (SD2) to each other.

[0034] The first and second source / drain patterns (SD1, SD2) may be epitaxial patterns formed by an optional epitaxial growth (SEG) process. For example, the upper surface of each of the first and second source / drain patterns (SD1, SD2) may be higher than the upper surface of the third semiconductor pattern (SP3). For another example, at least one of the upper surfaces of the first and second source / drain patterns (SD1, SD2) may be located at substantially the same level as the upper surface of the third semiconductor pattern (SP3).

[0035] The first source / drain patterns (SD1) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate (100). Thus, a pair of first source / drain patterns (SD1) can provide compressive stress to the first channel pattern (CH1) between them. The second source / drain patterns (SD2) may include the same semiconductor element (e.g., Si) as the substrate (100).

[0036] Each of the first source / drain patterns (SD1) may include a buffer layer (BFL) and a main layer (MAL) on the buffer layer (BFL). Referring to FIG. 5a below, the shape of the cross-section in the second direction (D2) of the first source / drain pattern (SD1) will be described.

[0037] The buffer layer (BFL) may cover the inner wall of the first recess (RS1). In one embodiment, the thickness of the buffer layer (BFL) may become thinner from its lower part to its upper part. For example, the thickness of the buffer layer (BFL) in the third direction (D3) on the bottom of the first recess (RS1) may be greater than the thickness of the buffer layer (BFL) in the second direction (D2) on the upper part of the first recess (RS1). The buffer layer (BFL) may have a U-shape along the profile of the first recess (RS1).

[0038] The main layer (MAL) can fill most of the remaining area of ​​the first recess (RS1), excluding the buffer layer (BFL). The volume of the main layer (MAL) may be larger than the volume of the buffer layer (BFL). In other words, the ratio of the volume of the main layer (MAL) to the total volume of the first source / drain pattern (SD1) may be greater than the ratio of the volume of the buffer layer (BFL) to the total volume of the first source / drain pattern (SD1).

[0039] Each of the buffer layer (BFL) and the main layer (MAL) may contain silicon-germanium (SiGe). Specifically, the buffer layer (BFL) may contain a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer (BFL) may contain only silicon (Si) excluding germanium (Ge). The concentration of germanium (Ge) in the buffer layer (BFL) may be 0 at% to 10 at%. More specifically, the concentration of germanium (Ge) in the buffer layer (BFL) may be 2 at% to 8 at%.

[0040] The main layer (MAL) may contain a relatively high concentration of germanium (Ge). For example, the concentration of germanium (Ge) in the main layer (MAL) may be 30 at% to 70 at%. The concentration of germanium (Ge) in the main layer (MAL) may increase toward the third direction (D3). For example, the main layer (MAL) adjacent to the buffer layer (BFL) may have a germanium (Ge) concentration of about 40 at%, but the upper part of the main layer (MAL) may have a germanium (Ge) concentration of about 60 at%.

[0041] Each of the buffer layer (BFL) and the main layer (MAL) may contain an impurity (e.g., boron, gallium, or indium) that causes the first source / drain pattern (SD1) to have a p-type. The impurity concentration of each of the buffer layer (BFL) and the main layer (MAL) may be 1E18 atomic / cm3 to 5E22 atomic / cm3. The impurity concentration of the main layer (MAL) may be greater than the impurity concentration of the buffer layer (BFL).

[0042] The buffer layer (BFL) can prevent stacking faults between the substrate (100) (i.e., the first active pattern (AP1)) and the main layer (MAL), and between the first to third semiconductor patterns (SP1, SP2, SP3) and the main layer (MAL). If a stacking fault occurs, the channel resistance may increase. A stacking fault can easily occur at the bottom of the first recess (RS1). Therefore, to prevent a stacking fault, it may be desirable for the thickness of the buffer layer (BFL) adjacent to the bottom of the first recess (RS1) to be relatively large.

[0043] The buffer layer (BFL) can protect the main layer (MAL) during the process of replacing the sacrificial layers (SAL), which will be described later, with the first to third portions (PO1, PO2, PO3) of the gate electrode (GE). In other words, the buffer layer (BFL) can prevent the etching material that removes the sacrificial layers (SAL) from penetrating into the main layer (MAL) and etching it.

[0044] Referring again to FIGS. 4 and FIGS. 5a through 5d, gate electrodes (GE) extending in a first direction (D1) across first and second channel patterns (CH1, CH2) may be provided. The gate electrodes (GE) may be arranged in a second direction (D2) according to a first pitch. Each gate electrode (GE) may be perpendicularly overlapped with the first and second channel patterns (CH1, CH2).

[0045] The gate electrode (GE) may include a first portion (PO1) interposed between an active pattern (AP1 or AP2) and a first semiconductor pattern (SP1), a second portion (PO2) interposed between a first semiconductor pattern (SP1) and a second semiconductor pattern (SP2), a third portion (PO3) interposed between a second semiconductor pattern (SP2) and a third semiconductor pattern (SP3), and a fourth portion (PO4) on the third semiconductor pattern (SP3).

[0046] Referring again to FIG. 5a, the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) on the PMOSFET region (PR) may have different widths. For example, the maximum width of the third portion (PO3) in the second direction (D2) may be greater than the maximum width of the second portion (PO2) in the second direction (D2). The maximum width of the first portion (PO1) in the second direction (D2) may be greater than the maximum width of the third portion (PO3) in the second direction (D2).

[0047] Referring again to FIG. 5d, the gate electrode (GE) may be provided on the top surface (TS), bottom surface (BS), and both sidewalls (SW) of each of the first to third semiconductor patterns (SP1, SP2, SP3). In other words, the transistor according to the present embodiment may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode (GE) surrounds the channel three-dimensionally.

[0048] Referring again to FIGS. 4 and FIGS. 5a through 5d, typically, a first single height cell (SHC1) may have a first boundary (BD1) and a second boundary (BD2) facing each other in a second direction (D2). The first and second boundaries (BD1, BD2) may extend in a first direction (D1). The first single height cell (SHC1) may have a third boundary (BD3) and a fourth boundary (BD4) facing each other in a first direction (D1). The third and fourth boundaries (BD3, BD4) may extend in a second direction (D2).

[0049] Gate cutting patterns (CT) may be placed on the boundary toward the second direction (D2) of each of the first and second single-height cells (SHC1, SHC2). For example, gate cutting patterns (CT) may be placed on the third and fourth boundaries (BD3, BD4) of the first single-height cell (SHC1). The gate cutting patterns (CT) may be arranged along the third boundary (BD3) at the first pitch. The gate cutting patterns (CT) may be arranged along the fourth boundary (BD4) at the first pitch. In a planar view, the gate cutting patterns (CT) on the third and fourth boundaries (BD3, BD4) may be placed so as to overlap each other on the gate electrodes (GE). The gate cutting patterns (CT) may include an insulating material such as a silicon oxide film, a silicon nitride film, or a combination thereof.

[0050] The gate electrode (GE) on the first single height cell (SHC1) can be separated from the gate electrode (GE) on the second single height cell (SHC2) by a gate cutting pattern (CT). A gate cutting pattern (CT) may be interposed between the gate electrode (GE) on the first single height cell (SHC1) and the gate electrode (GE) on the second single height cell (SHC2) aligned with it in the first direction (D1). In other words, the gate electrode (GE) extending in the first direction (D1) can be separated into a plurality of gate electrodes (GE) by the gate cutting patterns (CT).

[0051] A pair of gate spacers (GS) may be disposed on each of the sidewalls of the fourth portion (PO4) of the gate electrode (GE). The gate spacers (GS) may extend along the gate electrode (GE) in a first direction (D1). The upper surfaces of the gate spacers (GS) may be higher than the upper surface of the gate electrode (GE). The upper surfaces of the gate spacers (GS) may co-plane with the upper surface of the first interlayer insulating film (110) to be described later. In one embodiment, the gate spacers (GS) may include at least one of SiCN, SiCON, and SiN. In another embodiment, the gate spacers (GS) may include a multi-layer composed of at least two of SiCN, SiCON, and SiN.

[0052] A gate capping pattern (GP) may be provided on a gate electrode (GE). The gate capping pattern (GP) may extend along the gate electrode (GE) in a first direction (D1). The gate capping pattern (GP) may include a material that is etch selective with respect to the first and second interlayer insulating films (110, 120) described later. Specifically, the gate capping pattern (GP) may include at least one of SiON, SiCN, SiCON, and SiN.

[0053] A gate insulating film (GI) may be interposed between the gate electrode (GE) and the first channel pattern (CH1), and between the gate electrode (GE) and the second channel pattern (CH2). The gate insulating film (GI) may cover the top surface (TS), bottom surface (BS), and both side walls (SW) of each of the first to third semiconductor patterns (SP1, SP2, SP3). The gate insulating film (GI) may cover the top surface of the device isolation film (ST) below the gate electrode (GE).

[0054] In one embodiment of the present invention, the gate insulating film (GI) may include a silicon oxide film, a silicon oxynitride film and / or a high dielectric film. The high dielectric film may include a high dielectric constant material having a higher dielectric constant than that of the silicon oxide film. As an example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0055] In another embodiment, the semiconductor device of the present invention may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film (GI) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0056] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0057] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0058] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0059] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0060] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0061] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0062] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0063] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0064] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0065] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0066] For example, the gate insulating film (GI) may include a single ferroelectric material film. For another example, the gate insulating film (GI) may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film (GI) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0067] The gate electrode (GE) may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on a gate insulating film (GI) and may be adjacent to first to third semiconductor patterns (SP1, SP2, SP3). The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. By controlling the thickness and composition of the first metal pattern, a desired threshold voltage of the transistor can be achieved. For example, the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) may be composed of the first metal pattern, which is a work function metal.

[0068] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). Furthermore, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

[0069] The second metal pattern may include a metal having lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion (PO4) of the gate electrode (GE) may include the first metal pattern and the second metal pattern on the first metal pattern.

[0070] Referring again to FIG. 5b, inner spacers (IP) may be provided on the first and second NMOSFET regions (NR1, NR2). In other words, inner spacers (IP) may be provided on the second active pattern (AP2). The inner spacers (IP) may be interposed between the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) and the second source / drain pattern (SD2), respectively. The inner spacers (IP) may be in direct contact with the second source / drain pattern (SD2). Each of the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) may be spaced apart from the second source / drain pattern (SD2) by the inner spacers (IP).

[0071] A first interlayer insulating film (110) may be provided on a substrate (100). The first interlayer insulating film (110) may cover gate spacers (GS) and first and second source / drain patterns (SD1, SD2). The upper surface of the first interlayer insulating film (110) may substantially co-plane with the upper surface of the gate capping pattern (GP) and the upper surface of the gate spacer (GS). A second interlayer insulating film (120) covering the gate capping pattern (GP) may be disposed on the first interlayer insulating film (110). A third interlayer insulating film (130) may be provided on the second interlayer insulating film (120). A fourth interlayer insulating film (140) may be provided on the third interlayer insulating film (130). In one example, the first to fourth interlayer insulating films (110-140) may comprise a silicon oxide film.

[0072] A pair of separation structures (DB) facing each other in a second direction (D2) may be provided on both sides of each of the first and second single-height cells (SHC1, SHC2). For example, a pair of separation structures (DB) may be provided on the first and second boundaries (BD1, BD2) of the first single-height cell (SHC1), respectively. The separation structure (DB) may extend parallel to the gate electrodes (GE) in a first direction (D1). The pitch between the separation structure (DB) and the adjacent gate electrode (GE) may be the same as the first pitch.

[0073] The isolation structure (DB) can penetrate the first and second interlayer insulating films (110, 120) and extend into the first and second active patterns (AP1, AP2). The isolation structure (DB) can penetrate the top of each of the first and second active patterns (AP1, AP2). The isolation structure (DB) can electrically isolate the active region of each of the first and second single-height cells (SHC1, SHC2) from the active region of an adjacent cell.

[0074] Active contacts (AC) may be provided that penetrate the first and second interlayer insulating films (110, 120) and are electrically connected to the first and second source / drain patterns (SD1, SD2), respectively. A pair of active contacts (AC) may be provided on each side of the gate electrode (GE). In a planar view, the active contacts (AC) may have a bar shape extending in the first direction (D1).

[0075] The active contact (AC) may be a self-aligned contact. In other words, the active contact (AC) may be formed self-aligned using the gate capping pattern (GP) and the gate spacer (GS). For example, the active contact (AC) may cover at least a portion of the sidewall of the gate spacer (GS). Although not illustrated, the active contact (AC) may cover a portion of the top surface of the gate capping pattern (GP).

[0076] A metal-semiconductor compound layer (SC), for example, a silicide layer, may be interposed between the active contact (AC) and the first source / drain pattern (SD1), and between the active contact (AC) and the second source / drain pattern (SD2), respectively. The active contact (AC) may be electrically connected to the source / drain patterns (SD1, SD2) through the metal-semiconductor compound layer (SC). For example, the metal-semiconductor compound layer (SC) may include at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

[0077] Referring again to FIG. 5c, at least one active contact (AC) on the first single height cell (SHC1) can electrically connect the first source / drain pattern (SD1) of the first PMOSFET region (PR1) and the second source / drain pattern (SD2) of the first NMOSFET region (NR1). The active contact (AC) can extend in a first direction (D1) from the second source / drain pattern (SD2) of the first NMOSFET region (NR1) to the first source / drain pattern (SD1) of the first PMOSFET region (PR1).

[0078] Gate contacts (GC) that are electrically connected to gate electrodes (GE), respectively, by penetrating the second interlayer insulating film (120) and the gate capping pattern (GP) may be provided. In a planar view, two gate contacts (GC) on the first single height cell (SHC1) may be placed overlappingly on the first PMOSFET region (PR1). In other words, two gate contacts (GC) on the first single height cell (SHC1) may be provided on the first active pattern (AP1) (see FIG. 5a). In a planar view, one gate contact (GC) on the first single height cell (SHC1) may be placed overlappingly on the first NMOSFET region (NR1). In other words, one gate contact (GC) on the first single height cell (SHC1) may be provided on the second active pattern (AP2) (see FIG. 5b).

[0079] The gate contact (GC) can be freely positioned on the gate electrode (GE) without positional restrictions. For example, the gate contacts (GC) on the second single-height cell (SHC2) can be positioned on the second PMOSFET region (PR2), the second NMOSFET region (NR2), and the device isolation film (ST) filling the trench (TR), respectively (see FIG. 4).

[0080] In one embodiment of the present invention, referring to FIGS. 5a and 5b, the upper surface of an active contact (AC) adjacent to a gate contact (GC) may be filled with an upper insulating pattern (UIP). The bottom surface of the upper insulating pattern (UIP) may be lower than the bottom surface of the gate contact (GC). In other words, the upper surface of the active contact (AC) adjacent to the gate contact (GC) may be lower than the bottom surface of the gate contact (GC) by the upper insulating pattern (UIP). This prevents the problem of a short circuit occurring when the gate contact (GC) comes into contact with the active contact (AC) adjacent to it.

[0081] Each of the active contact (AC) and the gate contact (GC) may comprise a barrier metal (BM) and a fill metal (FM) on the barrier metal (BM). The barrier metal (BM) may cover the remaining surface excluding the upper surface of the fill metal (FM). For example, the fill metal (FM) may comprise at least one of molybdenum, tungsten, ruthenium, cobalt, and vanadium. In one embodiment of the present invention, the fill metal (FM) may comprise molybdenum. The barrier metal (BM) may comprise a metal nitride film. The metal nitride film may comprise at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0082] A first metal layer (M1) may be provided within the third interlayer insulating film (130). For example, the first metal layer (M1) may include a first power wiring (M1_R1), a second power wiring (M1_R2), a third power wiring (M1_R3), and first wirings (M1_I). Each of the wirings (M1_R1, M1_R2, M1_R3, M1_I) of the first metal layer (M1) may extend parallel to each other in a second direction (D2).

[0083] Specifically, the first and second power lines (M1_R1, M1_R2) may be provided on the third and fourth boundaries (BD3, BD4) of the first single height cell (SHC1), respectively. The first power line (M1_R1) may extend in a second direction (D2) along the third boundary (BD3). The second power line (M1_R2) may extend in a second direction (D2) along the fourth boundary (BD4).

[0084] The first wires (M1_I) of the first metal layer (M1) may be arranged along the first direction (D1) at a second pitch. The second pitch may be smaller than the first pitch. The line width of each of the first wires (M1_I) may be smaller than the line width of each of the first to third power wires (M1_R1, M1_R2, M1_R3).

[0085] The first metal layer (M1) may further include first vias (VI1). The first vias (VI1) may each be provided under the wirings (M1_R1, M1_R2, M1_R3, M1_I) of the first metal layer (M1). Through the first vias (VI1), the active contact (AC) and the wiring of the first metal layer (M1) may be electrically connected to each other. Through the first vias (VI1), the gate contact (GC) and the wiring of the first metal layer (M1) may be electrically connected to each other.

[0086] The first via (VI1) may include a barrier metal (BM) and a fill metal (FM) on the barrier metal (BM), just like the active and gate contacts (AC, GC). The wiring of the first metal layer (M1) and the first via (VI1) below it may each be formed by a separate process. In other words, the wiring of the first metal layer (M1) and the first via (VI1) may each be formed by a single damascene process. The semiconductor device according to the present embodiment may be formed using a process of less than 20 nm.

[0087] A second metal layer (M2) may be provided within the fourth interlayer insulating film (140). The second metal layer (M2) may include a plurality of second wires (M2_I). Each of the second wires (M2_I) of the second metal layer (M2) may have a line shape or a bar shape extending in a first direction (D1). In other words, the second wires (M2_I) may extend parallel to each other in the first direction (D1).

[0088] The second metal layer (M2) may further include second vias (VI2) provided below each of the second wirings (M2_I). Through the second vias (VI2), the wiring of the first metal layer (M1) and the wiring of the second metal layer (M2) can be electrically connected to each other. For example, the wiring of the second metal layer (M2) and the second vias (VI2) below it can be formed together by a dual damascene process.

[0089] The wiring of the first metal layer (M1) and the wiring of the second metal layer (M2) may include the same or different conductive materials. For example, the wiring of the first metal layer (M1) and the wiring of the second metal layer (M2) may include at least one metal selected from copper, ruthenium, aluminum, tungsten, molybdenum, and cobalt. Although not illustrated, metal layers (e.g., M3, M4, M5...) stacked on the fourth interlayer insulating film (140) may be additionally disposed. Each of the stacked metal layers may include wiring for routing between cells.

[0090] With reference to FIG. 6, the barrier metal (BM) and fill metal (FM) of the active contact (AC) are described in detail. A barrier metal (BM) may be provided on the inner wall of the contact trench (CNH) of the first interlayer insulating film (110). The barrier metal (BM) may have a uniform thickness.

[0091] In one embodiment of the present invention, the barrier metal (BM) may comprise a metal nitride film (e.g., TiN) formed by a PECVD process. In another embodiment of the present invention, the barrier metal (BM) may comprise a metal nitride film (e.g., TiN) that has been plasma-treated after deposition. In other words, the barrier metal (BM) may be a metal nitride film that has undergone ion bombardment using plasma during or immediately after its deposition process.

[0092] Barrier metals (BMs), such as TiN, can be denser through ion bombardment compared to TiN deposited simply by a CVD process. Barrier metals (BMs), such as TiN, can possess compressive stress due to densification by ion bombardment.

[0093] The filler metal (FM) can be formed on the barrier metal (BM) through a deposition process (e.g., ALD) after the barrier metal (BM) has been formed. When the filler metal (FM) is formed, its crystal structure may be influenced by the barrier metal (BM).

[0094] According to one embodiment of the present invention, molybdenum, which is the filling metal (FM), may include a first crystal region (CRS1) and a second crystal region (CRS2). The first crystal region (CRS1) may have a first crystal structure (e.g., a body-centered cubic structure (BCC)). The second crystal region (CRS2) may have a second crystal structure (e.g., a face-centered cubic structure (FCC)).

[0095] Grain boundaries (GRBs) can be defined between crystal regions. Grain boundaries (GRBs) may exist between a first crystal region (CRS1) and a second crystal region (CRS2) having different crystal structures. Additionally, grain boundaries (GRBs) may exist between adjacent first crystal regions (CRS1) having the same crystal structure.

[0096] The proportion of the first crystal regions (CRS1) of the filling metal (FM) may be 60% to 99%. In other words, the ratio of the volume of the first crystal regions (CRS1) to the total volume of the filling metal (FM) may be 60% to 99%. Or, in the two-dimensional cross-sectional image shown in FIG. 6, the ratio of the area of ​​the first crystal regions (CRS1) to the total area of ​​the filling metal (FM) may be 60% to 99%. The filling metal (FM) may have a BCC structure with a fraction of 60% to 99%. The remaining area of ​​the filling metal (FM), excluding the first crystal regions (CRS1), may be occupied by the second crystal regions (CRS2).

[0097] In one embodiment of the present invention, molybdenum, which is the filling metal (FM), may have a BCC structure in which 60% to 99% of its crystal structure is BCC. More specifically, molybdenum, which is the filling metal (FM), may have a BCC structure in which 80% to 99% of its crystal structure is BCC.

[0098] Molybdenum, which is the filling metal (FM), may have a BCC structure of 60% to 99%, more specifically 80% to 99%, so that the resistivity may be 16 μΩcm to 18 μΩcm. The filling metal (FM) according to the embodiments of the present invention may have a relatively low resistivity by having a BCC structure of 80% or more. In other words, the resistance of the active contact (AC) may be relatively small, which can improve the electrical characteristics of the semiconductor device.

[0099] The barrier metal (BM) and fill metal (FM) according to embodiments of the present invention have been described by exemplifying an active contact (AC). The gate contact (GC) and the first via (VI1) may also similarly include the barrier metal (BM) and fill metal (FM), and the description of the barrier metal (BM) and fill metal (FM) constituting the gate contact (GC) and the first via (VI1) may be substantially the same as that of the active contact (AC) described above.

[0100] Consequently, in the semiconductor device according to the embodiments of the present invention, the electrical resistance between the transistors constituting the logic circuit and the wiring of the first metal layer (M1) above them can be reduced, and thereby the electrical characteristics of the device can be improved.

[0101] According to one embodiment of the present invention, the ratio of the body-centered cubic structure (BCC) of the filling metal (FM) of the active contact (AC) may be greater than the ratio of the body-centered cubic structure (BCC) of the filling metal (FM) of the gate contact (GC) and the first via (VI1), respectively. Thus, the resistivity of the filling metal (FM) of the active contact (AC) may be smaller than the resistivity of the filling metal (FM) of the gate contact (GC) and the first via (VI1), respectively. This is because the active contact (AC) is a contact type filled within a relatively wide trench (see FIG. 5c), whereas the gate contact (GC) and the first via (VI1) are contact types filled within a relatively narrow hole (see FIG. 5d).

[0103] FIGS. 7a to 14d are cross-sectional views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. Specifically, FIGS. 7a, 8a, 9a, 10a, 11a, 12a, 13a, and 14a are cross-sectional views corresponding to line A-A' of FIG. 9b, 10b, 11b, 12b, 13b, and 14b are cross-sectional views corresponding to line B-B' of FIG. 9c, 10c, 11c, 12c, 13c, and 14c are cross-sectional views corresponding to line C-C' of FIG. 4. FIGS. 7b, FIGS. 8b, FIGS. 9d, FIGS. 10d, FIGS. 11d, FIGS. 12d, FIGS. 13d and FIGS. 14d are cross-sectional views corresponding to the line D-D' in FIGS. 4.

[0104] Referring to FIGS. 7a and 7b, a substrate (100) comprising first and second PMOSFET regions (PR1, PR2) and first and second NMOSFET regions (NR1, NR2) may be provided. Active layers (ACL) and sacrificial layers (SAL) may be formed alternately stacked on the substrate (100). The active layers (ACL) may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layers (SAL) may include the other of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0105] The sacrificial layer (SAL) may include a material capable of having an etch selectivity with respect to the active layer (ACL). For example, the active layers (ACL) may include silicon (Si), and the sacrificial layers (SAL) may include silicon-germanium (SiGe). The concentration of germanium (Ge) in each of the sacrificial layers (SAL) may be 10 at% to 30 at%.

[0106] Mask patterns may be formed on the first and second PMOSFET regions (PR1, PR2) and the first and second NMOSFET regions (NR1, NR2) of the substrate (100), respectively. The mask pattern may have a line shape or a bar shape extending in the second direction (D2).

[0107] A patterning process can be performed on the above mask patterns using an etching mask to form a trench (TR) defining a first active pattern (AP1) and a second active pattern (AP2). The first active pattern (AP1) can be formed on each of the first and second PMOSFET regions (PR1, PR2). The second active pattern (AP2) can be formed on each of the first and second NMOSFET regions (NR1, NR2).

[0108] A stacking pattern (STP) may be formed on each of the first and second active patterns (AP1, AP2). The stacking pattern (STP) may include active layers (ACL) and sacrificial layers (SAL) that are alternately stacked with each other. The stacking pattern (STP) may be formed together with the first and second active patterns (AP1, AP2) during the patterning process.

[0109] A device isolation layer (ST) that fills the trench (TR) can be formed. Specifically, an insulating layer covering the first and second active patterns (AP1, AP2) and stacked patterns (STP) can be formed on the front surface of the substrate (100). The device isolation layer (ST) can be formed by recessing the insulating layer until the stacked patterns (STP) are exposed.

[0110] The device isolation layer (ST) may include an insulating material such as a silicon oxide film. Stacked patterns (STP) may be exposed over the device isolation layer (ST). In other words, the stacked patterns (STP) may protrude vertically over the device isolation layer (ST).

[0111] Referring to FIGS. 8a and 8b, sacrifice patterns (PP) can be formed across stacked patterns (STP) on a substrate (100). Each sacrifice pattern (PP) can be formed in a line shape or a bar shape extending in a first direction (D1). The sacrifice patterns (PP) can be arranged along a second direction (D2) with a first pitch.

[0112] Specifically, forming the sacrificial patterns (PP) may include forming a sacrificial film on the front surface of a substrate (100), forming hard mask patterns (MP) on the sacrificial film, and patterning the sacrificial film using the hard mask patterns (MP) as an etching mask. For example, the sacrificial film may include polysilicon.

[0113] A pair of gate spacers (GS) may be formed on both sidewalls of each of the sacrifice patterns (PP). Forming the gate spacers (GS) may include conformally forming a gate spacer film on the front surface of the substrate (100) and anisotropically etching the gate spacer film. In one embodiment of the present invention, the gate spacer (GS) may be a multi-layer comprising at least two films.

[0114] Referring to FIGS. 9a through 9d, first recesses (RS1) may be formed within a stacked pattern (STP) on a first active pattern (AP1). Second recesses (RS2) may be formed within a stacked pattern (STP) on a second active pattern (AP2). While forming the first and second recesses (RS1, RS2), the device isolation film (ST) on each side of the first and second active patterns (AP1, AP2) may be further recessed (see FIG. 9c).

[0115] Specifically, first recesses (RS1) can be formed by etching a stacked pattern (STP) on a first active pattern (AP1) using hard mask patterns (MA) and gate spacers (GS) as etching masks. The first recesses (RS1) can be formed between a pair of sacrifice patterns (PP).

[0116] The second recesses (RS2) within the stacking pattern (STP) on the second active pattern (AP2) can be formed in the same way as the first recesses (RS1). Forming the second recess (RS2) may further include the sacrificial layer (SAL) forming an inner spacer (IP) within the recessed area.

[0117] First to third semiconductor patterns (SP1, SP2, SP3) can be formed sequentially between adjacent first recesses (RS1) from the active layers (ACL). First to third semiconductor patterns (SP1, SP2, SP3) can be formed sequentially between adjacent second recesses (RS2) from the active layers (ACL). The first to third semiconductor patterns (SP1, SP2, SP3) between adjacent first recesses (RS1) can form a first channel pattern (CH1). The first to third semiconductor patterns (SP1, SP2, SP3) between adjacent second recesses (RS2) can form a second channel pattern (CH2).

[0118] Referring to FIGS. 10a through 10d, first source / drain patterns (SD1) may each be formed within the first recesses (RS1). Specifically, a buffer layer (BFL) may be formed by performing a first SEG process in which the inner wall of the first recess (RS1) serves as a seed layer. The buffer layer (BFL) may be grown using the first to third semiconductor patterns (SP1, SP2, SP3) exposed by the first recess (RS1) and the substrate (100) as seeds. As an example, the first SEG process may include a Chemical Vapor Deposition (CVD) process or a Molecular Beam Epitaxy (MBE) process.

[0119] The buffer layer (BFL) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate (100). The buffer layer (BFL) may contain a relatively low concentration of germanium (Ge). In another embodiment of the present invention, the buffer layer (BFL) may contain only silicon (Si) excluding germanium (Ge). The concentration of germanium (Ge) in the buffer layer (BFL) may be 0 at% to 10 at%.

[0120] A second SEG process can be performed on the buffer layer (BFL) to form a main layer (MAL). The main layer (MAL) can be formed to completely fill the first recess (RS1). The main layer (MAL) may contain a relatively high concentration of germanium (Ge). For example, the concentration of germanium (Ge) in the main layer (MAL) may be 30 at% to 70 at%.

[0121] While forming the buffer layer (BFL) and the main layer (MAL), impurities (e.g., boron, gallium, or indium) that cause the first source / drain pattern (SD1) to have a p-type can be injected in-situ. As another example, impurities can be injected into the first source / drain pattern (SD1) after the first source / drain pattern (SD1) is formed.

[0122] Second source / drain patterns (SD2) may each be formed within the second recesses (RS2). Specifically, the second source / drain pattern (SD2) may be formed by performing a third SEG process in which the inner wall of the second recess (RS2) is used as a seed layer. As an example, the second source / drain pattern (SD2) may include the same semiconductor element (e.g., Si) as the substrate (100).

[0123] While the second source / drain pattern (SD2) is being formed, impurities (e.g., phosphorus, arsenic, or antimony) that cause the second source / drain pattern (SD2) to have an n-type can be injected in-situ. As another example, impurities can be injected into the second source / drain pattern (SD2) after the second source / drain pattern (SD2) has been formed.

[0124] Referring to FIGS. 11a through 11d, a first interlayer insulating film (110) covering first and second source / drain patterns (SD1, SD2), hard mask patterns (MP), and gate spacers (GS) may be formed. As an example, the first interlayer insulating film (110) may include a silicon oxide film.

[0125] The first interlayer insulating film (110) can be flattened until the upper surfaces of the sacrificial patterns (PP) are exposed. The flattening of the first interlayer insulating film (110) can be performed using an etch back or chemical mechanical polishing (CMP) process. During the flattening process, all hard mask patterns (MP) can be removed. Consequently, the upper surface of the first interlayer insulating film (110) can be co-planar with the upper surfaces of the sacrificial patterns (PP) and the upper surfaces of the gate spacers (GS).

[0126] By using photolithography, a region of the sacrificial pattern (PP) can be selectively opened. For example, a region of the sacrificial pattern (PP) on the third and fourth boundaries (BD3, BD4) of the first single height cell (SHC1) can be selectively opened. The opened region of the sacrificial pattern (PP) can be selectively etched and removed. An insulating material can be filled into the space where the sacrificial pattern (PP) has been removed to form a gate cutting pattern (CT).

[0127] Referring to FIGS. 12a through 12d, the exposed sacrificial patterns (PP) can be selectively removed. By removing the sacrificial patterns (PP), an outer region (ORG) exposing the first and second channel patterns (CH1, CH2) can be formed (see FIG. 12d). Removing the sacrificial patterns (PP) may include wet etching using an etchant that selectively etches polysilicon.

[0128] Sacrificial layers (SAL) exposed through the outer region (ORG) can be selectively removed to form inner regions (IRG) (see FIG. 12d). Specifically, an etching process that selectively etches the sacrificial layers (SAL) can be performed to remove only the sacrificial layers (SAL) while leaving the first to third semiconductor patterns (SP1, SP2, SP3) intact. The etching process can have a high etching rate for silicon-germanium having a relatively high germanium concentration. For example, the etching process can have a high etching rate for silicon-germanium having a germanium concentration greater than 10 at%.

[0129] During the etching process, sacrificial layers (SAL) on the first and second PMOSFET regions (PR1, PR2) and the first and second NMOSFET regions (NR1, NR2) may be removed. The etching process may be a wet etch. The etching material used in the etching process can rapidly remove the sacrificial layer (SAL) having a relatively high germanium concentration. Meanwhile, the first source / drain pattern (SD1) on the first and second PMOSFET regions (PR1, PR2) may be protected during the etching process by a buffer layer (BFL) having a relatively low germanium concentration.

[0130] Referring again to FIG. 12d, the sacrificial layers (SAL) are selectively removed so that only the stacked first to third semiconductor patterns (SP1, SP2, SP3) remain on each of the first and second active patterns (AP1, AP2). The first to third inner regions (IRG1, IRG2, IRG3) can each be formed through the regions where the sacrificial layers (SAL) have been removed.

[0131] Specifically, a first inner region (IRG1) may be formed between an active pattern (AP1 or AP2) and a first semiconductor pattern (SP1), a second inner region (IRG2) may be formed between the first semiconductor pattern (SP1) and a second semiconductor pattern (SP2), and a third inner region (IRG3) may be formed between the second semiconductor pattern (SP2) and a third semiconductor pattern (SP3).

[0132] Referring to FIGS. 13a through 13d, a gate insulating film (GI) may be conformally formed on exposed first to third semiconductor patterns (SP1, SP2, SP3). A gate electrode (GE) may be formed on the gate insulating film (GI). The gate electrode (GE) may include first to third portions (PO1, PO2, PO3) formed respectively within first to third inner regions (IRG1, IRG2, IRG3) and a fourth portion (PO4) formed within an outer region (ORG).

[0133] The gate electrode (GE) can be recessed so that its height can be reduced. While the gate electrode (GE) is recessed, the upper portions of the first and second gate cutting patterns (CT1, CT2) can also be slightly recessed. A gate capping pattern (GP) can be formed on the recessed gate electrode (GE).

[0134] Referring to FIGS. 14a through 14d, a second interlayer insulating film (120) may be formed on a first interlayer insulating film (110). The second interlayer insulating film (120) may include a silicon oxide film. Active contacts (AC) electrically connected to first and second source / drain patterns (SD1, SD2) may be formed through the second interlayer insulating film (120) and the first interlayer insulating film (110). Gate contacts (GC) electrically connected to gate electrodes (GE), respectively, may be formed through the second interlayer insulating film (120) and the gate capping pattern (GP).

[0135] Forming each active contact (AC) and gate contact (GC) may include forming a barrier metal (BM) and forming a filling metal (FM) on the barrier metal (BM). The barrier metal (BM) may be formed conformally and may include a metal film / metal nitride film. The filling metal (FM) may include a low-resistance metal.

[0136] A pair of isolation structures (DB) may be formed on both sides of each of the first and second single-height cells (SHC1, SHC2). The isolation structure (DB) may extend from the second interlayer insulating film (120) through the gate electrode (GE) into the active pattern (AP1 or AP2). The isolation structure (DB) may include an insulating material such as a silicon oxide film or a silicon nitride film.

[0137] Referring again to FIGS. 5a through 5d, a third interlayer insulating film (130) may be formed on active contacts (AC) and gate contacts (GC). A first metal layer (M1) may be formed within the third interlayer insulating film (130). Specifically, first vias (VI1) connected to the active and gate contacts (AC, GC), respectively, may be formed on the lower part of the third interlayer insulating film (130). Each of the first vias (VI1) may include a barrier metal (BM) and a fill metal (FM). Wiring (M1_R1, M1_R2, M1_R3, M1_I) in contact with the first vias (VI1) may be formed on the upper part of the third interlayer insulating film (130). A fourth interlayer insulating film (140) may be formed on the third interlayer insulating film (130). A second metal layer (M2) can be formed within the fourth interlayer insulating film (140).

[0138] FIGS. 15 to 17 are enlarged views illustrating a method for forming an active contact in the M region of FIG. 14a. Referring to FIG. 15, a contact trench (CNH) can be formed penetrating the first interlayer insulating film (110). For example, the contact trench (CNH) can expose a first source / drain pattern (SD1). The bottom of the contact trench (CNH) may be lower than the top surface of the first source / drain pattern (SD1).

[0139] A metal-semiconductor compound layer (SC) can be formed by performing a silicide process on a first source / drain pattern (SD1) exposed through a contact trench (CNH). The metal-semiconductor compound layer (SC) can be formed by the semiconductor material of the first source / drain pattern (SD1) exposed through the contact trench (CNH) reacting with a metal material supplied through the contact trench (CNH).

[0140] Referring to FIG. 16, a barrier metal film (BML) can be conformally formed on the inner wall of a contact trench (CNH). The barrier metal film (BML) can be formed using a chemical vapor deposition (CVD) process. The barrier metal film (BML) may include a metal nitride film (e.g., TiN).

[0141] A barrier metal film (BML) according to embodiments of the present invention can be formed using plasma. In one embodiment, the barrier metal film (BML) can be formed by a deposition process under plasma, for example, using a PECVD process. In another embodiment, a plasma post-treatment process can be performed on the barrier metal film (BML) after the deposition process of the barrier metal film (BML).

[0142] Since plasma treatment is performed on the barrier metal film (BML), ion bombardment by ions (IN) generated by the plasma can be applied to the barrier metal film (BML). The ions (IN) can be generated by introducing at least one of the inert gases nitrogen, argon, helium, neon, krypton, and xenon into the plasma process.

[0143] In one embodiment of the present invention, the ions (IN) impacting the barrier metal film (BML) may include nitrogen ions. In another embodiment of the present invention, the ions (IN) impacting the barrier metal film (BML) may include argon ions. In this case, argon (Ar) may remain as an impurity within the barrier metal film (BML). In other words, the impurity remaining within the barrier metal film (BML) may include at least one of argon, helium, neon, krypton, and xenon as ions used in the plasma. The concentration of impurities within the barrier metal film (BML) may be 1E18 atomic / cm3 to 1E21 atomic / cm3.

[0144] By applying ion bombardment to the barrier metal film (BML), the barrier metal film (BML) can become denser compared to the case where plasma treatment is not performed. The barrier metal film (BML) can have compressive stress.

[0145] Referring to FIG. 17, a filling metal film (FML) may be formed on a barrier metal film (BML). The filling metal film (FML) may be formed using a deposition process (e.g., ALD). The filling metal film (FML) may include at least one of molybdenum, tungsten, ruthenium, cobalt, and vanadium. In one embodiment of the present invention, the filling metal film (FML) may include molybdenum.

[0146] The filling metal film (FML) may include first crystal regions (CRS1) having a first crystal structure (e.g., body-centered cubic structure (BCC)) and second crystal regions (CRS2) having a second crystal structure (e.g., face-centered cubic structure (FCC)).

[0147] While the filling metal film (FML) is formed by a deposition process, at least two crystal structures may be formed within it. While the filling metal film (FML) is formed by a deposition process, crystal regions having specific crystal structures may be created within it, forming boundaries with one another. In other words, the filling metal film (FML) may include grain boundaries (GRBs) defined between the crystal regions.

[0148] The proportion of the first crystal regions (CRS1) of the filling metal film (FML) may be 60% to 99%. Preferably, the proportion of the first crystal regions (CRS1) of the filling metal film (FML) may be 80% to 99%. For example, the filling metal film (FML) may comprise molybdenum having a BCC structure of 80% or more. The filling metal film (FML) may be deposited on a dense barrier metal film (BML) to which ion bombardment has been applied, such that the proportion of the first crystal regions (CRS1) may be 60% or more, preferably 80% or more.

[0149] The resistivity of the filling metal film (FML) can decrease inversely proportionally as the proportion of the first crystal regions (CRS1) having a BCC structure increases. In other words, the resistivity of the filling metal film (FML) can decrease as the proportion of the first crystal regions (CRS1) increases. Since the filling metal film (FML) according to the present embodiment contains molybdenum having a BCC structure of 80% or more, the resistivity of the filling metal film (FML) can be relatively small to 16 μΩcm to 18 μΩcm.

[0150] Referring again to FIG. 14a, the fill metal film (FML) and barrier metal film (BML) within the contact trench (CNH) can then be recessed to form the fill metal (FM) and barrier metal (BM), respectively. The fill metal (FM) and barrier metal (BM) can form an active contact (AC). An upper insulating pattern (UIP) can be filled onto the recessed active contact (AC).

[0151] Although not separately illustrated, the method of forming the gate contact (GC) and the first via (VI1), respectively, may include the method of forming the barrier metal film (BML) and the filling metal film (FML) described above with reference to FIGS. 15 to 17.

[0152] According to one embodiment of the present invention, since the active contact (AC) is formed within a relatively wide contact trench (CNH), ion bombardment on the barrier metal film (BML) can be performed more smoothly. As a result, the barrier metal film (BML) of the active contact (AC) can be relatively dense. On the other hand, since the gate contact (GC) and the first via (VI1) are formed within a relatively narrow hole, ion bombardment on the barrier metal film (BML) may not be performed somewhat smoothly. As a result, the barrier metal film (BML) of each of the gate contact (GC) and the first via (VI1) may be less dense than the barrier metal film (BML) of the active contact (AC).

[0153] Since the barrier metal film (BML) of the active contact (AC) is relatively dense, the proportion of the body-centered cubic structure (BCC) of the filling metal film (FML) formed thereon may be relatively large. On the other hand, since the barrier metal film (BML) of each of the gate contact (GC) and the first via (VI1) is relatively less dense, the proportion of the body-centered cubic structure (BCC) of the filling metal film (FML) formed thereon may be relatively small.

[0154] FIG. 18 is an enlarged view illustrating a method for forming an active contact in the M region of FIG. 14a according to a comparative example of the present invention. Referring to FIG. 18, the barrier metal film (BML) according to the comparative example of the present invention may omit plasma during its formation process. For example, the barrier metal film (BML) according to the comparative example may be formed by a simple CVD process alone, and subsequent plasma post-treatment may also be omitted. Therefore, the barrier metal film (BML) according to the comparative example may not be as dense as the ion-bombed barrier metal film (BML) described above with reference to FIG. 16.

[0155] The filling metal film (FML) deposited on the barrier metal film (BML) according to the comparative example may have a relatively small proportion of first crystal regions (CRS1). For example, the proportion of first crystal regions (CRS1) of the filling metal film (FML) according to the comparative example may be less than 60%. In other words, the proportion of second crystal regions (CRS2) of the filling metal film (FML) may be relatively increased.

[0156] The filling metal film (FML) according to the present comparative example has a relatively small BCC structure ratio, so its resistivity may be relatively high. For example, the resistivity of the filling metal film (FML) according to the present comparative example may be greater than 18 μΩcm. This is because the crystal structure of the filling metal film (FML) is determined by the characteristics of the underlying film (i.e., barrier metal film (BML)) during its deposition process.

[0158] FIGS. 19a to 19d are for illustrating a semiconductor device according to an embodiment of the present invention and are cross-sectional views along lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively. In the embodiments of the present invention described below, detailed descriptions of technical features that overlap with those described with reference to FIGS. 4 and FIGS. 5a to 5d are omitted, and differences are described in detail.

[0159] Referring to FIG. 4 and FIG. 19a through 19d, the device isolation layer (ST) can define a first active pattern (AP1) and a second active pattern (AP2) on the upper surface of the substrate (100). The first active pattern (AP1) can be defined on each of the first PMOSFET region (PR1) and the second PMOSFET region (PR2), and the second active pattern (AP2) can be defined on each of the first NMOSFET region (NR1) and the second NMOSFET region (NR2).

[0160] The device isolation layer (ST) can cover the lower sidewalls of each of the first and second active patterns (AP1, AP2). The upper portions of each of the first and second active patterns (AP1, AP2) can protrude over the device isolation layer (ST) (see FIG. 19d).

[0161] A first active pattern (AP1) may include first source / drain patterns (SD1) on its upper side and a first channel pattern (CH1) between them. A second active pattern (AP2) may include second source / drain patterns (SD2) on its upper side and a second channel pattern (CH2) between them.

[0162] Referring again to FIG. 19d, each of the first and second channel patterns (CH1, CH2) may not include the stacked first to third semiconductor patterns (SP1, SP2, SP3) described earlier with reference to FIG. 5a through 5d. Each of the first and second channel patterns (CH1, CH2) may have the form of a single semiconductor pillar protruding over the device isolation layer (ST) (see FIG. 19d).

[0163] A gate electrode (GE) may be provided on the upper surface (TS) and both sidewalls (SW) of each of the first and second channel patterns (CH1, CH2). In other words, the transistor according to the present embodiment may be a three-dimensional field-effect transistor (e.g., FinFET) in which the gate electrode (GE) surrounds the channel three-dimensionally.

[0164] A first interlayer insulating film (110) and a second interlayer insulating film (120) may be provided on the front surface of the substrate (100). Active contacts (AC) connected to first and second source / drain patterns (SD1, SD2), respectively, through the first and second interlayer insulating films (110, 120) may be provided. A gate contact (GC) connected to a gate electrode (GE) through the second interlayer insulating film (120) and a gate capping pattern (GP) may be provided. A detailed description of the active contacts (AC) and the gate contacts (GC) may be substantially the same as that previously described with reference to FIGS. 4, FIGS. 5a to 5d and FIG. 6.

[0165] A third interlayer insulating film (130) may be provided on the second interlayer insulating film (120). A fourth interlayer insulating film (140) may be provided on the third interlayer insulating film (130). A first metal layer (M1) may be provided within the third interlayer insulating film (130). A second metal layer (M2) may be provided within the fourth interlayer insulating film (140). A detailed description of the first metal layer (M1) and the second metal layer (M2) may be substantially the same as that previously described with reference to FIGS. 4 and FIGS. 5a through 5d.

[0167] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor device comprising: a substrate including an active pattern; a channel pattern and a source / drain pattern on the active pattern, wherein the channel pattern is connected to the source / drain pattern; a gate electrode on the channel pattern; and an active contact electrically connected to the source / drain pattern, wherein the active contact comprises a first barrier metal and a first filling metal on the first barrier metal, wherein the first barrier metal comprises a metal nitride film, the first filling metal comprises at least one of molybdenum, tungsten, ruthenium, cobalt, and vanadium, and the first filling metal comprises a first crystal region having a body-centered cubic structure (BCC) and a second crystal region having a face-centered cubic structure (FCC), and wherein the ratio of the first crystal region within the first filling metal is 60% to 99%. Claim 2 A semiconductor device according to claim 1, wherein the ratio of the first crystal region within the first filling metal is greater than the ratio of the second crystal region. Claim 3 A semiconductor device according to claim 1, wherein the first barrier metal comprises a titanium nitride film, the first filling metal comprises molybdenum, and the ratio of the first crystal region within the first filling metal is 80% to 99%. Claim 4 A semiconductor device according to claim 1, wherein the first filling metal further comprises a grain boundary between the first crystal region and the second crystal region. Claim 5 In claim 1, the first barrier metal comprises at least one impurity among argon, helium, neon, krypton, and xenon. Claim 6 A semiconductor device according to claim 1, wherein the resistivity of the first filling metal is 16 μΩcm to 18 μΩcm. Claim 7 A semiconductor device according to claim 1, further comprising a gate contact electrically connected to the gate electrode, wherein the gate contact comprises a second barrier metal and a second filling metal on the second barrier metal, and the second filling metal comprises a third crystal region having a body-centered cubic structure (BCC) and a fourth crystal region having a face-centered cubic structure (FCC), and the ratio of the first crystal region within the first filling metal is greater than the ratio of the third crystal region within the second filling metal. Claim 8 A semiconductor device according to claim 1, further comprising: wiring on the active contact; and via interposed between the wiring and the active contact to electrically connect them, wherein the via comprises a second barrier metal and a second filling metal on the second barrier metal, and the second filling metal comprises a third crystal region having a body-centered cubic structure (BCC) and a fourth crystal region having a face-centered cubic structure (FCC), and the ratio of the first crystal region within the first filling metal is greater than the ratio of the third crystal region within the second filling metal. Claim 9 In claim 1, the first barrier metal is a semiconductor device covering a surface excluding the upper surface of the first filling metal. Claim 10 A semiconductor device according to claim 1, wherein the resistivity of the first filling metal decreases as the ratio of the first crystal region within the first filling metal increases. Claim 11 A substrate including an active pattern; a channel pattern and a source / drain pattern on the active pattern, wherein the channel pattern is connected to the source / drain pattern; a gate electrode on the channel pattern; and an active contact connected to the source / drain pattern. A semiconductor device comprising a metal layer on the active contact, wherein wiring within the metal layer is electrically connected to each other through the active contact and vias, wherein the active contact comprises a first barrier metal and a first fill metal on the first barrier metal, and the via comprises a second barrier metal and a second fill metal on the second barrier metal, wherein the first and second barrier metals comprise a metal nitride film, and the first and second fill metals comprise at least one of molybdenum, tungsten, ruthenium, cobalt, and vanadium, and wherein the ratio of the volume of the body-centered cubic structure (BCC) to the total volume of the first fill metal is greater than the ratio of the volume of the body-centered cubic structure (BCC) to the total volume of the second fill metal. Claim 12 A semiconductor device according to claim 11, wherein the ratio of the body-centered cubic (BCC) structure of each of the first filling metal and the second filling metal is 60% to 99%. Claim 13 A semiconductor device according to claim 11, wherein each of the first and second barrier metals comprises a titanium nitride film, and each of the first and second filling metals comprises molybdenum. Claim 14 A semiconductor device according to claim 11, wherein the resistivity of the first filling metal is smaller than the resistivity of the second filling metal. Claim 15 A semiconductor device according to claim 14, wherein the resistivity of each of the first and second filling metals is 16 μΩcm to 18 μΩcm. Claim 16 A substrate comprising a PMOSFET region and an NMOSFET region; a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region; a first channel pattern and a first source / drain pattern on the first active pattern; a second channel pattern and a second source / drain pattern on the second active pattern; a gate electrode extending in a first direction across the first and second channel patterns; a gate insulating film interposed between the gate electrode and the first and second channel patterns; a gate spacer on the sidewall of the gate electrode; a gate capping pattern on the upper surface of the gate electrode; a gate cutting pattern penetrating the gate electrode; an interlayer insulating film on the gate capping pattern and the gate cutting pattern; an active contact electrically connected to the first and second source / drain patterns penetrating the interlayer insulating film; metal-semiconductor compound layers respectively interposed between the active contact and the first and second source / drain patterns; penetrating the interlayer insulating film and the gate capping pattern, electrically connected to the gate electrode A semiconductor device comprising: a connected gate contact; a first metal layer on the interlayer insulating film, wherein the first metal layer comprises power wiring vertically superimposed with the gate cutting pattern and first wiring electrically connected to the active and gate contacts, respectively; and a second metal layer on the first metal layer, wherein the second metal layer comprises second wiring electrically connected to the first metal layer, wherein the active contact comprises a first barrier metal and a first filling metal on the first barrier metal, and the gate contact comprises a second barrier metal and a second filling metal on the second barrier metal, wherein the ratio of the volume of the body-centered cubic structure (BCC) to the total volume of the first filling metal is greater than the ratio of the volume of the body-centered cubic structure (BCC) to the total volume of the second filling metal. Claim 17 A semiconductor device according to claim 16, wherein each of the first and second barrier metals comprises a titanium nitride film, and each of the first and second filling metals comprises molybdenum. Claim 18 A semiconductor device according to claim 16, wherein the body-centered cubic (BCC) ratio of each of the first and second filling metals is 60% to 99%. Claim 19 A semiconductor device in which the resistivity of the first filling metal is smaller than the resistivity of the second filling metal in claim 16. Claim 20 A semiconductor device according to claim 19, wherein the resistivity of each of the first and second filling metals is 16 μΩcm to 18 μΩcm.

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