Display device

Abstract

The display device may include a first data wiring group comprising a plurality of first data wirings that are positioned in a fan-out area and extend to a display area adjacent to the fan-out area, a second data wiring group comprising a plurality of second data wirings that are positioned in the fan-out area and extend to the display area, a plurality of pixels that are positioned in the display area and connected to the first and second data wirings, and a dummy pattern that is positioned between the first data wiring group and the second data wiring group in the fan-out area and is in a floating state.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] Generally, electronic devices that provide video to users, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions, include a display device for displaying the video. The display device generates video and provides the generated video to the user through a display screen.

[0003] Generally, a display device includes a display panel and a plurality of driving ICs connected to the display panel. The driving ICs are placed on flexible circuit boards and connected to the display panel through the flexible circuit boards.

[0004] The display panel includes multiple pixels that display an image and wiring connected to the pixels. Driving ICs are connected to the wiring through flexible circuit boards. Driving signals generated by the driving ICs are provided to the pixels through the wiring, and the pixels are driven in response to the driving signals.

[0005] During the manufacturing process of display panels, a substrate with formed wiring may be transported via transport rollers. At this time, the wiring may become charged due to friction between the substrate and the transport rollers. In such cases, a burnt phenomenon may occur, in which the components on the substrate are damaged by static electricity generated by the charged wiring. Therefore, the development of technology to prevent this burnt phenomenon is required. The problem to be solved

[0006] The objective of the present invention is to provide a display device capable of preventing damage to components on a substrate. means of solving the problem

[0007] A display device according to an embodiment of the present invention may include a first data wiring group comprising a plurality of first data wirings disposed in a fan-out area and extending to a display area adjacent to the fan-out area, a second data wiring group comprising a plurality of second data wirings disposed in the fan-out area and extending to the display area, a plurality of pixels disposed in the display area and connected to the first and second data wirings, and a dummy pattern disposed between the first data wiring group and the second data wiring group in the fan-out area and in a floating state.

[0008] A display device according to an embodiment of the present invention comprises: a first data wiring group comprising a plurality of first data wirings disposed in a fan-out area and extending to a display area adjacent to the fan-out area; a second data wiring group comprising a plurality of second data wirings disposed in the fan-out area and extending to the display area; a plurality of pixels disposed in the display area and connected to the first and second data wirings; and a dummy pattern disposed between the first data wiring group and the second data wiring group in the fan-out area, wherein the dummy pattern may extend parallel to a first-1 data wiring adjacent to the second data wiring group among the first data wirings and a second-1 data wiring adjacent to the first data wiring group among the second data wirings.

[0009] A display device according to an embodiment of the present invention comprises a first data wiring group comprising a plurality of first data wirings disposed in a fan-out area and extending to a display area adjacent to the fan-out area, a second data wiring group comprising a plurality of second data wirings disposed in the fan-out area and extending to the display area, a plurality of pixels disposed in the display area and connected to the first and second data wirings, and a dummy pattern disposed between the first data wiring group and the second data wiring group in the fan-out area, wherein the dummy pattern may be insulated from surrounding conductors and may not receive voltage. Effects of the invention

[0010] According to an embodiment of the present invention, the first-1 data wiring of the first data wirings and the first-2 data wiring of the second data wirings may be adjacent to each other. A dummy pattern may be placed between the first-1 data wiring and the first-2 data wiring. Parasitic capacitors may be formed by the dummy pattern and the first-1 and first-2 data wirings.

[0011] The capacitance of the parasitic capacitor formed between the 1-1 data line and the 1-2 data line can be increased by the dummy pattern. When the capacitance of the parasitic capacitor increases, the potential difference between the 1-1 and 1-2 data lines is relatively reduced, which can reduce the generation of electrostatic charge. Therefore, the burning phenomenon is prevented, and damage to the components on the substrate can be prevented. Brief explanation of the drawing

[0012] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention. Figure 2 is an exploded perspective view of the display device shown in Figure 1. FIG. 3 is a drawing exemplarily illustrating a cross-section of the display panel shown in FIG. 2. Figure 4 is a plan view of the display panel shown in Figure 3. FIG. 5 is a diagram exemplarily illustrating a cross-section of a pixel shown in FIG. 4. FIG. 6 is a cross-sectional view of a portion of the display area of ​​the display module shown in FIG. 2. Figure 7 is an enlarged view of the area (AA1) shown in Figure 4. Figure 8 is a cross-sectional view of the line I-I' shown in Figure 7. FIGS. 9a and 9b are cross-sectional views along line I-I' shown in FIG. 7 according to another embodiment of the present invention. FIG. 10 is a diagram exemplarily illustrating the movement state of the first substrate after predetermined layers are formed on the first substrate shown in FIG. 8. FIG. 11a is a diagram illustrating, exemplarily, layers formed on the first substrate shown in FIG. 10 corresponding to the cross-section of line II-II' shown in FIG. 8. FIG. 11b is a diagram illustrating the damaged state of the configurations on the first substrate shown in FIG. 11a. FIG. 12 is a circuit diagram for a first parasitic capacitor formed by the first-1 data wiring and the second-1 data wiring when there is no dummy pattern in FIG. 7. FIG. 13 is a circuit diagram illustrating first and second parasitic capacitors formed by a dummy pattern, a first-1 data wiring, and a second-1 data wiring. FIGS. 14 to 17 are drawings illustrating the configuration of dummy patterns according to various embodiments of the present invention. Specific details for implementing the invention

[0013] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0014] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content.

[0015] "And / or" includes all one or more combinations that the associated configurations can define.

[0016] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0017] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined herein.

[0019] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0020] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0021] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention.

[0022] Referring to FIG. 1, the display device (DD) may have a plane defined by first and second directions (DR1, DR2). The display device (DD) may have a rectangular shape having short sides extending in the first direction (DR1) and long sides extending in the second direction (DR2) intersecting the first direction (DR1). However, it is not limited thereto, and the display device (DD) may have various shapes such as a circle or a polygon.

[0023] The direction that intersects substantially perpendicularly to the plane defined by the first and second directions (DR1, DR2) below is defined as the third direction (DR3).

[0024] The upper surface of the display device (DD) can be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). An image generated by the display device (DD) can be provided to a user through the display surface (DS).

[0025] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may display an image, and the non-display area (NDA) may not display an image. The non-display area (NDA) may surround the display area (DA) and define a border of a display device (DD) that is printed in a predetermined color.

[0026] The display device (DD) can be used in large electronic devices such as televisions, monitors, or external billboards. Additionally, the display device (DD) can be used in small and medium-sized electronic devices such as personal computers, laptop computers, personal digital terminals, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented only as exemplary embodiments and may be used in other electronic devices without departing from the concept of the invention.

[0027] Figure 2 is an exploded perspective view of the display device shown in Figure 1.

[0028] Referring to FIG. 2, the display device (DD) may include a window (WM), a display module (DM), and a case (HAU). The window (WM), the display module (DM), and the case (HAU) may have a rectangular shape having short sides extending in a first direction (DR1) and long sides extending in a second direction (DR2) that intersects the first direction (DR1).

[0029] Hereinafter, "up" or "down" in this specification may be defined based on the third direction (DR3).

[0030] The window (WM) can be placed on the display module (DM). The window (WM) may have optically transparent properties. The window (WM) can protect the display module (DM) from external shocks and scratches. The front surface of the window (WM) may correspond to the display surface (DS) of the aforementioned display device (DD).

[0031] The front surface of the window (WM) may include a transparent area (TA) and a bezel area (BA). The transparent area (TA) may transmit light, and the bezel area (BA) may be printed in a predetermined color to block light. The transparent area (TA) may overlap with the aforementioned display area (DA), and the bezel area (BA) may overlap with the aforementioned non-display area (NDA).

[0032] A display module (DM) may be placed between a window (WM) and a case (HAU). The display module (DM) may include a display area (DA) and a non-display area (NDA) around the display area (DA). The display area (DA) and the non-display area (NDA) may correspond to the display area (DA) and the non-display area (NDA) respectively illustrated in FIG. 1.

[0033] The non-display area (NDA) may surround the display area (DA). The display area (DA) may generate an image, while the non-display area (NDA) may not generate an image. The image generated in the display area (DA) may be provided to an external user through the transparent area (TA). The non-display area (NDA) may not be exposed to the outside by the bezel area (BA).

[0034] The display module (DM) may include a display panel (DP) and a light conversion unit (LCP) disposed on the display panel (DP). Light can be generated from the display panel (DP) to create an image. The light conversion unit (LCP) receives light generated from the display panel (DP) and can convert the color of the received light. Additionally, the light conversion unit (LCP) can reduce the reflectivity of external light. This configuration will be described in detail below.

[0035] The case (HAU) is positioned below the display module (DM) to accommodate the display module (DM). The case (HAU) can protect the display module (DM) by absorbing external shocks and blocking external foreign substances and moisture.

[0036] Although not illustrated, the display device (DD) may further include an input sensing unit disposed between the display panel (DP) and the light conversion unit (LCP). The input sensing unit may include a plurality of sensing units (not illustrated) for detecting external input. The sensing units may detect external input in a capacitive manner. The input sensing unit may be manufactured directly on the display panel (DP) during the manufacturing of the display panel (DP).

[0037] FIG. 3 is a drawing exemplarily illustrating a cross-section of the display panel shown in FIG. 2.

[0038] For example, FIG. 3 shows a cross-section of a display panel (DP) viewed from a first direction (DR1).

[0039] Referring to FIG. 3, the display module (DM) may include a display panel (DP), a light converter (LCP), a filler (FL), and a sealant (SAL). The light converter (LCP) may be placed on the display panel (DP), and the filler (FL) and sealant (SAL) may be placed between the light converter (LCP) and the display panel (DP).

[0040] A display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel and is not particularly limited. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0041] The sealant (SAL) may be placed between the light conversion unit (LCP) and the display panel (DP) by overlapping the non-display area (NDA). The light conversion unit (LCP) and the display panel (DP) may be bonded together by the sealant (SAL). The sealant (SAL) may include a UV-curable material.

[0042] The filler (FL) may be placed between the light converter (LCP) and the display panel (DP) overlapping the display area (DA). The filler (FL) may extend toward the non-display area (NDA) and come into contact with the sealant (SAL). The filler (FL) may include silicone, epoxy, and acrylic-based thermosetting materials.

[0043] The display panel (DP) may include a first substrate (SUB1), a circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE). The light conversion unit (LCP) may include a second substrate (SUB2), a color filter layer (CFL), and a light conversion layer (LCL).

[0044] A second substrate (SUB2) is disposed on a first substrate (SUB1) and can face the first substrate (SUB1). A circuit element layer (DP-CL), a display element layer (DP-OLED), a thin film encapsulation layer (TFE), a color filter layer (CFL), a light conversion layer (LCL), a filler (FL), and a sealant (SAL) can be disposed between the first substrate (SUB1) and the second substrate (SUB2).

[0045] The first substrate (SUB1) and the second substrate (SUB2) may comprise glass or flexible plastic material. When viewed in a planar view, the first substrate (SUB1) may include a display area (DA) and a non-display area (NDA) around the display area (DA), such as a display panel (DP).

[0046] The circuit element layer (DP-CL) can be disposed on the first substrate (SUB1). The display element layer (DP-OLED) can be disposed on the circuit element layer (DP-CL). The display element layer (DP-OLED) can be disposed on the display area (DA).

[0047] Multiple pixels may be disposed in the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor disposed in the circuit element layer (DP-CL) and a light-emitting element disposed in the display element layer (DP-OLED) and connected to the transistor. The configuration of the pixel will be described in detail below.

[0048] A thin film encapsulation layer (TFE) can be placed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) can protect the pixels from moisture, oxygen, and external foreign substances.

[0049] A color filter layer (CFL) can be placed under a second substrate (SUB2). When viewed in a planar view, the color filter layer (CFL) can overlap the display area (DA). A portion of the color filter layer (CFL) can overlap the non-display area (NDA).

[0050] A light conversion layer (LCL) may be placed below a color filter layer (CFL). When viewed in a planar view, the light conversion layer (LCL) may overlap the display area (DA). A portion of the light conversion layer (LCL) may overlap the non-display area (NDA).

[0051] A sealant (SAL) may be placed between a first substrate (SUB1) and a second substrate (SUB2). The first substrate (SUB1) and the second substrate (SUB2) may be bonded together by the sealant (SAL). The sealant (SAL) may be placed between a thin film encapsulation layer (TFE) and a color filter layer (CFL). The sealant (SAL) may surround a light conversion layer (LCL). A filler (FL) may be placed between the light conversion layer (LCL) and the thin film encapsulation layer (TFE) by overlapping it in a display area (DA).

[0052] Light generated from the display element layer (DP-OLED) can be provided to the light conversion layer (LCL). The light conversion layer (LCL) can convert the color of the light provided from the display element layer (DP-OLED). The color-converted light can be emitted externally through the color filter layer (CFL) and the second substrate (SUB2).

[0053] The color filter layer (CFL) can prevent reflection of external light supplied to the display panel (DP) from the outside. The function of this color filter layer (CFL) will be explained in detail below.

[0054] Figure 4 is a plan view of the display panel shown in Figure 3.

[0055] Referring to FIG. 4, the display device (DD) may include a display panel (DP), a scan driver (SDV), a plurality of data drivers (DDV), a plurality of flexible circuit boards (FPCB), an emission driver (EDV), and a printed circuit board (PCB).

[0056] The display panel (DP) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) and the non-display area (NDA) of the display panel (DP) may correspond to the display area (DA) and the non-display area (NDA) shown in FIG. 2, respectively.

[0057] The display panel (DP) may include a plurality of pixels (PX), a plurality of scanning lines (SL1~SLm), a plurality of data lines (DL1~DLn), a plurality of light-emitting lines (EL1~ELm), and a plurality of dummy patterns (DPT). m and n are natural numbers.

[0058] Pixels (PX) can be placed in a display area (DA). A scanning driver (SDV) and an emitting driver (EDV) can be placed in a non-display area (NDA) adjacent to the short sides of the display panel (DP), respectively.

[0059] Data drivers (DDV) may be positioned adjacent to the lower side of the display panel (DP), which is defined as one of the long sides of the display panel (DP) when viewed in a planar view. Data drivers (DDV) may be defined as driving ICs.

[0060] A printed circuit board (PCB) may be positioned adjacent to the lower side of a display panel (DP) when viewed in a planar view. Flexible circuit boards (FPCBs) may be connected to the lower side of the display panel (DP) and to the printed circuit board (PCB). Data drivers (DDVs) may be fabricated in the form of integrated circuit chips and mounted on each of the flexible circuit boards (FPCBs).

[0061] Scanning wires (SL1~SLm) can be extended in a second direction (DR2) and connected to pixels (PX) and a scanning driver (SDV). Light emitting wires (EL1~ELm) can be extended in a second direction (DR2) and connected to pixels (PX) and a light emitting driver (EDV).

[0062] Hereinafter, when viewed on a plane (e.g., when viewed from the third direction (DR3)), the area between the lower side of the display panel (DP) and the display area (DA) is defined as the fan-out area (F-OT).

[0063] Data lines (DL1~DLn) can be extended in a first direction (DR1) from a display area (DA) and connected to pixels (PX) and data drivers (DDV). Scan lines (SL1~SLm) and light-emitting lines (EL1~ELm) can be extended in the display area (DA) to intersect with the data lines (DL1~DLn) while being insulated from them.

[0064] Multiple data wires may be connected to each of the data drivers (DDV). For example, the data wires (DL1 to DLn) may be divided into multiple data wire groups (DLG), and each of the data wire groups (DLG) may include multiple data wires (DLI). Each data wire (DLI) of the data wire groups (DLG) may be connected to a corresponding data driver (DDV) among the data drivers (DDV) through a corresponding flexible circuit board (FPCB) among the flexible circuit boards (FPCB).

[0065] Each data wiring group (DLG)'s data wiring (DLI) can extend radially from the fan-out area (F-OT) toward the display area (DA). The radially extended data wiring (DLI) can extend from the display area (DA) toward a first direction (DR1).

[0066] Dummy patterns (DPT) can be placed between data wiring groups (DLG) in the fan-out area (F-OT). The dummy patterns (DPT) can have a cap shape (cap shape or caret symbol shape) toward the display area (DA) between the data wiring groups (DLG). The function of the dummy patterns (DPT) will be described in detail below.

[0067] Dummy patterns (DPT) may not be connected to scanning lines (SL1–SLm) and light-emitting lines (EL1–ELm). Dummy patterns (DPT) may not be connected to data lines (DL1–DLn) and data drivers (DDV). That is, dummy patterns (DPT) may be insulated from surrounding conductors. Additionally, dummy patterns (DPT) may not be connected to the ground terminal (not shown) and power terminal (not shown) of the display device (DD). Dummy patterns (DPT) may be independent patterns not connected to other conductors.

[0068] Although not illustrated, the display device (DD) may further include a timing controller for controlling the operation of the scanning driver (SDV), data drivers (DDV), and light-emitting driver (EDV). The timing controller may be fabricated in the form of an integrated circuit chip and mounted on a printed circuit board (PCB). The timing controller may be connected to the data drivers (DDV), scanning driver (SDV), and light-emitting driver (EDV) through the printed circuit board (PCB) and a flexible circuit board (FPCB).

[0069] The scanning driver (SDV) generates multiple scanning signals, and the scanning signals can be applied to pixels (PX) through scanning lines (SL1~SLm). The data drivers (DDV) generate multiple data voltages, and the data voltages can be applied to pixels (PX) through data lines (DL1~DLn). The light emission driver (EDV) generates multiple light emission signals, and the light emission signals can be applied to pixels (PX) through light emission lines (EL1~ELm).

[0070] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display an image by emitting light of a brightness corresponding to the data voltages in response to light emission signals. The light emission time of the pixels (PX) can be controlled by the light emission signals.

[0071] FIG. 5 is a diagram exemplarily illustrating a cross-section of a pixel shown in FIG. 4.

[0072] Although the configuration of one pixel (PX) is illustrated as an example, other pixels (PX) may have the same configuration as the pixel (PX) illustrated in FIG. 5.

[0073] Referring to FIG. 5, the pixel (PX) may include a transistor (TR) and a light-emitting element (OLED). The light-emitting element (OLED) may include a first electrode (AE) (or anode), a second electrode (CE) (or cathode), a hole control layer (HCL), an electronic control layer (ECL), and a light-emitting layer (EML).

[0074] A transistor (TR) and a light-emitting element (OLED) may be disposed on a first substrate (SUB1). Although one transistor (TR) is illustrated as an example, substantially, the pixel (PX) may include a plurality of transistors and at least one capacitor for driving the light-emitting element (OLED).

[0075] The display area (DA) may include a light-emitting area (EA) corresponding to each of the pixels (PX) and a non-light-emitting area (NEA) surrounding the light-emitting area (EA). A light-emitting element (OLED) may be placed in the light-emitting area (EA).

[0076] A light-blocking layer (BML) may be disposed on a first substrate (SUB1). The light-blocking layer (BML) may include a metallic material. A buffer layer (BFL) may be disposed on the light-blocking layer (BML). The buffer layer (BFL) may be disposed on the first substrate (SUB1) to cover the light-blocking layer (BML).

[0077] A semiconductor layer (S, A, D) may be disposed on a buffer layer (BFL). The semiconductor layer (S, A, D) may comprise polysilicon, amorphous silicon, or a metal oxide. The semiconductor layer may be doped with an N-type dopant or a P-type dopant. The semiconductor layer may include a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than that of the low-doping region and may substantially serve as the source electrode (S) and drain electrode (D) of the transistor (TR). The low-doping region may substantially correspond to the active (A) (or channel) of the transistor.

[0078] The source electrode (S), active (A), and drain electrode (D) of the transistor (TR) can be formed from semiconductor layers (S, A, D). A first insulating layer (INS1) can be disposed on the semiconductor layers (S, A, D). A gate electrode (G) of the transistor (TR) can be disposed on the first insulating layer (INS1). When viewed in a planar view, the gate electrode (G) can overlap with the active (A). A second insulating layer (INS2) can be disposed on the gate electrode (G). A third insulating layer (INS3) can be disposed on the second insulating layer (INS2).

[0079] A connecting electrode (CNE) is positioned between a transistor (TR) and a light-emitting element (OLED) to connect the transistor (TR) and the light-emitting element (OLED). The connecting electrode (CNE) may include a first connecting electrode (CNE1) and a second connecting electrode (CNE2).

[0080] A first connecting electrode (CNE1) is disposed on a third insulating layer (INS3) and can be connected to a drain electrode (D) through a first contact hole (CH1) defined in the first to third insulating layers (INS1 to INS3). A fourth insulating layer (INS4) can be disposed on the first connecting electrode (CNE1). The fourth insulating layer (INS4) can be disposed on the third insulating layer (INS3) to cover the first connecting electrode (CNE1).

[0081] The second connecting electrode (CNE2) may be disposed on the fourth insulating layer (INS4). The second connecting electrode (CNE2) may be connected to the first connecting electrode (CNE1) through a second contact hole (CH2) defined in the fourth insulating layer (INS4).

[0082] A fifth insulating layer (INS5) may be disposed on the second connecting electrode (CNE2). The layers from the buffer layer (BFL) to the fifth insulating layer (INS5) may be defined as circuit element layers (DP-CL). The buffer layer (BFL) and the first to third insulating layers (INS1~INS3) may be inorganic layers. The fourth and fifth insulating layers (INS4,INS5) may be organic layers.

[0083] A first electrode (AE) may be disposed on the fifth insulating layer (INS5). The first electrode (AE) may be connected to a second connecting electrode (CNE2) through a third contact hole (CH3) defined in the fifth insulating layer (INS5). A pixel defining film (PDL) may be disposed on the first electrode (AE) and the fifth insulating layer (INS5), wherein a pixel opening (PX_OP) is defined to expose a predetermined portion of the first electrode (AE).

[0084] A hole control layer (HCL) may be disposed on a first electrode (AE) and a pixel definition film (PDL). The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

[0085] The emitting layer (EML) may be disposed on the hole control layer (HCL). The emitting layer (EML) may be disposed on the pixel aperture (PX_OP). The emitting layer (EML) may include organic and / or inorganic materials. The emitting layer (EML) may generate blue light.

[0086] An electronic control layer (ECL) may be disposed on an emitting layer (EML) and a hole control layer (HCL). The electronic control layer (ECL) may include an electron transport layer and an electron injection layer. The hole control layer (HCL) and the electronic control layer (ECL) may be disposed in common in the emitting region (EA) and the non-emitting region (NEA).

[0087] The second electrode (CE) may be placed on the electronic control layer (ECL). The second electrode (CE) may be placed in common on the pixels (PX). The layer on which the light-emitting element (OLED) is placed may be defined as a display element layer (DP-OLED).

[0088] A thin film encapsulation layer (TFE) can be placed on a second electrode (CE) to cover a pixel (PX). Although not illustrated, the thin film encapsulation layer (TFE) may include two inorganic layers and an organic layer between the inorganic layers. The inorganic layers can protect the pixel (PX) from moisture / oxygen. The organic layer can protect the pixel (PX) from foreign substances such as dust particles.

[0089] A first voltage can be applied to a first electrode (AE) through a transistor (TR), and a second voltage can be applied to a second electrode (CE). Holes and electrons injected into the light-emitting layer (EML) combine to form excitons, and as the excitons transition to a ground state, the light-emitting element (OLED) can emit light.

[0090] When viewed in a planar view, the light-blocking layer (BML) can be positioned to overlap the semiconductor layer (S, A, D). The light-blocking layer (BML) can block light provided to the semiconductor layer (S, A, D) from the bottom of the first substrate (SUB1). When light is provided to the semiconductor layer (S, A, D), the threshold voltage characteristics of the transistor (TR) may change. Since the light provided to the semiconductor layer (S, A, D) is blocked by the light-blocking layer (BML), the threshold voltage characteristics of the transistor (TR) may not change.

[0091] FIG. 6 is a cross-sectional view of a portion of the display area of ​​the display module shown in FIG. 2.

[0092] For example, FIG. 6 shows a cross-sectional view of a region corresponding to three light-emitting regions (EA1, EA2, EA3). Also, for example, in FIG. 6, the circuit element layer (DP-CL) and the display element layer (DP-OLED) are shown as a single layer, but the circuit element layer (DP-CL) and the display element layer (DP-OLED) may be provided with multiple transistors (TR) and light-emitting elements (OLED) as shown in FIG. 5.

[0093] Referring to FIG. 6, the display area (DA) may include a first light-emitting area (EA1), a second light-emitting area (EA2), a third light-emitting area (EA3), and a non-light-emitting area (NEA) positioned around each of the first, second, and third light-emitting areas (EA1, EA2, EA3). The first, second, and third light-emitting areas (EA1, EA2, EA3) may generate a first light (L1). For example, the first light (L1) may be blue light. The light-emitting area (EA) illustrated in FIG. 5 may be any one of the first, second, and third light-emitting areas (EA1, EA2, EA3).

[0094] The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), a third color filter (CF3), a low refractive index layer (LRL), and a first insulating layer (IL1). For example, one first color filter (CF1), one second color filter (CF2), and one third color filter (CF3) are shown, but substantially, each of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may be provided in multiple numbers.

[0095] The light conversion layer (LCL) may include a first quantum dot layer (QDL1), a second quantum dot layer (QDL2), a light-transmitting layer (LTL), a bank layer (BNK), and a second insulating layer (IL2). For example, one first quantum dot layer (QDL1), one second quantum dot layer (QDL2), and one light-transmitting layer (LTL) are shown, but substantially, each of the first quantum dot layer (QDL1), the second quantum dot layer (QDL2), and the light-transmitting layer (LTL) may be provided in multiple numbers.

[0096] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may be placed under the second substrate (SUB2). When viewed in a planar view, the first color filter (CF1) may overlap the first light-emitting region (EA1), the second color filter (CF2) may overlap the second light-emitting region (EA2), and the third color filter (CF3) may overlap the third light-emitting region (EA3). The first color filter (CF1) may include a red color filter. The second color filter (CF2) may include a green color filter. The third color filter (CF3) may include a blue color filter.

[0097] A low-refractive index layer (LRL) may be disposed below a second substrate (SUB2) to cover first, second, and third color filters (CF1, CF2, CF3). The low-refractive index layer (LRL) may have a lower refractive index than the first quantum dot layer (QDL1), the second quantum dot layer (QDL2), and the light-transmitting layer (LTL). The low-refractive index layer (LRL) may include an organic layer and a plurality of scattering particles disposed within the organic layer that can scatter light. A first insulating layer (IL1) may be disposed below the low-refractive index layer (LRL). The first insulating layer (IL1) may include an inorganic layer.

[0098] The bank layer (BNK) may be placed below the first insulating layer (IL1). When viewed in a planar view, the bank layer (BNK) may overlap the non-emissive region (NEA). In the bank layer (BNK), openings (QOP) that overlap the first, second, and third emissive regions (EA1, EA2, EA3) may be defined. The width of each opening (QOP) may be greater than the width of the aforementioned pixel opening (PX_OP). The bank layer (BNK) may be black.

[0099] First and second quantum dot layers (QDL1, QDL2) and a light-transmitting layer (LTL) may be disposed in the openings (QOP). Thus, the first and second quantum dot layers (QDL1, QDL2) and the light-transmitting layer (LTL) may overlap the first, second, and third light-emitting regions (EA1, EA2, EA3) when viewed in a planar view. The first quantum dot layer (QDL1) may overlap the first light-emitting region (EA1), the second quantum dot layer (QDL2) may overlap the second light-emitting region (EA2), and the light-transmitting layer (LTL) may overlap the third light-emitting region (EA3).

[0100] The second insulating layer (IL2) may be disposed below the bank layer (BNK), the first and second quantum dot layers (QDL1, QDL2), and the light-transmitting layer (LTL). The second insulating layer (IL2) may include an inorganic layer.

[0101] The first light (L1) generated in the first, second, and third light-emitting regions (EA1, EA2, EA3) can be supplied to the first and second quantum dot layers (QDL1, QDL2) and the light-transmitting layer (LTL). The first light (L1) generated in the first light-emitting region (EA1) can be supplied to the first quantum dot layer (QDL1), and the first light (L1) generated in the second light-emitting region (EA2) can be supplied to the second quantum dot layer (QDL2). The first light (L1) generated in the third light-emitting region (EA3) can be supplied to the light-transmitting layer (LTL).

[0102] The first quantum dot layer (QDL1) can convert the first light (L1) into the second light (L2). The second quantum dot layer (QDL2) can convert the first light (L1) into the third light (L3). For example, the second light (L2) may be red light and the third light (L3) may be green light. The first quantum dot layer (QDL1) may include first quantum dots (not shown), and the second quantum dot layer (QDL2) may include second quantum dots (not shown). The light-transmitting layer (LTL) may include light-scattering particles (not shown).

[0103] The first quantum dots can convert a first light (L1) having a blue wavelength band into a second light (L2) having a red wavelength band. The second quantum dots can convert the first light (L1) having a blue wavelength band into a third light (L3) having a green wavelength band. The first and second quantum dots can scatter the second and third lights (L2, L3).

[0104] The light-transmitting layer (LTL) can transmit the first light (L1) without performing a light conversion operation. The first light (L1) can be scattered and emitted by light-scattering particles of the light-transmitting layer (LTL). The light-scattering particles may be included in the first and second quantum dot layers (QDL1, QDL2).

[0105] The first quantum dot layer (QDL1) can emit a second light (L2), the second quantum dot layer (QDL2) can emit a third light (L3), and the light-transmitting layer (LTL) can emit a first light (L1). Accordingly, an image can be displayed by the second light (L2), the third light (L3), and the first light (L1) displaying red, green, and blue.

[0106] The first, second, and third lights (L1, L2, L3) emitted from the light conversion layer (LCL) can be provided to the user by passing through the low-refractive index layer (LRL), the first, second, and third color filters (CF1, CF2, CF3), and the second substrate (SUB2). After being refracted in the low-refractive index layer (LRL), the first, second, and third lights (L1, L2, L3) can be emitted after being further scattered by scattering particles placed in the low-refractive index layer (LRL).

[0107] A portion of the first light (L1) may pass through the first quantum dot layer (QDL1) without being converted by the first quantum dots and be supplied to the first color filter (CF1). That is, there may be first light (L1) that is not converted into second light (L2) because it is not in contact with the first quantum dots. The first color filter (CF1) may block other colored light. The first light (L1) that is not converted in the first quantum dot layer (QDL1) may be blocked by the first color filter (CF1), which has a red color filter, and may not be emitted upward.

[0108] A portion of the first light (L1) may pass through the second quantum dot layer (QDL2) without being converted by the second quantum dots and be provided to the second color filter (CF2). That is, there may be first light (L1) that is not converted into third light (L3) because it does not come into contact with the second quantum dots. The second color filter (CF2) may block other colored light. The first light (L1) that is not converted in the second quantum dot layer (QDL2) may be blocked by the second color filter (CF2), which has a green color filter, and may not be emitted upward.

[0109] External light may be provided from the display device (DD) toward the display panel (DP). The external light may be white light. The white light may include red light, green light, and blue light. If the first, second, and third color filters (CF1, CF2, CF3) are not used, the external light may be provided directly to an external user after being reflected from metal layers (e.g., wiring) inside the display panel (DP). In this case, the external light may be visible to the user, such as light reflected from a mirror.

[0110] The first, second, and third color filters (CF1, CF2, CF3) can prevent reflection of external light. For example, the first, second, and third color filters (CF1, CF2, CF3) can filter external light into red, green, and blue.

[0111] Specifically, the green and blue light of the external light provided to the first color filter (CF1) can be blocked by the first color filter (CF1) which includes a red color filter. Accordingly, the external light provided to the first color filter (CF1) can be filtered by the first color filter (CF1) into red light identical to the light emitted from the first quantum dot layer (QDL1).

[0112] The red and blue light of the external light supplied to the second color filter (CF2) can be blocked by the second color filter (CF2), which is a green color filter. Therefore, the external light supplied to the second color filter (CF2) can be filtered by the second color filter (CF2) into green light identical to the light emitted from the second quantum dot layer (QDL2).

[0113] The red and green light of the external light supplied to the third color filter (CF3) can be blocked by the third color filter (CF3), which is a blue color filter. Therefore, the external light supplied to the third color filter (CF3) can be filtered by the third color filter (CF3) into blue light identical to the light emitted from the light-transmitting layer (LTL). Thus, the external light is blocked by the first, second, and third color filters (CF1, CF2, CF3), and the reflection of the external light can be reduced.

[0114] A bank layer (BNK) having black color can block unwanted light in a non-emissive region (NEA). For example, the bank layer (BNK) can prevent color mixing between the first light (L1), the second light (L2), and the third light (L3) in the non-emissive region (NEA).

[0115] Figure 7 is an enlarged view of the area (AA1) shown in Figure 4.

[0116] The data wiring groups (DLG) shown in the area (AA1) below are defined as a first data wiring group (GP1) and a second data wiring group (GP2).

[0117] Referring to FIG. 7, data wiring groups (DLG) may include a first data wiring group (GP1) and a second data wiring group (GP2). The first data wiring group (GP1) and the second data wiring group (GP2) may be placed in a fan-out area (F-OT) and be adjacent to each other in a second direction (DR2).

[0118] A first data wiring group (GP1) may include a plurality of first data wirings (DLI1) extending to a display area (DA) adjacent to a fan-out area (F-OT). A second data wiring group (GP2) may include a plurality of second data wirings (DLI2) extending to a display area (DA) adjacent to a fan-out area (F-OT). The first data wirings (DLI1) and the second data wirings (DLI2) may be the aforementioned data wirings (DLI).

[0119] The first data lines (DLI1) can extend radially from the fan-out area (F-OT) toward the display area (DA). The second data lines (DLI2) can extend radially from the fan-out area (F-OT) toward the display area (DA).

[0120] The first data lines (DLI1) and the second data lines (DLI2) may be extended radially to have substantially the same shape. The first data lines (DLI1) and the second data lines (DLI2) may be formed by simultaneous patterning with the same material on the same layer. The first data lines (DLI1) and the second data lines (DLI2) may be extended in a first direction (DR1) from a fan-out area (F-OT) adjacent to a display area (DA).

[0121] Dummy patterns (DPT) may be placed between the first data wiring group (GP1) and the second data wiring group (GP2). The dummy patterns (DPT) may have a cap shape and be placed adjacent to the first data wiring group (GP1) and the second data wiring group (GP2). As described above, the dummy patterns (DPT) may be independent patterns that are electrically isolated and insulated from surrounding conductors.

[0122] Multiple extension patterns (EXP) may be placed between dummy patterns (DPT). The extension patterns (EXP) may extend from parts of the h-th dummy pattern (DPT) among the multiple dummy patterns (DPT) to parts of the h+1-th dummy pattern (DPT). h is a natural number. For example, the h-th dummy pattern (DPT) may be closer to the first data wiring group (GP1) and the second data wiring group (GP2) than the h+1-th dummy pattern (DPT).

[0123] The extension patterns (EXP) may be formed integrally with the dummy patterns (DPT). The dummy patterns (DPT) may be formed integrally by the extension patterns (EXP). However, not limited thereto, the extension patterns (EXP) may be placed on a different layer from the dummy patterns (DPT) and connected to the dummy patterns (DPT) by contact holes.

[0124] The dummy patterns (DPT) may be in a floating state. For example, no separate voltage may be applied to the dummy patterns (DPT). The first voltage and the second voltage applied to the anode (AE) and cathode (CE) of the aforementioned pixel (PX) may not be applied to the dummy patterns (DPT). The display device (DD) of the present invention may include a voltage generating unit (not shown) for generating the first voltage and the second voltage. The dummy patterns (DPT) may not be connected to the power terminal of the voltage generating unit.

[0125] Hereinafter, among the first data wires (DLI1), the wire adjacent to the second data wire group (GP2) is defined as the first-1 data wire (DL1-1), and among the second data wires (DLI2), the wire adjacent to the first data wire group (GP1) is defined as the second-1 data wire (DL2-1).

[0126] Hereinafter, on a plane defined by the first and second directions (DR1, DR2), the direction intersecting the first and second directions (DR1, DR2) is defined as the first diagonal direction (DDR1). The direction intersecting the first diagonal direction (DDR1) is defined as the second diagonal direction (DDR2).

[0127] The first-1 data line (DL1-1) and the second-1 data line (DL2-1) may have a shape that is adjacent to each other in the second direction (DR2) and symmetrical. Toward the display area (DA), the first-1 data line (DL1-1) may extend in the first direction (DR1), then extend in the first diagonal direction (DDR1), and then extend again in the first direction (DR1). Toward the display area (DA), the second-1 data line (DL2-1) may extend in the first direction (DR1), then extend in the second diagonal direction (DDR2), and then extend again in the first direction (DR1).

[0128] The distance between the portion of the first-1 data line (DL1-1) extending in the first diagonal direction (DDR1) and the portion of the second-1 data line (DL2-1) extending in the second diagonal direction (DDR2) can gradually increase as it moves away from the display area (DA).

[0129] Dummy patterns (DPTs) may be placed adjacent to the first-1 data line (DL1-1) and the second-1 data line (DL2-1). The dummy patterns (DPTs) may extend parallel to each other. The dummy patterns (DPTs) may be spaced apart from each other and extend parallel to the first-1 data line (DL1-1) and the second-1 data line (DL2-1).

[0130] Each of the dummy patterns (DPT) may include a first dummy wiring pattern (DLP1) extending parallel to the first-1 data wiring (DL1-1) and a second dummy wiring pattern (DLP2) extending parallel to the second-1 data wiring (DL2-1). The first dummy wiring pattern (DLP1) may be positioned adjacent to the first-1 data wiring (DL1-1), and the second dummy wiring pattern (DLP2) may be positioned adjacent to the second-1 data wiring (DL2-1).

[0131] The first dummy wiring pattern (DLP1) and the second dummy wiring pattern (DLP2) can be extended symmetrically to each other. Toward the display area (DA), the first dummy wiring pattern (DLP1) can be extended in the first direction (DR1) and then in the first diagonal direction (DDR1). Toward the display area (DA), the second dummy wiring pattern (DLP2) can be extended in the first direction (DR1) and then in the second diagonal direction (DDR2).

[0132] The distance between the portion of the first dummy wiring pattern (DLP1) extending in the first diagonal direction (DDR1) and the portion of the second dummy wiring pattern (DLP2) extending in the second diagonal direction (DDR2) can gradually increase as it moves away from the display area (DA).

[0133] The second dummy wiring pattern (DLP2) can be bent and extended from the end of the first dummy wiring pattern (DLP1) adjacent to the display area (DA). Depending on the structure of the first dummy wiring pattern (DLP1) and the second dummy wiring pattern (DLP2), each of the dummy patterns (DPT) may have a conical shape.

[0134] A first parasitic capacitor (CP1) can be formed by a first-1 data line (DL1-1) and a second-1 data line (DL2-1) extending in a first direction (DR1) adjacent to the display area (DA) than the dummy wiring patterns (DPT).

[0135] A second parasitic capacitor (CP2) can be formed by the first-1 data wiring (DL1-1) and the first dummy wiring pattern (DLP1). Additionally, a second parasitic capacitor (CP2) can be formed by the second-1 data wiring (DL2-1) and the second dummy wiring pattern (DLP2).

[0136] Figure 8 is a cross-sectional view of the line I-I' shown in Figure 7.

[0137] Referring to FIG. 8, dummy patterns (DPT) and second data lines (DLI2) may be placed on a first substrate (SUB1). Although not shown, first data lines (DLI1) may also be placed on the first substrate (SUB1). Hereinafter, the configuration of the present invention will be described assuming that the first data lines (DLI1) are also placed on the first substrate (SUB1).

[0138] Dummy patterns (DPT) and first and second data lines (DLI1, DLI2) can be placed on the same layer. Dummy patterns (DPT) and first and second data lines (DLI1, DLI2) can be formed by simultaneously patterning with the same material on the same layer.

[0139] Dummy patterns (DPT) and first and second data lines (DLI1, DLI2) can be placed directly on the first substrate (SUB1). Dummy patterns (DPT) and first and second data lines (DLI1, DLI2) can be placed on the same layer as the light-blocking layer (BML) shown in FIG. 5. Dummy patterns (DPT) and first and second data lines (DLI1, DLI2) can be formed by simultaneously patterning with the same material as the light-blocking layer (BML).

[0140] A buffer layer (BFL) may be disposed on dummy patterns (DPT) and first and second data lines (DLI1, DLI2). The buffer layer (BFL) may be disposed on a first substrate (SUB1) to cover the dummy patterns (DPT) and the first and second data lines (DLI1, DLI2). A first insulating layer (INS1) and a second insulating layer (INS2) may be disposed sequentially on the buffer layer (BFL). The buffer layer (BFL), the first insulating layer (INS1), and the second insulating layer (INS3) may be defined as insulating layers.

[0141] For example, the first substrate (SUB1) to the second insulating layer (INS2) is shown in the cross-sectional view of FIG. 8, and the configurations on the second insulating layer (INS2) are omitted.

[0142] FIGS. 9a and 9b are cross-sectional views along line I-I' shown in FIG. 7 according to another embodiment of the present invention.

[0143] The configurations shown in FIG. 9a and FIG. 9b will be described below, focusing on configurations different from those shown in FIG. 8.

[0144] Referring to FIG. 9a, dummy patterns (DPT) may be placed on a different layer from the first and second data lines (DLI1, DLI2). Dummy patterns (DPT) may be placed directly on the first substrate (SUB1). A buffer layer (BFL) may be placed on the first substrate (SUB1) to cover the dummy patterns (DPT), and a first insulating layer (INS1) may be placed on the buffer layer (BFL).

[0145] The first and second data lines (DLI1, DLI2) may be placed on the first insulating layer (INS1). The second insulating layer (INS2) may be placed on the first insulating layer (INS1) to cover the first and second data lines (DLI1, DLI2).

[0146] The first and second data lines (DLI1, DLI2) may be placed on the same layer as the gate electrode (G) shown in FIG. 5. The first and second data lines (DLI1, DLI2) may be formed by simultaneously patterning with the same material as the gate electrode (G).

[0147] Referring to FIG. 9b, the first and second data lines (DLI1, DLI2) may be placed on a different layer from the dummy patterns (DPT). The first and second data lines (DLI1, DLI2) may be placed directly on the first substrate (SUB1). A buffer layer (BFL) may be placed on the first substrate (SUB1) to cover the first and second data lines (DLI1, DLI2), and a first insulating layer (INS1) may be placed on the buffer layer (BFL).

[0148] Dummy patterns (DPT) can be placed on the first insulating layer (INS1). A second insulating layer (INS2) can be placed on the first insulating layer (INS1) to cover the dummy patterns (DPT).

[0149] Dummy patterns (DPT) can be placed on the same layer as the gate electrode (G) shown in FIG. 5. Dummy patterns (DPT) can be formed by simultaneously patterning with the same material as the gate electrode (G).

[0150] FIG. 10 is a diagram illustrating, in an exemplary manner, the moving state of the first substrate after certain layers are formed on the first substrate illustrated in FIG. 8. FIG. 11a is a diagram illustrating, in an exemplary manner, the layers formed on the first substrate illustrated in FIG. 10 corresponding to the cross-section of line II-II' illustrated in FIG. 8. FIG. 11b is a diagram illustrating the damaged state of the configurations on the first substrate illustrated in FIG. 11a.

[0151] In FIGS. 10, FIGS. 11a, and FIGS. 11b below, configurations on the first substrate (SUB1) will be described assuming that the dummy patterns (DPT) shown in FIG. 8 are absent.

[0152] Referring to FIG. 10 and FIG. 11a, a first-1 data line (DL1-1) and a second-1 data line (DL2-1) are formed on a first substrate (SUB1), and a buffer layer (BFL) may be formed on the first-1 data line (DL1-1) and the second-1 data line (DL2-1). A semiconductor layer (SML) may be formed on the buffer layer (BFL). The semiconductor layer (SML) may be patterned to form the aforementioned source electrode (S), drain electrode (D), and active (A).

[0153] Referring to FIGS. 10, FIGS. 11a, and FIGS. 11b, a first substrate (SUB1) can be transferred to a process chamber for patterning a semiconductor layer (SML). The first substrate (SUB1) can be transferred via transfer rollers (ROL). The first substrate (SUB1) can be transferred from right to left via transfer rollers (ROL).

[0154] When the first substrate (SUB1) is transported, the first-1 data wiring (DL1-1) can be electrically charged by friction between the first substrate (SUB1) and the transport rollers (ROL). The first-1 data wiring (DL1-1) that first comes into contact with the transport rollers (ROL) through the first substrate (SUB1) can be charged first.

[0155] In such cases, the potential difference between the first-1 data line (DL1-1) and the second-1 data line (DL2-1) increases rapidly, and a burnt phenomenon (BNT) may occur due to static electricity. Due to the burnt phenomenon (BNT), parts of the buffer layer (BFL) and the semiconductor layer (SML) on the first-1 data line (DL1-1) and the second-1 data line (DL2-1) may be damaged.

[0156] FIG. 12 is a circuit diagram for a first parasitic capacitor formed by the first-1 data wiring and the second-1 data wiring when there is no dummy pattern in FIG. 7. FIG. 13 is a circuit diagram for first and second parasitic capacitors formed by the dummy pattern, the first-1 data wiring, and the second-1 data wiring.

[0157] Referring to FIG. 12, the first parasitic capacitor (CP1) formed by the first-1 data wiring (DL1-1) and the second-1 data wiring (DL2-1) can have a first capacitance.

[0158] Referring to FIG. 13, when second parasitic capacitors (CP2) are connected in parallel to a first parasitic capacitor (CP1), a composite capacitor (CM) can be formed by the first and second parasitic capacitors (CP1, CP2). That is, a composite capacitor (CM) can be formed between the first-1 data line (DL1-1) and the second-1 data line (DL2-1). The capacitance of the composite capacitor (CM) can have a second capacitance. The second capacitance can be larger than the first capacitance.

[0159] In FIG. 12 and FIG. 13, the amount of charge charged on the first-1 data wiring (DL1-1) may be the same.

[0160] When the amount of charge accumulated is the same, if the capacitor's capacitance is small, the potential difference between the two ends of the capacitor can become relatively large relative to the capacitance. Therefore, if the capacitor's capacitance is small, the amount of charge accumulated can exceed the capacitance, and as a result, the capacitor may be damaged by static electricity.

[0161] Conversely, when the amount of charge is the same, if the capacitor has a large capacitance, the potential difference between the two ends of the capacitor can be relatively smaller relative to the capacitance. Therefore, when the capacitor has a large capacitance, it can sufficiently accommodate the amount of charge, and as a result, the generation of static electricity is reduced, which can prevent the capacitor from being damaged.

[0162] In the first parasitic capacitor (CP1) having a smaller first capacitance, the potential difference between the first-1 data line (DL1-1) and the second-1 data line (DL2-1) can become relatively large due to the amount of charge accumulated on the first-1 data line (DL1-1). Therefore, as described in FIG. 11b, a burnt phenomenon (BNT) may occur due to static electricity, and the components on the first substrate (SUB1) may be damaged.

[0163] However, in an embodiment of the present invention, a composite capacitor (CM) having a larger second capacitance may be formed between the first-1 data line (DL1-1) and the second-1 data line (DL2-1). Accordingly, the potential difference between the first-1 data line (DL1-1) and the second-1 data line (DL2-1) may be relatively reduced. As a result, electrostatic discharge is reduced, preventing burnt phenomena (BNT), and preventing damage to the components on the first substrate (SUB1).

[0164] FIGS. 14 to 17 are drawings illustrating the configuration of dummy patterns according to various embodiments of the present invention.

[0165] For example, FIGS. 14 to 17 are illustrated as plan views corresponding to FIG. 7. Hereinafter, the configurations of the dummy patterns (DPT-1 to DPT-4) illustrated in FIGS. 14 to 17 will be described, focusing on the configurations different from the dummy patterns (DPT) illustrated in FIG. 7. Since the configurations of the first and second data wiring groups (GP1, GP2) are identical to the configurations of the first and second data wiring groups (GP1, GP2) illustrated in FIG. 7, the description is omitted.

[0166] Referring to FIG. 14, dummy patterns (DPT-1) may be placed between the first-1 data line (DL1-1) and the second-1 data line (DL2-1). Each of the dummy patterns (DPT-1) may have a conical shape. The dummy patterns (DPT-1) may be spaced apart from each other and extend parallel to each other. The dummy patterns (DPT-1) may extend parallel to the first-1 data line (DL1-1) and the second-1 data line (DL2-1).

[0167] Unlike in FIG. 7, the extension patterns (EXP) are omitted in FIG. 14. Except for the omission of the extension patterns (EXP), the dummy patterns (DPT-1) may have substantially the same configuration as the dummy patterns (DPT) shown in FIG. 7. The dummy patterns (DPT-1) may not be formed integrally and may be electrically separated from each other.

[0168] Referring to FIG. 15, a dummy pattern (DPT-2) having a polygonal shape may be placed between the first-1 data line (DL1-1) and the second-1 data line (DL2-1). The dummy pattern (DPT-2) may be formed in the shape of a polygonal through electrode.

[0169] The area of ​​the dummy pattern (DPT-2) may be larger than the area of ​​the dummy pattern (DPT) shown in FIG. 7. Therefore, as the capacitance of the second parasitic capacitors (CP2) increases, the generation of electrostatic charge is further reduced, and the burnt phenomenon (BNT) can be further prevented.

[0170] Referring to FIG. 16, a dummy pattern (DPT-3) having a mesh shape may be placed between the first-1 data line (DL1-1) and the second-1 data line (DL2-1). The area of ​​the dummy pattern (DPT-3) may be larger than the area of ​​the dummy pattern (DPT) shown in FIG. 7. Thus, as the capacitance of the second parasitic capacitors (CP2) increases, electrostatic discharge is further reduced, and burnt phenomena (BNT) can be further prevented.

[0171] Referring to FIG. 17, dummy patterns (DPT-4) having a polygonal closed-loop shape may be placed between the first-1 data line (DL1-1) and the second-1 data line (DL2-1). The area of ​​the dummy patterns (DPT-4) may be larger than the area of ​​the dummy pattern (DPT) shown in FIG. 7. Thus, as the capacitance of the second parasitic capacitors (CP2) increases, electrostatic discharge is further reduced, and burnt phenomena (BNT) can be further prevented.

[0172] Although the invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Furthermore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the invention, and all technical spirits within the scope of the following claims and equivalents should be interpreted as being included within the scope of the rights of the present invention. Explanation of the symbols

[0173] DD: Display device DA: Display area F-OT: Fan-out area PX: Pixel GP1,GP2: 1st and 2nd data wiring groups DLI1, DLI2: 1st and 2nd data wiring DL1-1, DL2-1: Data wiring for 1-1 and 2-1 DPT: Dummy pattern DLP1, DLP2: 1st and 2nd dummy wiring patterns

Claims

Claim 1 A display device comprising: a first data wiring group including a plurality of first data wirings disposed in a fan-out area and extending to a display area adjacent to the fan-out area; a second data wiring group including a plurality of second data wirings disposed in the fan-out area and extending to the display area; a plurality of pixels disposed in the display area and connected to the first and second data wirings; and a dummy pattern disposed between the first data wiring group and the second data wiring group in the fan-out area and in a floating state, wherein the dummy pattern is provided in a plurality of numbers and the plurality of dummy patterns are folded and extended at least twice. Claim 2 A display device according to claim 1, wherein the first data lines extend radially from the fan-out area toward the display area, and the second data lines extend radially from the fan-out area toward the display area. Claim 3 In claim 2, the dummy patterns are a display device having a conical shape. Claim 4 In claim 2, the dummy patterns are a display device positioned adjacent to a first-1 data line adjacent to the second data line group among the first data lines and a second-1 data line adjacent to the first data line group among the second data lines. Claim 5 In claim 4, the dummy patterns are a display device extending parallel to the first-1 data line and the second-1 data line. Claim 6 A display device according to claim 4, wherein the dummy patterns include: a first dummy wiring pattern extending parallel to the first-1 data wiring adjacent to the first-1 data wiring; and a second dummy wiring pattern extending by being bent from the end of the first dummy wiring pattern adjacent to the display area and extending parallel to the second-1 data wiring adjacent to the second-1 data wiring. Claim 7 In claim 1, the plurality of dummy patterns are integrally formed in a display device. Claim 8 A display device according to claim 7, further comprising a plurality of extension portions extending from portions of the h-th dummy pattern to portions of the h+1-th dummy pattern, wherein the extension portions are integrally formed with the h-th dummy pattern and the h+1-th dummy pattern, and h is a natural number. Claim 9 In claim 1, the dummy patterns are a display device insulated from surrounding conductors. Claim 10 In claim 1, the dummy patterns are a display device disposed on the same layer as the first and second data lines. Claim 11 A display device according to claim 10, further comprising: a substrate; and an insulating layer disposed on the substrate, wherein the dummy patterns and the first and second data lines are disposed directly on the substrate, and the insulating layer is disposed on the dummy patterns and the first and second data lines. Claim 12 In claim 1, the dummy patterns are a display device disposed on a different layer from the first and second data lines. Claim 13 A display device according to claim 12, further comprising: a substrate; and an insulating layer disposed on the substrate, wherein the dummy patterns are disposed directly on the substrate, the insulating layer is disposed on the dummy patterns, and the first and second data lines are disposed on the insulating layer. Claim 14 In claim 1, the display device extending parallel to each other, spaced apart so as to be electrically separated from one another. Claim 15 In claim 1, the dummy patterns are a display device having a polygonal shape. Claim 16 In claim 1, the dummy patterns are a display device having a mesh shape. Claim 17 In claim 1, the dummy patterns are a display device having a polygonal closed-loop shape. Claim 18 A display device comprising: a first data wiring group including a plurality of first data wirings disposed in a fan-out area and extending to a display area adjacent to the fan-out area; a second data wiring group including a plurality of second data wirings disposed in the fan-out area and extending to the display area; a plurality of pixels disposed in the display area and connected to the first and second data wirings; and a dummy pattern disposed between the first data wiring group and the second data wiring group in the fan-out area, wherein the dummy pattern extends parallel to a first-1 data wiring adjacent to the second data wiring group among the first data wirings and a second-1 data wiring adjacent to the first data wiring group among the second data wirings, wherein the dummy pattern is provided in a plurality, and the plurality of dummy patterns are extended by being folded at least twice. Claim 19 A display device according to claim 18, wherein the dummy patterns include: a first dummy wiring pattern extending parallel to the first-1 data wiring adjacent to the first-1 data wiring; and a second dummy wiring pattern extending by being bent from the end of the first dummy wiring pattern adjacent to the display area and extending parallel to the second-1 data wiring adjacent to the second-1 data wiring. Claim 20 A display device comprising: a first data wiring group including a plurality of first data wirings disposed in a fan-out area and extending to a display area adjacent to the fan-out area; a second data wiring group including a plurality of second data wirings disposed in the fan-out area and extending to the display area; a plurality of pixels disposed in the display area and connected to the first and second data wirings; and a dummy pattern disposed between the first data wiring group and the second data wiring group in the fan-out area, wherein the dummy pattern is insulated from surrounding conductors and is not subjected to voltage, wherein the dummy pattern is provided in a plurality of numbers, and the plurality of dummy patterns are folded and extended at least twice.

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