Three-dimensional memory device with backside interconnect structures

Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In one example, the 3D memory device comprises a substrate, a memory stack including interleaved conductive layers and dielectric layers on the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer on and in contact with the plurality of channel structures, a plurality of source contacts on the memory stack and in contact with the semiconductor layer, a plurality of contacts penetrating the semiconductor layer, and a back interconnect layer on the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below the source line mesh in contact with it. A first set of the plurality of contacts is distributed below the source line mesh in contact with it.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims the benefit of priority rights to International Application No. PCT / CN2020 / 084600, filed April 14, 2020, with the title of invention "THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT", and International Application No. PCT / CN2020 / 084603, filed April 14, 2020, with the title of invention "METHOD FOR FORMING THREE-DIMENSIONAL MEMORY DEVICE WITH BACKSIDE SOURCE CONTACT", both of which are incorporated herein by reference in their entirety.

[0003] The embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for manufacturing the same. Background Technology

[0004] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature sizes of memory cells approach a lower limit, planar process and manufacturing techniques become difficult and costly. Consequently, memory density for planar memory cells is approaching an upper limit.

[0005] A 3D memory architecture can overcome density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

[0006] Examples of 3D memory devices and methods for forming the same are disclosed in this specification.

[0007] In one example, a 3D memory device comprises a substrate, a memory stack including interleaved conductive layers and dielectric layers on the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer on and in contact with the plurality of channel structures, a plurality of source contacts on the memory stack and in contact with the semiconductor layer, a plurality of contacts penetrating the semiconductor layer, and a back interconnect layer on the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below the source line mesh in contact with it. A first set of the plurality of contacts is distributed below the source line mesh in contact with it.

[0008] In another example, a 3D memory device comprises a substrate, a memory stack including interleaved conductive layers and dielectric layers on the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer on and in contact with the plurality of channel structures, a plurality of source contacts in contact with the semiconductor layer, and a back interconnect layer on the semiconductor layer including a source line mesh in a plan view. Each of the channel structures is located below and laterally aligned with one of the source contacts. The source line mesh is located above and in contact with each of the source contacts.

[0009] In another example, a method for forming a 3D memory device is disclosed. Peripheral circuits are formed on a first substrate. A plurality of channel structures are formed on the front surface of a second substrate, each extending vertically through a memory stack. The first substrate and the second substrate are bonded face-to-face so that the channel structures are placed over the peripheral circuits. The second substrate is thinned. A plurality of contacts penetrating the thinned second substrate and a plurality of source contacts in contact with the thinned second substrate are formed. A source line mesh is formed on the rear surface of the thinned second substrate such that the source line mesh is placed over the plurality of source contacts and a first set of contacts and contacts therewith. Brief explanation of the drawing

[0010] The accompanying drawings included herein and forming part of this specification illustrate embodiments of the present disclosure and, additionally, together with the description, explain the principles of the present disclosure and serve to enable a person skilled in the art to create and use the present disclosure. FIG. 1 illustrates a cross-sectional plan view of an exemplary 3D memory device having a central staircase region according to some embodiments of the present disclosure. FIG. 2a illustrates a cross-sectional plan view of an exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIG. 2b illustrates a cross-sectional plan view of another exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIG. 2c illustrates a cross-sectional plan view of another exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIG. 3 illustrates a cross-sectional side view of an exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIG. 4 illustrates a cross-sectional plan view of another exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIG. 5 illustrates a cross-sectional side view of another exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIGS. 6a through 6d illustrate a manufacturing process for forming an exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIG. 7 illustrates a flowchart of a method for forming an exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. Embodiments of the present disclosure will be described with reference to the accompanying drawings. Specific details for implementing the invention

[0011] Specific configurations and arrangements are discussed, but it should be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. It will also be apparent to a person skilled in the art that this disclosure may be employed in various other applications.

[0012] It should be noted that references to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., in this specification indicate that while the described embodiment may include a specific feature, structure, or characteristic, not all embodiments are required to include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in relation to an embodiment, performing that feature, structure, or characteristic in relation to other embodiments, whether or not explicitly described, would be within the knowledge of a person skilled in the art.

[0013] Generally, terms may be understood at least in part from their use in context. For example, depending at least in part on context, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on context, terms such as “one,” “one,” or “the” may also be understood to convey a singular usage or a plural usage. Furthermore, it should be understood that the term “based on” is not intended to convey an exclusive set of factors, but instead, depending at least in part on context, may allow for the existence of additional factors not explicitly described.

[0014] It should be readily understood that the meanings of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest possible way so that “on” means not only “directly on” something but also “on” something having an intermediate feature or layer between them, and “over” or “over” means not only “on” or “over” something but also “on” or “over” something without any intermediate feature or layer between them (i.e., directly on something).

[0015] Additionally, spatially relative terms such as “bottom,” “below,” “lower,” “top,” and “upper” may be used herein for convenience of description to explain the relationship between one element or feature and another element(s) or feature(s), as exemplified in the drawings. Spatially relative terms are intended to include different orientations of the device during use or operation, in addition to the orientations depicted in the drawings. The device may be oriented differently (it may be rotated 90 degrees or be in other orientations), and spatially relative descriptors used herein may be interpreted accordingly.

[0016] As used herein, the term “substrate” refers to a material upon which subsequent material layers are added. The substrate itself may be patterned. Materials added to the top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

[0017] As used herein, the term “layer” refers to a portion of material comprising an area having thickness. A layer may extend over the entirety of a structure placed below or above, or may have an area smaller than the area of ​​the structure placed below or above. Additionally, a layer may be an area of ​​a homogeneous or heterogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or between any pair of horizontal planes on the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include a plurality of layers. For example, the interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect access (VIA) contacts are formed) and one or more dielectric layers.

[0018] As used herein, the term “nominal” refers to a desired or target value of a characteristic or parameter of a component or process behavior set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” refers to a given quantity of value that may vary based on a specific technical node associated with the target semiconductor device. Based on a specific technical node, the term “about” may refer to a given quantity of value that varies within, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, the term “3D memory device” refers to a semiconductor device having vertically oriented strings of memory cell transistors on a laterally oriented substrate (referred to herein as “memory strings,” such as NAND memory strings) such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term “vertical / vertically” means nominally perpendicular to the lateral surface of the substrate.

[0020] In some 3D memory devices, peripheral circuits and memory arrays are stacked to reduce wafer area and increase memory cell density. For example, direct bonding techniques have been proposed to manufacture some 3D NAND memory devices (e.g., having 96 or more layers) by joining peripheral devices and memory arrays face-to-face on different substrates. Then, the memory array substrate is thinned to form through-silicon vertical interconnect access (VIA), known as "TSV," which penetrates to pad-outs and vertical interconnections on the back of the thinned substrate having wire bonding pads. However, because only wire bonding pads and TSVs are formed on the back of the thinned substrate (i.e., the top surface of the bonded 3D memory device), a significant amount of area on the back of the thinned substrate is wasted.

[0021] Various embodiments according to the present disclosure provide 3D memory devices having backside interconnect structures to better utilize the backside area and optimize metal routing. Some or all of the source lines, source select gate (SSG) lines, and power lines may be routed as "backside interconnect structures" from the front side of the memory array substrate (i.e., the middle of the bonded 3D memory device) to the back side of the memory array substrate (i.e., the top surface of the bonded 3D memory device). In some embodiments, the backside source lines allow source contacts to also be formed on the back side of the memory array substrate, which can avoid leakage current and parasitic capacitance between the source contacts and word lines on the front side through the memory stack. Various back interconnect structures can be arranged in different layouts, such as meshes (e.g., comb shapes) or parallel straight lines, to further improve the electrical performance of 3D memory devices by optimizing metal routings and reducing overall resistance based on different memory array structures.

[0022] FIG. 1 illustrates a cross-sectional plan view of an exemplary 3D memory device (100) having a central stepped region according to some embodiments of the present disclosure. As illustrated in FIG. 1, in the plan view, the memory stack of the 3D memory device (100) may include two core array regions (106A and 106B) having channel structures (110) therein and a stepped region (104) between the core array regions (106A and 106B) in a first lateral direction. Note that the x-axis and y-axis are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. According to some embodiments, the 3D memory device (100) includes a central staircase area (104) that laterally separates the memory stack into two parts in the x-direction (e.g., word line direction): a first core array area (106A) and a second core array area (106B)—each of which includes an array of channel structures (110).

[0023] According to some embodiments, the 3D memory device (100) also includes insulating structures (108) (e.g., gate line slits (GLS)) parallel in the y-direction (e.g., bit line direction), and each of the parallel insulating structures (108) extends laterally in the x-direction to separate core array regions (106A and 106) and arrays of channel structures (110) within them into blocks (102). The 3D memory device (100) may further include drain select gate (DSG) cuts (112) (sometimes known as top select gate (TSG) cuts) parallel in the y-direction in the blocks (102) to further separate the blocks (102) into fingers. It is understood that the layout of the step regions and core array regions is not limited to the example of FIG. 1 and may include any other suitable layouts, such as having lateral step regions on the edges of the memory stack in other examples.

[0024] A cross-section of the 3D memory device (100) is located on the front surface of the 3D memory device (100) where channel structures (110) are formed. In some embodiments, the 3D memory device (100) is inverted and bonded to another semiconductor device, such as a peripheral device having peripheral circuits to facilitate the operation of the 3D memory device (100). Thus, the rear surface of the 3D memory device (100) can become the top surface of the bonded device that can be used for pad-out. As described in detail below, in addition to the bonding pads, the area on the rear surface of the 3D memory device (100) (i.e., the top surface of the bonded device) can be utilized to form various rear interconnect structures in various layouts to optimize metal routing and reduce overall resistance, as well as to reduce leakage current and parasitic capacitance on the front surface of the 3D memory device (100).

[0025] FIG. 2a illustrates a cross-sectional plan view of an exemplary 3D memory device (200) having rear interconnect structures according to some embodiments of the present disclosure. The 3D memory device (200) may be an example of a 3D memory device (100) after flip-chip bonding, and FIG. 2a illustrates an example of a rear side of a 3D memory device (100) after flip-chip bonding. As illustrated in FIG. 2a, according to some embodiments, in the plan view, the memory stack of the 3D memory device (200) comprises two core array regions (206A and 206B) having channel structures (not illustrated) therein and a stepped region (204) between the core array regions (206A and 206B) in the x-direction (e.g., word line direction). In some embodiments, in the plan view, the 3D memory device (200) additionally includes a peripheral region (208) outside the core array region (206A or 206B) of the memory stack. In the y-direction (e.g., bit line direction), FIG. 2a illustrates rear interconnect structures within one block (202) of the 3D memory device (200), which may be repeated any appropriate number of times in a plurality of blocks.

[0026] In some embodiments, the 3D memory device (200) in the plan view includes a source line mesh (210). As illustrated in FIG. 2a, according to some embodiments, the source line mesh (210) has a comb-like shape. For example, the source line mesh (210) may include a shaft source line (214) extending laterally in the y-direction (e.g., bit line direction) in one of the core array regions (206A and 206B). The source line mesh (210) may also include a plurality of parallel tooth source lines (212), each of which extends laterally from the shaft source line (214) in one core array region (206A) to another core array region (206B) through a step region (204) in the x-direction (e.g., word line direction). In some embodiments, the source line mesh (210) extends in the x-direction across the core array regions (206A and 206B) and the step region (204), for example, the core array regions (206A and 206B) and the step region (204), but does not extend in the surrounding region (208).

[0027] The 3D memory device (200) may also include back source contacts (216) in the core array regions (206A and 206B) (e.g., in the form of VIA contacts), but not in the step region (204) or the peripheral region (208). For example, the back source contacts (216) may be evenly distributed in the core array region (206A or 206B). In some embodiments, the back source contacts (216) are distributed below and in contact with the source line mesh (210). For example, the back source contacts (216) may be evenly distributed below and in contact with the source line mesh (210) in the core array region (206A or 206B). That is, the distances between adjacent back source contacts (216) (e.g. in the x-direction and / or y-direction) are the same in the core array region (206A or 206B). In some embodiments, the rear source contacts (216) are distributed in contact with the toothed source lines (212) of the source line mesh (210) rather than the shaft source line (214) of the source line mesh (210). It is understood that in some examples, the rear source contacts (216), which are in the form of VIA contacts, may be replaced by one or more source wall-shaped contacts, i.e., interconnect lines.

[0028] The 3D memory device (200) may further include a plurality of sets of contacts (218, 226 and 230), such as through-silicon contacts (TSCs). In some embodiments, the contacts (218) are distributed in contact with the source line mesh (210) in parts of the step region (204) and core array regions (206A and 206B). According to some embodiments, since the contacts (218) may be TSCs extending through a silicon substrate, the contacts (218) are distributed in contact with the peripheral part of the source line mesh (210) (including parts in the step region (204)) to avoid overlapping with channel structures in the central part of the source line mesh (210) in the core array regions (206A and 206B). For example, as illustrated in FIG. 2a, contacts (218) may be distributed in contact with the outermost tooth source lines (212) and shaft source line (214) of the source line mesh (210) in the core array regions (206A and 206B). Contacts (218) may also be distributed in contact with the respective tooth source line (212) of the source line mesh (210) in the step region (204).

[0029] As described in detail below, each rear source contact (216) may be electrically connected to a common source of NAND memory strings in block (202) (e.g., array common source (ASC)), and the source line mesh (210) electrically connects each rear source contact (216) and, in turn, electrically connects to a common source of NAND memory strings in block (202). Similarly, each contact (218) may be electrically connected to peripheral circuits of the 3D memory device (200), and the source line mesh (210) electrically connects each contact (218) and, in turn, electrically connects to peripheral circuits of the 3D memory device (200). As a result, peripheral circuits are electrically connected to a common source of NAND memory strings in block (202) and can control and / or detect the common source through metal routing including contacts (218), a source line mesh (210), and rear source contacts (216) on the rear surface of the 3D memory device (200). The layout of the contacts (218), the source line mesh (210), and the rear source contacts (216), for example, the comb-like shape of the source line mesh (210) and a number of distributed contacts (218) and rear source contacts (216), can reduce the overall resistance of the metal routing.

[0030] In some embodiments, the 3D memory device (200) includes another rear interconnect structure—a power line mesh (220) in the plan view. As illustrated in FIG. 2a, according to some embodiments, the power line mesh (220) has a comb-like shape. For example, the power line mesh (220) may include a shaft power line (224) extending laterally in the y-direction (e.g., bit line direction) from the peripheral region (208). The power line mesh (220) may also include a plurality of parallel toothed power lines (222), each of which extends laterally from the shaft power line (224) in the peripheral region (208) in the x-direction (e.g., word line direction) through one core array region (206B) and a step region (204) to another core array region (206A). In some embodiments, the power line mesh (220) extends in the x-direction from the periphery area (208) across the core array areas (206A and 206B) and the step area (204), for example, in the periphery area (208), the core array areas (206A and 206B) and the step area (204). In some embodiments, the toothed power lines (222) are interleaved with the toothed source lines (212) in the y-direction.

[0031] In some embodiments, the contacts (226) are distributed in contact with the power line mesh (220) in the step region (204) and the peripheral region (208), but not in the core array region (206A and 206B). According to some embodiments, since the contacts (226) may be TSCs extending through the silicon substrate, the contacts (226) are not in the core array region (206A and 206B) to avoid overlapping with the channel structures in the core array region (206A and 206B). For example, as shown in FIG. 2a, the contacts (226) may be distributed in contact with the shaft power line (224) in the peripheral region (208) and parts of the toothed power lines (222) in the step region (204). In some examples, it is understood that the contacts (226) may be distributed in either the surrounding area (208) or the step area (204), but not in both. That is, the contacts (226) may be distributed in at least one of the step area (204) or the surrounding area (208) outside the memory array in the plan view.

[0032] Each contact (226) can be electrically connected to the power lines of peripheral circuits of the 3D memory device (200), and the power line mesh (220) electrically connects each contact (226) and, in turn, is electrically connected to the power lines of peripheral circuits of the 3D memory device (200). A power supply can be electrically connected to the power line mesh (220) through bonding pads (not shown) to provide power to the 3D memory device (200) through metal routing including the contacts (226) and the power line mesh (220) on the rear surface of the 3D memory device (200). The bonding pads may be part of rear interconnect structures and can be electrically connected to the power line mesh (220) through the contacts (226). The layout of the contacts (226) and the power line mesh (220), for example, the comb-like shape of the power line mesh (220) and the number of distributed contacts (226), can reduce the overall resistance of the metal routing.

[0033] In some embodiments, the 3D memory device (200) includes another rear interconnect structure—multiple SSG lines (228) in the plan view. Each SSG line (228) may extend in the x-direction (e.g., word line direction) across two core array regions (206A and 206B) and a step region (204). In some embodiments, the SSG lines (228) are evenly distributed parallel in the y-direction (e.g., bit line direction) in the plan view. The SSG lines (228), toothed power lines (222), and toothed source lines (212) may be parallel. As shown in FIG. 2a, each SSG line (228) may be sandwiched between two toothed power lines (222) in the y-direction. It is understood that the arrangement of the SSG lines (228), tooth power lines (222), and tooth source lines (212) may vary in other examples. For example, the SSG lines (228), tooth power lines (222), and tooth source lines (212) may be interleaved with each other in the y-direction.

[0034] In some embodiments, in the plan view, the contacts (230) are distributed in contact with the SSG lines (228) below the core array regions (206A and 206B), but not in the step region (204) and the surrounding region (208). For example, as shown in FIG. 2a, at least one contact (230) in the core array region (206A) and at least one contact (230) in the core array region (206B) are below and in contact with the respective SSG line (228). The SSG in the memory stack of the 3D memory device (200) may be cut off at the step region (204) to become two separate parts in each of the core array regions (206A and 206B). Each contact (230) may be electrically connected to one part of the SSG of the 3D memory device (200) in its respective core array region (206A or 206B). By extending over the step area (204) between the two core array areas (206A and 206B) in the x-direction and electrically connecting the contacts (230) in each core array area (206A or 206B), the SSG lines (228) can thus electrically connect two separate parts of the SSG in the core array areas (206A and 206B). That is, the two separate parts of the SSG in the core array areas (206A and 206B) can be "bridged" across the step area (204) by metal routing including the SSG lines (228) and contacts (230) on the back of the 3D memory device (200). The layout of contacts (230) and SSG lines (228), for example, a plurality of parallel SSG lines (228) and a plurality of distributed contacts (230), can reduce the overall resistance of the metal routing.

[0035] It is understood that rear interconnect structures are not limited to the example of FIG. 2a and may include any other suitable layouts depending on the design of the 3D memory device, such as specifications of electrical performance (e.g., voltage and resistance). It is also understood that additional rear interconnect structures may be placed on the same surface as the source line mesh (210), power line mesh (220), and SSG lines (228) as shown in FIG. 2a. For example, bonding pads (not shown) for wire bonding may also be placed on the rear surface of the 3D memory device (200), as in the peripheral area (208). It is further understood that in other examples, one or more rear interconnect structures shown in FIG. 2a may not be placed on the rear surface of the 3D memory devices and may be replaced, for example, by corresponding front interconnect structures placed on the front surface of the 3D memory devices.

[0036] FIG. 2b illustrates a cross-sectional plan view of another exemplary 3D memory device (201) having rear interconnect structures according to some embodiments of the present disclosure. The 3D memory device (201) may be substantially identical to the 3D memory device (200) of FIG. 2a except that the 3D memory device (201) does not include the SSG lines (228) and contacts (230) of FIG. 2a. FIG. 2c illustrates a cross-sectional plan view of yet another exemplary 3D memory device (203) having rear interconnect structures according to some embodiments of the present disclosure. The 3D memory device (203) may be substantially identical to the 3D memory device (200) of FIG. 2a except that the 3D memory device (203) does not include the SSG lines (228), power line mesh (220), and contacts (230 and 226) of FIG. 2a. Furthermore, by removing the power line mesh (220), the source line mesh (210) in the 3D memory device (203) may have two parallel shaft source lines (214) in the core array regions (206A and 206B), respectively.

[0037] FIG. 3 illustrates a cross-sectional side view of an exemplary 3D memory device (300) having rear interconnect structures according to some embodiments of the present disclosure. The 3D memory device (300) may be an example of the 3D memory devices (200, 201, and 203) of FIG. 2a through 2c may illustrate plan views of cross-sections on the AA plane of the 3D memory device (300) of FIG. 3, i.e., on the rear side of the 3D memory device (300). In some embodiments, the 3D memory device (300) is a bonded chip comprising a first semiconductor structure (302) and a second semiconductor structure (304) stacked on the first semiconductor structure (302). According to some embodiments, the first and second semiconductor structures (302 and 304) are bonded at a bonding interface (306) between them. As illustrated in FIG. 3, the first semiconductor structure (302) may include a substrate (301) that may include silicon (e.g., single-crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0038] The first semiconductor structure (302) of the 3D memory device (300) may include peripheral circuits (308) on the substrate (301). Note that the x-axis, y-axis, and z-axis are included in FIG. 3 to illustrate the spatial relationships of the components in the 3D memory device (300). The substrate (301) includes two lateral surfaces extending laterally in the xy plane: a front surface on the front of the wafer and a back surface on the back facing the front of the wafer. The x-direction and the y-direction are two orthogonal directions in the wafer plane: the x-direction is the word line direction, and the y-direction is the bit line direction. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, whether one component (e.g., a layer or device) of a semiconductor device (e.g., a 3D memory device (300)) is "on," "above," or "below" another component (e.g., a layer or device) is determined with respect to the substrate of the semiconductor device (e.g., substrate (301)) in the z-direction (a vertical direction perpendicular to the xy plane) when the substrate is positioned at the lowest plane of the semiconductor device in the z-direction. The same concept for describing spatial relationships applies throughout this disclosure.

[0039] In some embodiments, peripheral circuits (308) are configured to control and sense the 3D memory device (300). Peripheral circuits (308) may be any suitable digital, analog, and / or mixed-signal control and sense circuits used to facilitate the operation of the 3D memory device (300), including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuits (308) may include transistors formed "on" the substrate (301), wherein all or part of the transistors are formed within the substrate (301) (e.g., below the top surface of the substrate (301)) and / or directly on the substrate (301). Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source regions and drain regions of transistors) may also be formed within the substrate (301). According to some embodiments, the transistors are high-speed using advanced logic processes (e.g., technology nodes such as 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, etc.). In some examples, it is understood that the peripheral circuit (308) may additionally include any other circuits compatible with advanced logic processes, such as logic circuits like processors and PLDs (programmable logic devices), or memory circuits like SRAM (static random-access memory). In some embodiments, the peripheral circuit (308) includes one or more power lines that provide power (e.g., voltages) to the peripheral circuit (308).

[0040] In some embodiments, the first semiconductor structure (302) of the 3D memory device (300) further comprises an interconnect layer (not shown) on the peripheral circuits (308) to transmit electrical signals to and from the peripheral circuits (308). The interconnect layer may comprise a plurality of interconnects (also referred to herein as “contacts”) including lateral interconnect lines and VIA contacts. As used herein, the term “interconnects” may broadly include any suitable types of interconnects, such as MEOL (middle-end-of-line) interconnects and BEOL (back-end-of-line) interconnects. The interconnect layer may further comprise one or more interlayer dielectric (ILD) layers (also known as "intermetal dielectric (IMD) layers") in which interconnect lines and VIA contacts can be formed. That is, the interconnect layer may comprise interconnect lines and VIA contacts within a plurality of ILD layers. The interconnect lines and VIA contacts in the interconnect layer may comprise conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer may comprise dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

[0041] As illustrated in FIG. 3, the first semiconductor structure (302) of the 3D memory device (300) may further include a bonding layer (310) at the bonding interface (306) and on the interconnect layer and peripheral circuits (308). The bonding layer (310) may include a plurality of bonding contacts (311) and dielectrics that electrically isolate the bonding contacts (311). The bonding contacts (311) may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer (310) may be formed of dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts (311) and the surrounding dielectrics within the bonding layer (310) may be used for hybrid bonding.

[0042] Similarly, as illustrated in FIG. 3, the second semiconductor structure (304) of the 3D memory device (300) may also include a bonding layer (312) at the bonding interface (306) and on the bonding layer (310) of the first semiconductor structure (302). The bonding layer (312) may include a plurality of bonding contacts (313) and dielectrics that electrically isolate the bonding contacts (313). The bonding contacts (313) may include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer (312) may be formed of dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts (313) within the bonding layer (312) and the surrounding dielectrics may be used for hybrid bonding. According to some embodiments, the bonding contacts (313) are in contact with the bonding contacts (311) at the bonding interface (306).

[0043] As described in detail below, the second semiconductor structure (304) can be bonded to the top of the first semiconductor structure (302) in a face-to-face manner at the bonding interface (306). In some embodiments, the bonding interface (306) is positioned between the bonding layers (310 and 312) as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (forming a bond between surfaces without using intermediate layers such as solder or adhesives) and can simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface (306) is the place where the bonding layers (312 and 310) meet and are bonded. Actually, the bonding interface (306) may be a layer having a specific thickness including the upper surface of the bonding layer (310) of the first semiconductor structure (302) and the lower surface of the bonding layer (312) of the second semiconductor structure (304).

[0044] In some embodiments, the second semiconductor structure (304) of the 3D memory device (300) further comprises an interconnect layer (not shown) on the bonding layer (312) to transmit electrical signals. The interconnect layer may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may further comprise one or more ILD layers on which interconnect lines and VIA contacts may be formed. The interconnect lines and VIA contacts in the interconnect layer may comprise conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer may comprise dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0045] In some embodiments, the 3D memory device (100) is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As illustrated in FIG. 3, a second semiconductor structure (304) of the 3D memory device (300) may include an array of channel structures (324) that function as an array of NAND memory strings. As illustrated in FIG. 3, each channel structure (324) may extend vertically through a plurality of pairs each comprising a conductive layer (316) and a dielectric layer (318). The interleaved conductive layers (316) and dielectric layers (318) are part of a memory stack (314). The number of pairs of conductive layers (316) and dielectric layers (318) within the memory stack (314) (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells within the 3D memory device (300). It is understood that in some examples, the memory stack (314) may have a multi-deck architecture (not shown) comprising multiple memory decks stacked on top of each other. The number of pairs of conductive layers (316) and dielectric layers (318) within each memory deck may be the same or different.

[0046] A memory stack (314) may include a plurality of interleaved conductive layers (316) and dielectric layers (318). The conductive layers (316) and dielectric layers (318) within the memory stack (314) may alternate in a vertical direction. That is, except for those at the top or bottom of the memory stack (314), each conductive layer (316) may be adjacent to two dielectric layers (318) on both sides, and each dielectric layer (318) may be adjacent to two conductive layers (316) on both sides. The conductive layers (316) may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each conductive layer (316) may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer (316) extends laterally as a word line and may end at one or more stepped structures of the memory stack (314). In some embodiments, the top conductive layer (316) functions as an SSG for controlling the source of the NAND memory string. The dielectric layers (318) may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0047] As illustrated in FIG. 3, the second semiconductor structure (304) of the 3D memory device (300) may also include a first semiconductor layer (320) on the memory stack (314) and a second semiconductor layer (322) on the first semiconductor layer (320) and in contact with it. The types of dopants within each semiconductor layer (320 and 322) may vary in different examples. The semiconductor layers (320 and 322) may be shown as a single semiconductor layer when the semiconductor layers (320 and 322) have the same type of dopants. It is understood that the number of semiconductor layers may vary in other examples and is not limited to the example illustrated in FIG. 3.

[0048] In some embodiments, each channel structure (324) comprises a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel (328)) and a composite dielectric layer (e.g., as a memory film (326)). In some embodiments, the semiconductor channel (328) comprises silicon such as amorphous silicon, polysilicon, or single-crystal silicon. In some embodiments, the memory film (326) is a composite layer comprising a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of the channel structure (324) may be partially or completely filled with dielectric materials such as silicon oxide and / or a capping layer comprising an air gap. The channel structure (324) may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the capping layer, semiconductor channel (328), tunneling layer, storage layer, and blocking layer of the memory film (326) are arranged radially in this order from the center of the column toward the outer surface. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may comprise silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, the memory film (326) may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0049] In some embodiments, the channel structure (324) further comprises a channel plug (329) at the bottom portion (e.g., at the bottom end) of the channel structure (324). As used herein, when the substrate (301) is positioned on the bottom plane of the 3D memory device (300), the “upper end” of the component (e.g., channel structure (324)) is the end further from the substrate (301) in the z-direction, and the “lower end” of the component (e.g., channel structure (324)) is the end closer to the substrate (301) in the z-direction. The channel plug (329) may comprise semiconductor materials (e.g., polysilicon). In some embodiments, the channel plug (329) functions as a drain of the NAND memory string.

[0050] As illustrated in FIG. 3, each channel structure (324) may extend vertically through the interleaved conductive layers (316), dielectric layers (318), and first semiconductor layer (320) of the memory stack (314). In some embodiments, the first semiconductor layer (320) surrounds a portion of the channel structure (324) and contacts a semiconductor channel (328) comprising polysilicon. That is, according to some embodiments, a memory film (326) is separated from a portion of the channel structure (324) adjacent to the first semiconductor layer (320) to expose the semiconductor channel (328) to contact the surrounding first semiconductor layer (320). In some embodiments, each channel structure (324) may extend further vertically into a second semiconductor layer (322). It is understood that the structure of the upper part of the channel structure (324) and its relative position to the semiconductor layers (320 and 322) are not limited to the example of FIG. 3 and may vary in other examples.

[0051] As illustrated in FIG. 3, the second semiconductor structure (304) of the 3D memory device (300) may additionally include insulating structures (330) that extend vertically through the interleaved conductive layers (316) and dielectric layers (318) of the memory stack (314), respectively. Each insulating structure (330) may also extend laterally to separate the channel structures (324) into a plurality of blocks. That is, the memory stack (314) may be divided into a plurality of memory blocks by the insulating structures (330), so that an array of channel structures (324) may be separated into each memory block. According to some embodiments, unlike the slit structures in the conventional 3D NAND memory devices described above, which include front ACS contacts, the insulating structure (330) does not contain any contacts therein (i.e., does not function as source contacts) and thus does not introduce parasitic capacitance and leakage current into the conductive layers (316) (including word lines). In some embodiments, each insulating structure (330) includes an opening (e.g., a slit) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure (330) may be filled with silicon oxide.

[0052] Instead of having front source contacts, the 3D memory device (300) may include rear source contacts (332) that are on the memory stack (314) and in contact with the second semiconductor layer (322). The rear source contact (332) may be an example of the rear source contact (216) of FIGS. 2a through 2c. The source contact (332) and the memory stack (314) (and the insulating structure (330) through it) may be placed on opposite sides of the semiconductor layer (322) (thinned substrate) and thus may be viewed as a "rear" source contact. In some embodiments, the source contact (332) extends further into the second semiconductor layer (322) and is electrically connected to the semiconductor channel (328) of the channel structure (324) through the semiconductor layers (320 and 322). It is understood that the depth to which the source contact (332) extends into the second semiconductor layer (322) may vary in different examples. In some embodiments where the second semiconductor layer (322) is an N-well, the source contact (332) is also known as a back "N-well pick up". The source contacts (332) may include any suitable types of contacts. In some embodiments, the source contacts (332) include a VIA contact (e.g., as the back source contact (216) of FIGS. 2a through 2c). In some embodiments, the source contacts (332) include a wall-shaped contact extending laterally. The source contact (332) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0053] As illustrated in FIG. 3, the 3D memory device (300) may further include a BEOL back interconnect layer (333) that is on and contacts a source contact (332) for pad-out, for example, to transmit electrical signals between the 3D memory device (300) and external circuits. The back interconnect layer (333) may also include examples of back interconnect structures previously described in FIG. 2a through 2c. In some embodiments, the back interconnect layer (333) includes one or more ILD layers (334) on the second semiconductor layer (322) and a redistribution layer (336) on the ILD layers (334). According to some embodiments, the upper end of the source contact (332) is coplanar with the upper surface of the ILD layers (334) and the lower surface of the redistribution layer (336), and the source contact (332) extends vertically into the second semiconductor layer (322) through the ILD layers (334). The ILD layers (334) in the back interconnect layer (333) may comprise dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0054] The redistribution layer (336) in the rear interconnect layer (333) may comprise conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. In one example, the redistribution layer (336) comprises Al. It is understood that, although not illustrated in FIG. 3, the redistribution layer (336) may be patterned to form various types of rear interconnect structures described herein, such as the source line mesh (210), power line mesh (220), and SSG lines (228) of FIG. 2a. In one example, source contacts (332) may be located below and in contact with the source line mesh (210) in the redistribution layer (336). In some embodiments, the rear interconnect layer (333) further comprises a passivation layer (338) as an outermost layer for passivation and protection of the 3D memory device (300). A portion of the redistribution layer (336) may be exposed from the passivation layer (338) as bonding pads (340). That is, the rear interconnect layer (333) of the 3D memory device (300) may also include bonding pads (340) for wire bonding and / or bonding with an interposer. Although not illustrated in FIGS. 2a through 2c, the bonding pads (340) may also be part of the rear interconnect structures in some examples.

[0055] In some embodiments, the second semiconductor structure (304) of the 3D memory device (300) further comprises contacts (342 and 344) penetrating the second semiconductor layer (322). According to some embodiments, since the second semiconductor layer (322) may be a thinned substrate, the contacts (342 and 344) are TSCs. The contact (342) may be an example of the contact (218 or 226) of FIG. 2a and FIG. 2b. In some embodiments, the contact (342) extends through the second semiconductor layer (322) and ILD layers (334) to contact a redistribution layer (336) (e.g., including a source line mesh (210) and a power line mesh (220)). For example, the source of the NAND memory string may be electrically connected to a contact (342) (e.g., as a contact (218) in FIGS. 2a to 2c) through semiconductor layers (320 and 322), a source contact (332), and a redistribution layer (336) (e.g., having a source line mesh (210) in FIGS. 2a to 2c). That is, the contacts (342) (as contacts (218 or 226)) may be located below and in contact with the source line mesh (210) or power line mesh (220), respectively, in the redistribution layer (336). Although not illustrated in FIG. 3, as an example of the contact (230) of FIG. 2a, the 3D memory device (300) may also include contacts (e.g., an example of the contacts (230) of FIG. 2a) that extend further into the memory stack (314) to contact one of the conductive layers (316) of the memory stack (314) (i.e., SSG). (e.g., as the contacts (230) of FIG. 2a) the contacts may be located below the SSG lines (228) in the redistribution layer (336) and may contact it.

[0056] In some embodiments, the contact (344) extends through the second semiconductor layer (322) and ILD layers (334) to contact the bonding pad (340). Each of the contacts (342 and 344) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least the contact (344) further includes a spacer (e.g., a dielectric layer) to electrically insulate the contact (344) from the second semiconductor layer (322).

[0057] In some embodiments, the 3D memory device (300) further comprises peripheral contacts (346 and 348) that extend vertically, respectively, to a second semiconductor layer (322) outside the memory stack (314). Each peripheral contact (346 or 348) may have a depth greater than the depth of the memory stack (314) so ​​as to extend vertically from the bonding layer (312) to the second semiconductor layer (322) in a peripheral area corresponding to, for example, the peripheral area (208) and the step area (204) of FIGS. 2a through 2c or the peripheral area of ​​the core array regions (206A and 206B) where the contacts (218) are placed. In some embodiments, the peripheral contact (346) is below and contacts the contact (342) so that the source line mesh (210) or power line mesh (220) is electrically connected to the peripheral circuit (308) within the first semiconductor structure (302). In one example, the source of the NAND memory string may be electrically connected to a part of the peripheral circuit (308) to control / detect the source of the NAND memory string through a redistribution layer (336) (e.g., source line mesh (210)), a contact (342) (e.g., as contact (218)), and a peripheral contact (346). In another example, the power may be electrically connected to the power line of the peripheral circuit (308) to provide power to the 3D memory device (300) through a redistribution layer (336) (e.g., power line mesh (220)), a contact (342) (e.g., as contact (226)), and a peripheral contact (346). In some embodiments, the peripheral circuit (308) within the first semiconductor structure (302) is electrically connected to the bonding pad (340) for pad-out through at least the contact (344) and the peripheral contact (348), so that the peripheral contact (348) is located below and in contact with the contact (344).Each of the surrounding contacts (346 and 348) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., TiN).

[0058] As illustrated in FIG. 3, the 3D memory device (300) also includes various local contacts (also known as “C1”) as part of an interconnect structure that are in direct contact with a structure within the memory stack (314). In some embodiments, the local contacts include channel local contacts (350), each of which is located below and contacts the lower end of its respective channel structure (324). Each channel local contact (350) may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts (352), each of which is located below and contacts its respective conductive layer (316) (containing the word line) in the stepped structure of the memory stack (314) for word line fan-out. Local contacts, such as channel local contacts (350) and word line local contacts (352), can be electrically connected to peripheral circuits (308) of the first semiconductor structure (302) through at least bonding layers (312 and 310). Each of the local contacts, such as channel local contacts (350) and word line local contacts (352), may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., TiN).

[0059] FIG. 4 illustrates a cross-sectional plan view of another exemplary 3D memory device (400) having rear interconnect structures according to some embodiments of the present disclosure. The 3D memory device (400) may be an example of a 3D memory device (100) after flip-chip bonding, and FIG. 4 illustrates an example of a rear side of a 3D memory device (100) after flip-chip bonding. As illustrated in FIG. 4, according to some embodiments, in the plan view, the memory stack of the 3D memory device (400) includes two core array regions (406A and 406B) having channel structures (408) therein and a stepped region (404) between the core array regions (406A and 406B) in the x-direction (e.g., word line direction). In the y-direction (e.g., bit line direction), FIG. 4 illustrates rear interconnect structures within one block (402) of a 3D memory device (400), which can be repeated any appropriate number of times in a plurality of blocks.

[0060] In some embodiments, in a plan view, the 3D memory device (400) includes a source line mesh (410). In some embodiments, the source line mesh (410) is located in the core array regions (406A and 406B) and the step region (404). As illustrated in FIG. 4, according to some embodiments, in a plan view, the source line mesh (410) includes a plurality of parallel source lines (412) that extend laterally in the x-direction (e.g., word line direction) across the step region (404) and the core array regions (406A and 406B), similar to the toothed source lines (212) of the source line mesh (210) of FIG. 2a through 2c. Unlike the source line mesh (210) having a single shaft source line (214) in FIGS. 2a and 2b, in the plan view, the source line mesh (410) may also include a plurality of parallel source lines (414) each extending laterally in the y-direction (e.g., bit line direction). As illustrated in FIG. 4, the parallel source lines (414) may be placed in the core array regions (406A and 406B) and in the step region (404). It is understood that in some examples, the source lines (414) may not be placed in the step region (404) but only in the core array regions (406A and 406B).

[0061] The 3D memory device (400) may also include back source contacts (416) in the core array regions (406A and 406B) (e.g., in the form of VIA contacts), but not in the step region (404). For example, the back source contacts (416) may be evenly distributed in the core array region (406A or 406B). As illustrated in FIG. 4, according to some embodiments, each channel structure (408) is located below and laterally aligned with each of the back source contacts (416). That is, each channel structure (408) may overlap with each of the back source contacts (416) located just above the top of the channel structure (408), thereby reducing the resistance between the source of the NAND memory string and the back source contacts (416). In some embodiments, since the channel structures (408) are arranged in an array having rows and columns, the rear source contacts are also arranged in an array having rows and columns. In the top view, each source line (414 or 412) may contact each of the rear source contacts (416) in a row or column of the array. In some embodiments, each source line (414) extending in the y-direction may contact each of the rear source contacts (416) in a column. In some examples, it is understood that each source line (412) extending in the x-direction may contact each of the rear source contacts (416) in a row. In some embodiments, in the top view, each source line (414 or 412) contacts each of the rear source contacts (416) in two adjacent rows or columns of the array. For example, as illustrated in FIG. 4, each source line (414) extending in the y-direction may contact each of the rear source contacts (416) in two adjacent columns. Although not illustrated, similarly, in other examples, each source line (412) extending in the x-direction may contact each of the rear source contacts (416) in two adjacent rows.

[0062] The 3D memory device (400) may additionally include contacts (418), such as TSCs. In some embodiments, the contacts (418) are distributed in contact with the source line mesh (410) below in parts of the step region (404) and core array regions (406A and 406B). According to some embodiments, since the contacts (418) may be TSCs extending through a silicon substrate, the contacts (418) are distributed in contact with the source line mesh (410) below a peripheral part (including a part in the step region (404)) to avoid overlapping with the channel structures (408) in the central part of the source line mesh (410) in the core array regions (406A and 406B). For example, as illustrated in FIG. 4, contacts (418) may be distributed in contact with the outermost source lines (412 and 414) in the core array regions (406A and 406B). Contacts (418) may also be distributed in contact with the source line (414) in the step region (404).

[0063] As described in detail below, each rear source contact (416) can be electrically connected to the source of each NAND memory string, and the source line mesh (410) is electrically connected to each rear source contact (416) and, in turn, is electrically connected to the sources of the NAND memory strings. Similarly, each contact (418) can be electrically connected to the peripheral circuits of the 3D memory device (400), and the source line mesh (410) is electrically connected to each contact (418) and, in turn, is electrically connected to the peripheral circuits of the 3D memory device (400). As a result, the peripheral circuits are electrically connected to the sources of the NAND memory strings and can control and / or detect the sources through a metal routing comprising the contacts (418), the source line mesh (410), and the rear source contacts (416) on the rear of the 3D memory device (400). Compared to the examples of FIGS. 2a to 2c, the layout of the contacts (418), source line mesh (410), and rear source contacts (416), for example, an array of rear source contacts (416) corresponding to an array of channel structures (408), and source lines (414) contacting the rear source contacts (416) in two adjacent columns in the core array regions (406A and 406B) can further reduce the overall resistance of the metal routing.

[0064] FIG. 5 illustrates a cross-sectional side view of another exemplary 3D memory device (500) having rear interconnect structures according to some embodiments of the present disclosure. The 3D memory device (500) may be an example of the 3D memory device (400) of FIG. 4. The 3D memory (500) is similar to the 3D memory device (300) of FIG. 3 except for the arrangement of source contacts (502). As shown in FIG. 5, each channel structure (324) is located below its respective source contact (502) (e.g., an example of the rear source contact (416) of FIG. 4) which contacts the semiconductor layer (322) and is aligned laterally with it (e.g., in both the x-direction and the y-direction). It is understood that details of other identical structures in both 3D memory devices (500 and 300) are not repeated for ease of explanation.

[0065] FIGS. 6a through 6d illustrate a manufacturing process for forming an exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. FIG. 7 illustrates a flowchart of a method (700) for forming an exemplary 3D memory device having rear interconnect structures according to some embodiments of the present disclosure. Examples of 3D memory devices depicted in FIGS. 6a through 6d and FIG. 7 include 3D memory devices (200, 201, 203, and 400) depicted in FIGS. 2a through 2c and FIG. 4. FIGS. 6a through 6d and FIG. 7 will be described together. It is understood that the operations illustrated in the method (700) are not exhaustive and that other operations may also be performed before, after, or in between any of the illustrated operations. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 7.

[0066] Referring to FIG. 7, the method (700) begins with an operation (702) in which peripheral circuits are formed on a first substrate. The first substrate may be a silicon substrate. As illustrated in FIG. 6a, peripheral circuits (604) having a plurality of transistors are formed on the first silicon substrate (602) using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes.

[0067] As illustrated in FIG. 7, the method (700) proceeds to operation (704), wherein a plurality of channel structures are formed, each extending vertically through a memory stack on the front surface of the second substrate. In some embodiments, in the plan view, the memory stack includes two core array regions having channel structures and a step region between the two core array regions in the first lateral direction. As illustrated in FIG. 6a, an array of channel structures (608) is formed, each extending vertically through a memory stack on the front surface of the second silicon substrate (606).

[0068] As illustrated in FIG. 7, the method (700) proceeds to operation (706), wherein the first substrate and the second substrate are bonded face-to-face so that the channel structures are placed over the peripheral circuits. The bonding may include hybrid bonding. As illustrated in FIG. 6a and 6b, according to some embodiments, the second silicon substrate (606) and the components formed thereon (e.g., channel structures (608)) are inverted and the first silicon substrate (602) and the components formed thereon (e.g., peripheral circuits (604)) are placed face-to-face so that they are placed upward, i.e., bonded to form a bonding interface (609) between the silicon substrates (602 and 606).

[0069] As illustrated in FIG. 7, the method (700) proceeds to operation (708), wherein the second substrate is thinned. The thinning is performed from the back side of the second substrate. As illustrated in FIG. 6b, the second silicon substrate (606) (shown in FIG. 6a) is thinned from the back side using CMP, grinding, dry etching, and / or wet etching to become a semiconductor layer (610) (i.e., the thinned second silicon substrate (606)).

[0070] As illustrated in FIG. 7, the method (700) proceeds to operation (710), wherein a plurality of contacts penetrating the thinned second substrate are formed and a plurality of source contacts in contact with the thinned second substrate are formed. The contacts and source contacts are formed from the back surface of the thinned second substrate. In some embodiments, each channel structure is located below one source contact of the source contacts and is laterally aligned with it. In some embodiments, the source contacts are arranged in an array having rows and columns. As illustrated in FIG. 6c, the back source contacts (612) are formed in contact with the semiconductor layer (610) from the back surface of the semiconductor layer (610). In some embodiments, each channel structure (608) is located below its back source contact (612) and is laterally aligned with it. A plurality of TSCs (614, 616, and 618) may be formed from the back surface of the semiconductor layer (610) through the semiconductor layer (610). In some embodiments, the TSCs (616) extend further into the memory stack to contact the SSG within the memory stack.

[0071] As illustrated in FIG. 7, the method (700) proceeds to operation (712), wherein a source line mesh is formed on the back surface of a thinned second substrate such that the source line mesh is on and contacts a plurality of source contacts and a first set of contacts. In some embodiments, in the top view, the source line mesh comprises a plurality of parallel source lines extending laterally, each of which. In some embodiments, the source line mesh is on and contacts each of the source contacts. In some embodiments, in the top view, each of the source lines contacts each of the source contacts in a row or column of the array. In some embodiments, in the top view, each of the source lines contacts each of the source contacts in two adjacent rows or columns of the array. As illustrated in FIG. 6d, a source line mesh (620) is formed on the back surface of the semiconductor layer (610) such that the source line mesh (620) is on and contacts the back source contacts (612) as well as the TSCs (614). The layout of the source line mesh (620), rear source contacts (612), and TSCs (614) may vary in different examples, for example, as in the examples shown in FIGS. 2a through 2c and FIG. 4.

[0072] As illustrated in FIG. 7, the method (700) proceeds to operation (714), wherein a plurality of SSG lines are formed on the back surface of a thinned second substrate such that the SSG lines are on and contact a second set of contacts. In some embodiments, in the plan view, each of the SSG lines extends in a first lateral direction across two core array regions and a step region, and the second set of contacts is distributed in the core array regions. In some embodiments, in the plan view, the SSG lines are evenly distributed parallel in a second lateral direction perpendicular to the first lateral direction. As illustrated in FIG. 6d, SSG lines (624) are formed on the back surface of the semiconductor layer (610) such that the SSG lines (624) are on and contact the TSCs (616). The layout of the SSG lines (624) and the TSCs (616) may vary in different examples, for example, as in the example illustrated in FIG. 2a.

[0073] As illustrated in FIG. 7, the method (700) proceeds to operation (716), wherein a power line mesh is formed on the back surface of a thinned second substrate such that the power line mesh is on and contacts a third set of multiple contacts. In some embodiments, in a plan view, the third set of contacts is distributed in at least one of a stepped region or a peripheral region outside the memory array. As illustrated in FIG. 6d, a power line mesh (622) is formed on the back surface of a semiconductor layer (610) such that the power line mesh (622) is on and contacts the TSCs (618). The layout of the power line mesh (622) and the TSCs (618) may vary in different examples, for example, as in the example illustrated in FIG. 2a and FIG. 2b. Although the operations (712, 714, and 716) are described above as three sequential operations, it is understood that the operations (712, 714, and 716) can be performed in the same manufacturing processes. For example, one or more of the source line mesh (620), power line mesh (622), and SSG lines (624) can be patterned and formed in the same manufacturing processes.

[0074] According to one aspect of the present disclosure, a 3D memory device comprises a substrate, a memory stack comprising interleaved conductive layers and dielectric layers on the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer on and in contact with the plurality of channel structures, a plurality of source contacts on the memory stack and in contact with the semiconductor layer, a plurality of contacts penetrating the semiconductor layer, and a back interconnect layer on the semiconductor layer comprising a source line mesh in a plan view. The plurality of source contacts are distributed below the source line mesh in contact with it. A first set of the plurality of contacts is distributed below the source line mesh in contact with it.

[0075] In some embodiments, in the plan view, the memory stack includes two core array regions having channel structures and a step region between the two core array regions in a first lateral direction.

[0076] In some embodiments, the rear interconnect layer in the plan view further includes a plurality of SSG lines, and a second set of contacts is distributed below the SSG lines in contact with them.

[0077] In some embodiments, in the plan view, each of the SSG lines extends in a first lateral direction across two core array regions and a step region, and a second set of contacts is distributed in the core array regions.

[0078] In some embodiments, each of the second set of contacts extends further into the memory stack to contact one of the conductive layers of the memory stack.

[0079] In some embodiments, in the plan view, the SSG lines are evenly distributed parallel to each other in the second lateral direction perpendicular to the first lateral direction.

[0080] In some embodiments, the rear interconnect layer in the plan view further includes a power line mesh, and a third set of multiple contacts is distributed below the power line mesh in contact with it.

[0081] In some embodiments, a third set of contacts in the plan view is distributed in at least one of the stepped area or surrounding area outside the memory array.

[0082] In some embodiments, the power line mesh has a comb-like shape.

[0083] In some embodiments, the rear interconnect layer further includes bonding pads that are electrically connected to the power line mesh through a third set of contacts.

[0084] In some embodiments, the source line mesh has a comb-like shape.

[0085] According to another aspect of the present disclosure, a 3D memory device comprises a substrate, a memory stack comprising interleaved conductive layers and dielectric layers on the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer on and in contact with the plurality of channel structures, a plurality of source contacts in contact with the semiconductor layer, and a back interconnect layer on the semiconductor layer comprising a source line mesh in a plan view. Each of the channel structures is located below and laterally aligned with one of the source contacts. The source line mesh is located above and in contact with each of the source contacts.

[0086] In some embodiments, the 3D memory device further includes a plurality of contacts distributed below the source line mesh in contact with the semiconductor layer penetrating it.

[0087] In some embodiments, in the plan view, the memory stack includes one or more core array regions having channel structures, and contacts are distributed outside the core array regions.

[0088] In some embodiments, the source line mesh in the plan view includes a plurality of parallel source lines that each extend laterally.

[0089] In some embodiments, in the plan view, source contacts are arranged in an array, and each source line contacts each of the source contacts in a row or column of the array.

[0090] In some embodiments, in the plan view, each source line contacts each source contact in two adjacent rows or columns of the array.

[0091] According to another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. Peripheral circuits are formed on a first substrate. A plurality of channel structures are formed on the front surface of a second substrate, each extending vertically through a memory stack. The first substrate and the second substrate are bonded face-to-face so that the channel structures are placed over the peripheral circuits. The second substrate is thinned. A plurality of contacts penetrating the thinned second substrate and a plurality of source contacts in contact with the thinned second substrate are formed. A source line mesh is formed on the rear surface of the thinned second substrate such that the source line mesh is placed over the plurality of source contacts and a first set of contacts and contacts therewith.

[0092] In some embodiments, in the plan view, the memory stack includes two core array regions having channel structures and a step region between the two core array regions in a first lateral direction.

[0093] In some embodiments, a plurality of SSG lines are formed on the back surface of a thinned second substrate such that the SSG lines are on a second set of a plurality of contacts and contact therewith.

[0094] In some embodiments, in the plan view, each of the SSG lines extends in a first lateral direction across two core array regions and a step region, and a second set of contacts is distributed in the core array regions.

[0095] In some embodiments, in the plan view, the SSG lines are evenly distributed parallel to each other in the second lateral direction perpendicular to the first lateral direction.

[0096] In some embodiments, a power line mesh is formed on the back surface of a thinned second substrate such that the power line mesh is on a third set of a plurality of contacts and contacts it.

[0097] In some embodiments, the source line mesh in the plan view includes a plurality of parallel source lines that each extend laterally.

[0098] In some embodiments, each channel structure is located below and laterally aligned with one of the source contacts, and a source line mesh is located above and in contact with each of the source contacts.

[0099] In some embodiments, in the plan view, source contacts are arranged in an array, and each source line contacts each of the source contacts in a row or column of the array.

[0100] In some embodiments, in the plan view, each source line contacts each source contact in two adjacent rows or columns of the array.

[0101] The foregoing description of specific embodiments is intended to reveal the general nature of the disclosure so that others, by applying their knowledge within the art, can easily modify and / or adapt these specific embodiments for various applications without departing from the general concept of the disclosure and without excessive experimentation. Accordingly, based on the teachings and guidelines set forth in this specification, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the terminology or language of this specification is for descriptive purposes, not limiting, so that it may be interpreted by a person skilled in the art in the context of the teachings and guidelines.

[0102] The embodiments of the present disclosure have been described above with the help of functional building blocks that exemplify the implementation of specific functions and their relationships. The boundaries of these functional building blocks are defined arbitrarily for convenience of description in this specification. Alternative boundaries may be defined as long as the specific functions and their relationships are properly performed.

[0103] The sections of the description and summary of the invention may describe one or more (but not all) exemplary embodiments of the present disclosure as considered by the inventor(s) and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0104] The scope and range of the present disclosure shall not be limited by any of the exemplary embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A three-dimensional (3D) memory device comprising: a memory stack including interleaved conductive layers and dielectric layers; a channel structure extending vertically through the memory stack; a semiconductor layer positioned on the memory stack and electrically connected to the channel structure; a source contact positioned on the memory stack and electrically connected to the semiconductor layer, wherein the source contact and the memory stack are positioned on opposite sides of the semiconductor layer in a first direction; a first contact extending through the semiconductor layer and spaced apart from the semiconductor layer; and a second contact extending in the first direction, wherein the second contact is spaced apart from the memory stack in a second direction perpendicular to the first direction, and the dimension of the second contact in the first direction is greater than the dimension of the memory stack in the first direction. Claim 2 A 3D memory device according to claim 1, wherein the source contact extends into the semiconductor layer. Claim 3 A 3D memory device according to claim 1, wherein the semiconductor layer comprises a first semiconductor layer above the memory stack and a second semiconductor layer above the first semiconductor layer, the source contact extends into the second semiconductor layer, the channel structure comprises a semiconductor channel, and the source contact is electrically connected to the semiconductor channel through the first semiconductor layer and the second semiconductor layer. Claim 4 A 3D memory device according to claim 3, wherein the channel structure extends vertically through the memory stack and the first semiconductor layer, and the channel structure extends vertically into the second semiconductor layer. Claim 5 A 3D memory device according to claim 3, wherein the channel structure further comprises a memory film, the memory film is separated from a part of the channel structure adjacent to the first semiconductor layer, and the semiconductor channel is surrounded by the first semiconductor layer and in contact with the first semiconductor layer. Claim 6 A 3D memory device according to claim 1, further comprising a back interconnect layer on the semiconductor layer, wherein the back interconnect layer comprises a source line mesh, and the source contact is located below the source line mesh and contacts the source line mesh. Claim 7 A 3D memory device according to claim 6, wherein the back interconnect layer further comprises one or more interlayer dielectric (ILD) layers on the semiconductor layer, the source contact extends vertically into the semiconductor layer through the ILD layers, and the ILD layers comprise dielectric materials. Claim 8 A 3D memory device according to claim 6, wherein the rear interconnect layer further comprises an insulating layer on the source line mesh. Claim 9 A 3D memory device according to claim 6, comprising a plurality of source contacts arranged in rows or columns. Claim 10 In claim 9, the source line mesh comprises a source line, and the source line contacts the source contacts in rows or columns, a 3D memory device. Claim 11 A 3D memory device according to claim 6, further comprising contacts, wherein the contacts are distributed in contact with the source line mesh below the source line mesh in parts of the step region and the core array region, and the contacts are electrically connected to peripheral circuits of the 3D memory device. Claim 12 A 3D memory device according to claim 3, further comprising a peripheral contact and a contact structure electrically connected to said peripheral contact, wherein the peripheral contact extends vertically to the second semiconductor layer outside the memory stack, the contact structure extends through the second semiconductor layer, and the peripheral contact is electrically connected to a peripheral circuit. Claim 13 A 3D memory device according to paragraph 3, wherein the source contact comprises a metal layer and an adhesive layer, and a portion of the adhesive layer is located between the second semiconductor layer and the metal layer. Claim 14 A 3D memory device according to claim 1, further comprising peripheral circuits, wherein the peripheral circuits are bonded to the memory stack, and the memory stack is located between the peripheral circuits and the semiconductor layer. Claim 15 A three-dimensional (3D) memory device comprising: a memory stack including interleaved conductive layers and dielectric layers; a channel structure extending vertically through the memory stack and including a semiconductor channel; a first semiconductor layer above the memory stack and electrically connected to the channel structure; a second semiconductor layer above the first semiconductor layer; a source contact above the second semiconductor layer, wherein the source contact extends into the second semiconductor layer and the source contact is electrically connected to the semiconductor channel through the first semiconductor layer and the second semiconductor layer; a first contact extending through the second semiconductor layer and spaced apart from the second semiconductor layer; and a second contact extending in a first direction, wherein the second contact is spaced apart from the memory stack in a second direction perpendicular to the first direction, and the dimensions of the second contact in the first direction are greater than the dimensions of the memory stack in the first direction. Claim 16 A 3D memory device according to claim 15, wherein the channel structure further comprises a memory film surrounding a portion of the semiconductor channel, and the first semiconductor layer surrounds a portion of the channel structure and contacts the semiconductor channel. Claim 17 A 3D memory device according to claim 16, wherein the memory film comprises a first portion and a second portion distributed on opposite sides of the first semiconductor layer, the first portion of the memory film is in the second semiconductor layer, and the second portion of the memory film is in the memory stack. Claim 18 A 3D memory device according to claim 15, wherein the source contact comprises a metal layer and an adhesive layer, and a portion of the adhesive layer is located between the second semiconductor layer and the metal layer. Claim 19 A 3D memory device according to claim 15, further comprising a back interconnect layer on the semiconductor layer, wherein the back interconnect layer comprises a source line mesh, and the source contact is located below the source line mesh and contacts the source line mesh. Claim 20 A 3D memory device according to claim 19, comprising a plurality of source contacts arranged in rows or columns, wherein the source line mesh comprises source lines, and the source lines contact the source contacts in rows or columns.

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