Digital radio head control

Abstract

Technologies related to digital wireless control and operation are described. Various technologies described herein enable the generation of high-frequency local oscillator (LO) signals using injection locked cock multipliers (ILCMs). These technologies also include using LO signals in carrier aggregation (CA) applications for phase array front ends. Additionally, the disclosed technologies include using array element-level control with per-chain DC-DC converters. Furthermore, the disclosed technologies include the use of adaptive spatial filtering and the optimal connection of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

Description

Technology Field

[0001] The aspects described herein generally relate to digital radios, and in particular to frequency multiplication, digital control, and radio designs implementing novel radio architectures. Background Technology

[0002] Modern RF radios generally utilize a Local Oscillator (LO), which must be distributed across one or more radio chains (e.g., receivers, transmitters, or transceivers). Furthermore, modern RF radios can implement beamforming and / or may require high-frequency signal distribution. Generating, distributing, and processing these signals can lead to complex designs that need to be addressed. For instance, modern RF radios face issues such as signal loss, excessive power consumption (and consequent heat generation), and the use of expensive and lossy cables and connectors as interconnects between RF radio boards. To date, no suitable attempts have been made to address these and other problems. Brief explanation of the drawing

[0003] The accompanying drawings included in and forming part of this specification illustrate aspects of the disclosure together with the detailed description of the invention, explain the principles of the aspects, and enable those skilled in the art to make and use the aspects. FIG. 1 illustrates an example of multi-phase signal injection that generates one or more LO signals through frequency multiplication according to one aspect of the present disclosure. FIG. 2 illustrates the amplification of harmonics required as part of LO signal generation and the suppression of harmonics not required, according to one aspect of the present disclosure. FIG. 3 shows a block diagram of an exemplary transceiver design implementing local oscillator distribution and generation according to one aspect of the present disclosure. FIG. 4 shows a block diagram of an exemplary delay-locked loop (DLL) implementing a controlled delay line according to one aspect of the present disclosure. FIG. 5 shows a block diagram of an exemplary interpolation delay line according to one aspect of the present disclosure. FIG. 6 illustrates a block diagram of an exemplary DLL implementing a two-dimensional delay line according to one aspect of the present disclosure. FIG. 7 is an exemplary M showing a phase generated for a two-dimensional delay line (600) as illustrated in FIG. 6, according to one aspect of the present disclosure. x ×M y Represents a matrix. FIG. 8a shows an injection-locked clock multiplier (ILCM) using serial injection according to one aspect of the present disclosure. FIG. 8b shows an ILCM using parallel injection according to one aspect of the present disclosure. FIGS. 9a through 9d illustrate an exemplary oscillator circuit that can be used as an oscillator part of an ILCM according to one aspect of the present disclosure. FIG. 10 shows a block diagram of a device according to one aspect of the present disclosure. FIGS. 11a through 11c illustrate an example of a transceiver architecture that implements a single-die digital beamformer using multiple frequency operating bands according to one aspect of the present disclosure. FIG. 12a or FIG. 12b illustrates an example of a transceiver architecture that implements a multi-die digital beamformer using a single frequency operating band according to one aspect of the present disclosure. FIGS. 13a through 13c illustrate an example of a transceiver architecture that implements a multi-die digital beamformer using multiple frequency operating bands according to one aspect of the present disclosure. FIG. 14 shows a block diagram of a device according to one aspect of the present disclosure. FIG. 15 illustrates a block diagram of an exemplary transceiver design according to one aspect of the present disclosure. FIG. 16a shows a block diagram of a conventional transceiver architecture using a common DC-DC converter between each of the transceiver chains. FIG. 16b shows a block diagram of a transceiver architecture using a plurality of DC-DC converters, one for each transceiver chain, according to one aspect of the present disclosure. Figure 17a shows the simulated far-field radiation pattern for a 4×4 antenna array without aperture tapering. FIG. 17b shows a simulated far-field radiation pattern for a 4×4 antenna array with aperture tapering indicating a reduction in the side lobe level, according to one aspect of the present disclosure. FIG. 18a illustrates a constant amplifier supply voltage using a common DC-DC converter as part of a conventional transceiver architecture. FIG. 18b shows a modulated amplifier supply voltage using a plurality of DC-DC converters according to one aspect of the present disclosure. FIG. 19 illustrates a processing flow for VSWR (voltage standing wave ratio) correction and collaboration with a DPD (digital pre-distortion) front-end module according to one aspect of the present disclosure. FIG. 20a shows a simulated far-field radiation pattern for a 4×4 antenna array without element failure, according to one aspect of the present disclosure. Figure 20b shows a simulated far-field radiation pattern for a 4×4 antenna array associated with three failed or disabled elements. FIG. 21 shows a block diagram of an exemplary device according to one aspect of the present disclosure. FIG. 22 shows a block diagram of an exemplary receiver design using multi-element combined estimation of a received (RX) signal in an adaptive space filter according to one aspect of the present disclosure. FIG. 23a shows a block diagram of an exemplary receiver design that implements spatial blocker detection with a coarse sector scan according to one aspect of the present disclosure. FIG. 23b shows a block diagram of an exemplary ADC design according to one aspect of the present disclosure. FIG. 23c shows a block diagram of an exemplary ADC design using a feedback path according to one aspect of the present disclosure. FIG. 24 illustrates a block diagram of an exemplary receiver design that implements a feed-forward spatial filter using a combination between sets of nearest neighbor RF chains according to one aspect of the present disclosure. FIG. 25 shows a block diagram of an exemplary device according to one aspect of the present disclosure. Exemplary aspects of the present disclosure will be described with reference to the accompanying drawings. The drawing in which a component first appears is generally indicated by the leftmost number(s) of the corresponding reference number. Specific details for implementing the invention

[0004] In the following description, many specific details are provided to provide a complete understanding of the aspects of the present disclosure. However, it will be obvious to those skilled in the art that aspects including structures, systems, and methods can be practiced without these specific details. The descriptions and expressions in this specification are general means used by those experienced or skilled in the art to most efficiently convey their work to other skilled in the art. In other cases, well-known methods, procedures, components, and circuits are not described in detail to avoid unnecessarily obscuring aspects of the present disclosure.

[0005] Section I - Injection-Locked Clock-Multiplication for Mixer Local Oscillator (LO) Generation

[0006] The aspects described in this section generally relate to transceivers, and in particular, to transceiver designs that implement a combination of a low-frequency delay-locked-loop (DLL) and an injection-locked clock multiplier (ILCM) to generate a local oscillator (LO) signal at a higher frequency.

[0007] RF transceivers require a local oscillator (LO) at the channel frequency or a frequency close to it for mixing. For example, one or more LO signals must be generated at each carrier frequency or channel of interest. For higher frequency applications, such as the millimeter wave (mm-Wave) band, the required LO signals are typically large in terms of signal magnitude. Consequently, generating and distributing these mm-Wave LO signals in on-chip implementations is not simple and requires significant power. Furthermore, mm-Wave transceiver designs typically use orthogonal LOs, which further complicates the issue, and LO beamforming-based transceivers also require multi-phase LOs. Therefore, generating the necessary LO signals for these transceivers is a complex, costly, and time-consuming task.

[0008] In other words, many transceiver designs, such as mm-Wave transceivers, implement, for example, orthogonal multiphase LO. Typical solutions for generating these LO signals include direct multiphase orthogonal LO generation techniques that aim to directly generate mm-Wave LO from a mm-Wave phase-locked loop using, for example, frequency division, 90° hybrid couplers, and poly-phase filters. The LO signal is then distributed to all transceiver chains of the mm-Wave system. In the case of 2xLO, a local frequency divider is also used to generate the orthogonal LO clock. Phase-shifting of the orthogonal LO clock is typically performed in various ways, such as using individual phase-shifters on the orthogonal LO clock to phase-shift the 2xLO clock before division, or using Cartesian combinations of the orthogonal LO clocks to generate the phase-shifted orthogonal LO.

[0009] However, these conventional technologies require the use of mm-Wave PLLs, which also require mm-Wave voltage-controlled oscillators (VCOs). Furthermore, designing this is not easy when considering the strict phase-noise requirements for modulation according to mm-Wave standards (e.g., "5G" wireless protocols). Consequently, mm-Wave PLLs consume a significant amount of power. Additional power is also consumed when distributing mm-Wave LOs (or 2xLOs). Therefore, because the power consumption of existing direct multi-phase orthogonal LO generation solutions is very high, these solutions are not suitable for handheld and mobile applications.

[0010] Another solution for generating mm-Wave orthogonal multi-phase LO involves the use of frequency-multiplication-based LO signals. In this design, a central PLL is used to generate a clock signal at the sub-harmonics of the LO frequency, which is then distributed to each transceiver chain. This clock signal is then multiplied to the LO frequency using an injection-locked oscillator or a self-mixing multiplier, typically local to each transceiver. Thus, phase-shifted orthogonal LO can be generated by implementing a direct phase shifter and / or using an orthogonal injection-locked oscillator. Another option unique to this frequency-multiplication solution involves using phase-shifting at the sub-harmonics of the LO frequency (i.e., prior to multiplication). In other words, according to these conventional methods, the order of frequency multiplication and phase shifting may be reversed.

[0011] In this sub-harmonic injection-locking, the target harmonic is amplified while other harmonics of the sub-harmonic clock are suppressed. However, in single-phase sub-harmonic injection used according to this technique, unintended harmonics may not be sufficiently suppressed as they are suppressed only by the oscillator's tank, and spurious frequencies may be generated. This also applies to self-mixing frequency multiplication topologies.

[0012] Generating a square wave clock at higher frequencies (e.g., mm-Wave frequencies) (e.g., having a 25% duty cycle according to common use cases) is highly inefficient and, in some cases, impossible, depending on whether a technology node is manufactured. Therefore, to address the requirement to generate an orthogonal multi-phase LO, particularly for mm-Wave transceivers that implement beamforming, aspects disclosed herein implement a combination of a low-frequency delay-locked-loop (DLL) and an injection-locked clock multiplier (ILCM) to generate a phase-shifted mm-Wave mixer LO signal. Preferably, a typical mm-Wave transceiver uses active mixers versus passive mixers for downconversion, and the output of the DLL and ILCM combination aspect described herein is a sinusoidal wave, which is suitable for active mixer operation.

[0013] As discussed in more detail below, the aspects include a common RF-PLL implemented at the odd sub-harmonics of the desired LO, which is distributed to different transceiver chains. A DLL local to each transceiver chain is used to generate a signal in multiple phases of the LO sub-harmonics. An ILCM local to each chain is optionally supplied as an injected input along with a subset of the signal generated in multiple phases of the LO sub-harmonics. As a result of the injected signal, the ILCM generates an orthogonally phase-shifted large-swing LO signal at mm-wave frequencies, which has the appropriate LO phase for the transceiver chain while suppressing the fundamental harmonic (i.e., LO sub-harmonic) and its unwanted harmonics.

[0014] The advantages derived from aspects described herein include performing PLL and LO distribution at RF frequencies (not mm-Wave frequencies) while saving significant power. Additionally, the digitally-controlled oscillator (VCO / DCO) of the PLL can be designed for optimal phase-noise (without additional penalty to Q degradation for mm-Wave operation). Furthermore, the divider of the PLL feedback can be CMOS-based or injection-locked instead of current mode logic (CML). Both of these designs save power in the PLL. The RF LO distribution network realized as a result of the aspects described herein also saves power compared to mm-Wave LO distribution. Thus, the local DLL provides a simple method for generating multi-phase (including orthogonal) at LO subharmonic frequencies, which can be used as an alternative to the frequency-multiplying digital-to-analog converter (FM-DAC) that can be implemented for this purpose.

[0015] Additional benefits include the suppression of unwanted harmonics as a result of the injection mechanism for the ILCM, thereby generating a cleaner frequency spectrum compared to previous technologies. Furthermore, connecting the ILCM output directly to the active mixer's LO input eliminates the need for additional buffering. The load impedance of the mixer's LO input can also be absorbed by the ILCM block design.

[0016] As further referenced in this section and in other sections, the term “mm-Wave frequency” in which the aspects described in this section and in other sections may be operated may include frequencies and frequency bands up to, for example, 20 GHz, 24 GHz, 28 GHz, etc. and higher frequencies. For example, mm-Wave frequency bands may include frequencies in the range of 20 GHz to 300 GHz, 24 GHz to 300 GHz, etc. This may include or refer to various frequency bands known to be associated with mm-Wave frequency bands, for example, 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc.

[0017] FIG. 1 illustrates an example of multi-phase signal injection that generates one or more LO signals through frequency multiplication according to one aspect of the present disclosure. As illustrated in FIG. 1, a local oscillator generation (LOG) (100) having an injection locked clock multiplier (ILCM) (104) into which a multi-phase shifted signal (102) of a lower frequency signal is injected is illustrated. This lower frequency may be a sub-harmonic of a desired higher frequency LO signal resulting from clock multiplication. Generally, as illustrated in FIG. 1, frequency multiplication can be achieved by injecting a set of specific sub-harmonic signals having specific phase shifts relative to each other based on the desired frequency multiplication.

[0018] To provide an exemplary example of achieving a five-fold frequency multiplication, each of the multi-phase shifted signals (102) has a frequency that is 1 / 5 of the LO frequency to be output from the ILCM (104). In one aspect, the multi-phase shifted signals (102) also have phase shifts relative to each other representing the same portion of the sub-harmonic LO signal. For example, FIG. 1 shows each of the multi-phase shifted signals (102) that are equally spaced from each other by 1 / 5 of a full clock cycle or 2π (i.e., 72 degrees) in terms of phase relationship.

[0019] As a result, a consistent addition of desired harmonics and a destructive combination of unwanted harmonics are achieved through the ILCM (104). This technique works particularly well when the desired harmonics are odd. Additionally, in the example illustrated in FIG. 1 and further described herein, the desired sub-harmonic is selected as the fifth sub-harmonic of the desired high-frequency LO signal, which may correspond, for example, to an LO signal in the mm-Wave frequency band. The use of the fifth sub-harmonic is exemplary and not limiting. The aspects described herein are not limited to a specific sub-harmonic and may be implemented according to any suitable sub-harmonic of the LO signal.

[0020] For example, as illustrated in FIG. 2, the side generates cancellation of sub-harmonic LO / 5 using odd harmonics (3LO / 5, 7LO / 5, etc.) (e.g., through destructive interference) by summing multi-phase-shifted signals (102) through ILCM (104). This signal cancellation may include a resulting (summed) signal having a significantly attenuated amplitude (e.g., 100% attenuation, 95% attenuation, 90% attenuation, etc.) compared to one of the individually combined phase-shifted signals. Furthermore, the aspects include the combination of multi-phase-shifted signals (102) via ILCM (104) that causes amplification of sub-harmonics of the LO signal equivalent to the odd harmonics of the higher frequency LO signal (e.g., 5LO / 5=LO, 15LO / 5=3LO, etc.) (e.g., through constructive interference). Amplifying the signal in this way through constructive interference may include, for example, amplification of the summed signal, so that the resulting (summed) signal has substantially the same amplitude as the summed amplitudes of the individually combined phase-shifted signals (e.g., within 1%, 5%, 10%, etc.). This concept is further illustrated in the spectral power distribution (200) and phase diagram (250) as shown in FIG. 2.

[0021] This concept can be mathematically generalized so that when (2N+1) multiple phase-shifted signals are combined—each spaced equally apart by 2π / (2N+1) at the frequency of LO / (2N+1)—the sub-harmonic (low-frequency) LO signal is consistently added at the LO frequency (and the harmonics of the LO signal frequency) and canceled out at all other odd harmonics of LO / (2N+1) as a result of canceling interference. In this case, N represents an arbitrary integer. In conventional frequency-multiplicative techniques implementing injection locking or self-mixing, these sub-harmonics are not fundamentally canceled out and thus generate spurts that may occur within one or more critical frequency bands of interest. Therefore, it is advantageous to use low-frequency signals to generate higher-frequency LO signals using these multi-phase signal injection and phase-additive techniques.

[0022] Although not illustrated in FIG. 1, as further discussed below for ease of explanation, the multi-phase shifted signal (102) may be a subset selected from an upper set of additional phase shifted signals, which is injected into the ILCM (104). In one aspect, the multi-phase shifted signal (102) may include all of the orthogonal phase signal components of the in-phase signal, as further discussed below. For example, the multi-phase shifted signal (102) illustrated in FIG. 1 may represent in-phase signal components having relative phases with respect to each other of 0°, 72°, 144°, 216°, and 288°. For brevity, although not illustrated in FIG. 1, the multi-phase shifted signal (102) injected into the ILCM (104) may further include orthogonal phase signal components. Continuing from the previous example, the multi-phase shifted signal (102) illustrated in FIG. 1 may further include these orthogonal phase signal components having relative phases of 90°, 162°, 234°, 309°, and 16° relative to each other.

[0023] FIG. 3 illustrates a block diagram of an exemplary transceiver design implementing local oscillator distribution and generation according to one aspect of the present disclosure. As illustrated in FIG. 3 and further discussed herein, the transceiver design (300) comprises any suitable K individual LOG (local oscillator generation) units (304.1 to 304.K). Each LOG unit (304.1 to 304.K) may, in turn, comprise a respective LOG circuit (306), each LOG circuit comprising a DLL (delay-locked loop) (306.1), a phase configuration circuit (306.2), and an ILCM (306.3).

[0024] As further discussed herein with reference to FIG. 10, aspects include a transceiver design (300) implemented as part of an overall transceiver design with some components omitted for brevity and ease of explanation. For example, the transceiver design (300) enables a separate set of LO signals to be generated for each receiving chain (RX-1 to RX-K) which can be subsequently utilized by each transceiver chain for downconversion of the received signal and subsequent signal processing (i.e., each receiving chain exists within each transceiver chain or, alternatively, as part of a dedicated receiver system). As illustrated in FIG. 3 as an example, not a limitation, the set of LO signals generated through each LOG unit (304) may be orthogonal differential LO signals. And, since each transceiver chain is provided with its own set of LO signals, phase changes between different transceiver chains can be facilitated in this way. Accordingly, the aspects described herein may be particularly useful for transceivers implementing beamforming through multiple antennas, because each transceiver chain can utilize its own dedicated set of orthogonal LO signals having a phase tuned for the corresponding specific transceiver chain and antenna combination.

[0025] Accordingly, aspects include each transceiver chain using its own set of orthogonal LO signals for downconversion, demodulation, and signal processing. To this end, various aspects include each individual transceiver chain (RX-1 to RX-K) including additional components, circuits, processors, antennas, etc., to ensure that received signals are received and the data contained therein is processed accordingly. For example, these additional components may include mixers, demodulators, filters, amplifiers, processors, etc., which implement the processing of received data through one or more processors (e.g., baseband processors) in combination with any other suitable components. For example, when LO signals are generated, they may be used according to any suitable technique (e.g., known technique) to process the data contained in the signal received wirelessly.

[0026] In one aspect, the transceiver design (300) includes a common phase-locked loop (PLL) circuit (302) that generates a reference clock signal that can be used as an input signal by each LOG unit (304.1 to 304.K). This input signal may be generated at a sub-harmonic frequency of a desired high-frequency LO signal as described with reference to FIG. 1. In aspects, the high-frequency LO signal may have a frequency associated with the mm-Wave spectrum, for example, the proposed 24 GHz to 86 GHz spectrum. However, aspects are not limited to these specific bands, and aspects described herein may be implemented according to any frequency or frequency range suitable for a particular wireless communication use case.

[0027] The common PLL circuit (302) may be implemented to generate a reference clock signal using any suitable and / or known circuit component. As illustrated in FIG. 3, the common PLL circuit (302) generates a reference input signal at a sub-harmonic frequency of a high-frequency LO signal represented as LO / (2N+1), where LO is a high target LO signal frequency and N is any positive integer value based on the desired frequency multiplication scaling used for a particular application. The input signal generated at a sub-harmonic frequency of the high-frequency LO signal is distributed to any suitable number (K) of individual RX chains (RX-1 to RX-K) through their respective LOG units (304.1 to 304.K).

[0028] In other words, the reference signal (i.e., the “input signal” used in connection with the input to the LOG unit (304.1 to 304.K)) is generated at a frequency lower than the target LO signal by using frequency multiplication (e.g., RF frequency versus mm-Wave frequency). Consequently, the input signal can be distributed to each receiving chain (RX-1 to RX-K) using a power distribution system that preferably saves power and requires less design effort compared to the embodiment used for high-frequency signals. This may be particularly advantageous, for example, when the transceiver design (300) implements a transceiver chain distributed in “large quantities,” such as K being 10, 20, 100, etc. In one aspect, each receiving chain (RX-1 to RX-K) implements a respective LOG circuit (304) to perform frequency multiplication and phase shifting using the input signal, as illustrated in additional details for the receiving chain (304.2) and further discussed below.

[0029] For example, a LOG unit (306) is illustrated in FIG. 3 and is associated with a receiving chain (RX-2) and a LOG unit (304.2). In other words, aspects include each receiving chain (RX-1 to RX-K) implementing a separate LOG unit such as the LOG unit (306), but for brevity, only details regarding the operation of the LOG unit (306) are discussed herein. In one aspect, the LOG unit (306) includes a delay-locked loop (DLL) (306.1), a phase configuration circuit (306.2), and an ILCM (306.3). In one aspect, the LOG unit (306) may receive a reference input signal generated by a common PLL circuit (302) and provide a set of orthogonal LO signals as output. As illustrated in FIG. 3, these orthogonal LO clock signals may be, for example, differential orthogonal LO clock signals. Although the aspects disclosed in this specification are described primarily by reference to LO clock signals being orthogonal and essentially differential, the references are not limited thereto and may include generating any appropriate number or type of LO signals having any relationship with one another suitable for signal processing of the received radio signal.

[0030] In any case, the aspects include the LO signal set having a high target frequency (e.g., mm-Wave frequency), and the LO signal set includes an in-phase LO signal component (I) at 0 degrees, an in-phase LO signal component at 180 degrees ( ), orthogonal LO signal component at 90 degrees (Q), and orthogonal LO signal component at 270 degrees ( It is expressed as ). Of course, the orthogonal LO signals can maintain a 90-degree phase shift relative to each other, but the orthogonal LO signals can include any appropriate phase shift, and the "0-degree" phase component represents a reference phase value and can deviate from 0 degrees for each of the receiving chains (RX-1 to RX-K).

[0031] In other words, while the generated orthogonal LO signals may include LO signal components having phases of 0, 90, 180, and 270 degrees relative to each other, each LOG unit (204.1 to 204.K) may generate its own set of orthogonal LO signals that can be phase-shifted relative to other sets of orthogonal LO signals. For example, LOG unit (304.1) may generate orthogonal LO signals that are phase-shifted by 5, 10, 15 degrees, etc., from the orthogonal LO signals generated by LOG unit (304.2), even though they are separated by 90 degrees from each other. Details regarding how the orthogonal LO signals are generated through each LOG unit (304.1 to 304.K) are discussed further below.

[0032] In various aspects, the DLL (306.1) may be implemented using different architectures, each of which offers a trade-off of increasing design complexity in exchange for more precise control over the phase used to generate the orthogonal LO signal. In one aspect, the DLL (306.1) may be implemented as a multi-stage controlled delay line, an embodiment of which is illustrated as the DLL (400) in FIG. 4. In one aspect, the DLL (400) may generate a sub-harmonic phase signal input to the phase configuration circuit (306.2). Additionally, according to these aspects, the DLL (400) may include a phase detector and a loop filter (402) which may be implemented as one or more processors configured to control the state of one or more of the M delay elements (404.1 to 404.M) included in the M-stage controlled delay line (404) by executing computer-readable instructions. Although the M-stage controlled delay line (404) is illustrated in FIG. 4 as being implemented with an inverter as a delay element (404.1 to 404.M), aspects include the M-stage controlled delay line (404) being implemented with any suitable type and / or combination of delay elements (404.1 to 404.M), such as a buffer, for example.

[0033] In one aspect, the phase detector and loop filter (402) can facilitate analog and / or digital control of the M-stage controlled delay line (404), which can be adjusted so that the delay line input and output can be separated into one clock cycle. The clock signal may include, for example, a distributed input signal generated by a common PLL circuit (302), as discussed with reference to FIG. 3. Furthermore, the phase detector and loop filter (402) can control the state of the delay elements implemented by the M-stage controlled delay line (404) using any suitable technique, such as load control, current deprivation control, power supply control, etc.

[0034] In any case, the aspects include the DLL (400) providing a set of phase-shifted signals to the phase configuration circuit (306.2). These phase-shifted signals, as illustrated in FIG. 4, are separated by phases that are a function of M delay elements (404.1 to 404.M). Thus, the unit-phase granularity associated with the amount of phase shift between the set of phase-shifted signals (i.e., "CLK phases") provided by the DLL (400) is increased according to the M delay elements (404.1 to 404.M). However, the DLL (400) is limited in that the unit-phase shift (2π / M) equivalent time delay may, in some cases, be reduced more than the unit-inverter delay of the individual delay elements. Therefore, to allow for finer granularity of the unit-phase shift, the aspects include implementing alternative types of delay lines, as further discussed below with reference to FIGS. 5 and 6.

[0035] FIG. 5 shows a block diagram of an exemplary interpolation delay line according to aspects of the present disclosure. In one aspect, a DLL (306.1) as shown in FIG. 3 can be implemented using an interpolation delay line (500) as illustrated in FIG. 5 by modifying an implementation of a DLL (400) as shown in FIG. 4. For example, an M-stage controlled delay line (404) can be replaced with other delay element configurations such as the interpolation delay line (500) as shown in FIG. 5. Thus, according to these aspects, the DLL (306.1) can be implemented as a combination of a phase detector and a loop filter (402) as shown in FIG. 4 and an interpolation delay line (500) as shown in FIG. 5.

[0036] The interpolation delay line (500) includes a delay element represented as an inverter in FIG. 5, but aspects include the interpolation delay line (500) implementing any suitable type of delay element. As illustrated in FIG. 5, M delay elements may be associated with one clock cycle, and the number k represents any number of elements between 1 and M. For example, the phase at a node denoted as (k+1)*(2π / M) may be associated with a delay element (502.k). By staggering the inputs between each column as illustrated in FIG. 5, the set of phase-shifted signals provided by the DLL (500) may provide unit phase shifts such as (k*2π / M), (k+1)*(2π / M), (k+2)*(2π / M), etc., which represent a higher level of phase granularity compared to the DLL (400). That is, the DLL (500) utilizes interpolation between sets of delay elements to overcome the limitations imposed by the DLL (400) and achieves a unit phase shift less than that associated with the delay of individual delay elements.

[0037] For the DLL (400) and DLL (500) as illustrated in FIGS. 4 and 5, respectively, each DLL represents a single DLL implemented in a specific configuration (e.g., non-interpolated DLL (400) versus interpolated DLL (500)). In other aspects, as further discussed below, one or more DLLs may be implemented to achieve finer control over unit phase shifts.

[0038] FIG. 6 illustrates a block diagram of an exemplary DLL implementing a two-dimensional delay line according to one aspect of the present disclosure. In one aspect, the DLL (306.1) may be implemented as a two-dimensional delay line (600) as illustrated in FIG. 6. The two-dimensional DLL (600) may implement two separate delay line control systems, DLL-X core (602) and DLL-Y core (604), each of which controls a set of delay elements in a manner similar to the DLLs (400 and 500). Additionally, similar to the DLLs (400 and 500), the two-dimensional delay line (600) may implement any appropriate type of control (load control, current depletion control, power supply control, etc.) for delay elements that may be implemented as any appropriate type of delay element. Accordingly, like the DLLs (400 and 500), the two-dimensional DLL (600) receives a reference clock signal generated by the common PLL circuit (302) at the input (606) and can output any appropriate number of phase-shifted versions of this reference clock signal. Then, these phase-shifted reference clock signals can be used by the phase configuration circuit (306.2) to inject a specific subset of the phase-shifted signals into the ILCM (306.3), as further discussed below. In this way, the ILCM (306.3) facilitates frequency-multiplication of the subset of the phase-shifted input signals and generates a set of LO signals at the desired frequency and phase.

[0039] However, unlike the DLLs (400 and 500), the sides are the two-dimensional DLL (600) M x ×M y It includes two orthogonal sets of M delay elements forming a two-dimensional matrix of delay elements having dimensions. The aspects include that the matrix has any appropriate dimension and does not need to be symmetric. Thus, the delay element matrix is, as illustrated in FIG. 6, M x DLL-X core (602) and M controlling delay elements y It may be composed of a DLL-Y core that controls delay elements. Additionally, the two-dimensional matrix of delay elements may be interleaved with each other, as exemplified in detail part (608), so that each node within the two-dimensional matrix is ​​supplied by two delay elements.

[0040] In one aspect, it is common for each delay element to be controlled by the DLL (-X or -Y) core output. However, the delay element chain on the "top" (i.e., the last inverter output returns as input to DLL-X) and the delay element on the "left" (i.e., the last inverter output returns as input to DLL-Y) are "fully" controlled; that is, their delays are controlled and constrained by their respective DLLs. In addition to these chains, other delay elements are partially controlled by the DLL. Thus, aspects involve utilizing the configuration of a two-dimensional DLL (600) to reduce delay variations in stages not fully controlled by the DLL. As an additional advantage, the two-dimensional DLL (600) also allows for a more organized "floor-planning" of the design, which, in some aspects, can advantageously allow for easier implementation than the DLL (400 or 500). An exemplary M representing the phases generated by the two-dimensional delay line (600). x ×M y The matrix is ​​shown in Fig. 7.

[0041] In various aspects, appropriate phases can be generated by any appropriate delay line implementation, such as any DLL (400, 500, or 600). In other words, each LOG unit (304) can output an appropriate phase through each DLL (306.1), which is selected by the phase configuration circuit (306.2) portion of the LOG unit (304) as further described below, and injected into the ILCM (306.3) to provide a desired LO signal for each receiving chain.

[0042] In other words, referring to FIG. 3, aspects include the DLL (306.1) generating a superset of phases necessary to ensure frequency multiplication by the ILCM (306.3). Aspects include the DLL (306.1) generating a phase-shifted input signal with a phase difference according to the DLL architecture implemented for all desired beam angle scenarios. The phase configuration circuit may be controlled via a phase control block (308) capable of generating one or more control signals through one or more processors executing stored instructions. In some aspects, the phase control block (308) may represent a purely hardware solution. In any case, the phase configuration circuit may be implemented with any suitable number and / or type of switching elements that optionally connect and inject the signal generated by the DLL (306.1) into the ILCM (306.3).

[0043] By selectively injecting a specific combination of phase-shifted input signals from a superset (i.e., a subset of the superset) generated by the DLL (306.1), the phase configuration circuit (306.2) injects appropriately phase-shifted (in-phase and quadrature-phase) input signals into the ILCM (306.3). Thus, by distinguishing and selecting specific generated phase-shifted input signals, a change in the frequency and phase of the output quadrature LO signal (i.e., appropriate frequency scaling) can be realized.

[0044] In one aspect, and as further discussed below, the ILCM (306.3) can implement any suitable type of architecture to ensure frequency multiplication and generate LO signals at appropriate frequency and phase shifts. As further described below with reference to FIGS. 8a and 8b, the ILCM (306.3) can be implemented using any suitable type of hardware circuit configured to perform injection locking and can implement any suitable type of oscillator topology.

[0045] In one aspect, the ILCM (306.3) may implement a serial or parallel injection architecture, as described separately below with reference to FIGS. 8a and 8b. Each architecture presents trade-offs in terms of current consumption, start-up gain requirements, and lock-range functionality. Regardless of the specific ILCM architecture used, aspects include injecting each phase-shifted input signal, selected by the phase configuration circuit (306.2), into the ILCM (306.3), which implements one or more oscillators tuned to a frequency equal to or substantially equal to the intended LO frequency (e.g., 1%, 5%, 10%, etc.). In other words, the oscillator(s) implemented within the ILCM (306.3) may be tuned to have an intrinsic oscillation frequency that is a specific harmonic of the sub-harmonic frequency associated with the phase-shifted input signal provided by the phase configuration circuit (306.2). To provide an example using the five clock signals illustrated in FIGS. 1 and 2, the oscillator(s) implemented as part of the ILCM (306.3) can be tuned to have natural resonance at the LO frequency, which is 1 / 5 of the frequency of the sub-harmonics ( ) and therefore frequency( It resonates in ).

[0046] Conventional ILCM circuits are generally designed to inject a single signal and lock to the nearest harmonic frequency of this injected signal to generate a frequency multiplication. However, because the harmonic components of the signal may be somewhat weak, the resulting phase lock range is typically very narrow, making it difficult to track the final phase noise. Furthermore, in some cases, harmonics may be significant and are not inherently suppressed (as in the aspects described herein), so conventional ILCM circuits risk locking to the wrong harmonic and resonating at unwanted frequencies.

[0047] As described herein with reference to FIG. 2, the aspects described herein address this problem by using a multi-phase signal injection approach that uses a phase interval that can be selectively adjusted based on the desired frequency multiplication. In doing so, unwanted harmonics among the sub-harmonic signals are rejected or suppressed, thereby helping to prevent false locking occurring at these unwanted harmonic frequencies. Furthermore, by injecting a specific subset of phase-shifted input signals at sub-harmonic frequencies of the LO frequency (i.e., signals having a specific phase relationship with each other), the constructive interference of these phase-shifted input signals facilitates better frequency multiplication by producing signals with higher signal strength to better ensure injection locking at the desired higher LO frequency.

[0048] For example, as illustrated in FIG. 3, a subset of phase-shifted input signals provided by a phase configuration circuit (306.2) is connected to a set of phase (I) and quadrature (Q) buffers. Subsequently, current supplied by these buffers is injected into an ILCM (306.3). The ILCM (306.3) includes an oscillator configured in a series or parallel architecture, which receives input current from the I and Q buffers associated with the connected phase-shifted signals. Consequently, the oscillator(s) sum the connected phase-shifted signals and, assuming the injected signals have an appropriate phase relationship with each other for the level of the desired frequency multiplication, cause constructive interference at the desired LO frequency as described herein. This summing may occur in the current domain or the voltage domain depending on the specific oscillator implementation used in various aspects.

[0049] FIG. 8a illustrates an injection-locked clock multiplier (ILCM) using serial injection according to one aspect of the present disclosure. As illustrated in FIG. 8a, the serial injection ILCM (800) is represented by a feedback path (806) connected between a tank circuit (804) and an oscillator circuit (802), which provides a transconductance gain (Gm) representing the gain used in the oscillator circuit (802) to drive the tank circuit and compensate for natural losses. For simplification, details of the oscillator circuit (802) are not illustrated, but aspects include an ILCM (800) implementing any suitable type of oscillator topology. For example, aspects include an oscillator circuit (802) implemented using any known configuration of transistors to provide a suitable transconductance gain. This may include, for example, a common source amplifier, cross-connected transistors, etc. As illustrated in FIG. 8a, the ILCM (800) uses serial injection fixation to connect multiple connected phase-shifted signals to the oscillator circuit (802), which is connected to the tank circuit (804).

[0050] FIG. 8b illustrates an injection-locked clock multiplier (ILCM) using parallel injection according to one aspect of the present disclosure. The ILCM (850) illustrated in FIG. 8b operates in a manner similar to the ILCM (800) illustrated in FIG. 8b. Similar to the ILCM (800) illustrated in FIG. 8a, the ILCM (850) illustrated in FIG. 8b is represented by a feedback path (856) connected between a tank circuit (854) and an oscillator circuit (852), which provides a transconductance gain (Gm) representing the gain used in the oscillator circuit (852) to drive the tank circuit (854) and compensate for natural losses. As with the ILCM (800), details of the oscillator circuit (852) for the ILCM (850) are not shown for simplification, but aspects include the ILCM (850) implementing any type of oscillator topology or known transistor configuration to provide appropriate transconductance gain. As shown in FIG. 8b, the parallel injection fixed configuration of the ILCM (850) directly injects a multi-phase shifted input signal into the tank circuit (854).

[0051] Regardless of whether the ILCM configuration is a serial or parallel implementation, the aspects in this example are f LO / 5 includes a multi-phase shifted signal, which is a 5-phase clock signal, and this entails phase noise. In the case of five multi-phase signals as illustrated in FIGS. 8a and 8b, the phase noise of the injected signal is at the output ("out") of each ILCM (800, 850). It is upconverted to that extent. To provide a more general expression, the aspects are phase noise It includes upconverting to the extent that N is an arbitrary integer used to generate a specific sub-harmonic LO signal frequency (in the example shown in FIG. 8a and 8b, N=2 when there are 5).

[0052] The ILCMs (800, 850) illustrated in FIGS. 8a and 8b, respectively, represent a single oscillator circuit, but the ILCM (306.3) may be implemented with any appropriate number of oscillator circuits to output any appropriate number of LO signals. For example, a phase-shifted input signal output by the phase configuration circuit (306.2) may be connected to any appropriate number of oscillator circuits implemented through the ILCM (306.3). For example, the ILCM (306.3) may implement two different oscillator circuits, one for the in-phase (I) phase-shifted signal and the other for the quadrature phase (Q) phase-shifted component output by the phase configuration circuit (306.2). To provide another example, the ILCM (306.3) may implement an orthogonal oscillator system to receive the I and Q phase-shifted signals output by the phase configuration circuit (306.2) and generate an orthogonal phase-shifted LO signal of a higher frequency as illustrated in FIG. 3. In one aspect, this may be implemented by phase-shifting the LO signal generated through the respective I and Q-only oscillator circuits by 180 degrees (e.g., through an inverter or other suitable circuit component).

[0053] In one aspect, the LO signal output by the ILCM (306.3) can be supplied directly to a higher frequency (e.g., mm-Wave) mixer as shown in FIG. 3. Preferably, since the load of the active mixer is inherently capacitive, it is absorbed by an oscillator circuit implemented as part of the ILCM (306.3) with a fixed capacitance during design, so no additional buffer is required.

[0054] FIGS. 9a through 9d illustrate exemplary oscillator circuits that may be used as the oscillator portion of an injection-locked clock multiplier (ILCM) according to one aspect of the present disclosure. In particular, the oscillator circuits illustrated in FIGS. 9a through 9d include two different oscillator configurations as examples, not limitations. For example, as further described below, FIGS. 9a and 9b illustrate two parts of a complete Quadrature Voltage-Controlled Oscillator (QVCO) implementation, whereas FIGS. 9c and 9d represent mutually exclusive dual VCO implementations. Again, the exemplary oscillator configurations illustrated in FIGS. 9a through 9d are for ease of explanation, and the aspects described herein may implement any suitable number and / or type of oscillator configuration as part of an ILCM circuit. For example, the aspects include the oscillator being implemented as a Colpitts oscillator or a transformer feedback oscillator. In any case, as described in this specification, the aspects include tuning the oscillator to a frequency that is the same or substantially the same (e.g., 1%, 5%, 10%, etc.) as the LO frequency intended.

[0055] In one aspect, the oscillator circuits illustrated in FIGS. 9a, 9b, 9c, and 9d, respectively, can be implemented as part of an ILCM (306.3) as illustrated in FIG. 3 and thus can be identified as oscillator circuits (802, 852) as illustrated in FIGS. 9a and 9b. The oscillator circuits illustrated in FIGS. 9a through 9d can be implemented according to any suitable known oscillator design technique. For example, as illustrated in FIGS. 9a through 9d, QVCO and dual VCO oscillator circuits may include a transistor forming a tank circuit, a tunable capacitor and / or inductor, and a voltage supply Vdd. The tunable components included in the oscillator configuration may be controlled via an ILCM tuning control module (1010), for example, as further described below in relation to FIG. 10.

[0056] Additionally, FIGS. 9a through 9d each illustrate an orthogonal sub-harmonic injection mechanism for coupling a subset of phase-shifted signals generated through a phase configuration circuit (306.2) (as shown in FIG. 3) to an ILCM (306.3) through respective I and Q buffered lines. For example, FIGS. 9a through 9d each illustrate a sub-harmonic signal (902) (for the in-phase component) and a sub-harmonic signal (904) (for the orthogonal phase component) coupled through a parallel inverter array. In the example illustrated in FIGS. 9a through 9d, the sub-harmonic signals (902, 904) are f as discussed herein. LO It can be identified as an orthogonal 5-phase clock signal having a sub-harmonic frequency of / 5 (e.g., multi-phase shifted signal (102) shown in FIG. 1, f shown in FIG. 8a and FIG. 8b, etc.). LO(5-phase clock in / 5). In each of FIGS. 9a to 9d, the injection mechanism is an example, not a limitation, and includes, in any suitable configuration, the injection mechanism being implemented to combine these signals for ILCM injection.

[0057] Now, referring to FIGS. 9a and 9b, an exemplary QVCO implementation shows an orthogonal subharmonic injection mechanism for a subset of phase-shifted signals corresponding to the in-common signal component (Fig. 9a) and the orthogonal phase signal component (Fig. 9b) provided by the phase configuration circuit (306.2) as shown in FIG. 3. As shown in FIG. 9a, the orthogonal subharmonic injection mechanism is a phase-shifted signal (902) associated with each of the in-common components (indicated as I or I+ in FIGS. 9a through 9d) and a 180-degree phase-shifted version thereof (in FIGS. 9a through 9d). (or denoted as I-) is connected, and this is coupled to the tank circuit input as shown on the right side of Fig. 9a. Thus, the QVCO implementation shown in Fig. 9a uses an injected and coupled subset of the phase-shifted signal corresponding to the in-phase signal component to obtain the quadrature phase LO signal component (here or generates (indicated as Q+, Q- respectively).

[0058] Similarly, in FIG. 9b, the quadrature sub-harmonic injection mechanism combines the phase shift signal (904) associated with each quadrature phase component (Q+) as well as its 180-degree phase-shifted version (Q-), and connects this to the tank circuit input as shown on the left side of FIG. 9b. Thus, the QVCO implementation shown in FIG. 9b generates in-phase LO signal components I+ and I- by using the injected and combined subset of the phase-shifted signals corresponding to the quadrature phase signal components Q+ and Q-. In this way, the QVCO implementation as shown in FIG. 9a and FIG. 9b can use the combined sub-harmonic phase-shifted signals of each signal component I+, I-, Q+, and Q-, which are multiplied in frequency while suppressing unintended harmonics as described herein. Thus, as shown in FIG. 3, the sub-harmonic frequency f in this example is as described herein. LO / 5, or f LO Generates an orthogonal differential LO signal (in this example) with a higher frequency multiple of .

[0059] Now, referring to FIGS. 9c and 9d, an exemplary dual VCO implementation illustrates an orthogonal sub-harmonic injection mechanism for a subset of phase-shifted signals (902, 904) corresponding to the in-common signal components I+, I- (in FIG. 9c) and the orthogonal phase components Q, Q+ (in FIG. 9d) provided by the phase configuration circuit (306.2), as illustrated in FIG. 3. The orthogonal sub-harmonic injection mechanism illustrated in FIGS. 9c and 9d may operate in the same or substantially similar manner as the orthogonal sub-harmonic injection mechanism illustrated in FIGS. 9a and 9b, but this is not limited to exemplary. As illustrated in FIG. 9c, the orthogonal sub-harmonic injection mechanism combines the phase-shifted signal (902) associated with the in-common components I+, I-, which is connected to the tank circuit input as illustrated on the right side of FIG. 9c. Similarly, in FIG. 9d, the quadrature sub-harmonic injection mechanism combines the phase-shifted signal (904) associated with quadrature phase components Q and Q+, which is connected to the tank circuit input as shown on the left side of FIG. 9d. In this way, the individual VCO configurations shown in FIG. 9c and 9d, respectively, can generate half of the entire quadrature differential LO signal (in this example) shown in FIG. 3.

[0060] FIG. 10 illustrates a block diagram of a device according to aspects of the present disclosure. In various aspects, the device (1000) may be implemented as any suitable type of device configured to transmit and / or receive wireless signals according to any suitable number and / or type of communication protocol. For example, the device (1000) may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. Providing additional embodiments, the device (1000) may be implemented as an access point or a base station. The device (1000) may implement one or more aspects as described herein to facilitate the reception of wireless signals according to a frequency or frequency band, such as, for example, a mm-Wave frequency further described below.

[0061] In one aspect, the device (1000) may include a processing circuit (1002), a memory (1004), and any suitable number (N) of transceiver chains (1012.1 to 1012.N), each receiving chain being connected to one or more respective antennas (1014.1 to 1014.N). The components illustrated in FIG. 10 are provided for convenience of explanation, and aspects include the device (1000) including additional, fewer, or alternative components compared to those illustrated in FIG. 10. For example, the device (1000) may include one or more power sources, display interfaces, peripheral devices, ports, etc. Providing additional embodiments, the device (1000) may additionally include one or more transmitter or receiving chains as an alternative to the transceiver chains (1012.1 to 1012.N), each capable of receiving and transmitting wireless signals through antennas (1014.1 to 1014.N).

[0062] In one aspect, various components of the device (1000) may be identified as functions further described herein by reference to the generation of an LO signal using a common reference or input signal at a sub-harmonic of the LO frequency. For example, the wireless device (1000) may be configured to receive a wireless signal through one or more antennas (1014.1 to 1014.N) at a mm-Wave or other suitable frequency, and to demodulate and process data included in the wirelessly received signal through a transceiver chain (1012.1 to 1012.N). One or more of the transceiver chains (1012.1 to 1012.N) illustrated in FIG. 10 may be identified as transceiver chains that include, for example, each receiving chain of a receiving chain (RX-1 to RX-K) as illustrated in FIG. 3 and each LOG unit (304.1 to 304.K) as illustrated in FIG. 3. Accordingly, the receiving chain (1012.1 to 1012.N) may include additional components (mixer, demodulator, filter, amplifier, etc.) to generate an LO signal from a common PLL operating at a sub-harmonic LO frequency, as discussed in this specification.

[0063] To this end, the processor circuit (1002) may be composed of any suitable number and / or type of computer processors capable of facilitating the control of the device (1000) as described herein. In some aspects, the processor circuit (1002) may be identified as a baseband processor (or suitable parts thereof) implemented by the device (1000). In other aspects, the processor circuit (1002) may be identified as one or more processors implemented by the device (1000) distinct from the baseband processor. In any case, aspects include the processor circuit (1002) being configured to perform arithmetic, logical, and / or input / output (I / O) operations, and / or to execute instructions for controlling the operation of one or more components of the device (1000). For example, the processor circuit (1002) may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include the processor circuit (1002) communicating with the memory (1004) and / or transceiver chain (1012.1 to 1012.N) and / or controlling associated functions. This may include, for example, controlling and / or arbitrating the transmission and / or reception functions of the device (1000), and performing one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.).

[0064] In one aspect, the memory (1004) stores data and / or instructions so that when instructions are executed by the processor circuit (1002), the processor circuit (1002) performs various functions described herein. The memory (1004) may be implemented as any well-known volatile and / or non-volatile memory, including, for example, read-only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical discs, eraseable and programmable read-only memory (EPROM), programmable read-only memory (PROM), etc. The memory (1004) may be fixed, removable, or a combination thereof.

[0065] For example, memory (1004) may be implemented as a non-transient computer-readable medium that stores one or more executable instructions, such as logic, algorithms, executable code, etc. As further discussed below, the instructions, logic, code, etc. stored in memory (1004) are represented by various modules, such as those illustrated in FIG. 10, which enable the aspects disclosed herein to be functionally realized. The modules illustrated in FIG. 10 are provided for convenience of explanation regarding the functional relationship between hardware components and software components. Accordingly, the aspects include the processor circuit (1002) executing instructions stored in each of these modules together with one or more hardware components to perform various functions associated with the various aspects, as further described herein.

[0066] In one aspect, the executable instruction stored in the phase generation module (1006), together with the processor circuit (1002), can facilitate the generation of a phase through any suitable type of DLL (e.g., DLL (400, 500, 600, etc.)). For example, the executable instruction stored in the phase generation module (1006) may provide functions associated with a phase detector and a loop filter (402) as shown in FIG. 4 to manage the control of an M-stage controlled delay line (404) for a DLL (400) or a DLL (500) according to a specific embodiment used by the device (1000). In another embodiment, the executable instruction stored in the phase generation module (1006) may provide functions associated with a DLL-X core (602) and a DLL-Y core (604), respectively, as shown in FIG. 6, to control the phase generated by a two-dimensional DLL (600).

[0067] In one aspect, an executable instruction stored in the phase control module (1008) can facilitate the selection of a phase generated by a DLL implemented by the device (1000) together with the processor circuit (1002). For example, an executable instruction stored in the phase control module (1008) can provide a function associated with a phase control block (308) as illustrated in FIG. 3. Thus, the phase control module (1008) ensures that a suitable subset of phase-shifted signals is injected into the ILCM (306.2) so as to select a subset of phase-shifted input signals generated by the implemented DLL, thereby ensuring the occurrence of frequency multiplication, suppressing unwanted harmonics, and ensuring that LO signals are generated at the appropriate phase for each transceiver chain (1012.1 to 1012.N). For example, the phase control module (1008) can facilitate the processing circuit (1002) to interface and communicate with the phase configuration circuit (306.2) and to generate a control signal that causes the phase configuration circuit (306.2) to connect a subset of the upper set of phase-shifted signals generated by the DLL (306.1) as in FIG. 3 to the I and Q buffer lines.

[0068] The phase control module (1008), in implementation, may include instructions related to how to generate a specific frequency and phase from a sub-harmonic frequency phase combination. For example, executable instructions stored in the phase control module (1008) may include lookup tables and / or instructions related to calculations to be performed to determine a specific set of phases that will generate a desired LO signal set with an optional phase shift at a target (multiplied) frequency. In the case of orthogonal LO, these instructions allow each transceiver chain (1012.1 to 1012.N) to select a subset of the DLL-generated phases, for example, for signal downconversion, a desired LO signal component (I, as illustrated in FIG. 3 , Q and Can generate ).

[0069] In one aspect, executable instructions stored in the ILCM tuning control module (1010) can likewise facilitate the processing circuit (1002), together with the processor circuit (1002), to interface, communicate, and / or control one or more components of the ILCM (306.3) as illustrated in FIG. 3. For example, although not illustrated in the drawings for brevity, one or more components of the ILCM (306.3) may be electronically tuned. This may include, for example, one or more components of the tank circuit (804, 854) or any other suitable component of the ILCM (306.3), as illustrated in FIG. 8a and FIG. 8b. Continuing this example, executable instructions stored in the ILCM tuning control module (1010) can facilitate the generation of tuning control signals capable of changing the inductance, capacitance, resistance, etc., of the components implemented by the ILCM (306.3).

[0070] When implemented, the ILCM tuning control module (1010) may include instructions regarding a method of tuning the ILCM (306.3) for a specific operating frequency of the device (1000) for an injected multi-phase signal having a specific frequency of a certain frequency range, etc. For example, executable instructions stored in the ILCM tuning control module (1010) may include lookup tables and / or instructions regarding calculations to be performed to determine a specific combination of tuning values ​​(e.g., inductance, capacitance, resistance, etc.) to dynamically adapt to changes in the frequency of the injected multi-phase signal.

[0071] Section II - Local Oscillator (LO) Generation for Carrier Aggregation of Phase Array Front End

[0072] The aspects described in this section generally relate to transceiver designs that implement a single phase-locked loop (PLL) LO generation for a transceiver, specifically for a phase array front end.

[0073] RF transceivers require a local oscillator (LO) at the channel frequency or a local oscillator (LO) near the channel frequency for mixing. For example, one or more LO signals must be generated at each carrier frequency or channel of interest, and each transceiver chain may use a separate set of LO signals for phase array applications. Additionally, inter-band Carrier Aggregation (CA), which requires two LO frequencies simultaneously, increases the number of LO signals implemented by phase array transceiver designs and further complicates the issues associated with LO signal generation and distribution. For instance, in the case of digital phase arrays, the number of LO signals can exceed 16, causing LO distribution to consume a significant portion of system power. Consequently, generating and distributing high-frequency LO signals (e.g., mm-wave frequencies) in on-chip implementations is not simple and requires substantial power. Therefore, generating the LO signals required for these transceivers is a complex, costly, and time-consuming task.

[0074] Many RF transceiver designs implement orthogonal multi-phase LO for use in phase array applications. In mm-Wave phase array applications, since phase noise can be a major cause of Error Vector Magnitude (EVM) degradation, transceiver designs must generate multispectral pure (orthogonal) LO at mm-Wave frequencies while maintaining low power consumption. However, as mentioned above, conventional mm-Wave transceivers use LO distribution schemes that consume a significant amount of power.

[0075] As further mentioned in this section and in other sections, the term “mm-Wave frequency” in which the aspects described in this section and in other sections may operate may include frequencies and frequency bands up to and above frequencies, such as, for example, 20 GHz, 24 GHz, 28 GHz, etc. For example, the mm-Wave frequency band may include frequencies in the range of 20 GHz to 300 GHz, 24 GHz to 300 GHz, etc. This may include various bands known to be associated with or referred to as mm-Wave frequency bands, such as, for example, 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc.

[0076] Typical solutions for generating these signals involve the use of multiple high-performance, fractional phased-locked loops (PLLs). However, particularly for digital phased arrays, a large number of mm-wave LO frequency distribution networks are required. Consequently, these conventional solutions consume a significant amount of power along with large overhead.

[0077] Therefore, to address these issues, the aspects described herein combine a fractional divider, a digital-to-time converter (DTC), and a frequency multiplier to generate multiple mm-Wave LO signals at different individual frequencies. As further described below, this can be accomplished using one or more dies or "chips." Preferably, these aspects require only a single low-to-medium frequency (RF) reference signal generator (i.e., a common frequency synthesizer), which is easier to divide than higher mm-Wave signals. Furthermore, the spectral purity of the LO signal can be controlled by the reference signal generator, and thus the high-frequency LO generation aspects described herein introduce only a small amount of additional noise during operation.

[0078] The aspects described herein also facilitate LO signal distribution at lower (e.g., RF) frequencies, which consume significantly less power and require significantly less design effort compared to the distribution of higher mm-Wave LO signals. Furthermore, the aspects described herein are particularly useful for digital beamforming array operations and can be extended to multiple transceiver chains that can be distributed off-chip using optionally less expensive low-frequency cabling or board traces. By distributing LO signals at lower frequencies in this manner, the aspects described herein eliminate the need to design an entire PLL to generate multi-frequency signals. Thus, the aspects described herein require less die area and consume less power compared to a typical phase array design that uses a PLL for generating and distributing higher-frequency LO signals.

[0079] As described in more detail below, aspects include distributing a mid-to-low frequency reference clock generated from a single frequency synthesizer and implementing frequency multiplication directly in each mixer. Aspects further described herein may include additional variations. One of the primary applications using the aspects described herein involves using a large array of mixers in a digital beamformer. Another primary application involves a two-die solution in which intermediate (IF) LO ​​generation and mm-Wave LO generation are separated by a certain distance within the overall system. Furthermore, the aspects described herein may be particularly useful for carrier aggregation (CA), as CA requires the simultaneous generation of two or more LO frequencies that are not integer-related (i.e., not proportional through integer scaling). Accordingly, to support these various configurations, the aspects include an array and / or addition of various blocks, which may include fractional dividers, digital-to-time converters (DTCs), and edge-coupled frequency multipliers.

[0080] FIGS. 11a through 11c illustrate examples of transceiver architectures that implement a single-die digital beamformer using multiple frequency operating bands according to one aspect of the present disclosure. As shown in FIG. 11a, the transceiver architecture (1100) is f synthIt includes a frequency synthesizer (1102) configured to generate a reference signal (1108) having a frequency indicated by . In one aspect, the frequency synthesizer (1102) may be implemented using any suitable and / or known circuit component to generate the reference signal (1108), which may include a PLL (e.g., a digital PLL) configured to generate low-level phase noise. Furthermore, aspects include a transceiver architecture (1100) having any suitable number of transceiver chains, each transceiver chain being connected to each set (e.g., one or more) of antenna elements associated with a phase array front end. Aspects include the frequency synthesizer (1102) being a common reference frequency generator used by each transceiver chain.

[0081] In the various aspects described herein, a common frequency synthesizer (e.g., frequency synthesizers (1102, 1202, 1302), etc.) may be implemented within various transceiver architectures utilizing different types of conversion technologies. For example, a transceiver architecture (1100) as illustrated in FIGS. 11a through 11c uses direct conversion (i.e., homodyne). By using direct conversion technology, the exemplary transceiver architecture (1100) illustrated in FIGS. 11a through 11c may preferably be implemented as part of a single die or chip. In other words, the transceiver circuit and the phase array front-end circuit may be integrated into a single die. However, the transceiver architectures (1200, 1300) illustrated in FIGS. 12a, 12b, and FIGS. 13a through 13c, and further described herein, use superheterodyne conversion. In the case of a transceiver architecture (1200, 1300), as further described in this specification, preferably, the transceiver circuit and the phase array front end circuit can utilize the use of an intermediate frequency (IF) to transmit the converted IF signal through a cable or trace to a separate die associated with the phase array front end.

[0082] In any case, the aspects described herein have a frequency f lower than the frequency of the transmitted or received signal. synth A single-frequency synthesizer is used to generate a reference signal. For example, the reference frequency signal is a frequency f of several GHz. synth While it may have, the transmitted upconverted signal may be several times this frequency, such as a frequency associated with the mm-Wave band, for example. Thus, the transceiver architecture aspects described herein can simplify the design of the PLL circuit implemented through the frequency synthesizer, thereby lowering power consumption.

[0083] Referring further to FIG. 11a, to utilize a lower frequency reference signal, the transceiver architecture (1100) may implement different component configurations based on the level and / or amount of granularity of frequency control required in relation to the frequency scaling of the reference signal (1108). In various aspects, these optional components may be implemented alone or in combination with each other when implemented. For example, aspects include the reference signal (1108) being supplied to a digital-to-time converter (DTC) (1104A) directly or through an optional frequency divider circuit (1106). f synth When additional control or granularity is required to provide a frequency-divided reference signal having a frequency corresponding to a fraction of , an optional frequency divider circuit (1106) may be configured. Accordingly, aspects include the optional frequency divider circuit (1106) being implemented through any suitable and / or known circuit component configured to perform frequency division of the reference signal (1108). For convenience of explanation, this frequency division factor may be referred to herein as γ, and thus the frequency of the signal supplied to the DTC (1104A) when the optional frequency divider circuit (1106) is implemented Makes it so.

[0084] In various aspects, the DTC (1104A) is a non-integer method of the frequency f of the reference signal (1108). synthIt is configured to output a fractionally multiplied reference signal (1110) having a frequency scaled by . As further described herein, using a fractionally multiplied frequency relationship between the reference signal (1108) and the fractionally multiplied reference signal (1110) may be particularly useful for transceiver applications where individual carrier frequencies are used, which may have a non-integer scaled relationship with respect to each other (e.g., for CA applications used according to mm-Wave frequency bands).

[0085] The aspects include having any suitable configuration that can be implemented using any suitable circuit component and / or known circuit component configured to convert a digital phase ramp received by the DTC (1104A) into a fractional frequency shift. For example, if the optional frequency divider circuit (1106) is not used, the aspect is that the DTC (1104A) It includes generating a fractional-multiplied reference signal (1110) having a ratio expressed as . Aspects include the DTC (1104A) performing fractional frequency multiplication of the reference signal (1108) up to a scaling factor of 1.0, so that the reference signal (1108) and the fractional-multiplied reference signal (1110) have the same frequency. As another example, where an optional frequency divider circuit (1106) is used, aspects include the DTC (1104A) It includes generating a fraction-multiplied reference signal (1110) having a ratio expressed as . Furthermore, although shown as separate components in FIG. 11a, aspects include the optional frequency divider circuit (1106) and the DTC (1104A) being combined as a single circuit component. For example, the optional frequency divider circuit (1106) can output signals in a phase relationship orthogonal to each other, and this output from the optional frequency divider circuit (1106) can be utilized to reduce the number of stages of the delay line implemented through the DTC (1104A).

[0086] Although the transceiver architecture (1100) may optionally include another DTC (1104B) configured in a manner similar to or identical to DTC (1104A), DTCs (1104A, 1104B) may be configured to independently provide frequency division according to their respective division values. Accordingly, the fraction-multiplied reference signal provided in the low-band path illustrated in FIG. 11a and further described herein may be a lower frequency that is the same frequency as or part thereof as the reference signal (1108). In addition to this, or alternatively, the reference signal (1108) provided in the high-band path may be the frequency f of the reference signal (1108). synth It could be a lower frequency that is a fraction of that, for example, through the use of DTC(1104B).

[0087] Aspects include the transceiver architecture (1100) providing a reference signal (1108) and a fractional-multiplied reference signal (1110) through a high-band path and a low-band path, respectively, and each frequency can be dynamically adjusted and may have a non-integer relationship with each other. For example, DTCs (1104A, 1104B) may provide their respective fractional frequency multiplications according to the received digital phase ramp values. Although not illustrated for the optional DTC (1104B), each of the DTCs (1104A, 1104B) may operate in a similar manner in this regard. Thus, DTC (1104A) and / or DTC (1104B) may receive digital values ​​representing each digital phase ramp that generates the desired fractional frequency multiplication (e.g., via one or more control lines). These digital phase ramp values ​​may be generated and transmitted through any appropriate type of processor circuit. Processor control of the DTC (1104A) and / or DTC (1104B) may be implemented by executing stored instructions by one or more hardware processors, for example, as further described herein. Similarly, an optional frequency divider circuit (1106) controls the frequency f of the reference signal (1108). synth Digital control signals may also be received through one or more processor components to change the frequency division factor applied to it.

[0088] Regardless of whether the optional frequency divider (1106) is implemented, the transceiver architecture aspects described herein may allow mid-low frequencies to be distributed to each of the phase array elements within the transceiver architecture. Furthermore, the fractional ratios introduced by the optional frequency divider (1106) and / or DTC (1104A, 1104B) do not need to be integer ratios to each other, according to the aspects described herein. This may be particularly useful, for example, in relation to microchanneling in cellular band applications (e.g., <1 MHz) and CA applications.

[0089] Now, referring to FIG. 11b and FIG. 11c, which respectively represent a successive high-band (HB) path and a low-band (LB) path as illustrated in FIG. 11a, the transceiver architecture (1100) generates any appropriate number of LO signals using a reference signal (1108) and a fractionally multiplied reference signal (1110). In particular, the transceiver architecture (1100) illustrated in FIG. 11b receives the reference signal (1108) as an input and generates any appropriate number of HB LO signals through an injection fixed-frequency multiplier (ILFM) (1120.1 to 1120.A). Furthermore, as illustrated in FIG. 11c, the transceiver architecture (1100) receives the fractionally multiplied reference signal (1110) as an input and generates any appropriate number of LB LO signals through an ILFM (1130.1 to 1130.B).

[0090] In various aspects, the IFLM (1120, 1130) may be implemented using any suitable type of ILFM circuit, which may include, for example, a known ILFM configuration. In other aspects, the IFLM (1120, 1130) may be implemented using the ILCM (306.3) described herein with reference to FIGS. 1 through 10, which may be implemented using a serial or parallel injection architecture. For example, the frequency synthesizer (1102) and the frequency synthesizer (1202, 1302) described further below may be represented as a PLL (302) as shown in FIG. 3. Continuing this example, the transceiver architecture (1100) may be represented as part of a transceiver design (300) as shown in FIG. 3. For example, an HB path as illustrated in FIG. 11b may be associated with any suitable number of transceiver chains, of which four are illustrated in FIG. 11b. Each transceiver chain may include each ILFM (1120.1 to 1120.A), and each IFLM (1120) may be represented as one of the LOG units (304) illustrated in FIG. 3. Additionally, an LB path as illustrated in FIG. 11c may be associated with any suitable number of transceiver chains, of which four are illustrated in FIG. 11c. Each transceiver chain may include each ILFM (1130.1 to 1130.B), and each IFLM (1130) may be represented as one of the LOG units (304) illustrated in FIG. 3.

[0091] As further described herein, the IFLM implemented in various aspects relating to FIGS. 11a through 11c and the IFLM described below relating to FIGS. 12a, FIG. 12b and FIGS. 13a through 13c (e.g., IFLM(1120, 1130, 1220, 1305A-1305B, 1352, 1356), etc.) may be represented as an ILCM (306.3) as described above relating to FIGS. 1 through 10. Furthermore, as further described herein, aspects include further modifying these ILFMs to incorporate optional DTCs (e.g., IFLM(1220) and DTC(1210) as illustrated in FIG. 12b). According to these aspects, the DTC may be designed on a common die or may be composed of individual IFLMs as part of a single integrated design, which may be represented as part of one of the LOG units (300) as shown in FIG. 3. In particular, the aspects include implementing a DLL (306.1) (which may be implemented as one of the delay lines (400, 500, 600) as shown in FIG. 4 through 6) to generate a multiphase-shifted signal for both digital time control and edge-coupled multiplier (e.g., one of the architectures of the ILCM (306.3) described above in relation to FIG. 3, FIG. 8a and FIG. 8b).

[0092] FIGS. 11b and FIGS. 11c illustrate that each ILCM (1120, 1130) generates a respective set of frequency-multiplied signals connected to a respective mixer. In one aspect, the fractional-multiplied signals generated by each ILCM (1120, 1130) may correspond to one or more LO signals generated by the ILCM (306.3) as described herein with reference to FIG. 3. In various aspects, as described above, the signals generated by the LO ILCM (1120, 1130) may be a single LO signal or a set of orthogonal LO signals. Where a set of orthogonal LO signals is generated, aspects include each mixer illustrated in FIGS. 11b through 11c actually constituting a mixer set, and each mixer having a unique I, , Q and It involves signal components and orthogonal LO signals corresponding to each received signal component. In other words, the aspects include each transceiver chain associated with an HB path as shown in FIG. 11b and an LB path as shown in FIG. 11c generating its own set of higher frequency orthogonal LO signals to directly downconvert the received signal to baseband. However, the transceiver aspects are not limited to this, and the aspects include the transceiver architecture (1100) generating any appropriate number of LO signals per transceiver chain.

[0093] Aspects include the ILFM (1120, 1130) associated with the HB path and LB path, as illustrated in FIG. 11b and FIG. 11c, respectively, being dynamically adjusted in relation to the frequency multiplication of the LO signal input to each mixer. The amount of frequency multiplication can be controlled and adjusted through appropriate processor circuitry as described herein. For example, in the case of an aspect implementing the ILFM (1120, 1130) as an ILCM (306.3), the frequency multiplication of the input signal for each mixer can be controlled through a phase control block (308) to select a specific set of phase-shifted versions of the reference signal (1108) (for the HB path) and to select a specific set of phase-shifted versions of the fractional-multiplied reference signal (1110) (for the LB path). This type of frequency multiplication described in the previous section in relation to FIG. 1 through 10 may be referred to herein as edge combination frequency multiplication.

[0094] Accordingly, as illustrated in FIG. 11b, each transceiver chain in the HB path can downconvert the signal (RX signal). The ILCM (1120) substantially matches the frequency f of the input signal (1108) by an integer factor to facilitate direct downconversion and to substantially match the frequency of the RX signal in the HB path. synth It can provide an integer frequency multiplication. For example, the RX signal may have a frequency associated with a mm-Wave band frequency. Furthermore, as illustrated in FIG. 11c, each transceiver chain within the LB path may down-convert the RX signal, which may have a frequency associated with, for example, a mm-Wave band frequency. Thus, the ILCM (1130) uses the frequency of the fractional-multiplied reference signal (1110) to substantially match the frequency to the frequency of the RX signal in the LB path. (or depending on the case) It can provide integer frequency multiplication (which may be). In one aspect, the variable used to set the frequency division factor γ and the fractional frequency-multiplication factor can be defined as any suitable integer. Consequently, the resulting fractional frequency-multiplication factor (e.g., (or ) can be a rational number.

[0095] In other words, frequency multiplication is used in each ILFM (1120, 1130) implemented within the HB path and LB path, respectively, to multiply the received reference signal frequency by an integer ratio to create a desired higher frequency (e.g., mm-wave frequency). As mentioned above, since each transceiver chain within the transceiver architecture (100) can generate its own LO signal set, aspects include the integer multiplication performed by each ILFM (1120, 1130) being programmable and / or dynamically adjustable so that each transceiver chain can be independently tuned to support various bands. Furthermore, by using a programmable ratio as described with reference to FIG. 11a, aspects include setting the frequencies of the reference signal (1108) and the fractional-multiplied reference signal (1110) to any appropriate value lower than the frequency of the frequency synthesizer. Aspects include the fact that these frequencies are established using, for example, prior knowledge of cellular or other communication channels used for access and / or using feedback measured during operation. This can facilitate the adaptive use of frequencies to open up preferred frequencies to prevent interference and use without complex frequency planning.

[0096] FIGS. 12a and 12b illustrate an example of a transceiver architecture that implements a multi-die digital beamformer using a single frequency operating band according to one aspect of the present disclosure. Additionally, the transceiver architecture (1200) as illustrated in FIGS. 12a and 12b uses superheterodyne conversion. Furthermore, unlike the transceiver architecture (1100), the transceiver architecture (1200) illustrated in FIGS. 12a and 12b uses a multi-die implementation, and the transceiver circuit and the phase array front-end circuit are implemented on separate dies. Furthermore, the exemplary transceiver architectures (1200, 1300) described below represent a transmission path of upconversion within the transceiver chain for the receiving path of downconversion described above in relation to the transceiver architecture (1100). The aspects described in this specification are equally applicable to downconversion / receiving paths or upconversion / transmission paths, and the process described in this specification is reversible.

[0097] In one aspect, the transceiver architecture (1200) portion illustrated in FIG. 12a has a structure similar to the transceiver architecture (1100) portion illustrated in FIG. 11a and uses similar components. Accordingly, only the differences between these transceiver portions are further described in this specification. For example, the transceiver architecture (1200) illustrated in FIG. 12a, such as the transceiver architecture (1100) illustrated in FIG. 11a, uses a common frequency synthesizer (1202), an optional frequency divider circuit (1206), and one or more DTCs (1204A-B) that generate fractional frequency multiplication of a reference signal generated through the frequency synthesizer (1202) and / or, when the optional frequency divider circuit (1206) is used, generate additional frequency divided versions of the reference signal.

[0098] Furthermore, the portion of the transceiver architecture (1200) illustrated in FIG. 12a may further include a DTC (1204B), which may be connected to the input of the mixer circuit as illustrated to provide additional flexibility for the desired frequency of the upconverted IF signal (1208). In addition to this, or alternatively, the portion of the transceiver architecture (1200) illustrated in FIG. 12a may include an optional IFLM (1205), which is connected to the input of the mixer circuit as illustrated to provide additional flexibility for the desired frequency of the upconverted IF signal (1208).

[0099] The optional IFLM (1205) may be implemented using any suitable type of circuit configured to provide an integer frequency multiplication of the signal generated through the frequency synthesizer (1202). In some aspects, the optional IFLM (1205) may be implemented using known circuit components and / or known configurations that facilitate this function. In other aspects, the optional IFLM (1205) may be implemented as an IFCM (306.3) as described above for the ILFMs (1120, 1130) shown in FIG. 11b and FIG. 11c. In any case, when implemented, the ILFM (1205) may provide a frequency-multiplication value that is adjusted dynamically through processor control. Additionally, as described herein with reference to FIG. 11c, the IFLM (1205) may generate any suitable number of LO signals. In one aspect, the IF mixing stage (e.g., an upconversion and downconversion mixing stage between baseband (BB) and intermediate frequency (IF)) may utilize an orthogonal LO signal, whereas additional upconversion and downconversion stages in the RF mixing stage (i.e., upconversion and downconversion between the IF frequency and other higher frequencies) do not require an orthogonal LO signal (e.g., in a TX mixing stage providing upconversion from IF to a transmission frequency as illustrated in FIG. 12b, or in an RX mixing stage providing downconversion from a transmission frequency to an IF frequency not illustrated). In any case, when an orthogonal LO signal is generated (e.g., by ILCM 1205), aspects include the IF mixing stage as illustrated in FIG. 12a actually constituting a set of mixers, each mixer being I, , Q and An analog IF signal is generated by upconverting an analog baseband signal that matches the phase of the signal component. Thus, the analog IF signal as illustrated in FIG. 12a can constitute a set of orthogonal analog IF signals according to these aspects.

[0100] In various aspects, any combination of the optional frequency divider circuit (1206), DTC (1204A–B), and / or IFLM (1205) may be implemented. In some aspects, one or more of these components may be present in the transceiver implementation, but may be implemented optionally to facilitate greater control over the frequency of the analog IF signal (1208). For example, in a particular design, the DTC (1204B) and IFLM (1205) may both be connected in series with each other, whereas other implementations may include each being optionally enabled or connected to the mixer LO input. In the latter case, the DTC (1204B) may be used to fractionally multiply (i.e., divide) the frequency of the reference signal generated by the frequency synthesizer (1202) used as the LO signal to the IF mixer, while the IFLM (1205) may be enabled when frequency multiplication is required. Regardless of the components implemented, the aspects include the transceiver architecture (1200) generating an upconverted analog IF reference signal (1208) and a fraction-multiplied reference signal (1210).

[0101] Additionally, to limit the number of frequency synthesizers in order to reduce power, area, crosstalk, and design complexity, the frequency synthesizer (1202) may be common to multiple transceiver chains, and the digital interface may be implemented to dynamically adjust the programmable ratio provided by the DTC (1204A, 1204B), frequency divider circuit (1206), IFLM (1205), etc. (not shown). By doing so, the frequencies of the upconverted analog IF reference signal (1208) and the fractionally multiplied reference signal (1210) can be dynamically adjusted.

[0102] As illustrated in FIG. 12b, the transceiver architecture (1200) spans multiple dies and interfaces, with one part (transceiver (1200A)) associated with one die and another part of the transceiver (phase array front end (1200B)) associated with another die. Because the transceiver architecture (1200) implements a superheterodyne system, the die associated with the transceiver part (1200A) and the die associated with the phase array front end part (1200B) each include an IF interface that facilitates the distribution of an upconverted analog IF reference signal (1208) and a fraction-multiplied reference signal (1210) between each die. As illustrated in FIG. 12b, this IF interface may include, for example, one or more cables, traces, etc.

[0103] Because the upconverted analog IF reference signal (1208) and the fractional-multiplied reference signal (1210) are lower frequency signals compared to the transmitted signal, the IF interface can be constructed with lower loss and cheaper components, and is easier to design than a high-frequency solution. Furthermore, as illustrated in FIG. 12b, to limit connections between dies, the aspects include multiplexing the signal into a single cable or trace using a multiplexing block (1214) and a demultiplexing block (1216). Although referred to herein as a multiplexer and a demultiplexer, the multiplexing block (1214) and the demultiplexing block (1216) may be implemented as any suitable type of known component configured to combine and separate signals, respectively.

[0104] For example, the multiplexing block (1214) and the demultiplexing block (1216) may be implemented as any number of electronically tunable components controlled by one or more processors via digital control signals (1212, 1218). In various aspects, the multiplexing block (1214) and the demultiplexing block (1216) may be implemented as any suitable type of component to facilitate one or more of a tunable low-pass filter, a tunable band-stop filter, a tunable high-pass filter, a tunable band-pass filter, etc., which may be coupled to the IF interface (1201) and tuned and frequency-shifted according to a specific band of the IF signal extracted from the IF interface (1201). For example, since the reference signal generated through the frequency synthesizer (1202) is generally a continuous wave (CW) signal, the fractional-multiplied reference signal (1210) may also be a CW signal, and, for example, using a deep and narrow tunable notch filter profile, the demultiplexer (1216) can be tuned to remove the fractional-multiplied reference signal (1210) from the analog IF signal transmitted to the phase array front end (1200B) through the IF interface (1201).

[0105] Referring again to FIG. 12b, the aspects include a phase array front end (1200B) separating a signal transmitted through an IF interface (1201) into an upconverted analog IF reference signal (1208) and a fractional multiplication reference signal (1210). Additionally, the fractional-multiplied reference signal (1210) is the frequency f of the reference signal generated by the frequency synthesizer (1202). synthCompared to, it may include fractional frequency shifts. The phase array front end (1200B) may further include an ILFM (1220), which may be substantially similar or identical to an IFLM (1205) and may also be implemented as an ILCM (306.3) as described herein. Therefore, additional details regarding the ILFM (1220) are not provided for brevity.

[0106] The aspects include the ILFM (1220) receiving a fractional-multiplied reference signal (1210) as illustrated in FIG. 12b and using an integer frequency multiplier to frequency-multiply the fractional-multiplied reference signal (1210) to generate a higher frequency LO signal (1221). The phase array front end (1200B) may optionally include a DTC (1211) to facilitate greater control and tunability of the high-frequency transmission signal, which may operate in a manner similar or identical to the DTC (1204A-B) to provide a fractional frequency shift of the already fractional-multiplied reference signal (1210).

[0107] Additionally, although not illustrated in FIG. 12b for brevity, aspects include the ILFM (1220) generating any appropriate number of high-frequency LO signals (1221) from a fractional-multiplied reference signal (1210) (which may also be fractionally frequency-shifted via an optional DTC (1211)), which may be distributed to any appropriate number of mixers within the TX mixing stage as illustrated, each mixer receiving the upconverted analog IF reference signal (1208) as input to generate a higher frequency signal to transmit. For example, because the ILFM (1220) is implemented within the final mixing stage of a superheterodyne architecture, the ILFM (1220) may provide a single-phase LO signal compared to a multi-phase LO signal (i.e., the BB to IF interface requires orthogonal modulation, while the IF to RF interface requires only frequency conversion). Accordingly, these higher frequency transmission signals can be generated at any appropriate frequency based on fractional multiplication performed in the transceiver (1200A) (and optionally, DTC (1211) is implemented in the phase array front end (1200B)) and integer multiplication performed through the phase array front end (1200B) (e.g., through ILFM (1220)). For example, the high frequency transmission signal may have a frequency within the mm-Wave frequency band.

[0108] FIGS. 13a through 13c illustrate examples of transceiver architectures that implement a multi-die digital beamformer using multiple frequency operating bands according to one aspect of the present disclosure. Additionally, the transceiver architecture (1200) illustrated in FIGS. 12a and 12b uses superheterodyne upconversion. Similar to the transceiver architecture (1200), the transceiver architecture (1300) illustrated in FIGS. 13a through 13c uses a multi-die implementation, and the transceiver circuit and the phase array front-end circuit are implemented on separate dies.

[0109] In one aspect, the transceiver architecture (1300) illustrated in FIGS. 13a through 13c has a structure similar to the transceiver architecture (1200) illustrated in FIGS. 12a and 12b and uses similar components. Therefore, only the differences between these transceiver parts will be further described in this specification. For example, the transceiver architecture (1300) illustrated in FIG. 13a, like the transceiver architecture (1200) illustrated in FIG. 12a, uses a common frequency synthesizer (1302), an optional frequency divider circuit (1306), and a DTC (1304A) to generate fractional frequency multiplication of a reference signal generated through the frequency synthesizer (1302), and / or, if the optional frequency divider circuit (1306) is used, to generate an additional frequency divided version of the reference signal. Furthermore, as with the transceiver architecture (1200) shown in FIG. 12a, the transceiver architecture (1300) shown in FIG. 13a can implement one or more optional DTCs (1304B–C) and IFLMs (1305A–B), which can provide fractional or integer multiplication of a reference signal generated through a frequency synthesizer (1302).

[0110] In this way, the transceiver architecture (1300) illustrated in FIG. 13a can independently provide a set of two different LO signals (or, in some cases, individual signals) to each individual IF mixer. Thus, the portion of the transceiver architecture (1300) illustrated in FIG. 13a can be configured to deliver two individual IF analog signals, each at its own frequency, to the phase array front end as illustrated in FIG. 13b. Again, as described in relation to FIG. 12a and FIG. 12b, when the orthogonal LO signal is generated by the IFLM (1305A, 1305B), the analog IF signal illustrated in FIG. 13a may include a set of orthogonal signal components. However, the transceiver architecture (1300) illustrated in FIG. 13a can provide additional IF signals (or sets of IF signals) compared to the transceiver architecture (1200) illustrated in FIG. 12a. This may be particularly useful for applications that use two independent carrier frequencies simultaneously for communication, such as CA applications, for example. Regardless of the various optional components implemented, aspects include the transceiver architecture (1300) generating two upconverted analog IF signals (1308, 1309) and a fraction-multiplied reference signal (1310).

[0111] Now, referring to FIG. 13b, a transceiver architecture (1300) similar to the transceiver architecture (1200) also spans multiple dies and interfaces, where the transceiver portion (1300A) is associated with one die and the phase array front end portion (1300B) is associated with another die. The transceiver architecture (1300) also includes an IF interface (1301) that facilitates the distribution of upconverted analog IF signals (1308, 1309) and fractionally multiplied reference signals (1310) between each die. Furthermore, as illustrated in FIG. 13b, the transceiver architecture (1300) includes a multiplexing block (1314) and a demultiplexing block (1316) to facilitate the combination of upconverted analog IF signals (1308, 1309) and fractional-multiplied reference signals (1310) and extraction from the IF interface (1301) to provide separate signals as illustrated in FIG. 13b.

[0112] Now, referring to FIG. 13c, the aspects are such that the fractionally multiplied reference signal (1310) is the frequency f of the reference signal generated by the frequency synthesizer (1302). synthCompared to, it includes having a fractional frequency shift. The phase array front end (1300B) may further include two separate mixers (or a set of mixers, each mixer being shown as representing the in-phase and quadrature phase paths described above in relation to FIG. 12b) for upconverting the upconverted analog IF signals (1308, 1309) into HB and LB transmission signals, respectively. For example, each mixer as shown in FIG. 13c may be associated with a separate upconversion frequency, where one mixer generates the HB transmission signal and the other mixer generates the LB transmission signal. In one aspect, these high-band and low-band transmission signals may be mm-Wave frequencies implemented according to the CA communication scheme, but the aspects described herein are not limited to this particular application and may be driven according to any suitable frequency band and / or communication protocol.

[0113] Furthermore, the phase array front end (1300B) may include ILFM (1352, 1356), where ILFM (1352) provides an HB LO signal to the HB mixer input. The HB LO signal (1353) may represent the integer frequency multiplication of the fractional-multiplied reference signal (1310) (or its additional fractional multiplication if the optional DTC (1350) is also implemented). Similarly, ILFM (1356) may provide an LB LO signal (1357) to the LB mixer input. The LB LO signal (1357) may represent the integer frequency multiplication of the fractional-multiplied reference signal (1310) (or its additional fractional multiplication if the optional DTC (1350) is also implemented).

[0114] The optional DTC (1350, 1354) may be substantially similar or identical to the optional DTC (1211) shown in FIG. 12b as described herein, while the IFLM (1352, 1356) may be substantially similar or identical to the IFLM (1220) as shown in FIG. 12b. In other words, the IFLM (1352, 1356) may also be implemented as an ILCM (306.3) as described herein. Additionally, as described herein for the transceiver architecture (1100, 1200), aspects include ILFM (1352, 1356) generating any suitable number of high-frequency LO signals (1353, 1357) using a fractional-multiplied reference signal (1310) (which may be further fractionally frequency-shifted via an optional DTC (1350, 1354). As described above, the high-frequency LO signals (1353, 1357) may be one of multiple LO signals distributed to any suitable number of individual mixers, each HB and LB mixer receiving an upconverted analog IF signal (1308, 1309) as an input to generate a higher frequency signal for transmission.

[0115] The aspects include the frequency ratio provided by the DTC (1304A-C, 1350, 1354), the frequency multiplication provided by the IFLM (1305A, 1305B, 1354, 1356), and / or the frequency division provided by the frequency divider circuit (1306) being programmable so that a number of different frequency bands can be selected and adjusted dynamically, and can be dynamically modified during communication or other appropriate periods. As a result of this flexibility, the hardware associated with the transceiver architecture (1300) can be reused for different operating frequency bands and / or used simultaneously to provide different operating frequency bands (e.g., in CA applications). Thus, high frequency bands and low frequency bands can be set and adjusted independently, and a frequency can be selected to prevent cross-talk or other known or detected sources of interference.

[0116] FIG. 14 illustrates a block diagram of a device according to aspects of the present disclosure. In various aspects, the device (1400) may be implemented as any suitable type of device configured to transmit and / or receive wireless signals according to any suitable number and / or type of communication protocol. For example, the device (1400) may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. To provide additional examples, the device (1400) may be implemented as an access point or base station. The device (1400) may implement one or more aspects as described herein to facilitate the transmission of wireless signals according to a frequency or frequency band, such as, for example, a mm-Wave frequency, which is further described below. In various aspects, the device (1400) may include additional functions or alternative functions of the device (1000) described in relation to FIG. 10.

[0117] In one aspect, the device (1400) may include a processor circuit (1402), a memory (1404), and any suitable number (K) of transceiver chains (1412.1 to 1412.K), each transceiver chain being connected to one or more respective antennas (1414.1 to 1414.K). The components shown in FIG. 14 are provided for convenience of explanation, and aspects include the device (1400) including additional, fewer, or alternative components compared to those shown in FIG. 14. For example, the device (1400) may include one or more power sources, display interfaces, peripherals, ports, etc. In providing additional embodiments, the device (1400) may further include one or more transmitters and / or receivers, or the transceiver chain (1412.1 to 1412.K) may be implemented as a transmitter configured to transmit a wireless signal through an antenna (1414.1 to 1414.K) in another manner.

[0118] In one aspect, various components of the device (1400) may be identified as functions further described herein in relation to the generation of an LO signal using fractional frequency multiplication. For example, the wireless device (1400) may be configured to transmit a wireless signal through one or more antennas (1414.1 to 1414.N) at mm-Wave or other suitable frequencies, and to demodulate and process data included in a signal received wirelessly through a transceiver chain (1412.1 to 1412.N). The receiving chain (1412.1 to 1412.N) may be identified, for example, as each receiving chain of the receiving chains (RX-1 to RX-K) as illustrated in FIG. 3, and each includes a respective LOG unit (304.1 to 304.K) as illustrated in FIG. 3.

[0119] In one aspect, the processor circuit (1402) may be composed of any suitable number and / or type of computer processors capable of facilitating the control of the device (1400) as described herein. In some aspects, the processor circuit (1402) may be identified as a baseband processor (or suitable parts thereof) implemented by the device (1400). In other aspects, the processor circuit (1402) may be identified as one or more processors implemented by the device (1400) distinct from the baseband processor. In any case, aspects include the processor circuit (1402) being configured to perform arithmetic, logical, and / or input / output (I / O) operations, and / or to execute instructions for controlling the operation of one or more components of the device (1400). For example, the processor circuit (1402) may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include the processor circuit (1402) communicating with the memory (1404) and / or transceiver chain (1412.1 to 1412.N) and / or controlling associated functions. This may include, for example, controlling and / or arbitrating the transmission and / or reception functions of the device (1400), and performing one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.).

[0120] In one aspect, the memory (1404) stores data and / or instructions so that when instructions are executed by the processor circuit (1402), the processor circuit (1402) performs various functions described herein. The memory (1404) may be implemented as any well-known volatile and / or non-volatile memory, including, for example, read-only memory (ROM), random access memory (RAM), flash memory, magnetic storage media, optical discs, eraseable and programmable read-only memory (EPROM), programmable read-only memory (PROM), etc. The memory (1404) may be fixed, removable, or a combination thereof.

[0121] For example, memory (1404) may be implemented as a non-transient computer-readable medium that stores one or more executable instructions, such as logic, algorithms, code, etc. As further discussed below, the instructions, logic, code, etc. stored in memory (1404) are represented by various modules, such as those illustrated in FIG. 14, which enable the aspects disclosed herein to be functionally realized. The modules illustrated in FIG. 14 are provided for convenience of explanation regarding the functional relationship between hardware components and software components. Accordingly, the aspects include the processor circuit (1402) executing instructions stored in each of these modules together with one or more hardware components to perform various functions associated with the aspects, as further discussed herein.

[0122] In one aspect, an executable instruction stored in the DTC control module (1406) can facilitate the generation of digital phase ramp data transmitted to various DTCs implemented through the transceiver architecture (1100, 1200, 1300) together with the processor circuit (1402) as described herein. For example, an executable instruction stored in the DTC control module (1406) can control one or more DTCs to generate a partial phase shift as a function of the digital phase ramp data. In one aspect, the digital phase ramp data can be selected based on a correlation for a desired fractional frequency shift, which can be calculated, for example, through an appropriate algorithm, function, lookup table (LUT), etc., and can be stored in memory (1404) or accessed by the processor circuit (1402).

[0123] In one aspect, an executable instruction stored in the frequency multiplier / divider control module (1408) facilitates generating and transmitting a control signal to set an appropriate value for an ILFM (e.g., IFLM (1120, 1130, 1205, 1220, 1305A, 1305B, 1352, 1356, 1352, 1356) etc.) implemented through a frequency divider circuit (e.g., 1106, 1206, 1306, etc.) and / or a transceiver architecture (1100, 1200, 1300) as disclosed herein, together with the processor circuit (1402). For example, executable commands stored in the frequency multiplier / divider control module (1408) may cause the generated reference frequency to be divided and / or divided and multiplied before or after upconversion through the frequency divider circuit and the frequency multiplier, depending on the specific implementation of the transceiver architecture. As another example, the function associated with the frequency multiplier / divider control module (1408) may also set the desired integer multiplication through various ILFMs as described herein. Again, these values ​​may be dynamically changed to provide flexibility with respect to one or more transmission frequencies used during the operation of the device (1400), and may be selected based, for example, on the desired transmission frequency, prior knowledge of the operation, measured feedback, etc., as described herein. In one aspect, the value generated by the frequency multiplier / divider control module (1408) may be selected based on the correlation of the desired change in the frequency of the input signal for each controlled component. This may be calculated, for example, through an appropriate algorithm, function, LUT, etc. stored in memory (1404), or accessed by a processor circuit (1402).

[0124] In one aspect, executable instructions stored in the tuning control module (1410) facilitate generating and transmitting control signals to tune a multiplexer (e.g., multiplexer (1214, 1314)) and a demultiplexer (e.g., demultiplexer (1216, 1316)) to facilitate an IF interface between individual transceivers and a phase array front-end die, as described in the specification, for example, in relation to FIGS. 12b and 13b, together with the processor circuit (1402). In one aspect, executable instructions stored in the tuning control module (1410) may include instructions for calculations to be performed to derive a set of appropriate algorithms, functions, LUTs, etc., and / or tuning parameters, which may yield a specific filter type and / or filter response that enables the combination of signals in the transceiver die and the extraction and separation of these signals in the phase array front-end die. Therefore, these tuning parameters can facilitate appropriate bandwidth, filter coefficients, etc., based on the current IF frequency band transmitted through the IF interface. Additionally, these tuning parameters include dynamic adjustment according to the currently used IF frequency, and can be changed according to operating conditions to prevent cutoff signals based on measured feedback, etc.

[0125] Section III - Array Element-Level Control Using Per-Chain DC-DC Converters

[0126] The aspects described in this section generally relate to transceivers, and more specifically to a multi-transceiver chain architecture that implements a dedicated DC-DC converter for each transceiver chain.

[0127] The RF front-end can implement phased array antennas for beam steering on both the User Equipment (UE) and base station sides. On the UE side, a common configuration is to implement an analog phased array in which signals from multiple (e.g., four or more) antennas are consistently combined with appropriate phase and amplitude weights to scan a beam in a specific direction. However, due to the requirement for consistent power coupling, tuning at the element level (i.e., components within each transceiver chain) is limited. Consequently, current transceiver architectures may face performance limitations that cannot be easily resolved.

[0128] As described in this specification, current transceiver architectures may have performance limitations that are not easily resolved. Some examples of these performance limitations include the influence of the enclosure, variations in semiconductor processes and aging, variations in the packaging process, wireless link conditions, and mutual coupling between antennas, which can cause mismatch between the amplifier and the antenna as the beam is steered widely laterally. Typically, this results in output power fluctuations, increased side-lobes, and beam pointing errors. Another example of a performance limitation in current transceiver designs involves creating a suboptimal bias setting for some amplifiers compared to other amplifiers within a specific transceiver chain when amplitude tapering is implemented to reduce side-lobe levels, which can waste DC power and cause overheating.

[0129] Moreover, temperature differences across the die implemented in traditional transceiver architectures can cause performance differences between transceiver chains. And process changes, while limited to a single chip, can further exacerbate these effects. Additionally, existing transceiver architectures may experience issues such as failure or shutdown of individual elements when temperatures exceed thermal thresholds, which can cause problems with the overall array operation (pointing errors, low Pout, side lobes, grating lobes, etc.).

[0130] Conventional transceiver architectures, which further complicate this problem, typically use one or two data streams (in the case of MIMO (multiple-input multiple-output) operation) and feed them into separate analog phase arrays used to perform beam scanning by setting appropriate phase and amplitude weights for various transceiver chains. In these conventional transceiver architectures, a small number of DC-DC converters are used to supply different voltages to various transceiver components. Conventionally, each of these DC-DC converters provides an output voltage used to power a specific element common to each transceiver chain. In other words, the DC-DC converters are shared among different transceiver chain components within the overall transceiver architecture.

[0131] For example, a conventional transceiver architecture may use one DC-DC converter providing a first supply voltage used for digital circuits, a second DC-DC converter providing a second supply voltage to most analog / RF components (such as low noise amplifiers (LNAs), switches, active mixers, etc.), and a third DC-DC converter providing a third supply voltage to power amplifiers (PAs). Generally, since the first, second, and third supply voltages output different supply voltages, the first DC-DC converter provides the lowest supply voltage, the second DC-DC converter provides the highest supply voltage, and the second DC-DC converter provides an intermediate supply voltage between the first and third supply voltages. Additionally, in the case of a conventional transceiver architecture, each of the transceiver chains shares the same first, second, and third power supply voltages provided by the first, second, and third DC-DC converters, respectively. For example, the same third supply voltage (i.e., the highest voltage) can be applied to all active power amplifiers within the transceiver array architecture, that is, to all active power amplifiers associated with each transceiver chain of the array.

[0132] Generally, for the operation of a phase array, transceivers utilize a pre-configured codebook, which is typically loaded into chip memory. This codebook can define various transceiver parameters for each transceiver chain to operate with specific communication protocols, frequency bands, and the number and type of antenna elements within the phase array. For example, the codebook may include transceiver parameters such as optimal amplifier bias, amplitude, and phase settings per transceiver chain, depending on frequency, beam pointing angle, data modulation and waveform, and current die temperature. These codebooks are generally based on array calibration performed in advance at the factory and cannot compensate for changes occurring during element-level post-calibration (e.g., random element failure, individual element shutdown due to temperature overshoot, changes in antenna VSWR (voltage standing wave ratio) due to external conditions).

[0133] In other words, a major drawback of conventional transceiver architectures is that individual transceiver chains within a phase array system cannot be tuned and controlled separately, which has several implications. First, as the antenna beam scans, the VSWR between each power amplifier and its corresponding antenna changes. This change in VSWR affects the power amplifier's output power, gain, and power dissipation. Consequently, as the beam scans through space, the power transmitted from each amplifier changes, and this change can vary for each amplifier in the array. This also affects the nonlinearity of the power amplifiers (amplitude modulation (AM)-AM and AM-phase modulation (PM) errors), thereby reducing the benefits of using digital pre-distortion (DPD).

[0134] Secondly, as the antenna beam is scanned, the mutual coupling between the antennas changes. This also affects the VSWR between the power amplifier and the antenna, further complicating the aforementioned problem.

[0135] Thirdly, to reduce the level of the side lobes, the amplitude transmitted from each transceiver chain is typically "tapered," meaning that the amplitude transmitted from each chain relative to one another can be changed. This tapering is generally achieved by adding a variable attenuator to the output of each transceiver chain to reduce the transmitted signal magnitude according to a predefined codebook. This is explained further below with reference to Fig. 16a. However, in most cases, this means that when aperture tapering is applied, the amplifiers are not biased at their optimal settings. Instead, since each amplifier is biased to the same voltage, power is wasted when using the attenuator.

[0136] Fourth, temperature differences based on location on the die can cause performance differences among various transceiver chains. For example, transceiver chains located in the center of the chip generally operate at higher junction temperatures compared to those at the chip edges because they are not surrounded by other high-temperature components. These temperature variations affect the gain and noise figure of low-noise amplifiers (LNAs), as well as the gain, output power, and efficiency of power amplifiers. In conventional transceiver designs, since it is only possible to control the bias settings of all amplifiers as a single entity, the bias can only be set as an average value based on the average temperature of the entire chip. In other words, there is no way to individually apply optimal bias conditions to amplifiers based on individual junction temperatures.

[0137] Fifth, as the junction temperature increases, individual component failures or shutdowns (due to temperatures exceeding the temperature threshold) may occur, which can cause problems with the operation of the entire array. In particular, the transceiver system consistently combines the operational transceiver chain signals, which may include chains that act as a suboptimal alternative because of the higher temperature, as well as chains that are turned off (e.g., due to failure or shutdown). Consequently, this leads to system-level performance degradation, manifesting as pointing errors, low Pout, side lobes, grid lobes, low throughput, and high EVM (error vector magnitude).

[0138] Accordingly, to address the problems present in conventional transceiver architecture solutions, the aspects disclosed in this section relate to a transceiver implementation using multiple DC-DC converters to control individual digital transceiver chains associated with a digital RF head. In particular, the aspects described herein eliminate the need for multiple DC-DC converters that provide various supply voltages shared among specific components of all transceiver chains. Instead, the aspects described herein enable each transceiver chain, which may alternatively be referred to herein as a transceiver "slice" or transceiver "part," to implement a single DC-DC converter that can be used for each component within that transceiver chain. This provides several advantages in terms of providing the ability to control the bias of each transceiver chain, optimizing performance, and reducing the impact of performance degradation when individual transceiver chains fail or operate under suboptimal conditions.

[0139] As further explained below, the various aspects described in this section facilitate a digitally controlled RF head capable of individually tuning and biasing each transceiver chain according to specific application examples and / or current operating conditions. For example, when the beam is widely laterally steered, the bias of each transceiver chain can be adjusted to account for aperture tapering, changes in VSWR, mutual coupling between elements, process and temperature variations, and DPD usage. Thus, the amplifier associated with each transceiver chain can be biased to its respective value to achieve optimal RF performance and provide significant DC power savings.

[0140] FIG. 15 shows a block diagram of an exemplary transceiver design according to one aspect of the present disclosure. Generally, the transceiver design illustrated in FIG. 15 represents a digital RF head comprising a common digital front end (DFE) (1502) and any suitable number of digital transceiver slices (1504.1 to 1504.N). The digital RF head is connected to a modem via a digital interface (e.g., a flex cable or other suitable connection) so that digital data is communicated between the modem and the digital RF head. While the common DFE (1502) may be configured to manage digital processing, the multiple digital transceiver slices (1504.1 to 1504.N) may function to convert digital transmission signals into analog and to upconvert these analog signals for transmission through a corresponding connected antenna (downconverting analog signals received through the connected antenna and digitizing the downconverted received analog signals during reception). Accordingly, signals transmitted and received through antennas within the phase array are passed between antennas (1-N) (or antenna groups) respectively connected to a common DFE (1502) through a switching component (1514).

[0141] As further described herein, aspects include the transceiver design (1500) being implemented as part of an overall transceiver architecture having several components omitted for brevity and ease of explanation. In one aspect, a common DFE (1502) may be connected to any suitable number N digital transceiver slices (1504.1 to 1504.N). The transceiver design (1500) illustrated in FIG. 15 illustrates the shared DFE (1502) being connected to only one digital transceiver slice (1504) for brevity. However, the aspects include being connected to each of the digital transceiver slices (1504.1 to 1504.N) via any suitable number and / or type of wired or wireless link, which may include a wired bus configured to transmit digital baseband data streams (e.g., "digital RX data" and "digital TX data") between the shared DFE (1502) and the digital transceiver slices (1504.1 to 1504.N).

[0142] In any case, the DFE (1502) may include any suitable number and / or type of components configured to perform functions known to be associated with a digital front end. For example, the DFE (1502) may be implemented as a processing circuit, a part of a processing circuit, one or more parts of an onboard chip having dedicated digital front end functions (e.g., a digital signal processor). For example, the DFE (1502) may provide digital baseband data to be transmitted to each of the digital transceiver slices (1504.1 to 1504.N) through an antenna connected to each, as further described below. To provide another example, the common DFE (1502) may facilitate receiving digital baseband data from each of the digital transceiver slices (1504.1 to 1504.N), which can be processed to recover data included in the wireless data transmission.

[0143] To this end, the common DFE (1502) may be implemented with a decimator and components (e.g., a virtual reconfigurable circuit (VRC)) suitable for performing reconfigurable computing, as well as a processing circuit configured to perform reception corruption corrections such as DC offset correction, IQ imbalance correction, and ADC skew. To provide additional examples, the common DFE (1502) may further facilitate adjacent channel rejection (ACR) filtering, receiver digital gain control (DGC), downsampling, etc.

[0144] To provide another example, the common DFE (1502) may be implemented with an interpolator and a VRC connected to each digital transceiver slice (1504.1 to 1504.N). Furthermore, the common DFE (1502) may include other components related to data transmission, such as transmitter damage correction (e.g., LO correction), IQ imbalance, digital pre-distortion (DPD) calculation, correction factor (CF) calculation, and pre-emphasis (pre. emp.) calculation. To provide an additional example, the common DFE (1502) may facilitate transmitter DGC, upsampling, zero-crossing detection algorithms, phase modulation, etc. Furthermore, aspects include the common DFE (1502) being implemented with components suitable for performing beam management, digital blocker removal, RSSI (Received Signal Strength Indicator) measurement, DPD and correction accelerators, test signal generation, etc.

[0145] In any case, aspects include the common DFE (1502) selectively performing specific functions based on the operating mode of the transceiver design (1500). In particular, as further described below, the common DFE (1502) and / or slice DFEs (1510, 1522) implemented within each digital transceiver slice (1504.1 to 1504.N) can dynamically recalculate and / or update DPD coefficients based on feedback measured during the operation of the wireless device in which the transceiver design (1500) is implemented. In addition to this, or alternatively, aspects include the common DFE (1502) and / or slice DFEs (1510, 1522) dynamically adjusting various transceiver parameters associated with one or more respective digital transceiver slices (1504.1 to 1504.N). In various aspects, as further explained below, DPD coefficients and / or transceiver parameters can be adjusted on a per-transceiver chain basis by utilizing the use of DC-DC converters (1520.1 to 1520.N) per transceiver chain as illustrated in FIG. 15.

[0146] In one aspect, the transceiver design (1500) may include a digital phase-locked loop circuit (DPLL) (1550), which may be implemented using any suitable known circuit component to generate a reference signal (1551) that may include a low-phase noise DPLL. Furthermore, aspects include the reference signal (1551) being distributed to a frequency multiplier / shifter circuit (1506) and a phase generation circuit (1508). Thus, aspects include the phase generation circuit (1508) being identified, for example, as the phase configuration circuit (306.2) shown in FIG. 3. Furthermore, the frequency multiplier / shifter (1506) may be implemented as any suitable type of frequency multiplier, such as the edge combination frequency multiplier (e.g., ILCM (306.3)) described in the previous section, which can provide any suitable number of LO signals to the mixer (1518). Furthermore, aspects include the frequency-multiplication radio frequency digital-to-analog converter (FM-RFDAC) (1512) being implemented as any suitable known FM-RFDAC design.

[0147] Additionally, the transceiver design (1500) includes any suitable number N of transceiver slices (1504). In one aspect, each transceiver slice (1504) has a separate transmission path and a reception path. For brevity and ease of description, each transceiver slice (1504) is depicted as being connected to a single individual antenna throughout the drawings of this section. However, in various aspects, each transceiver slice (1504) may be connected to any suitable number of antennas, low-noise amplifiers, etc., in any suitable configuration to facilitate transmitting and receiving data according to a phase array architecture.

[0148] Referring again to FIG. 15, the transceiver slice (1504.N) may represent each of the transceiver slices (1504.1 to 1504.N) and may implement a transmission path including a TX slice DFE (1510) connected to an FM-RFDAC (1512). The FM-RFDAC (1512) is then connected to a power amplifier (PA) (1517) and connected to antenna N via a switching component (1514), which may represent any suitable type of component(s) to facilitate TX and RX mode switching. In one aspect, the transmission path of each transceiver slice (1504) may include a TX slice DFE (1510), which functions to provide additional DFE functions on a per-transmission chain basis (i.e., individual TX DFE (1510) may be implemented for each transceiver slice (1504). Additional DFE features include, for example, interpolation, digital pre-distortion, I / Q compensation, and gain control.

[0149] Furthermore, aspects include each transceiver slice (1504) also including a receiving path connected to a switching component (1514). For example, the receiving path includes one or more amplifiers (1516) (e.g., LNA), a frequency multiplier / shifter circuit (1506), one or more mixers (1508), an I / Q ADC and baseband filter circuit (1520), and an RX slice DFE (1522). Additionally, aspects include each transceiver slice (1504) implementing a separate receiving path, each having components similar to those represented by the transceiver slice (1504.N) as illustrated in FIG. 15. Thus, aspects further include each component associated with the receiving path being controlled independently on a per-receiving chain basis (i.e., each transceiver slice (1504) may have a receiving path having components that are controlled individually from each other).

[0150] In one aspect, each transceiver slice (1504) may include its own DC-DC converter (1520.1 to 1520.N), which may be implemented as any suitable type of circuit configured to output a stable DC supply voltage using a reference input voltage. This reference input voltage may include any suitable DC voltage generated in the transceiver design (1500) using known techniques, and such connection and reference input voltage are not shown in the drawings for brevity. In various aspects, each of the DC-DC converters (1520.1 to 1520.N) may provide independent supply voltages, so that the DC-DC converters (1520.1 to 1520.N) may provide the same supply voltage or different supply voltages to each transceiver slice (1504).

[0151] The aspects include the supply voltage output from each DC-DC converter (1520.1 to 1520.N) being fixed or adjustable (e.g., adjusted via a control signal from a suitable processor circuit as described further below). In one aspect, the DC-DC converter (1520) may be formed on the same chip or die as other components implemented within each transceiver slice (1504). For example, the DC-DC converter (1520.N) may be integrated as part of the same die (i.e., formed as part of the same silicon) used for the mixer (1518), amplifier (1516), etc. As another example, one or more of the transceiver slices (1504.1 to 1504.N) are integrated as part of the same chip as the common or shared DFE (1502) (and / or the modem referenced in FIG. 15 but not illustrated), whereas other aspects include the DFE (1502) and one or more of the transceiver slices (1504.1 to 1504.N) (and / or the modem referenced in FIG. 15) being integrated as separate chips. Thus, all functions provided by the transceiver slices (1504.1 to 1504.N), the shared DFE (1502), and / or the modem referenced in FIG. 15 may be performed by one or more of these components on the same chip or a different chip in which the components are integrated. For brevity, although not illustrated in FIG. 15, each transceiver slice (1504) may likewise include additional components that can share power provided by each DC-DC converter (1520). Furthermore, aspects include one or more of the transceiver slices (1504.1 to 1504.N) including one or more DC-DC converters (1520), and a specific component within each transceiver slice utilizes a supply voltage provided by a different DC-DC converter implemented within a specific transceiver slice.

[0152] In one aspect, each transceiver slice (1504) has any suitable number N of feedback components (FC1-FC) in FIG. 15. N A set of self-feedback components (FC), illustrated as ), may be further included. For brevity, various interconnections of the feedback components are not illustrated in FIG. 15. However, as further described below, these feedback components may include any suitable number and / or type of known sensors, measuring devices, sampling devices, couplers, etc., capable of monitoring various states of each transceiver slice (1504) during operation. For example, these feedback components may include a temperature monitor at one or more die locations to facilitate the measurement of the junction temperature of various components associated with each transceiver slice (1504), a power meter measuring forward and reverse power in the transmission path and / or reception path, an element fault detector, etc.

[0153] FIGS. 16a and FIGS. 16b illustrate general block diagrams of digital transceiver slices. In particular, FIG. 16a illustrates a block diagram of a conventional transceiver architecture using a DC-DC converter common between each transceiver chain. However, FIG. 16b illustrates a block diagram of a transceiver portion using multiple DC-DC converters, i.e., one per transceiver slice, as shown in FIG. 15. Thus, the block diagrams shown in FIG. 16 may represent alternative representations of transceiver slices (1504.1 to 1504.N) as shown in FIG. 15.

[0154] As mentioned above, one advantage of the DC-DC converter aspects per transceiver slice described herein relates to aperture tapering. In a typical phase array, the amplitude transmitted through each transceiver chain is tapered to reduce power leakage into the side lobes. This can be observed in the radiation patterns illustrated in FIGS. 17a and 17b, which represent the simulated far-field radiation patterns of a 4×4 array without (Fig. 17a) and with (Fig. 17b) aperture tapering. The simulation shows that applying amplitude tapering reduces the side lobe level by approximately 15 dB.

[0155] As illustrated in FIG. 16a, a conventional transceiver design uses a DC-DC converter common to the components across all transceiver slices, implemented to bias all transceiver slice components. However, FIG. 16b illustrates a block diagram of a transceiver architecture using multiple DC-DC converters, one for each transceiver chain, according to one aspect of the present disclosure. The aspects include, as illustrated in FIG. 16b, that the DC-DC converter per transceiver chain facilitates various options for tuning and optimizing the bias settings for each transceiver slice, and enables the digital RF head to achieve optimal RF performance using lower DC power consumption.

[0156] For example, as illustrated in Fig. 16a, a single shared DC supply voltage (VRF) is used. This supply voltage can be used, for example, to bias the receive amplifier and the transmit amplifier within each transceiver chain. By doing so, the receive and transmit amplifiers within all transceiver chains are biased with the same voltage VRF, so changing the VRF supply voltage affects the amplifiers within all transceiver chains. As mentioned above, to lower the level of the side lobes, the amplitude transmitted from each transceiver chain is "tapered" overall; that is, the amplitude transmitted from each chain can differ relative to one another. However, since the same supply voltage VRF is distributed to all transceiver chains, existing solutions utilize variable attenuators (Variable Att) within the transmit and receive paths of each transceiver chain while the amplifiers are fully biased. This allows the magnitude of the transmit signal and / or receive signal to be reduced to a desired value according to a predefined codebook. In other words, since all amplifiers within the transceiver are biased at the same level and must operate at maximum power while transmitting attenuated power, using the same supply voltage to fully bias each amplifier results in wasted power. In this inefficient solution, the same amount of DC power must be used even when lower RF power actually needs to be received or transmitted from multiple transceiver slices (i.e., based on codebook values).

[0157] In contrast, the transceiver architecture illustrated in FIG. 16b can be represented as the transceiver architecture (1500) illustrated in FIG. 15, with additional details regarding the DC-DC converters. Thus, DC-DC converters 1, 2, and N, respectively associated with "VRF_Slice 1", "VRF_Slice 2", "VRF_Slice N", etc., can be identified as DC-DC converters (1520.1 to 1520.N). Thus, these supply voltages can be used to bias the amplifiers within each transceiver slice using different voltage values, as illustrated in FIG. 16b. By doing so, aspects include reducing power by eliminating variable attenuators implemented as part of the conventional transceiver architecture and enabling a more efficient transceiver design. In particular, instead of attenuating the signal within each transceiver chain, aspects include facilitating direct amplitude tapering through the amplifiers by adjusting the respective bias conditions to obtain appropriate output power. In this way, each amplifier can be individually biased under optimal conditions based on the desired tapering and the output power that actually needs to be transmitted or received. Since there is no DC power wasted through the attenuator, the overall DC-to-RF efficiency of the transceiver is improved.

[0158] In other words, referring again to FIG. 15, the aspects described in this section can improve the efficiency of a PA (1517) included in one or more of the digital transceiver slices (1504.1 to 1504.N). In particular, a specific supply voltage provided by a DC-DC converter (1520.1 to 1520.N) can control the individual power rails used through each PA (1517) to optimize the load line for the transceiver design (1500). Since the DC converter (1520.1 to 1520.N) can be controlled independently in each of the digital transceiver slices (1504.1 to 1504.N), the aspects described in this section enable the transceiver design (1500) to maintain an optimal load line over the entire range of transmitter output power levels. That is, it is undesirable for the PA (1517) to use a high power supply to transmit to a low power level, as power is wasted in this process and the PA efficiency is low. The embodiment described herein facilitates individualized adjustment of the power rail for each PA (1517), thereby enabling the transceiver design (1500) to operate with optimal efficiency for all output power levels.

[0159] Another advantage of the aspects of the DC-DC converter per transceiver slice described herein that are more related to aperture tapering is described below with reference to FIGS. 18a and 18b. In particular, when the transceiver slice (1504) is implemented for the transmission of a signal according to a specific communication protocol (e.g., an OFDM signal), the output power of the transmitter varies significantly over time as a function of the modulation and waveform being transmitted. Therefore, if the same DC-DC power supply is used for each transceiver slice as in the case of the conventional method, a constant voltage is applied during signal transmission, as shown in FIG. 18a. This is generally done to compensate for the highest level of output power, but DC power is wasted when the amplifier transmits at a lower output power level.

[0160] However, according to aspects described in this specification, individual DC-DC converters (1520) integrated within each transceiver slice can independently power each amplifier within its own transceiver slice. Consequently, the aspects include modulating the amplifier bias voltage so that the DC bias level tracks the envelope of the transmitted signal, as illustrated in FIG. 18b, thereby providing an improvement in DC-RF efficiency.

[0161] Another advantage of the DC-DC converter aspects per transceiver slice described herein is that individual bias control for each transceiver slice can function to mitigate some of the effects of VSWR mismatch from the antenna to the amplifier, as well as the interconnection between antennas. These effects may vary for each transceiver chain and change as the radiated beam is widely laterally steered. For example, a transceiver design having N transceiver slices (see FIG. 15 and 16b) is connected to N antennas. Additionally, each antenna will have slightly different impedances due to its physical location within the phase array, mutual coupling with adjacent antennas, and the overall environment (e.g., location of the antenna, radiation direction, enclosure type, enclosure material, distance between the antenna element and the enclosure, presence of a large reflector in the near-field of the UE, etc.).

[0162] Using each transceiver slice, these different impedances generate different VSWRs at each interface between the connected antenna and amplifier, which affects amplifier performance (e.g., output power, gain, and efficiency). Changes in VSWR can also affect the amplifier's nonlinearity (i.e., introduce AM-AM and AM-PM errors). Furthermore, as previously mentioned, if the antenna widely laterally steers the beam, the VSWR observed through each transceiver slice changes. Therefore, if it is possible to track changes in VSWR and subsequently adjust the amplifier bias state to account for these changes, it is advantageous for maintaining high performance while the beam is being steered and when the system radiates in suboptimal environments.

[0163] Furthermore, changes in semiconductor process can also result in different power amplifiers with different AM-AM and AM-PM characteristics. To account for these differences, different backoff values ​​may be required for each power amplifier (PA) (e.g., PA (1517) shown in FIG. 15). However, without a mechanism to increase the linearity of the weaker PA, the PAs for the entire transceiver system must operate at a transmission power backoff to support the weakest PA, thereby degrading overall efficiency and reducing transmission power. Therefore, another advantage of the DC-DC converter per transceiver slice aspect described herein is that the supply bias for the low-performance PA within an individual transceiver chain can be increased within the entire transceiver array to maintain the output power and efficiency of the entire system. This processing is further described below in relation to the processing flow shown in FIG. 19.

[0164] FIG. 19 illustrates a processing flow for VSWR (voltage standing wave ratio) correction and cooperation with a DPD (digital pre-distortion) front-end module according to one aspect of the present disclosure. In one aspect, the processing flow (1900) may be implemented through one or more parts of the transceiver design (1500) shown and described herein with reference to FIG. 15. Although the processing flow (1900) is described herein with reference to the transmission of a signal, this is an example and not a limitation. The aspects described herein may include the modification of various DPD coefficients and / or transceiver parameters associated with each transceiver slice implemented as part of the transceiver architecture as described herein, which may be utilized as part of the receiving chain and / or transmitting chain components.

[0165] For example, as illustrated in FIG. 15, each transceiver slice (1504.1 to 1504.N) may implement a slice DFE (1522, 1510) within each receiving path and transmitting path. In one aspect, the processing flow (1900) may be performed through any suitable combination of a processing circuit and / or other suitable components implemented by the common DFE (1502) and / or the shared DFE (1510, 1522) associated with each individual transceiver slice (1504). For example, the slice DFE (1510, 1522) may further modify, update, redefine, and / or adjust the DPD coefficients and / or transceiver parameters initially set by the common DFE (1502).

[0166] As illustrated in FIG. 19, the processing flow (1900) may begin by generating a digital transmission signal (block 1902). This may include the calculation of the digital data illustrated in FIG. 15, which can be performed, for example, by a modem or other suitable signal processing component connected to the common DFE (1502). Thus, the digital transmission signal may represent a digital data bitstream that is first processed by the common DFE (1502), and the common DFE (1502) applies an initial or common DPD correction to the digital transmission signal and then redistributes the digital transmission signal to each transceiver slice (1504.1 to 1504.N) through the slice DFE (1510, 1522) with the DPD correction (e.g., "digital TX data") as illustrated in FIG. 15. Applying the initial DPD correction through the common DFE (1502) may be performed, for example, using pre-corrected information.

[0167] Again, each transceiver architecture (1500) includes a dedicated DC-DC converter (1520.1 to 1520.N) implemented within each transceiver slice (1504), as well as a dedicated DFE slice (1510, 1522) for each transmission path and reception path. Accordingly, aspects further include each transceiver slice further modifying the settings of the transceiver component and / or providing additional DPD correction to the transmission (or reception) signal (in the case of the transmission signal, some DPD correction may already be present through the shared DFE (1502)). Accordingly, the processing flow (1900) includes the initial application of DPD parameters for the initial transmission of data through the phase array using each of the transceiver slices (1504.1 to 1504.N) (block 1904). This may include, for example, initializing each transceiver slice (1504) for data transmission according to the settings of a preset codebook.

[0168] Furthermore, aspects include additionally applying initial transceiver parameters through each transceiver slice (1504) in the processing flow (1900) (block 1906). These additional transceiver parameters may be separate from the DPD applied by the DFE slices (1510, 1522) associated with each transceiver slice (1504) (and / or the common DFE (1502)). For example, the initial transceiver parameters may include various transceiver component settings for each transceiver slice (1504) to be used when transmitting each DPD-corrected digital transmission signal. The initial transceiver parameters may also be specified by a stored preset codebook and may include any appropriate component settings that can be adjusted in each transceiver slice (1504) to improve system performance. Examples of these transceiver parameters include the initial amplifier bias state, the phase shifter setting, and the gain required by each transceiver slice (1502) based on the type of signal (e.g., modulation type, waveform, signal bandwidth, etc.) that needs to be transmitted in a certain direction in a certain frequency band (e.g., amplitude tapering parameter).

[0169] Again, as illustrated in FIG. 15, each of the transceiver chains (1504.1 to 1504.N) has any suitable number of feedback components (FC1-FC N...may include. In various aspects, these feedback components may include power monitoring circuits such as couplers, power detectors, etc. These power monitoring circuit components may be implemented within the transmission path and / or reception path of each transceiver slice (1504) and may include any suitable type of known circuit component that facilitates forward and reverse power measurements for each path. These power monitoring circuit components may enable the slice DFE (1510, 1522) (or other suitable components of the transceiver architecture (1500), such as a shared DFE (1502)) within each transceiver slice (1504) to monitor the forward and reverse power within the transmission path of each transceiver slice (1504) during signal transmission. Through these measurements, it may facilitate the calculation and tracking of the VSWR between each transmission transceiver slice (1504) and its connected antenna within the phase array during transmission (Block 1908). In other words, the VSWR between the amplifier output and the antenna in each transceiver slice (1504) can be calculated in a known way using numerical values ​​derived from forward and reverse power measurements.

[0170] In one aspect, if the monitored VSWR changes unexpectedly or exceeds a predetermined threshold, the bias of that particular transceiver chain amplifier can be adjusted to compensate. In one aspect, this can be implemented through slice DFEs (1510, 1522) within each transceiver slice (1504) (or other suitable components of the transceiver architecture (1500), such as a shared DFE (1502), for example) that adjust the settings of the DC-DC converter powering the amplifier on that particular transceiver slice (block 1910). Thus, the DC-DC converter can bias the amplifier to an adjusted DC voltage value.

[0171] The aspects also include slice DFEs (1510, 1522) (or shared DFE (1502), etc.) within each transceiver slice (1504) before, after, or simultaneously with DC-DC converter setting adjustments that update initial DPD parameters (block 1912) using VSWR calculations (block 1908). This allows for changing the signal pre-distortion of subsequently transmitted signals to correct amplifier nonlinearity. Accordingly, the aspects include VSWR retuning compensation being performed in one or more of the transceiver slices (1504). This retuning process may include adjusting the supply power provided by the DC-DC converter (1520) for one or more transceiver chains (1504) and applying an updated DPD to one or more transceiver chains (1504) through each slice DFE (1510, 1522) to retun the power amplifier with an adjusted bias setting while adjusting the amplifier performance for the new VSWR. This entire retuning process is desirable in that it facilitates the transmission of an improved quality signal while using less DC power. As illustrated in FIG. 19, the processing flow (1900) includes dynamically retuning the transceiver chains (1504) by repeating this processing for a certain period of time when a change in the VSWR value is detected. Of course, the aspects are not limited to performing both transceiver parameter updates and DPD parameter updates in response to a tracked VSWR change, and the aspects include performing transceiver parameter updates or DPD parameter updates independently of each other, or performing one and not the other.

[0172] The tuning procedure illustrated in FIG. 19 relates to detected VSWR changes and is an example of a dynamic tuning process that can be achieved using the dedicated DC-DC converter transceiver slice architecture described in this section. However, another aspect involves dynamically tuning the transceiver slice components to compensate for other conditions that may not be considered during factory calibration. For example, the amplifier bias supplied by each dedicated DC-DC converter (1520) can provide temperature compensation per transceiver slice (1504) by taking into account the position and aperture tapering of each antenna element within the phase array die. For example, amplifiers located in the center are generally hotter than amplifiers located at the edge of the die. This temperature difference can cause performance differences between antenna elements in terms of Pout, Gain, noise figure, noise factor, Error Vector Magnitude (EVM), etc.

[0173] For example, the transceiver architecture (1500) illustrated in FIG. 15 can be implemented on a chip or die. Feedback component (FC1-FC N ) may include multiple temperature sensors to track the temperature at various locations during normal operation. In addition to, or otherwise, the aspects described herein allow each dedicated DC-DC converter to adjust the amplifier bias of each transceiver slice using temperature readings from associated sensors located near the particular transceiver chain (1504) (e.g., through slice DFE (1510, 1522), shared DFE (1502), etc. within each transceiver slice (1504)), thereby compensating for temperature changes between different transceiver slices.

[0174] The aspects described herein also allow for compensating for the degradation of transceiver array performance using a dedicated DC-DC power converter when an individual component fails or shuts down due to exceeding a maximum operating temperature threshold, which may occur as a safety measure during the operation of the transceiver. For example, a feedback component (FC1-FC N ) may include multiple voltage / current sensors at various die locations. Aspects include adjusting the bias settings provided by a dedicated DC-DC converter (1520.1 to 1520.N) using trace data obtained through multiple temperature, voltage, and / or current sensors.

[0175] For example, if a specific transceiver slice (1504) component (e.g., a power amplifier) ​​exceeds a temperature threshold, the DC-DC converter (1520) may temporarily shut down this component, while other transceiver slice power amplifiers may continue to function according to the bias provided by each dedicated transceiver slice DC-DC converter. In addition, if a transceiver slice (1504) begins to fail (e.g., by drawing current exceeding a predetermined threshold), or if one or more measured voltage values ​​fall outside the operating range of a predetermined voltage value, the component may be turned off by switching off the DC power to each DC-DC converter (1520) of the corresponding component.

[0176] Thus, the aspects include reducing the impact of a failed transceiver slice (or a transceiver slice being temporarily shut down) by adjusting the DC-DC converter so that other transceiver slices adjust the individual performance of adjacent transceiver slices. Without the granularity of fine control facilitated by the dedicated DC-DC converter aspects described herein, such modification would be impossible. Additionally, the loss of individual elements of the array may result in errors in the pointing angle and an increase in side lobes. Examples of the impact of lost or failed elements on the radiation pattern are illustrated in FIGS. 20a and 20b. In particular, FIG. 20a shows a fully operational 4×4 antenna array, whereas FIG. 20b shows the same 4×4 antenna array with three elements failed or turned off. As illustrated in FIG. 20b, the failure of these three elements results in a 1.5 dB gain loss and significant distortion of the radiation pattern.

[0177] FIG. 21 illustrates a block diagram of an exemplary device according to one aspect of the present disclosure. In various aspects, the device (2100) may be implemented as any suitable type of device configured to transmit and / or receive wireless signals according to any suitable number and / or type of communication protocol. For example, the device (2100) may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. To provide additional examples, the device (2100) may be implemented as an access point or a base station. The device (2100) may implement one or more aspects as described herein that facilitate transmitting wireless signals according to a frequency band, such as a mm-Wave frequency, or a specific frequency, for example, as further described herein.

[0178] As further referenced in this section and other sections, the term “mm-Wave frequency” in which the aspects described in this section and other sections may operate may include frequencies and frequency bands up to, for example, 20 GHz, 24 GHz, 28 GHz and above, and higher frequencies. For example, a mm-Wave frequency band may include frequencies in the range from 20 GHz to 300 GHz, from 24 GHz to 300 GHz, etc. This may include various bands associated with or referred to as mm-Wave frequency bands, such as, for example, 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc.

[0179] In one aspect, the device (2100) may include a processing circuit (2102), a memory (2104), and any suitable number N of transceiver slices or chains (2112.1 to 2112.N), each connected to one or more individual antennas (2114.1 to 2114.N). The component illustrated in FIG. 21 is provided for convenience of explanation, and aspects include the device (2100) including additional components, fewer components, or alternative components such as those illustrated in FIG. 21. For example, the device (2100) may include one or more power supplies, display interfaces, peripherals, ports, etc.

[0180] In one aspect, various components of the device (2100) may be identified as functions further described herein with reference to the dynamic application of DPD and / or transceiver parameters. Each of the transceiver slices (2112.1 to 2112.N) may be identified as each of the transceiver slices (1504.1 to 1504.N) described with reference, for example, to the transceiver design (1500) illustrated in FIG. 15. Accordingly, aspects include each of the transceiver slices (2112.1 to 2112.N) implementing its own dedicated DC-DC converter to provide supply voltage to each of the transceiver components integrated as part of each transceiver slice (2112).

[0181] Aspects include the processing circuit (2102) being composed of any suitable number and / or type of computer processors that can facilitate the control of the device (2100) as discussed herein. In some aspects, the processing circuit (2102) may be identified as a baseband processor (or suitable parts thereof) implemented by the device (2100). In other aspects, the processing circuit (2102) may be identified as one or more processors implemented by the device (2100) that are distinct from the baseband processor (e.g., one or more digital signal processors, one or more processors associated with a shared DFE (1502) and / or transceiver slices (1510, 1522), etc.). In yet another aspect, the function of the device (2100) may be combined with that described herein with reference to the device (1400), which may have a combined function with that described herein with reference to the device (1000) as described above. In addition to this, or in other ways, aspects include various functions described in this specification with reference to the device (2100) being performed by one or more components associated with the device (1400) and / or the device (1000).

[0182] In any case, aspects include the processing circuit (2102) being configured to perform arithmetic operations, logical operations, and / or input / output (I / O) operations and / or execute instructions to control the operation of one or more components of the device (2100). For example, the processing circuit (2102) may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include the processing circuit (2102) controlling and / or communicating functions related to memory (2104) and / or transceiver slices (2112.1 to 2112.N).

[0183] This may include, for example, controlling and / or mediating the transmission and / or reception functions of the device (2100), facilitating the measurement of data provided by various feedback components described herein, and using the measured data obtained through the feedback components to adjust the supply bias provided by the DC-DC converter and / or DPD parameters described herein. In addition, the processing circuit (2102) may control the state of the device (2100) to operate in a receiving mode or a transmitting mode, perform one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.), identify a group of transceiver slices for DPD management, and facilitate the calculation of initial transceiver parameters, adjusted transceiver parameters, and / or initial and / or adjusted DPD parameters for one or more of the one or more transceiver slices (2112) for any other suitable function related to the aspects described herein.

[0184] In one aspect, data and / or instructions are stored in the memory (2104), and when the instructions are executed by the processing circuit (2102), the processing circuit (2102) performs the various functions described herein. The memory (2104) may be implemented as any known volatile and / or non-volatile memory, such as, for example, ROM (read-only memory), RAM (random access memory), flash memory, magnetic storage media, optical disks, EPROM (Erasable Programmable Read Only Memory), PROM (Programmable Read Only Memory), etc. The memory (2104) may be non-removable, removable, or a combination of both.

[0185] For example, memory (2104) may be implemented as a non-transient computer-readable medium that stores one or more executable instructions, such as logic, algorithms, code, etc. As further described below, instructions, logic, code, etc. stored in memory (2104) are represented by various modules as illustrated in FIG. 21, which enables the aspects disclosed herein to be functionally realized. The modules illustrated in FIG. 21 are provided to facilitate the explanation of the functional relationship between hardware components and software components. Accordingly, the aspects include the processing circuit (2102) executing instructions stored in each of these modules together with one or more hardware components to perform various functions associated with the aspects further described herein. Again, the modules illustrated in FIG. 21 are intended to facilitate the explanation in relation to the aspects described in this section of the disclosure.

[0186] In one aspect, executable commands stored in the transceiver parameter tuning control module (2108), together with the processing circuit (2102), can facilitate the device (2100) to adjust the settings of one or more DC-DC converters per dedicated transceiver chain implemented within the transceiver slices (2112.1 to 2112.N). This may include, for example, generating appropriate control signals transmitted to one or more DC-DC converters via a suitable communication medium and protocol. These control signals may cause each DC-DC converter to change the mode of operation in response thereto. For example, the control signals may adjust the DC-DC converter settings to modify the output supply voltage for a specific transceiver chain (2112) as described herein. To provide another example, the control signals may turn off one or more of the DC-DC converters, or reactivate a DC-DC converter that was previously turned off.

[0187] Again, the DC-DC converter settings may be adjusted in various ways to adjust transceiver parameters associated with one or more of the transceiver chains (2112). As used herein, the term 'transceiver parameters' may refer to any type of component settings that may be modified as a result of changes in the DC-DC converter settings or state. For example, the DC-DC converter settings for a specific transceiver chain (2112.1 to 2212.N) may be adjusted to change amplifier bias settings to compensate for various external factors such as VSWR mismatch or temperature, to comply with codebook settings for a desired amplitude taper, to compensate for low-performance PAs, and to track the modulation envelope. In addition to, or alternatively, this may include adjusting the bias settings of transceiver components other than amplifiers, such as mixers, for example.

[0188] In one aspect, transceiver parameters may be adjusted to achieve a desired result based on measurements provided through a feedback component as described herein. This may include, for example, using a lookup table (LUT), algorithm, etc., which is stored in memory (2104) or accessible by the processing circuit (2102). For example, the LUT or algorithm may define a set of bias settings for each transceiver slice (2112) based on each detected condition, thereby allowing the desired adjusted transceiver parameters to be correlated or derived from measurement data obtained through the feedback component.

[0189] In one aspect, executable commands stored in the DPD parameter tuning control module (2110), together with the processing circuit (2102), can facilitate the device (2100) to perform various functions related to DPD parameter calculation and application to baseband signals. For example, aspects include the executable commands stored in the DPD parameter tuning control module using measurements provided through a feedback component as described herein in relation to nonlinearity mismatch, temperature mismatch, VSWR mismatch, etc., or other mismatched characteristics between transceiver slices (2112.1 to 2112.N). Furthermore, executable commands stored in the DPD parameter tuning control module (2110) may enable the processing circuit (2102) to determine whether the common DFE (1502) or individual transceiver slice DFE (e.g., DFE (1510, 1522)) in each transceiver slice (2112) should calculate and / or apply DPD parameters. In any case, executable commands stored in the DPD parameter tuning control module facilitate the processing circuit (2102) to adjust initial DPD parameters (e.g., those provided in a pre-factory calibration and / or those provided by the common DFE (1502)) to realize the per-transceiver chain DPD correction described herein.

[0190] In one aspect, like transceiver parameters, DPD parameters can also be adjusted to achieve a desired result based on measurements provided through a feedback component as described herein. This may include, for example, the use of a lookup table (LUT), an algorithm, etc., stored in memory (2104) or accessible by the processing circuit (2102). For example, the LUT or algorithm may define DPD coefficients for each transceiver slice (2112) based on each detected condition or discrepancy, thereby allowing the desired adjusted DPD parameters to be correlated or derived from measurement data obtained through the feedback component.

[0191] Some examples described herein are provided for transmission paths associated with each transceiver slice, but this is exemplary and not limiting. The aspects described herein may be applied equally to any suitable component within the transmission path or reception path within each individual transceiver slice, and may use the same DC-DC converter on the same transceiver chain or different DC-DC converters (e.g., two DC-DC converters per transceiver slice). In aspects where a single DC-DC converter is used, the DC-DC converter settings may be further adjusted when switching between the transmit and receive modes. For example, the amplifier biasing described herein in relation to the PA (1517) may also be applied to the amplifier (1516) in the reception path circuit, as illustrated in FIG. 15, to bias the amplifier (1516) for any other suitable reason as described herein in relation to the transmit path circuit, or to match the codebook settings. As another example, the aspects described in this specification may be used to track the VSWR between the antenna and the receiving amplifier (1516) and to adjust the bias of the amplifier (1516) to compensate for the VSWR mismatch.

[0192] Section IV - Adaptive Spatial Filtering and Optimal Combination of ADCs to Maximize Dynamic Range in Digital Beamforming Systems

[0193] The aspects described in this section generally relate to wireless receivers, and more specifically to wireless receiver architectures that implement adaptive spatial filtering.

[0194] Compared to conventional phase arrays, where signals from multiple antenna elements are combined with gain and phase shifts in the RF or analog domains, digital beamforming requires duplication of the entire transceiver chain per antenna element, and signals are combined only within the digital domain. This hardware duplication results in higher power loss, and since the RF stage lacks array gain, an additional gain stage is required to maintain level planning.

[0195] Furthermore, conventional digital beamforming solutions result in higher power loss. In addition to this issue, since each transceiver chain is omnidirectional, existing receivers do not provide immunity to spatial blockers. Consequently, each complete transceiver chain must support a higher effective dynamic range, which has the greatest impact on data converters. Because the dynamic range required for each chain is greater, power loss increases significantly when combined with additional circuitry.

[0196] For example, for some communication protocols that implement mm-Wave communication frequencies, digital beamforming (DBF) enables the system to fully utilize the specific advantages provided by the mm-Wave band. Specifically, to support connectivity to multiple UEs and / or base stations, full DBF radios are expected to form multiple simultaneous beams and control them independently. This is a required capability to support vehicle-to-vehicle networks for autonomous vehicles and drones. It is also a core component of base station solutions. Furthermore, multi-beaming capabilities facilitate rapid beam acquisition and tracking, particularly for moving objects. Multiple independently controlled simultaneous beams can also be useful when implemented for diversity in uplink and downlink. For instance, auxiliary beams can scan for better link directions in parallel while maintaining connectivity via the primary beam.

[0197] Despite system-level advantages, digital beamforming has not yet been deployed in commercial systems, primarily due to the challenge of satisfying significant power penalties and strict shutdown scenarios. Particularly regarding mm-Wave systems, existing mm-Wave systems typically implement phase arrays. Because these conventional phase arrays generate a single TX or RX beam that can only be switched sequentially in different directions, they slow down acquisition and handoff and limit the number of users that can be supported simultaneously.

[0198] As further referenced in this section and other sections, the term “mm-Wave frequency” in which the aspects described in this section and other sections may operate may include frequencies and frequency bands up to, for example, 20 GHz, 24 GHz, 28 GHz and above, and higher frequencies. For example, a mm-Wave frequency band may include frequencies in the range from 20 GHz to 300 GHz, from 24 GHz to 300 GHz, etc. This may include various bands associated with or referred to as mm-Wave frequency bands, such as, for example, 24 GHz, 28 GHz, 37 GHz, 39 GHz, 40 GHz, 47 GHz, 60 GHz, etc.

[0199] Another approach to implementing a beamforming system involves a so-called "brute force implementation," which aims to perform thorough signal search using a large combination of steered beam directions. However, this technique incurs power overhead because it requires one mixer and one data converter per antenna element. As described above, each receiving chain, and specifically each data converter, must support a higher dynamic range because there is no spatial selectivity in the RF and analog sections of the transceiver, and array gain is lost from the RX lineup / level scheme. This further amplifies the power loss penalty.

[0200] With these future developments and benefits of digital beamforming in mind, the aspects presented in this section of the disclosure relate to a method for addressing these issues by optimally combining signals from each element to implement a DBF system while suppressing spatial blockers and mitigating dynamic range in each transceiver chain. In particular, the aspects described in this section address the constraints on dynamic range that present current problems for digital beamforming systems in various ways. First, this dynamic range can be addressed by performing multi-element estimation of the RX signal in an adaptive spatial filter to suppress correlated ADC quantization noise. Second, coarse sectored scans can be performed simultaneously (in parallel) in different directions to detect spatial blockers. Third, through low-latency feedback around the ADC or feedforward coupling between multiple RX elements, the detected spatial blocker can function to provide blocker signal attenuation and / or nulling in a specific spatial direction.

[0201] As explained in more detail throughout this section, some of the benefits derived from the described aspects include fast beam acquisition and tracking, simultaneous support for multiple beams, and nulling interferometers. Furthermore, to enable mm-Wave communication in mobile devices and base stations, having very low power consumption (battery life, heat generation, etc.) is of paramount importance. This can be achieved through the aspects described in this section, along with the other benefits mentioned earlier.

[0202] FIG. 22 illustrates a block diagram of an exemplary receiver design using multi-element combined estimation of a signal received in an adaptive spatial filter according to one aspect of the present disclosure. The receiver design (2200) illustrated in FIG. 22 may form part of a larger overall receiver design, or additionally or otherwise form part of a larger overall transceiver design. For example, the receiver design (2200) may be part of a transceiver design described herein with reference to other sections 1-3. In one aspect, the receiver design (2200) may include any suitable number N of receiver chains (2201.1 to 2201.N), each receiver chain (2201) being implemented within an individual transceiver chain. Furthermore, these aspects include each of the receiving chains (2202.1 to 2202.N) being implemented as part of a separate transceiver slice in a transceiver design using a transceiver slice architecture, as described in one of Sections 1-3 above.

[0203] As an example, each receiving chain (2201.1 to 2201.N) may be implemented as a receiving chain associated with each of the transceiver slices (1504.1 to 1504.N), as described in Section 3 above with reference to FIG. 15. In other words, the receiving chain (2201.1) may be implemented as a receiving chain associated with the transceiver slice (1504.1), and the receiving chain (2201.2) may be implemented as a receiving chain associated with the transceiver slice (1504.2). To provide an additional example, each receiving chain (2201.1 to 2201.N) may be implemented as a receiving chain associated with each of the transceiver chains (1012.1 to 1012.N), as described in Section 1 above with reference to FIG. 10. As another example, the receiving chain (2201.1 to 2201.N) may be implemented as a receiving chain associated with each of the transceiver slices (1412.1 to 1412.N), as described in Section 2 above with reference to FIG. 14. Of course, the aspects described in other Sections 1 to 3 may or may not be combined with the functions described in this section in various aspects.

[0204] The receiver design (2200) as illustrated in FIG. 22 omits some connections and components for ease of explanation. Accordingly, aspects of the receiver design (2200) described herein may include additional components, fewer components, or alternative components as illustrated in FIG. 22 and elsewhere in the disclosure.

[0205] As illustrated in FIG. 22, each receiving chain (2201.1 to 2201.N) is connected to each antenna, which is connected to each low-noise amplifier (LNA). The output of the LNA within each receiving chain (2201) is further connected to each in-phase (I) phase branch and orthogonal (Q) phase branch. Each I and Q branch includes a mixer, which may be connected to a local oscillator (not shown) to down-convert the received signal to baseband (or other suitable lower frequency). An ADC within each of the I and Q branches is configured to convert the down-converted received signal into a digital signal (e.g., a digital data stream), which is then processed through a digital front end (DFE) (2202). In various aspects, the ADC within each receiving chain (2201.1 to 2201.N) may be implemented in any suitable manner to provide a digital output to the DFE (2202). For example, the ADC can be implemented using successive approximation (SAR), sigma-delta, pipeline, flash ADC, etc., to support a sufficiently wide channel bandwidth.

[0206] In various aspects, the adaptive joint estimation circuit block (2204) may be implemented by any suitable combination of processing circuits and / or software implemented by the DFE (2202), which may include the execution of suitable algorithms for performing the related functions described throughout this section. The DFE (2202) may include any suitable number and / or type of components configured to perform functions known to be associated with a digital front end. For example, the DFE (2202) may be implemented as a processing circuit, a part of a processing circuit, one or more parts of an onboard chip having dedicated digital front end functions (e.g., a digital signal processor), etc. For example, the DFE (2202) may receive digital baseband data (e.g., a digital RX signal as illustrated) from each of the receiving chains (2201.1 to 2201.N), which may be processed to recover data included in a wireless data transmission. The DFE (2202) may perform other functions not shown or described in this specification for brevity, such as wireless data transmission functions, for example. Alternatively, the DFE (2202) may be implemented as one of the DFEs described in any of the previous sections 1-3. For example, the adaptive joint estimation block (2202) may be part of the DFE (2202) similar or identical to the DFE (1502) as described in Section 3 with reference to FIG. 15.

[0207] Furthermore, the DFE (2202) may be integrated with one or more other components of the receiver design (2200) to form part of a common IC (e.g., RFIC), or these components may be located on separate chips. As an example, one or more of the DFE (2202) and the receiving chain (2201.1 to 2201.N) may be integrated into a common RFIC, which may be particularly useful for handling signal bandwidth and delays that might exist if these components were located on separate chips. This may also apply to the DFE and other components described in various places throughout this section as well as in other sections. For example, the sectored scanning circuit block (2304) and the blocker extraction circuit block (2306) may be integrated as part of the DFE, which is part of the same IC as the receiving chain (2301.1 to 2301.N), as described with reference to FIG. 23a. As another example, the DFE circuit block (2404) can be integrated as part of the DFE, which is part of the same IC as the receiving chain (2401.1 to 2401.N), as described with reference to FIG. 24.

[0208] In the case of a digital beamforming solution, each antenna illustrated in FIG. 22 may be omnidirectional and thus may not distinguish between a signal received in one direction and a signal received in another direction. In other words, each individual antenna element may be omnidirectional, and beamforming is achieved as an aggregate function of gain and phase shift obtained as a result of digital processing in the DFE (2202). As a result of the omnidirectional nature of each antenna element, the antenna elements of each receiving chain (2201.1 to 2021.N) may receive a desired signal of interest from one direction (e.g., the main beam direction) and a blocking signal from another direction. These blocking signals may be associated with various signal interference sources unrelated to the signal of interest and may have a frequency very close to the signal of interest (e.g., the same channel), but are often mostly fixed for the receiver design (2200). This can be utilized to facilitate adaptive spatial filtering, as further described below.

[0209] In contrast, traditional digital beamforming systems do not implement spatial filtering, and co-channel asynchronous spatial blockers, which may include the exemplary blocker signal illustrated in FIG. 22, remain largely unfiltered. Furthermore, in a complete digital beamforming system, array gain associated with combining signals from multiple antenna elements occurs in the digital domain, and since there is no benefit from the gain applied in the analog domain, it consequently results in lower gain in the receiving chain. Due to these two problems, more ADCs with higher dynamic ranges are required for each.

[0210] However, the aspects described in this section recognize that the RX EVM (error vector magnitude) budget is generally dominated by phase noise and ADC quantization noise. Since each receiving chain (2201.1 to 2201.N) receives the signal in an omnidirectional manner to support digital beamforming, each receiving chain (2201) receives a signal correlated with a delay due to an unknown signal. And, while ADC quantization noise is often modeled as additional uniform noise, the aspects described herein utilize the fact that this originates from the nonlinear characteristics of the ADC quantizer. Thus, ADC quantization noise varies with the signal, and since the ADC sees the correlated signal, the quantization noise is also correlated.

[0211] For example, each receiving chain (2201.1 to 2202.N) is illustrated as receiving a desired signal of interest (S) and a blocker signal (B), which may be received at different angles of arrival at each antenna element. These signals are summed at each of the I and Q branches within each receiving chain (2201), but for clarity, FIG. 22 shows two separate signals in the signal graph (2206). The signal graph (2206) may correspond, for example, to the I or Q branch and shows that for each receiving chain (2201.1 to 2201.N), the desired signal and the blocker signal may have different delays not only within a single receiving chain (2201) but also for other receiving chains (2201), which depends on the different angles of incidence of the desired signal and the blocker signal at each antenna element and the physical position of each antenna element relative to each other.

[0212] In other words, each of the receiving chains (2201.1 to 2201.N) receives the desired signal A and the circuit breaker signal (B) with different delays depending on the arrival angle of each specific signal. Continuing this example, the desired signal is shown in each signal graph (2206) as having a larger delay while traveling from the receiving chains (2201.1 to 2201.N), and the receiving chain (2201.1) receives the signal S first and the receiving chain (2201.1) receives the signal S last. In this example, conversely, for the circuit breaker signal (B), the receiving chain (2201.N) receives the circuit breaker signal (B) first and the receiving chain (2201.1) receives the circuit breaker signal (B) last. Generally, these time relationships depend on the arrival angles of the two signals at each antenna element associated with each receiving chain (2201.1 to 2201.N), but the delay associated with the desired signal (S) and the blocker signal (B) for one receiving chain is generally not known a priori.

[0213] However, although the delay between each receiving chain (2201.1 to 2201.N) is unknown, each antenna element operates in an omnidirectional manner, which means that each receiving chain (2201.1 to 2201.N) receives essentially the same signal except for the (unknown) time-shifted delay between them. Accordingly, in one aspect, the adaptive joint estimation circuit block (2204) receives digital RX data signals in parallel from each ADC associated with the receiving chain (2201.1 to 2201.N). The RX data signals received in this manner include a combination of the desired signal (S) and the blocker signal (B) received from each receiving chain (2201). According to this aspect, the adaptive joint estimation circuit block (2204) removes the blocker signal while removing the signal S and the blocker signal B together.

[0214] For convenience of explanation, a hypothetical example is provided in which the delay between the desired signal (S) and the blocker signal (B) for each receiving chain (2201.1 and 2201.2), as well as the delay between the desired signal (S) and the blocker signal (B) from one receiving chain to another receiving chain (2201.1 to 2201.N), are known. In this case, for each of the desired signal (S) and the blocker signal (B), a time shift may be introduced as part of the processing of the digital RX signal (i.e., digital sample) received from the ADC of the receiving chain (2201.1), and as a result, is correlated independently of the actual received RX signal provided by the ADC of the receiving chain (2201.1). These two sets of correlations each amplify the desired signal in one case and the blocker signal in the other. Thus, this correlation may be repeated for each receiving chain to select a correlation result that amplifies only the desired signal (S) and not the blocker signal (B).

[0215] However, as mentioned above, the delay between the desired signal (S) and the blocker signal (B), as well as the delay between each receiving chain (2201.1 to 2201.N), is unknown. In this case, the signal delay must also be estimated for each receiving chain (2201.1 to 2201.N). The aspects described in this section facilitate this through a joint estimation technique performed via an adaptive joint estimation circuit block (2204). In one aspect, the adaptive joint estimation circuit block (2204) can estimate the delay associated with the desired signal (S) and the blocker signal (B) for each receiving chain (2201.1 to 2201.N) using digital RX signals received in parallel from each ADC shown in FIG. 22. The result of such delay estimation can subsequently be used to correlate the result of performing a phase shift or time delay for each receiving chain (2201.1 to 2201.N) with the desired signal (S) and blocker signal (B) for the digital RX signal received from the ADC of each receiving chain (2201.1 to 2201.N).

[0216] That is, since delay and correlation each influence each other, the aspects described herein perform the delay and correlation steps together. In one aspect, this may include the use of Maximum Likelihood Estimation (MLE) to determine the estimated signal and blocker delay that are best correlated with the digital RX signal received from the ADC of each receiving chain (2201.1 to 2201.N), for example. For example, correlation may be implemented through an adaptive joint estimation circuit block (2204) for each receiving chain (2201.1 to 2202.N) to time-shift the desired signal (S) received through the ADC for a specific receiving chain (2201) using an initial estimated delay, wherein the initial estimated delay is multiplied by an unshifted version of the same desired signal (S) from the same receiving chain (2201) and integrated over a period of time. Therefore, the accuracy of each estimated delay used to perform the time shift can be determined based on the fact that the estimated delay provides the maximum result when multiplied and integrated over each time in the manner mentioned above.

[0217] In one aspect, the technique described above may be performed by an adaptive joint estimation circuit block (2204) in parallel with the correlation for each of the other receiving chains (2201.1 to 2201.N). In other words, the estimated delay for the desired signal (S) and the blocker signal (B) for each receiving chain (2201.1 to 2201.N) may be correlated in parallel with each receiving chain and all other receiving chains (2201.1 to 2201.N). That is, instead of performing delay estimation and signal correlation sequentially and individually for each of the receiving chains (2201.1 to 2201.N), time-shifted versions of each of the desired signal (S) and the blocker signal (B) may be correlated in parallel (e.g., simultaneously) with the (unshifted) ADC outputs of each of the other receiving chains (2201.1 to 2201.N) until a solution is obtained that includes a set of estimated time delays of the desired signal (S) and the blocker signal (B) for each of the receiving chains (2201.1 to 2201.N). This set of estimated delay solutions may be obtained, for example, by analyzing the results of the receiving chain correlation in terms of maximum possibility of identifying a set of estimated delays that result in minimum error with respect to the distribution of the digital RX signal received through the adaptive joint estimation circuit block (2204).

[0218] The use of correlation through the adaptive joint estimation circuit block (2204) is merely an example of a technique that can be used to estimate signal delay in each receiving chain, and is provided herein as an example rather than a limitation. Aspects include the adaptive joint estimation circuit block (2204) adaptively estimating the delay of the desired signal (S) and the blocker signal (B) from each of the receiving chains (2201.1 to 2201.N) in an appropriate manner (also estimating the signal itself as a joint along with the estimated delay).

[0219] When a set of estimated delays is obtained in this manner, the aspects include the adaptive joint estimation circuit block (2204) offsetting the delays associated with the desired signal (S) and the blocker signal (B) in each receiving chain (2201.1 to 2201.N). Once this is completed, the signals received as digital RX signals from the ADC of each receiving chain (2201.1 to 2201.N) are substantially identical to each other because the delays are taken into account as mentioned above and the signals are received through each antenna element in an omnidirectional manner. This is desirable in that it can improve the signal-to-noise ratio of the receiver design (2200).

[0220] In addition, when signals received from other antenna elements are combined in the digital domain by applying gain and phase shift, the RX signal-to-noise ratio (SNR) is It is improved by the amount, where Nelem is the number of elements. As further explained below, the aspects described herein implement multi-element joint estimation of the received signal in an adaptive spatial filter to utilize the correlation properties between the receiving chains (2200.1 to 2201.N) as illustrated in FIG. 22. This suppresses any correlation noise, such as quantization noise and sampling jitter, for example. Thus, the aspects described in this section improve effective ADC resolution while implementing a digital beamforming solution, thereby enabling the use of lower resolution converters in each receiving chain (2201.1 to 2201.N). This enables a feasible implementation of the entire DBF system and is desirable as it lowers total power loss. In this regard, for clarity, system simulations were performed for various array sizes according to the adaptive joint estimation technique described in this section, and the SNR gain from the joint estimation is summarized in Table 1 below.

[0221] antenna Joint Estimated SNR Gain 16 14.5 dB 64 22.5 dB

[0222] In other words, the aspects described in this section involve utilizing parallel (e.g., simultaneous or joint) estimations of the desired signal (S), the blocker signal (B), and the time delays associated with all of these signals, and correlating the results with each of the other receiving chains (2201.1 to 2201.N). In this case, the fact that the signals received in the receiver design (2200) are partially correlated with each other is utilized, thereby relaxing the quantization requirements of the ADC and reducing the overall power consumption of the receiver. The receiver design (2200) may be configured to direct the main beam toward the signal of interest using information from the channel estimation. For example, a short preamble that is part of the communication protocol may contain channel estimation information that allows the direction of the main beam to be calculated. Once the direction of the signal of interest is known, the DFE (2202) may achieve beamforming of the main beam toward this direction by digitally applying gain and phase to the digital RX signal. However, the analog-to-digital converter (ADC) of the DBF can be saturated by blocker signals incident from a direction different from the main beam, given that the signal is received by the receiving chain in an omnidirectional manner as described above. Therefore, as further explained in FIGS. 23a–23c and FIG. 24 below, the receiver design aspects described in this section can enable spatial blocker detection, and once detected, feedback correction or feedforward correction can be applied to provide spatial filtering.

[0223] FIG. 23a shows a block diagram of an exemplary receiver design for implementing space breaker detection by a coarse sector scan according to one aspect of the present disclosure. The receiver design (2300) illustrated in FIG. 23 may include any suitable number of receiver chains (2301.1 to 2301.N). The receiver chains (2301.1 to 2301.N) may be identical or substantially similar to the receiver chains (2202.1 to 2201.N) as described above with reference to FIG. 22. Thus, only the differences between the receiver chains (2201 and 2301) are further described herein.

[0224] The ADC implemented by each of the receiving chains (2301.1 to 2301.N) may be configured to first digitize the most significant bit of the downsampled received signal. The aspect described with reference to FIGS. 23a to 23c uses coarse resolution to detect high-speed envelope signals in parallel along directions other than the main beam direction (known from the received packet preamble), and by utilizing this function of the ADC, the blocker signal is partially canceled out by using only the MSB or, alternatively, by using additional bits following the MSB.

[0225] To this end, the receiver design (2300) may include a sectored scanning circuit block (2304) and a circuit breaker extraction circuit block (2306). The sectored scanning circuit block (2304) and the circuit breaker extraction circuit block (2306) may be implemented as part of the DFE (2202) in a manner similar to that described with reference to the adaptive joint estimation circuit block (2204). This is described in more detail with reference to FIGS. 23b and FIGS. 23c, which show additional details of one of the ADCs shown in FIG. 23a. Thus, the sectored scanning circuit block (2304) can facilitate approximate scanning operations, which may be implemented using the digital parallel rotation method shown in FIG. 23a. The circuit breaker extraction circuit block (2306) may be configured to analyze the results of approximate scanning from each ADC in parallel using only the MSB outputs from one or more ADCs or some appropriate number of MSBs output from one or more ADCs. Accordingly, the circuit breaker signal can be estimated from partially digitized data (e.g., partially digitized as a result of processing only a portion of the bits output by the ADC) representing a coarse estimate of the circuit breaker signal. The circuit breaker extraction circuit block (2306) can use the estimate of the circuit breaker signal to provide digital feedback to each ADC through the ADC feedback path (2308) as shown in FIG. 23a.

[0226] To this end, the receiving design (2300) may utilize the architecture of an ADC implemented within each receiving chain (2301). Referring now to FIG. 23b, an exemplary ADC design is illustrated that implements a SAR-based design including a quantizer (2320) (e.g., a comparator circuit) configured to quantize a signal received at an input node (2310). This signal may be received, for example, through connected mixer outputs within one or more I and Q branches of the receiving chains (2301.1 to 2301.N). In other words, the exemplary ADC designs illustrated in FIG. 23b and 23c may be implemented in each ADC, but this particular ADC topology is merely an example and not a limitation. The ADC may be configured in any suitable configuration, provided that the MSB is first digitized in this arrangement in various aspects.

[0227] Accordingly, the ADC illustrated in FIGS. 23b and 23c outputs digital data representing a digitized and sampled version of the downsampled analog data within the I and Q branches of one or more (e.g., all) of the receiving chains (2301.1 to 2301.N). According to the SAR topology example illustrated in FIGS. 23b and 23c, the received signal is at any appropriate sampling frequency f s It is sampled by a quantizer (2320). Additionally, the ADC quantizer (2320) is configured to output a digitized bitstream corresponding to each sampling period of the received signal according to the sampling frequency. Thus, as illustrated in FIGS. 23b and 23c, the ADC quantizer (2320) can provide an N-bit output of the received signal within each sampling period. Thus, the quantizer (2320) in FIGS. 23b and 23c It can output data bits with an N-bit period at a higher frequency indicated by .

[0228] In a SAR configuration as illustrated in FIG. 23b and FIG. 23c, a rough estimation of the signal is performed through a quantizer (2320). Subsequently, the estimated value is output and used as feedback for subtraction from the input signal, and processing such as re-quantization is performed. Thus, when each bit is output by the quantizer (2320) in an N-bit cycle, the most recently output bit can be used as feedback through a logic circuit (2330), and the logic circuit (2330) supplies the voltage input from the node (2310) to the quantizer (2330). The logic circuit (2330) may include any suitable configuration of components for selectively connecting a desired adjustable voltage to the node (2310) according to SAR ADC technology, and may include known techniques for doing so.

[0229] For example, the logic circuit (2330) may include a digital-to-analog (DAC) converter (not shown) configured to change the voltage supplied to the node (2310) by selectively switching the connection of a capacitor, according to known techniques used in this example for a SAR-based ADC. This is merely an example of the logic circuit (2330), and aspects include using any suitable technique and / or DAC to provide a variable voltage to the node (2310). In any case, the logic circuit (2330) may therefore use the bit output from the quantizer (2320) as feedback. This feedback is used in relation to the current sampling of the signal received at the node (2310) so that the logic circuit (2330) can generate the next successive approximation of the received signal as the next bit of the N-bit cycle until the entire signal currently received at the node (2310) is fully sampled and digitized. In other words, the first bit output by the quantizer (2320) in this way may be the MSB of an N-bit cycle.

[0230] To provide an example referring again to FIG. 23a, in this example, the desired signal has an angle of incidence of approximately 30 degrees, while the blocker signal has an angle of incidence of approximately -45 degrees. The output of each ADC in each receiving chain (2301.1 to 2301.N) is provided in parallel to a sectored scanning circuit block (2304) and contains digitized data representing the sum of the desired signal and the blocker signal, given the omnidirectional operation characteristics of the receiver design (2300).

[0231] Continuing with this example, the sides include a sectored scanning circuit block (2304) that performs a "coarse" sectored scan in parallel across multiple regions of space, but sequential scanning may be used as an alternative side. This may include performing a coarse parallel scan across larger spatial regions, such as quadrants, quadrants, etc., which can be implemented through the sectored scanning circuit block (2304) using the digital rotation shown in FIG. 23a. In the example shown in FIG. 23a, the receiver design is associated with beam angles of -135°, -90°, -45°, 0°, +45°, +90°, +135°, and +180°, respectively. However, the sides include any suitable number of regions scanned in parallel with each other in this manner, and the scan may consider a known angle of incidence of the desired signal to calculate adjacent regions of the sectored scan when the entire space does not need to be scanned. Therefore, in contrast to analyzing energy along all possible angles of incidence, MSB(s) are used to perform schematic scans of several larger areas.

[0232] Continuing with this example, the sectored scanning circuit block (2304) can provide the partially digitized output from each ADC to the circuit breaker extraction circuit block (2306) as a result of the rough scanning operation. This partially digitized output may include a representation of energy received in parallel from each ADC using the MSB (or MSBs) as the initial output from each ADC. In this way, by using the outputs of the MSB(s) from one or more ADCs in parallel, the circuit breaker extraction circuit block (2306) can quickly determine whether additional signal energy is present (e.g., exceeding a threshold) in one of the rough-scanned areas corresponding to an area other than the known main beam position. If it is present, the sectored scanning circuit block (2304) can use this information to determine the presence of a circuit breaker signal in a specific scanned area with additional signal energy. Additionally, the circuit breaker extraction circuit block (2306) can calculate an estimate of the circuit breaker signal in one or more of the roughly scanned areas using the MSB(s) output by one or more ADCs. Preferably, since this rough scan uses the MSB(s) of the ADC instead of the full digital ADC output, the rough scan process can provide a result with a short delay, thereby allowing the signal processing task related to communication through the main beam to be performed in parallel.

[0233] Additionally, when a breaker is detected in this manner, aspects include the breaker extraction circuit block (2306) estimating the breaker signal and using this estimated breaker signal to attenuate the actual received breaker signal. According to one aspect, this can be accomplished by applying a cancellation signal through a switch-cap DAC in the feedback path of the ADC, as illustrated in FIG. 23c. FIG. 23c shows details of an ADC design similar to FIG. 23b. Since the exemplary ADC design illustrated in FIG. 23c operates in a manner similar to the exemplary ADC design illustrated in FIG. 23b, only the differences between these exemplary ADC designs are further explained.

[0234] In contrast to the exemplary ADC design illustrated in FIG. 23b, the exemplary ADC design illustrated in FIG. 23c includes a summing circuit block (2340) introduced into the ADC quantizer feedback path, which may exist within each ADC in each receiving chain (2301.1 to 2301.N) as illustrated in FIG. 23a. Thus, the spatial blocker estimate may represent a digitized estimate of the blocker signal based on the schematic scanning and analysis of the MSB(s) output by one or more ADCs described above, and may be provided to each ADC via the ADC feedback path (2308). The digitized spatial blocker estimate may be formatted in such a way that cancels the output of the quantizer (2320) provided to the logic circuit (2330) used to drive the ADC when added to the output of the ADC via the summing circuit block (2340). In this way, the blocker signal energy is not quantized by the ADC, thereby preventing saturation.

[0235] Aspects further include providing switch-cap DAC feedback to the N-path RF / IF for further optimization. For example, the exemplary receiver architecture described in this section provides a single ADC per receiver chain. However, embodiments are not limited to these examples and include using any suitable number N ADCs connected in parallel within one or more receiver chains. For example, a receiver chain (2201.1) may include any suitable number of ADCs in parallel within each of the I and Q branches. For example, if the use of the digitized space blocker estimates described in this section with reference to FIGS. 23b and 23c can be applied, it may be implemented and extended to such a suitable number of parallel ADCs. In this way, power consumption may be reduced as each ADC can operate at a lower resolution for the required RX signal EVM. Preferably, given the characteristics of the schematic scan, the aspects include selectively applying a breaker offset (e.g., via the DFE) only when an active breaker is detected (e.g., via the sectored scanning circuit block (2304)) to reduce power during normal operation.

[0236] Even if the precise angle of incidence of the breaker signal is not determined using the rough scan described above, and the estimated breaker signal may not perfectly match the actual breaker signal using only the ADC output MSB(s), the estimated breaker signal may still sufficiently attenuate the breaker signal to alleviate ADC saturation. Additionally, using the MSB for breaker signal estimation provides sufficiently low latency, ensuring that the breaker is sufficiently attenuated within the current sampling window processed by each ADC. Using only the MSB provides minimum latency in this regard, but the aspects are not limited to this implementation. In fact, additional bits following the MSB can be utilized as part of the breaker signal estimation. This increases latency but also improves the accuracy of estimating the breaker signal. Therefore, aspects include using only the MSB for rough beam scanning, or, alternatively, using any appropriate number of bits following the MSB depending on the application, recognizing the trade-off between lower latency and higher accuracy.

[0237] Using rough scanning offers an additional advantage in that the detection of the circuit breaker signal can be fully incorporated into the radio head itself (e.g., the component in which the DFE (2202) is implemented). Thus, the rough beam scanning described herein can be performed without introducing the delay introduced by baseband signal processing. This is particularly important for enabling modification of asynchronous circuit breaker signals. In other words, rough spatial scanning should be sufficient for circuit breaker detection, as there is no need to accurately digitize the circuit breaker signal, but only to estimate the circuit breaker signal sufficiently to reduce the dynamic range required for processing it. In this way, rough circuit breaker signal scanning preferably provides fast (e.g., low latency) results of circuit breaker signal estimation and requires low hardware complexity. For example, in contrast to conventional brute force techniques that scan each possible angle of reach, the embodiments described in this section detect the circuit breaker signal by implementing rough scanning. Thus, it is desirable to detect circuit breaker signals in a computationally intensive manner compared to conventional circuit breaker signal detection technology, and consequently, more power is saved.

[0238] In summary, as described in this section with reference to FIG. 22, spatial filtering can be performed using the correlation-adaptive joint estimation of the desired signal and the accompanying blocker signal to suppress the correlated ADC quantization noise. Furthermore, as described in this section with reference to FIG. 23a through 23c, a roughly sectored scan can be performed simultaneously (in parallel) in different directions to detect the spatial blocker, which can be estimated using the MSB(s) output from the ADC and used to at least partially cancel the blocker signal. As further described below, other aspects of the approach include implementing spatial filtering on a down-converted output (e.g., baseband) of the mixer output prior to the ADC via a digital front end or within one or more receiving chains, which is further described below with reference to FIG. 24.

[0239] FIG. 24 illustrates a block diagram of an exemplary receiver design that implements a feed-forward spatial filter using connections between sets of nearest neighbor RF chains according to one aspect of the present disclosure. In one aspect, the receiver design (2400) illustrated in FIG. 24 may function to perform a roughly sectored scan to detect a blocker in a direction deviating from the main beam direction in a manner similar or identical to that described above with reference to the receiver design (2300) illustrated in FIG. 23a. However, instead of using the MSB(s) output through the ADC to construct an estimate of the blocker signal used for blocker attenuation through feedback, the receiver design (2400) may implement the spatial filter using a feed-forward implementation as further described below.

[0240] Using a feedforward design can provide additional benefits, such as further reducing the overall system latency. For example, the receiver design (2300) may use only the MSB output by one or more ADCs in the receiving chain, but this still introduces a minimum amount of latency to facilitate subsequent breaker signal attenuation. Accordingly, aspects include detecting the angle of arrival of the breaker signal using a schematic sectored scan as described herein. However, instead of reconstructing the breaker signal to cancel out the signal, the implementation described with reference to the receiver design (2400) tunes a spatial notch filter along the breaker direction identified as in the aforementioned schematic spatial scan.

[0241] To this end, the receiver design (2400) implements an interconnected feedforward coupling of adjacent receiver chains to introduce a notch filter into the spatial response. For example, as illustrated in FIG. 24, the receiver design (2400) may include any suitable number of receiver chains (2401.1 to 2401.N), which may be configured in a manner similar to the receiver chains (2301.1 to 2301.N) described with reference to the receiver design (2300), and thus only the differences between these components will be further described. Furthermore, the receiver design (2400) may include a DFE circuit block (2404), which may be implemented as part of any suitable type of DFE, and may include a sectored scanning circuit block (2304) described herein with reference to FIG. 23. As with other DFEs described with reference to FIGS. 22 and FIGS. 23a through 23c, the DFE in which the sectored scanning circuit block (2304) is implemented may be one of the other DFEs described in this section in various aspects or part of one of the other sections 1-3.

[0242] The aspects also include each of a receiving chain (2401.1 to 2401.N) implementing any suitable number of tuning circuit blocks (2420.1 to 2420.N) that can be interconnected from adjacent receiving chains. The exemplary receiver design (2400) illustrated in FIG. 24 includes the interconnection of two adjacent receiving chains for convenience of explanation, but the aspects described herein are not limited to this and any suitable number of receiving chains may be interconnected in a feedforward manner. Furthermore, any suitable number of tuning circuit blocks (2420) may be implemented for each adjacent receiving chain connected in this manner. To utilize the correlation between the interconnected receiving chains, the aspects include an interconnected adjacent receiving chain associated with an antenna element that is physically close to one another.

[0243] For example, if the antenna as illustrated in FIG. 24 is part of a one-dimensional antenna array, three interconnected tuning circuit blocks (2420.1, 2420.2, and 2420.N) may be associated with a receiving chain (2401) connected to physically adjacent antennas, for example, each associated with the top, middle, and bottom antennas within the array. As another example, if the antenna as illustrated in FIG. 24 is part of a two-dimensional antenna array, there may be eight or more interconnected tuning circuit blocks (2420.1 to 2420.N) connected in a feedforward manner, for example, eight adjacent antenna elements connected to each of the surrounding antenna elements having a 2D antenna array. Aspects include the receiving design (2400) implementing an interconnected architecture in which any suitable number of receiving chains (2401) are connected in a feedforward manner based on adjacent connected antenna elements. However, in that returns are reduced as additional antenna elements are interconnected in this manner, the aspects include recognizing the trade-off between system complexity and cost, along with the advantage of connecting additional interconnected receiver chains.

[0244] The tuning circuit blocks (2420.1 to 2420.N) may be implemented with any suitable number and type of circuit components to facilitate the application of adjustable gain weights and / or adjustable phase shifts to the downsampled signals received through each receiving chain (2401). For example, the tuning circuit blocks (2420.1 to 2420.N) may include a plurality of amplifiers as illustrated in FIG. 24, and each tuning circuit block (2420) has an amplifier having an independent and electronically adjustable gain for each of the I and Q branches, connected to the downsampled received data output from the mixer within each receiving chain (2401). Referring to the receiving chain (2401.2) as an example, it may include three tuning circuit blocks (2420.1, 22420.2, 2420.N). The implementation of the tuning circuit blocks (2420.1 to 2420.N) as shown in FIG. 24 is exemplary and not limited. Accordingly, while the tuning circuit blocks (2420.1 to 2420.N) may be implemented as additional or alternative components to facilitate adjustable phase shifting of the baseband signal, the phase may be adjusted by adjusting only the amplifier gain of a specific amplifier within each tuning circuit block (2420.1 to 2420.N) using the configuration as shown in FIG. 24 with cross-coupled I and Q branches.

[0245] For example, in the case of the adjacent connection configuration shown in FIG. 24 where two adjacent antennas are connected in a feedforward architecture, the tuning circuit block (2420.1) is an adjustable weight It includes a configuration of a tunable amplifier and a summing circuit connected to output the downsampled and received signal. The weighted output of circuit block (2420.1) is connected to a summing circuit associated with the input of the ADC for each of the I and Q branches of the receiving chain (2401.1). Additionally, the tuning circuit block (2420.2) includes an adjustable weight It includes a configuration of a tunable amplifier and a summing circuit connected to output a downsampled and received signal having, wherein the weighted output of the tuning circuit block (2420.2) is connected to a summing circuit associated with the input of an ADC for each of the I and Q branches of the receiving chain (2401.2). Furthermore, the tuning circuit block (2420.N) has an adjustable weight It includes a configuration of a tunable amplifier and a summing circuit connected to output a downsampled and received signal having, wherein the weighted output of the tuning circuit block (2420.N) is connected to the summing circuit associated with the input of the ADC for each of the I and Q branches of the third receiving chain (2401.2). For brevity, this connection may be connected in the same manner as the connection between the tuning circuit block (2420.1) and the receiving chain (2401.1) as illustrated, although not shown in FIG. 24. Thus, the exemplary receiver design (2400) implements a feedforward architecture that connects the weighted downconverted signal received through its own antenna and the weighted downconverted signal received through each of two adjacent antennas within each receiving chain (2401.1 to 2401.N).

[0246] In various aspects, as illustrated in FIG. 24 (e.g., ADC 2440), a summing circuit (e.g., ADC (2440)) connected to the input of each ADC may include any circuit component of a suitable configuration for combining weighted signals from a suitable number of adjacent receiving chains (2401.1 to 2401.N), as illustrated with reference to the receiving chain (2041.2) as a summing circuit (2430.1, 2430.2). By doing so, aspects of the receiver design (2400) include implementing a hybrid beamforming technique as opposed to using a full digital beamforming system. In other words, the weighting associated with the tuning circuit blocks (2420.1 to 2420.N) may be applied in an analog domain such as baseband, or through a downconverted frequency lower than the signal received through each receiving chain antenna. The interconnections constituting the entire feedforward architecture of the receiver design (2400) may be connected at the overall level or as part of the system plan. However, aspects include selectively combining weighted signals from one or more adjacent antennas by controlling the gain of each tuning circuit block (2420). For example, the gain of one or more amplifiers within the tuning circuit block (2420) may be set to a sufficiently low value so that the weighted output from the tuning circuit block (2420) is not combined with other weighted outputs. Thus, different weights may be applied using the tuning circuit blocks (2420.1 to 2420.N) so that the ADCs within one or more receiving chains (2401.1 to 2401.N) receive different analog weighted signals from adjacent antennas.

[0247] The aspects include the DFE circuit block (2404) receiving digital data output from one or more of the ADCs (2440) according to any suitable subset of the antennas constituting the entire antenna array. By doing so, the DFE circuit block (2404) can calculate the resulting beamforming pattern to facilitate spatial filtering by forming a null in the beamforming pattern in the detected direction of the blocker signal. And, since the direction of the blocker signal can be identified based on the energy detected in each scanned direction by rough spatial scanning, various interconnections of adjacent receiving chains (2401-1 to 2401.N) can facilitate the application of different weights using the tuning circuit block (2420) based on the direction of the detected blocker signal. The beamforming implemented through the DFE (2404) can be implemented in any suitable manner to form a spatial notch filter in this way, using knowledge of the main beam direction and the detected spatial breaker direction (from the schematic scan mentioned herein) to form a final pattern having a spatial notch as needed. In one embodiment, the weights applied to the tuning circuit block (2420) can be calculated using the detected direction of the spatial breaker and applied based on the receiving chain based on the detected energy value. For example, the angle of the breaker signal can be estimated using the results of the schematic scan described above. Using this information, a combination of appropriate weights can be applied through the tuning circuit block (2420.1 to 2420.N) to generate a beamforming shape that functions as a spatial filter with respect to the estimated breaker signal direction.

[0248] For example, the DFE (2404) can utilize weighted outputs received through the ADCs of each receiving chain (2401.1 to 2401.N) in parallel with each other, and can use the weighted combined data to form appropriate beamforming weights such that the blocker signal is canceled out or at least partially attenuated as a result of the spatial filter. By connecting signals between multiple adjacent antenna elements in this way, a tunable spatial notch can be formed without significantly restricting the field of view of each receiving chain (2401.1 to 2401.N) while providing relaxation of the ADC dynamic range.

[0249] FIG. 25 illustrates a block diagram of an exemplary device according to one aspect of the present disclosure. In various aspects, the device (2500) may be implemented as any suitable type of device configured to transmit and / or receive wireless signals according to any appropriate number and / or type of communication protocol. For example, the device (2500) may be implemented as a user equipment (UE), such as a mobile phone, tablet, laptop computer, etc. Providing additional examples, the device (2500) may be implemented as an access point or base station. The device (2500) may implement one or more aspects as described herein to facilitate the reception and / or transmission of wireless signals according to a specific frequency or frequency band, such as a mm-Wave frequency, which is further described below, for example.

[0250] In one aspect, the device (2500) may include a processing circuit (2502), a memory (2504), and any suitable number (K) of transceiver slices or chains (2516.1 to 2516.N), each transceiver chain being connected to one or more respective antennas (2518.1 to 2518.N). The components shown in FIG. 25 are provided for convenience of explanation, and aspects include the device (2500) including additional, fewer, or alternative components compared to those shown in FIG. 25. For example, the device (2500) may include one or more power sources, display interfaces, peripherals, ports, etc.

[0251] In one aspect, various components of the device (2500) may be identified as functions further described in this specification by reference to performing multi-element estimation of the RX signal in an adaptive spatial filter, which is described in more detail in this section, to suppress correlated ADC quantization noise, to perform a roughly sectored scan in another direction simultaneously (in parallel) to detect a spatial blocker, and / or to provide attenuation / nulling in a specific spatial direction by suppressing the spatial blocker through low-latency feedback around the ADC or through feedforward connections between multiple RX elements. Each of the transceiver slices (2516.1 to 2516.N) can be identified, for example, as each of the transceiver slices (1504.1 to 1504.N) described with reference to the transceiver design (1500) shown in FIG. 15 and described in Section 3 and / or one of the receiving chains described throughout this section (e.g., receiving chains (2201.1 to 2201.N, 2301.1 to 2301.N, 2401.1 to 2401.N, etc.)).

[0252] Aspects include the processing circuit (2502) being composed of any suitable number and / or type of computer processors capable of facilitating the control of the device (2500) as discussed herein. In some aspects, the processing circuit (2502) may be identified as a baseband processor (or suitable parts thereof) implemented by the device (2500). In other aspects, the processing circuit (2502) may be identified as one or more processors implemented by the device (2500) distinct from the baseband processor (e.g., one or more digital signal processors, one or more processors associated with a DFE such as the DFE (2202, 2404) described in Section 3, DFE (1502), etc.). In other aspects, the function of the device (2500) may be combined with the function discussed herein with reference to the device (2100) (described in Section 3), which may have a function combined with the device (1400) (described in Section 3), which may also have a function combined with the function described with reference to the device (1000) (described in Section 1). In addition to, or otherwise, aspects include the various functions discussed herein with reference to the device (2500) being performed by one or more components associated with the device (2100), the device (1400), and / or the device (1000).

[0253] In any case, aspects include the processing circuit (2502) being configured to perform arithmetic, logical, and / or input / output (I / O) operations, and / or to execute commands to control the operation of one or more components of the device (2500). For example, the processing circuit (2502) may include one or more microprocessors, memory registers, buffers, clocks, etc. Additionally, aspects include the processing circuit (2502) communicating with memory (2504) and / or transceiver slices (2516.1 to 2516.N) and / or controlling associated functions.

[0254] This may include, for example, controlling and / or mediating the transmission and / or reception functions of the device (2500) as described in this specification, facilitating the detection of the circuit breaker signal as described in this specification, and using the detection of the circuit breaker signal to offset or remove the circuit breaker signal. Furthermore, the processing circuit (2502) may facilitate the calculation of beamforming weights that can be applied digitally (e.g., through a suitable DFE) and / or applied to the analog domain through a tuning circuit block (2420), the adjustment of various parameters such as the phase and / or gain of the tuning circuit block (2420), the adjustment of parameters for one or more of one or more transceiver slices (2516), the control of the state of the device (2500) to operate in a receive mode or a transmit mode, the performance of one or more baseband processing functions (e.g., media access control (MAC), encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.), the identification of a subset of interconnected receive chains for applying analog weights to spatial filtering, and any other suitable function related to the aspects disclosed herein.

[0255] In one aspect, the memory (2504) stores data and / or instructions so that when instructions are executed by the processing circuit (2502), the processing circuit (2502) performs various functions described herein. The memory (2504) may be implemented as any well-known volatile and / or non-volatile memory, including, for example, ROM (read-only memory), RAM (random access memory), flash memory, magnetic storage media, optical discs, erasable and EPROM (erasable programmable read-only memory), PROM (programmable read-only memory), etc. The memory (2504) may be fixed, removable, or a combination thereof.

[0256] For example, memory (2504) may be implemented as a non-transient computer-readable medium that stores one or more executable instructions, such as logic, algorithms, code, etc. As further discussed below, instructions, logic, code, etc. stored in memory (2504) are represented by various modules, such as those illustrated in FIG. 25, which enable the aspects disclosed herein to be functionally realized. The modules illustrated in FIG. 25 are provided for convenience of explanation regarding the functional relationship between hardware components and software components. Accordingly, the aspects include a processing circuit (2502) executing instructions stored in each of these modules together with one or more hardware components to perform various functions associated with the aspects, as further discussed herein. In other words, the modules illustrated in FIG. 25 are for convenience of explanation regarding the aspects described in this section of the disclosure.

[0257] In one aspect, an executable instruction stored in the adaptive joint estimation calculation module (2508), together with the processing circuit (2502), can facilitate the device (2500) to suppress correlated ADC quantization noise by performing multi-component estimation of the signal received from the adaptive spatial filter. This may include processing the digitized signal received through the ADC associated with each receiving chain (2201.1 to 2201.N), as described herein with reference to FIG. 22, for example.

[0258] In one aspect, an executable command stored in the sectored scanning control module (2510), together with the processing circuit (2502), can facilitate the device (2500) to perform a rough scan of various spatial regions to detect a circuit breaker signal in a direction deviating from the direction of the main beam. For example, aspects include the executable command stored in the sectored scanning control module (2510) facilitating a digital rotation of the scanning angle of data received through each of the receiving chains (2301), as described in this section with reference to FIGS. 23a through 23c. The sectored scanning control module (2510), together with the processing circuit (2502), can facilitate the device (2500) to receive digital data representing signal energy received in parallel through the spatial regions scanned for each of the receiving chains, as described herein.

[0259] In one aspect, an executable command stored in the circuit breaker signal estimation and cancellation module (2512), together with the processing circuit (2502), can facilitate the device (2500) to analyze digitized data obtained through the approximate scanning operation described herein. This may include, for example, the DFE (e.g., DFE (2202)) analyzing signal energy received through various scanned directions according to the MSB(s) output by the ADC in each receiving chain as described herein with reference to FIGS. 23a through 23c.

[0260] Furthermore, the blocker signal estimation and removal module (2512) can facilitate the calculation of signal energy within each scanned area. In the case of a scanned area (excluding the area occupied by the main beam) where an energy level exceeding a threshold energy value is detected, the estimation of the detected blocker signal can be calculated using the signal energy received across various scan directions according to the MSB output by the ADC in each receiving chain, as described in the specification with reference to FIGS. 23a through 23c. Additionally, once the blocker signal estimate is calculated, the blocker signal estimate can be used as feedback to one or more ADCs in the receiving chain to prevent the blocker signal energy from being quantized, thereby preventing ADC saturation.

[0261] In one aspect, executable commands stored in the spatial filter calculation module (2514), together with the processing circuit (2502), can facilitate dynamically adaptively tuning the spatial filter to prevent the device (2500) from receiving partial (or total) blocker signals from one or more detected directions. This may include generating and providing control signals to adjust various parameters, such as the phase and / or gain of the tuning circuit block (2420), for example, as described herein with reference to FIG. 24. Again, the output of the tuning circuit block (2420) may be combined in a weighted manner from adjacent receiver chains and used in a feedforward architecture, as described herein with reference to FIG. 24.

[0262] In addition to Sections 1 through 3, the various aspects described in this section may be combined with one another in any suitable manner to provide further improvements. For example, the aspect described in this specification with reference to FIG. 22, which aims to estimate the signal and time delay received through each receiving chain (2201) as a join, may be combined with the spatial filtering aspect described in relation to FIG. 23a through 23c and / or FIG. 24.

[0263] Yes I

[0264] The following examples relate to additional aspects.

[0265] Example 1. A local oscillator (LO) signal generator comprises a delay-locked loop (DLL) configured to generate a set of phase-shifted input signals of a sub-harmonic frequency from an input signal having a sub-harmonic frequency that is part of the output signal frequency, a phase configuration circuit connected to the DLL—the phase configuration circuit is configured to output a subset of phase-shifted signals from a set of phase-shifted input signals—and an injection-locked clock multiplier (ILCM) configured to receive a subset of phase-shifted signals as an injected input, combine the subset of phase-shifted signals, and frequency-multiply the subsets of phase-shifted signals to generate a set of LO signals of an output signal frequency.

[0266] Example 2. As the LO signal generator of Example 1, a subset of the phase-shifted signal has an equal-interval phase shift with respect to another subset that is part of the entire clock cycle, and part of the entire clock cycle is equal to part of the output signal frequency.

[0267] Example 3. As an LO signal generator of Example 1 or Example 2, the ILCM is configured to combine a subset of phase-shifted signals to cancel each other out, thereby suppressing harmonics of subharmonic frequencies except for harmonics of subharmonic signals that are equal to the output signal frequency, and the subset of phase-shifted signals canceling each other out provides a sum signal that is attenuated compared to the individual phase-shifted signals before combining, as a result of the phase relationship between the phase-shifted signals.

[0268] Example 4. As a signal generator of any one of Examples 1 to 3, the ILCM is configured to combine a subset of phase-shifted signals to interfere constructively with each other at the harmonics of the subharmonic signals that are equal to the output signal frequency, and the subset of phase-shifted signals interfering constructively with each other provides a simple summed signal compared to the individual combined phase-shifted signals prior to combining, as a result of the phase relationship between the phase-shifted signals.

[0269] Example 5. As an LO signal generator of any one of Examples 1 to 4, the LO signal set is an orthogonal differential LO signal.

[0270] Example 6. As an LO signal generator of any one of Examples 1 to 5, the output signal frequency is within the range of mm-Wave frequencies.

[0271] Example 7. As an LO signal generator of any one of Examples 1 to 6, the DLL comprises a controlled delay line having a plurality of delay elements, and the unit-phase shift associated with the phase-shifted input signal is a function of the number of delay elements.

[0272] Example 8. As an LO signal generator of any one of Examples 1 to 7, the DLL comprises an interpolation delay line having a plurality of delay elements, and the unit-phase shift associated with a set of phase-shifted input signals is smaller than the delay associated with a single delay element among the plurality of delay elements.

[0273] Example 9. As an LO signal generator of any one of Examples 1 to 8, the DLL comprises a two-dimensional matrix of delay elements interleaved with one another, and each node of the matrix is ​​supplied by two delay elements.

[0274] Example 10. As an LO signal generator of any one of Examples 1 to 9, the ILCM comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the input of the oscillator circuit is connected to a subset of phase-shifted signals.

[0275] Example 11. As an LO signal generator of any one of Examples 1 to 10, the ILCM comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the output of the oscillator circuit is connected to a subset of phase-shifted signals and the subset of phase-shifted signals is connected to the tank circuit.

[0276] Example 12. A wireless device comprises a plurality of transceiver chains; a processing circuit; and a memory configured to store executable instructions, wherein when the instructions are executed by the processing circuit, each transceiver chain among the plurality of transceiver chains generates a set of phase-shifted input signals of a sub-harmonic frequency from an input signal having a sub-harmonic frequency that is part of the output signal frequency, outputs a subset of phase-shifted signals from the set of phase-shifted input signals, and generates a set of LO signals of an output signal frequency by combining and frequency-multiplying the subset of phase-shifted signals through an Injection Locked Clock Multiplier (ILCM).

[0277] Example 13. As a wireless device of Example 12, a subset of the phase-shifted signal has an equal-spacing phase shift with respect to another subset that is part of the entire clock cycle, and part of the entire clock cycle is equal to part of the output signal frequency.

[0278] Example 14. As a wireless device of Example 12 or Example 13, each of the plurality of transceiver chains is configured to generate each set of LO signals at an output signal frequency having a phase-shifted phase with respect to the set of LO signals generated through the other transceiver chains.

[0279] Example 15. As a wireless device of any one of Examples 12 to 14, each transceiver chain of a plurality of transceiver chains combines each subset of phase-shifted signals to cancel each other, thereby suppressing harmonics of subharmonic frequencies excluding harmonics of subharmonic signals identical to the output signal frequency, and the subsets of phase-shifted signals cancel each other provide a sum signal that is attenuated compared to the individual phase-shifted signals prior to combining, as a result of the phase relationship between the phase-shifted signals.

[0280] Example 16. As a wireless device of any one of Examples 12 to 15, each transceiver chain of a plurality of transceiver chains is configured to combine a subset of phase-shifted signals to interfere constructively with each other at the same harmonic of the subharmonic signal as the output signal frequency, and the subset of phase-shifted signals interfering constructively with each other provides a simple summed signal compared to the individual combined phase-shifted signals prior to combining, as a result of the phase relationship between the phase-shifted signals.

[0281] Example 17. As a wireless device of any one of Examples 12 to 16, the LO signal set is an orthogonal differential LO signal, and the output signal frequency is within the range of mm-Wave frequencies.

[0282] Example 18. As a wireless device of any one of Examples 12 to 17, each transceiver chain of a plurality of transceiver chains comprises a DLL, wherein the DLL comprises a controlled delay line having a plurality of delay elements, and the unit-phase shift associated with the phase-shifted input signal is a function of the number of delay elements.

[0283] Example 19. As a wireless device of any one of Examples 12 to 18, each transceiver chain of a plurality of transceiver chains includes a DLL, and the DLL includes an interpolation delay line having a plurality of delay elements, and the unit-phase shift associated with a set of phase-shifted input signals is smaller than the delay associated with a single delay element among the plurality of delay elements.

[0284] Example 20. As a wireless device of any one of Examples 12 to 19, each transceiver chain of a plurality of transceiver chains includes a DLL, and the DLL includes a two-dimensional matrix of delay elements interleaved with each other, and each node of the matrix is ​​supplied by two delay elements.

[0285] Example 21. As a wireless device of any one of Examples 12 to 20, the ILCM associated with each transceiver chain of a plurality of transceiver chains comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the input of the oscillator circuit is connected to a subset of phase-shifted signals.

[0286] Example 22. As a wireless device of any one of Examples 12 to 21, an ILCM associated with each transceiver chain of a plurality of transceiver chains comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the output of the oscillator circuit is connected to a subset of phase-shifted signals and the subset of phase-shifted signals is connected to the tank circuit.

[0287] Example 23. A local oscillator (LO) signal generator comprises a delay-locked loop (DLL) configured to generate a set of phase-shifted input signals of a sub-harmonic frequency using a reference clock signal having a sub-harmonic frequency that is part of the output signal frequency, a phase configuration circuit connected to the DLL and a plurality of buffers, wherein the phase configuration circuit selectively connects each phase-shifted signal of a subset of the set of phase-shifted signals to each buffer of the plurality of buffers, and an injection locked clock multiplier (ILCM) including an oscillator circuit connected to the plurality of buffers, wherein the oscillator circuit is tuned to the output signal frequency, and the oscillator circuit is configured to generate a set of LO signals of an output signal frequency by combining and frequency-multiplying the subsets of the phase-shifted signals using current supplied by each buffer of the plurality of buffers associated with the subsets of the set of phase-shifted signals.

[0288] Example 24. As the LO signal generator of Example 23, a subset of the phase-shifted signal has an equal-interval phase shift with respect to another subset that is part of the entire clock cycle, and part of the entire clock cycle is equal to part of the output signal frequency.

[0289] Example 25. A local oscillator (LO) signal generator means comprises: a delay-locked loop (DLL) means for generating a set of phase-shifted input signals of a sub-harmonic frequency from an input signal having a sub-harmonic frequency that is part of the output signal frequency; a phase configuration means connected to the DLL, wherein the phase configuration means outputs a subset of phase-shifted signals from a set of phase-shifted input signals; and an injection locked clock multiplier (ILCM) means for receiving a subset of phase-shifted signals as an injected input, combining the subset of phase-shifted signals, and frequency-multiplying to generate a set of LO signals of an output signal frequency.

[0290] Example 26. As a means of the LO signal generator of Example 25, a subset of phase-shifted signals has an equal-interval phase shift with respect to another subset that is part of the entire clock cycle, and part of the entire clock cycle is equal to part of the output signal frequency.

[0291] Example 27. As an LO signal generator means of Example 25 or Example 26, the ILCM means is configured to combine a subset of phase-shifted signals to cancel each other, thereby suppressing harmonics of subharmonic frequencies, excluding harmonics of subharmonic signals that are equal to the output signal frequency, and the subset of phase-shifted signals canceling each other provides a sum signal that is attenuated compared to the individual phase-shifted signals prior to combining, as a result of the phase relationship between the phase-shifted signals.

[0292] Example 28. As an LO signal generator means of any one of Examples 25 to 27, the ILCM means is configured to combine a subset of phase-shifted signals to interfere constructively with each other at the harmonics of the subharmonic signals that are equal to the output signal frequency, and the subset of phase-shifted signals interfering constructively with each other provides a simple summed signal compared to the individual combined phase-shifted signals prior to combining, as a result of the phase relationship between the phase-shifted signals.

[0293] Example 29. As an LO signal generator means of any one of Examples 25 to 28, the LO signal set is an orthogonal differential LO signal.

[0294] Example 30. As an LO signal generator means of any one of Examples 25 to 29, the output signal frequency is within the range of mm-Wave frequencies.

[0295] Example 31. As an LO signal generator means of any one of Examples 25 to 30, the DLL means comprises a controlled delay line having a plurality of delay elements, and the unit-phase shift associated with the phase-shifted input signal is a function of the number of delay elements.

[0296] Example 32. As an LO signal generator means of any one of Examples 25 to 31, the DLL means comprises an interpolation delay line having a plurality of delay elements, and the unit-phase shift associated with a set of phase-shifted input signals is smaller than the delay associated with a single delay element among the plurality of delay elements.

[0297] Example 33. As an LO signal generator means of any one of Examples 25 to 32, the DLL means comprises a two-dimensional matrix of delay elements interleaved with one another, and each node of the matrix is ​​supplied by two delay elements.

[0298] Example 34. As an LO signal generator means of any one of Examples 25 to 33, the DLL means comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the input of the oscillator circuit is connected to a subset of phase-shifted signals.

[0299] Example 35. As an LO signal generator means of any one of Examples 25 to 34, the DLL means comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the output of the oscillator circuit is connected to a subset of phase-shifted signals and the subset of phase-shifted signals is connected to the tank circuit.

[0300] Example 36. A wireless device means comprises a plurality of transceiver chain means; a processing means; and a memory configured to store an executable instruction, wherein when the instruction is executed by the processing means, each transceiver chain means among the plurality of transceiver chain means generates a set of phase-shifted input signals of a sub-harmonic frequency from an input signal having a sub-harmonic frequency that is part of the output signal frequency, outputs a subset of phase-shifted signals from the set of phase-shifted input signals, and combines and frequency-multiplies the subset of phase-shifted signals through an ILCM to generate a set of LO signals of an output signal frequency.

[0301] Example 37. As a means of the wireless device of Example 36, a subset of phase-shifted signals has an equal-interval phase shift with respect to another subset that is part of the entire clock cycle, and part of the entire clock cycle is equal to part of the output signal frequency.

[0302] Example 38. As a wireless device means of Example 36 or Example 37, each transceiver chain means among a plurality of transceiver chain means is configured to generate each LO signal set at an output signal frequency having a phase-shifted phase with respect to the LO signal set generated through another transceiver chain.

[0303] Example 39. As a means of any one of Examples 36 to 38, each transceiver chain means among a plurality of transceiver chain means combines each subset of phase-shifted signals to cancel each other, thereby suppressing harmonics of subharmonic frequencies excluding harmonics of subharmonic signals identical to the output signal frequency, and the subset of phase-shifted signals canceling each other provides a summed signal that is attenuated compared to the individual phase-shifted signals prior to combining, as a result of the phase relationship between the phase-shifted signals.

[0304] Example 40. As a means of any one of Examples 36 to 39, each transceiver chain means among a plurality of transceiver chain means is configured to combine a subset of phase-shifted signals to interfere constructively with each other at the harmonics of a subharmonic signal identical to the output signal frequency, and the subset of phase-shifted signals interfering constructively with each other provides a simple summation signal compared to the individual combined phase-shifted signals prior to combining, as a result of the phase relationship between the phase-shifted signals.

[0305] Example 41. As a means of any one of Examples 36 to 40, the LO signal set is an orthogonal differential LO signal, and the output signal frequency is within the range of mm-Wave frequencies.

[0306] Example 42. As a wireless device means of any one of Examples 36 to 41, each of the plurality of transceiver chain means comprises a DLL means, and the DLL means comprises a controlled delay line having a plurality of delay elements, and the unit-phase shift associated with the phase-shifted input signal is a function of the number of delay elements.

[0307] Example 43. As a wireless device means of any one of Examples 36 to 42, each transceiver chain means among a plurality of transceiver chain means comprises a DLL means, and the DLL means comprises an interpolation delay line having a plurality of delay elements, and the unit-phase shift associated with a set of phase-shifted input signals is smaller than the delay associated with a single delay element among the plurality of delay elements.

[0308] Example 44. As a wireless device means of any one of Examples 36 to 43, each transceiver chain means among a plurality of transceiver chain means includes a DLL means, and the DLL means includes a two-dimensional matrix of delay elements interleaved with each other, and each node of the matrix is ​​supplied by two delay elements.

[0309] Example 45. As a wireless device means of any one of Examples 36 to 44, an ILCM associated with each transceiver chain means among a plurality of transceiver chain means comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the input of the oscillator circuit is connected to a subset of phase-shifted signals.

[0310] Example 46. As a wireless device means of any one of Examples 36 to 45, an ILCM associated with each transceiver chain means among a plurality of transceiver chain means comprises an oscillator circuit; a tank circuit connected to the output of the oscillator circuit; and a feedback path connected between the output of the oscillator circuit and the input of the oscillator circuit, wherein the output of the oscillator circuit is connected to a subset of phase-shifted signals and the subset of phase-shifted signals is connected to the tank circuit.

[0311] Example 47. A local oscillator (LO) signal generator means comprises a delay-locked loop (DLL) configured to generate a set of phase-shifted input signals of a sub-harmonic frequency using a reference clock signal having a sub-harmonic frequency that is part of the output signal frequency, a phase configuration means connected to the DLL means and a plurality of buffer means, wherein the phase configuration means selectively connects each phase-shifted signal of a subset of the set of phase-shifted signals to each buffer means of the plurality of buffer means, and an injection locked clock multiplier (ILCM) means including an oscillator circuit connected to the plurality of buffer means, wherein the oscillator circuit is tuned to the output signal frequency, and the oscillator circuit is configured to generate a set of LO signals of an output signal frequency by combining and frequency-multiplying a subset of phase-shifted signals using a current supplied by each buffer means of the plurality of buffer means associated with a subset of the set of phase-shifted signals.

[0312] Example 48. As a means of the LO signal generator of Example 47, a subset of phase-shifted signals has an equal-interval phase shift with respect to another subset that is part of the entire clock cycle, and part of the entire clock cycle is equal to part of the output signal frequency.

[0313] A device described and illustrated.

[0314] City and described method.

[0315] Example II

[0316] The following examples relate to additional aspects.

[0317] Example 49. A local oscillator (LO) signal generator comprises: a frequency synthesizer configured to generate a first reference signal having a first frequency; a digital-to-time converter (DTC) configured to generate a second reference signal based on the first reference signal, wherein the second reference signal has a second frequency that is a fractional multiple of the first frequency; an HB path including an Injection Locked Frequency Multiplier (ILM) of high-band (HB) ILFM, wherein the HB ILCM is configured to generate one or more HB LO signals having an HB LO frequency based on a first frequency associated with the first reference signal; and an LB frequency path including a low-band (LB) ILFM, wherein the LB ILCM is configured to generate one or more LB LO signals having an LB LO frequency based on a second frequency associated with the second reference signal.

[0318] Example 50. As an LO signal generator of Example 49, HB ILCM is one of a plurality of HB ILCMs in an HB path, and each of the plurality of HB ILCMs is associated with a respective transceiver chain, and LB ILCM is one of a plurality of LB ILCMs in an LB path, and each of the plurality of LB ILCMs is associated with a respective transceiver chain.

[0319] Example 51. As an LO signal generator of Example 49 or Example 50, the HB ILCM is configured to generate a set of orthogonal LO signals as one or more HB LO signals, and the LB ILCM is configured to generate a set of orthogonal LO signals as one or more LB LO signals.

[0320] Example 52. As an LO signal generator of any one of Examples 49 to 51, the HB ILCM is connected to one or more mixers configured to directly down-convert the received signal to baseband using one or more HB LO signals, and the LB ILCM is connected to one or more mixers configured to directly down-convert the received signal to baseband using one or more LB LO signals.

[0321] Example 53. As an LO signal generator of any one of Examples 49 to 52, the received signal directly down-converted to baseband through one or more mixers of the HB path and the received signal directly down-converted to baseband through one or more mixers of the LB path are within the mm-wave frequency range.

[0322] Example 54. As an LO signal generator of any one of Examples 49 to 53, the HB ILFM is configured to generate one or more HB LO signals having an HB LO frequency that is an integer multiple of a first frequency associated with a first reference signal.

[0323] Example 55. An LO signal generator of any one of Examples 49 to 54 further comprises another DTC configured to generate a fractionally multiplied first reference signal having a frequency that is a fractional multiple of a first frequency from a first reference signal, and the HB ILFM is configured to generate one or more HB LO signals having an HB LO frequency that is an integer multiple of a fractional multiple of a first frequency associated with the fractionally multiplied first reference signal.

[0324] Example 56. An LO signal generator of any one of Examples 49 to 55 further comprises a frequency divider circuit configured to generate a frequency divided reference signal by performing frequency division on a first reference signal, and the DTC is further configured to generate a second reference signal by performing fractional multiplication of the frequency divided reference signal.

[0325] Example 57. As an LO signal generator of any one of Examples 49 to 56, the DTC is configured to receive digital phase ramp data that is changed to adjust a fractional multiple of a first frequency and thereby adjust a second frequency associated with a second reference signal.

[0326] Example 58. A local oscillator (LO) signal generator comprising: a frequency synthesizer configured to generate a first reference signal having a first frequency; a first digital-to-time converter (DTC) configured to generate a second reference signal based on the first reference signal, wherein the second reference signal has a second frequency that is a fractional multiple of the first frequency; and an intermediate frequency (IF) mixing stage configured to generate (i) a first upconverted analog IF signal based on the first reference signal and (ii) a second upconverted analog IF signal based on the first reference signal, and a transmission mixing stage, wherein the transmission mixing stage comprises a first HB ILFM configured to generate one or more HB TX local oscillator (LO) signals and upconvert the first upconverted analog IF signal to a first transmission frequency, wherein the HB TX LO signal has an HB TX LO frequency based on the second frequency of the second reference signal. - and includes a first LB ILFM configured to generate one or more LB TX local oscillator (LO) signals and upconvert a second upconverted analog IF signal to a second transmission frequency - the LB TX LO signal has an LB TX LO frequency based on the second frequency of the second reference signal -

[0327] Example 59. As an LO signal generator of Example 58, the HB TX LO frequency is based on a first integer multiple of the first reference signal, and the LB TX LO frequency is based on a second integer multiple of the second reference signal, and the first integer multiple is different from the second integer multiple.

[0328] Example 60. As an LO signal generator of Example 58 or Example 59, further comprises a second DTC connected to a first HB ILFM, wherein the second DTC is configured to further fractionally multiply a second frequency associated with a second reference signal, and the first HB ILFM is configured to generate one or more HB TX LO signals having an HB LO TX frequency that is a first integer multiple of the additional fractional multiple of the second frequency of the second reference signal generated through the second DTC.

[0329] Example 61. An LO signal generator of any one of Examples 58 to 60 further comprises a third DTC connected to a first LB ILFM, wherein the third DTC is configured to further fractionally multiply a second frequency associated with a second reference signal, and the first LB ILFM is configured to generate one or more LB TX LO signals having an LB TX LO frequency that is a second integer multiple of an additional fractional multiple of the second frequency of the second reference signal generated through the third DTC.

[0330] Example 62. An LO signal generator of any one of Examples 58 to 61 further comprises a frequency divider circuit configured to generate a frequency divided reference signal by performing frequency division of a first reference signal, and the first DTC is further configured to generate a second reference signal by performing fractional multiplication of the frequency divided reference signal.

[0331] Example 63. An LO signal generator of any one of Examples 58 to 62 further comprises a second HB ILFM configured to generate one or more HB IF LO signals for upconverting a first baseband signal into a first upconverted analog IF signal through an IF mixing stage by multiplying a first reference signal by frequency, and a second LB ILFM configured to generate one or more LB IF LO signals for upconverting a second baseband signal into a second upconverted analog IF signal through an IF mixing stage by multiplying a first reference signal by frequency.

[0332] Example 64. As an LO signal generator of any one of Examples 58 to 63, the second HB ILCM is configured to generate an orthogonal LO signal set as one or more HB IF LO signals, and the second LB ILCM is configured to generate an orthogonal LO signal set as one or more LB IF LO signals.

[0333] Example 65. As an LO signal generator of any one of Examples 58 to 64, the first transmission frequency and the second transmission frequency are within the range of mm-Wave frequencies.

[0334] Example 66. A wireless device comprises a plurality of transceiver chains; a processing circuit; and a memory configured to store executable instructions, wherein when the instructions are executed by the processing circuit, each of the plurality of transceiver chains generates a first reference signal having a first frequency, generates a second reference signal based on the first reference signal through a digital-to-time converter (DTC) - the second reference signal has a second frequency that is a fractional multiple of the first frequency, generates one or more HB LO signals having an HB LO frequency based on the first frequency associated with the first reference signal through an HB ILCM, and generates one or more LB LO signals having an LB LO frequency based on the second frequency associated with the second reference signal through an LB ILCM.

[0335] Example 67. As a wireless device of Example 66, the HB ILCM is configured to generate a set of orthogonal LO signals as one or more HB LO signals, and the LB ILCM is configured to generate a set of orthogonal LO signals as one or more LB LO signals.

[0336] Example 68. As a wireless device of Example 66 or Example 67, the memory is further configured to store an executable instruction, and when the instruction is executed by a processing circuit, each of the multiple transceiver chains is caused to generate a fractional-multiplied first reference signal having a frequency that is a fractional multiple of the first frequency from a first reference signal through another DTC, and to generate one or more HB LO signals having an HB LO frequency that is an integer multiple of the fractional multiple of the first frequency associated with the fractional-multiplied first reference signal through an HB ILFM.

[0337] Example 69. A local oscillator (LO) signal generator means comprises: a frequency synthesizer means configured to generate a first reference signal having a first frequency; a DTC means configured to generate a second reference signal based on the first reference signal, wherein the second reference signal has a second frequency that is a fractional multiple of the first frequency; an HB path including an HB ILFM means, wherein the HB ILCM means is configured to generate one or more HB LO signals having an HB LO frequency based on a first frequency associated with the first reference signal; and an LB frequency path including an LB ILFM means, wherein the LB ILCM means is configured to generate one or more LB LO signals having an LB LO frequency based on a second frequency associated with the second reference signal.

[0338] Example 70. As an LO signal generator means of Example 69, the HB ILCM means is one of a plurality of HB ILCM means in the HB path, and each of the plurality of HB ILCM means is associated with a respective transceiver chain means, and the LB ILCM means is one of a plurality of LB ILCM means in the LB path, and each of the plurality of LB ILCM means is associated with a respective transceiver chain means.

[0339] Example 71. As an LO signal generator means of Example 69 or Example 70, the HB ILCM means generates a set of orthogonal LO signals as one or more HB LO signals, and the LB ILCM means generates a set of orthogonal LO signals as one or more LB LO signals.

[0340] Example 72. As an LO signal generator means of any one of Examples 69 to 71, the HB ILCM means is connected to one or more mixers configured to directly down-convert a received signal to baseband using one or more HB LO signals, and the LB ILCM means is connected to one or more mixers configured to directly down-convert a received signal to baseband using one or more LB LO signals.

[0341] Example 73. As an LO signal generator means of any one of Examples 69 to 72, the received signal directly down-converted to baseband through one or more mixers of the HB path and the received signal directly down-converted to baseband through one or more mixers of the LB path are within the mm-wave frequency range.

[0342] Example 74. As an LO signal generator means of any one of Examples 69 to 73, the HB ILFM means generates one or more HB LO signals having an HB LO frequency that is an integer multiple of a first frequency associated with a first reference signal.

[0343] Example 75. An LO signal generator means of any one of Examples 69 to 74 further comprises another DTC means configured to generate a fractionally multiplied first reference signal having a frequency that is a fractional multiple of a first frequency from a first reference signal, and the HB ILFM means generates one or more HB LO signals having an HB LO frequency that is an integer multiple of a fractional multiple of a first frequency associated with the fractionally multiplied first reference signal.

[0344] Example 76. As an LO signal generator means of any one of Examples 69 to 75, it further includes a frequency divider means that performs frequency division on a first reference signal to generate a frequency division reference signal, and the DTC means also performs fractional multiplication of the frequency division reference signal to generate a second reference signal.

[0345] Example 77. As an LO signal generator means of any one of Examples 69 to 76, the DTC means receives digital phase ramp data that is changed to adjust a fractional multiple of a first frequency and thereby adjust a second frequency associated with a second reference signal.

[0346] Example 78. A local oscillator (LO) signal generator means comprising: a frequency synthesizer means for generating a first reference signal having a first frequency; a first DTC means for generating a second reference signal based on the first reference signal, wherein the second reference signal has a second frequency that is a fractional multiple of the first frequency; and an IF (intermediate frequency) mixing means configured to generate (i) a first upconverted analog IF signal based on the first reference signal and (ii) a second upconverted analog IF signal based on the first reference signal; and a transmission mixing means, wherein the transmission mixing means comprises: a first HB ILFM means for generating one or more HB TX local oscillator (LO) signals and upconverting the first upconverted analog IF signal to a first transmission frequency, wherein the HB TX LO signal has an HB TX LO frequency based on the second frequency of the second reference signal; and one or more LB It includes a first LB ILFM means for generating a TX local oscillator (LO) signal and upconverting a second upconverted analog IF signal to a second transmission frequency - the LB TX LO signal has an LB TX LO frequency based on the second frequency of the second reference signal.

[0347] Example 79. As a means of the LO signal generator of Example 78, the HB TX LO frequency is based on a first integer multiple of the first reference signal, and the LB TX LO frequency is based on a second integer multiple of the second reference signal, and the first integer multiple is different from the second integer multiple.

[0348] Example 80. As an LO signal generator means of Example 78 or Example 79, further comprises a second DTC means connected to a first HB ILFM means, wherein the second DTC means further fractionally multiplies a second frequency associated with a second reference signal, and the first HB ILFM means generates one or more HB TX LO signals having an HB LO TX frequency which is a first integer multiple of an additional fractional multiple of the second frequency of the second reference signal generated through the second DTC means.

[0349] Example 81. An LO signal generator means of any one of Examples 78 to 80 further comprises a third DTC means connected to a first LB ILFM means, wherein the third DTC means is configured to further fractionally multiply a second frequency associated with a second reference signal, and the first LB ILFM means generates one or more LB TX LO signals having an LB TX LO frequency that is a second integer multiple of an additional fractional multiple of the second frequency of the second reference signal generated through the third DTC means.

[0350] Example 82. As an LO signal generator means of any one of Examples 78 to 81, it further includes a frequency divider means configured to generate a frequency divided reference signal by performing frequency division of a first reference signal, and the first DTC means further generates a second reference signal by performing fractional multiplication of the frequency divided reference signal.

[0351] Example 83. As an LO signal generator means of any one of Examples 78 to 82, it further comprises: a second HB ILFM means configured to generate one or more HB IF LO signals for upconverting a first baseband signal into a first upconverted analog IF signal through an IF mixing means by multiplying a first reference signal by frequency; and a second LB ILFM means configured to generate one or more LB IF LO signals for upconverting a second baseband signal into a second upconverted analog IF signal through an IF mixing means by multiplying a first reference signal by frequency.

[0352] Example 84. As an LO signal generator means of any one of Examples 78 to 83, the second HB ILCM means generates an orthogonal LO signal set as one or more HB IF LO signals, and the second LB ILCM means generates an orthogonal LO signal set as one or more LB IF LO signals.

[0353] Example 85. As an LO signal generator means of any one of Examples 78 to 84, the first transmission frequency and the second transmission frequency are within the range of mm-Wave frequencies.

[0354] Example 86. A wireless device means comprises a plurality of transceiver chain means; a processing circuit; and a memory configured to store an executable instruction, wherein when the instruction is executed by the processing circuit, each of the plurality of transceiver chain means generates a first reference signal having a first frequency, generates a second reference signal based on the first reference signal through a DTC means, the second reference signal having a second frequency that is a fractional multiple of the first frequency, generates one or more HB LO signals having an HB LO frequency based on the first frequency associated with the first reference signal through an HB ILCM means, and generates one or more LB LO signals having an LB LO frequency based on the second frequency associated with the second reference signal through an LB ILCM means.

[0355] Example 87. As a wireless device means of Example 86, the HB ILCM means generates a set of orthogonal LO signals as one or more HB LO signals, and the LB ILCM generates a set of orthogonal LO signals as one or more LB LO signals.

[0356] Example 88. As a wireless device means of Example 86 or Example 87, the memory is further configured to store an executable instruction, and when the instruction is executed by a processing circuit, each transceiver chain among a plurality of transceiver chains is configured to generate a fractionally multiplied first reference signal having a frequency that is a fractional multiple of a first frequency from a first reference signal through another DTC means, and to generate one or more HB LO signals having an HB LO frequency that is an integer multiple of a fractional multiple of a first frequency associated with the fractionally multiplied first reference signal through an HB ILFM means.

[0357] A device described and illustrated.

[0358] City and described method.

[0359] Example III

[0360] The following examples relate to additional aspects.

[0361] Example 89. A transceiver comprising a plurality of digital transceiver portions and a processor circuit, wherein each digital transceiver portion of the plurality of digital transceiver portions comprises a transmission path circuit connected to an antenna and configured to convert digital transmission data into an analog transmission signal transmitted through the antenna, a DC-DC converter corresponding to each digital transceiver portion and configured to provide a supply voltage, and one or more feedback components configured to provide a feedback measurement value regarding the operation of each digital transceiver portion, and the processor circuit is configured to adjust the supply voltage of the DC-DC converter based on the feedback measurement value.

[0362] Example 90. As a transceiver of Example 89, the processor circuit is configured to change the amplifier bias setting of the amplifier associated with the transmission path circuit by adjusting the supply voltage of the DC-DC converter.

[0363] Example 91. As a transceiver of Example 89 or Example 90, the processor circuit is configured to track the modulation envelope of an analog transmission signal transmitted through an antenna by adjusting the supply voltage of a DC-DC converter means to change the amplifier bias setting of the amplifier.

[0364] Example 92. As a transceiver of any one of Examples 89 to 91, one or more feedback means are configured to measure forward power and reverse power within a transmission path means associated with an analog transmission signal transmitted through an antenna, and a processor circuit is configured to (i) track the voltage standing wave ratio (VSWR) between the transmission path means and the antenna using the measured forward power and reverse power, and (ii) change the amplifier bias setting of an amplifier associated with the transmission path means based on the tracked VSWR.

[0365] Example 93. As a transceiver of any one of Examples 89 to 92, each digital transceiver portion of a plurality of digital transceiver portions further comprises a digital front end (DFE) corresponding to each digital transceiver portion in a transmission path circuit—the DFE is configured to apply digital pre-distortion (DPD) parameters to digital transmission data, and the processor circuit is configured to adjust the DPD parameters based on feedback measurements.

[0366] Example 94. As a transceiver of any one of Examples 89 to 93, each digital transceiver portion of a plurality of digital transceiver portions further comprises a digital front end (DFE) corresponding to each digital transceiver portion in a transmission path circuit—the DFE is configured to apply DPD parameters to digital transmission data, and the processor circuit is configured to adjust the DPD parameters based on the traced VSWR.

[0367] Example 95. As a transceiver of any one of Examples 89 to 94, one or more feedback means are configured to measure the junction temperature of an amplifier associated with a transmission path circuit, and a processor circuit is configured to change the amplifier bias setting of the amplifier based on the measured junction temperature by adjusting the supply current of a DC-DC converter.

[0368] Example 96. As a transceiver of any one of Examples 89 to 95, the processor circuit is configured to change the amplifier bias setting by adjusting the supply voltage of the DC-DC converter so that the analog transmission signal transmitted through the antenna has a magnitude according to the stored codebook value.

[0369] Example 97. As a transceiver of any one of Examples 89 to 96, a DC-DC converter included in each digital transceiver part of a plurality of digital transceiver parts provides an individual supply voltage that can be independently adjusted through a processor circuit in relation to other digital transceiver parts.

[0370] Example 98. As a transceiver of any one of Examples 89 to 97, it further includes a receiving path circuit connected to an antenna, and the processor circuit is configured to change the amplifier bias setting of an amplifier associated with the receiving path circuit by adjusting the supply voltage of a DC-DC converter means.

[0371] Example 99. A computer-implemented method of a transceiver comprising a plurality of digital transceiver parts, comprising the steps of: applying initial transceiver parameters associated with the settings of one or more transceiver components included in one of the plurality of digital transceiver parts through a DC-DC converter associated with one of the plurality of digital transceiver parts—one or more transceiver components are powered through a DC-DC converter—; tracking the voltage standing wave ratio (VSWR) between an amplifier and an antenna associated with one of the plurality of digital transceiver parts through a processing circuit; and adjusting the initial transceiver parameters by adjusting the settings of the DC-DC converter based on the tracked VSWR through a processing circuit.

[0372] Example 100. A computer-implemented method of Example 99 further comprises the steps of applying initial DPD parameters to digital data representing a signal to be transmitted through a common digital front end (DFE) shared among a plurality of digital transceiver parts, and updating DPD parameters based on a traced VSWR through a DFE associated with one of the plurality of digital transceiver parts.

[0373] Example 101. As a computer-implemented method of Example 99 or Example 100, (i) adjusting the settings of the DC-DC converter and (ii) adjusting the DPD parameters based on the tracked VSWR occur simultaneously.

[0374] Example 102. A computer-implemented method of any one of Examples 99 to 101 further comprises the steps of (i) adjusting the settings of a DC-DC converter and (ii) repeating the updating of DPD parameters during the operation of a transceiver over time as the tracked VSWR changes.

[0375] Example 103. As a computer-implemented method of any one of Examples 99 to 102, each of the plurality of transceiver parts includes a DC-DC converter.

[0376] Example 104. A wireless device comprises a plurality of digital transceiver portions—each digital transceiver portion of the plurality of digital transceiver portions is configured to provide a supply voltage through each DC-DC converter and to provide a feedback measurement regarding the operation of each digital transceiver portion—and a processor circuit configured to adjust the supply voltage of each DC-DC converter of each digital transceiver portion based on the feedback measurement from each digital transceiver portion.

[0377] Example 105. As a wireless device of Example 104, the processor circuit is configured to change the amplifier bias setting of the amplifier associated with the transmission path circuit included in each digital transceiver part by adjusting the supply voltage of each DC-DC converter of each digital transceiver part.

[0378] Example 106. As a wireless device of Example 104 or Example 105, the processor circuit is configured to change the amplifier bias setting of the amplifier associated with the receiving path circuit included in each digital transceiver part by adjusting the supply voltage of each DC-DC converter of each digital transceiver part.

[0379] Example 107. As a wireless device of any one of Examples 104 to 106, the processor circuit is configured to track the modulation envelope of a transmission signal associated with each digital transceiver part by changing the amplifier bias setting of an amplifier associated with a transmission path circuit included in each digital transceiver part.

[0380] Example 108. A wireless device of any one of Examples 104 to 107, wherein one or more feedback components included in each digital transceiver part are configured to measure forward power and reverse power in a transmission path circuit associated with each digital transceiver part, and a processor circuit is configured to (i) track the voltage standing wave ratio (VSWR) using the measured forward power and reverse power, and (ii) change the amplifier bias setting of an amplifier associated with a transmission path circuit included in each digital transceiver part based on the tracked VSWR.

[0381] Example 109. A wireless device of any one of Examples 104 to 108, wherein each digital transceiver portion of a plurality of digital transceiver portions further comprises a digital front end (DFE) within a transmission path circuit included in each digital transceiver portion—the DFE is configured to apply DPD parameters to digital transmission data—and a processor circuit is configured to adjust the DPD parameters based on feedback measurements.

[0382] Example 110. A wireless device of any one of Examples 104 to 109, wherein each digital transceiver part of a plurality of digital transceiver parts further comprises a digital front end (DFE) within a transmission path circuit included in each digital transceiver part—the DFE is configured to apply DPD parameters to digital transmission data—and a processor circuit is configured to adjust the DPD parameters based on the tracked VSWR.

[0383] Example 111. In any one of the wireless devices of Examples 104 to 110, one or more feedback components included in each digital transceiver part are configured to measure the junction temperature of an amplifier associated with a transmission path circuit included in each digital transceiver part, and a processor circuit is configured to change the amplifier bias setting of the amplifier based on the measured junction temperature by adjusting the supply voltage of a DC-DC converter.

[0384] Example 112. As a wireless device of any one of Examples 104 to 111, the processor circuit is configured to adjust the supply voltage of each DC-DC converter included in each digital transceiver part and change the amplifier bias setting of the amplifier associated with the transmission path circuit included in each digital transceiver part so that the transmission signal has a size according to the stored codebook size value.

[0385] Example 112B. As a wireless device of any one of Examples 104 to 112, each DC-DC converter of each digital transceiver part provides a separate supply voltage that is independently adjustable through a processor circuit to other digital transceiver parts of a plurality of digital transceiver parts.

[0386] Example 113. Transceiver means comprises a plurality of digital transceiver portions and a processor circuit, wherein each digital transceiver portion of the plurality of digital transceiver portions comprises a transmission path means connected to an antenna—the transmission path means converts digital transmission data into an analog transmission signal transmitted through the antenna—and a DC-DC converter means corresponding to each digital transceiver portion—the DC-DC converter means provides a supply voltage—and one or more feedback means providing a feedback measurement value regarding the operation of each digital transceiver portion, and the processor circuit is configured to adjust the supply voltage of the DC-DC converter based on the feedback measurement value.

[0387] Example 114. As a transceiver means of Example 113, the processor circuit is configured to change the amplifier bias setting of the amplifier associated with the transmission path means by adjusting the supply voltage of the DC-DC converter means.

[0388] Example 115. As a transceiver means of Example 113 or Example 114, the processor circuit is configured to track the modulation envelope of an analog transmission signal transmitted through an antenna by adjusting the supply voltage of the DC-DC converter means to change the amplifier bias setting of the amplifier.

[0389] Example 116. As a transceiver means of any one of Examples 113 to 115, one or more feedback means are configured to measure forward power and reverse power within a transmission path means associated with an analog transmission signal transmitted through an antenna, and a processor circuit is configured to (i) track the voltage standing wave ratio (VSWR) between the transmission path means and the antenna using the measured forward power and reverse power, and (ii) change the amplifier bias setting of an amplifier associated with the transmission path means based on the tracked VSWR.

[0390] Example 117. As a transceiver means of any one of Examples 113 to 116, each digital transceiver part of a plurality of digital transceiver parts further comprises a digital front end (DFE) means corresponding to each digital transceiver part in a transmission path means—the DFE means is configured to apply DPD parameters to digital transmission data, and the processor circuit is configured to adjust the DPD parameters based on feedback measurements.

[0391] Example 118. As a transceiver means of any one of Examples 113 to 117, each digital transceiver part of a plurality of digital transceiver parts further comprises a digital front end (DFE) means corresponding to each digital transceiver part in a transmission path means—the DFE means is configured to apply DPD parameters to digital transmission data, and the processor circuit is configured to adjust the DPD parameters based on the traced VSWR.

[0392] Example 119. As a transceiver means of any one of Examples 113 to 118, one or more feedback means are configured to measure the junction temperature of an amplifier associated with a transmission path means, and a processor circuit is configured to change the amplifier bias setting of the amplifier based on the measured junction temperature by adjusting the supply current of a DC-DC converter means.

[0393] Example 120. As a transceiver means of any one of Examples 113 to 119, the processor circuit is configured to change the amplifier bias setting by adjusting the supply voltage of the DC-DC converter means so that the analog transmission signal transmitted through the antenna has a magnitude according to the stored codebook value.

[0394] Example 121. As a transceiver means of any one of Examples 113 to 120, a DC-DC converter means included in each digital transceiver part of a plurality of digital transceiver parts provides an individual supply voltage that can be independently adjusted through a processor circuit in relation to other digital transceiver parts.

[0395] Example 122. As a transceiver means of any one of Examples 113 to 121, it further comprises a receiving path means connected to an antenna, and the processor circuit is configured to change the amplifier bias setting of an amplifier associated with the receiving path means by adjusting the supply voltage of the DC-DC converter means.

[0396] Example 123. A computer-implemented method of transceiver means comprising a plurality of digital transceiver parts, comprising the steps of: applying initial transceiver parameters associated with the settings of one or more transceiver means included in one of the plurality of digital transceiver parts through a DC-DC converter means associated with one of the plurality of digital transceiver parts—one or more transceiver means being powered through a DC-DC converter means—and tracking the VSWR between an amplifier means and an antenna associated with one of the plurality of digital transceiver parts through a processing circuit, and adjusting the initial transceiver parameters by adjusting the settings of the DC-DC converter means based on the tracked VSWR through a processing circuit.

[0397] Example 124. A computer-implemented method of Example 123 further comprises the steps of applying initial DPD parameters to digital data representing a signal to be transmitted through a common digital front end (DFE) means shared among a plurality of digital transceiver parts, and updating the DPD parameters based on a traced VSWR through a DFE means associated with one of the plurality of digital transceiver parts.

[0398] Example 125. As a computer-implemented method of Example 123 or Example 125, (i) adjusting the settings of the DC-DC converter means and (ii) adjusting the DPD parameters based on the tracked VSWR occur simultaneously.

[0399] Example 126. Any one of the computer-implemented methods of Examples 123 to 125 further comprises the steps of (i) adjusting the settings of the DC-DC converter means and (ii) repeating the updating of DPD parameters during the operation of the transceiver over time as the tracked VSWR changes.

[0400] Example 127. As a computer-implemented method of any one of Examples 123 to 126, each of the plurality of transceiver portions includes DC-DC converter means.

[0401] Example 128. A wireless device comprises a plurality of digital transceiver portions—each digital transceiver portion of the plurality of digital transceiver portions is configured to provide a supply voltage through each DC-DC converter means and to provide a feedback measurement regarding the operation of each digital transceiver portion—and a processor circuit configured to adjust the supply voltage of each DC-DC converter means of each digital transceiver portion based on the feedback measurement from each digital transceiver portion.

[0402] Example 129. As a wireless device of Example 128, the processor circuit is configured to change the amplifier bias setting of an amplifier associated with a transmission path means included in each digital transceiver part by adjusting the supply voltage of each DC-DC converter circuit of each digital transceiver part.

[0403] Example 130. As a wireless device of Example 128 or Example 129, the processor circuit is configured to change the amplifier bias setting of an amplifier associated with a receiving path means included in each digital transceiver part by adjusting the supply voltage of each DC-DC converter means of each digital transceiver part.

[0404] Example 131. As a wireless device of any one of Examples 128 to 130, the processor circuit is configured to track the modulation envelope of a transmission signal associated with each digital transceiver part by changing the amplifier bias setting of an amplifier associated with a transmission path means included in each digital transceiver part.

[0405] Example 132. A wireless device of any one of Examples 128 to 131, wherein one or more feedback component means included in each digital transceiver part are configured to measure forward power and reverse power within a transmission path means associated with each digital transceiver part, and a processor circuit is configured to (i) track VSWR using the measured forward power and reverse power, and (ii) change the amplifier bias setting of an amplifier associated with a transmission path means included in each digital transceiver part based on the tracked VSWR.

[0406] Example 133. A wireless device of any one of Examples 128 to 132, wherein each digital transceiver portion of a plurality of digital transceiver portions further comprises a digital front end (DFE) means within a transmission path means included in each digital transceiver portion—the DFE means is configured to apply DPD parameters to digital transmission data—and a processor circuit is configured to adjust the DPD parameters based on feedback measurements.

[0407] Example 134. A wireless device of any one of Examples 128 to 133, wherein each digital transceiver portion of a plurality of digital transceiver portions further comprises a digital front end (DFE) means within a transmission path means included in each digital transceiver portion—the DFE means is configured to apply DPD parameters to digital transmission data—and a processor circuit is configured to adjust the DPD parameters based on the tracked VSWR.

[0408] Example 135. In any one of the wireless devices of Examples 128 to 134, one or more feedback components included in each digital transceiver part are configured to measure the junction temperature of an amplifier associated with a transmission path means included in each digital transceiver part, and a processor circuit is configured to change the amplifier bias setting of the amplifier based on the measured junction temperature by adjusting the supply voltage of a DC-DC converter.

[0409] Example 136. As a wireless device of any one of Examples 128 to 135, the processor circuit is configured to adjust the supply voltage of each DC-DC converter means included in each digital transceiver part and change the amplifier bias setting of the amplifier associated with the transmission path means included in each digital transceiver part so that the transmission signal has a size according to the stored codebook size value.

[0410] A device described and illustrated.

[0411] City and described method.

[0412] Example IV

[0413] The following examples relate to additional aspects.

[0414] Example 137. A receiver comprising a digital front end (DFE) and a plurality of receiving chains, wherein each of the plurality of receiving chains is configured to receive a signal and downconvert the signal to a baseband signal, and each of the plurality of receiving chains includes at least one analog-to-digital converter (ADC) configured to output a digitized version of the downconverted baseband signal to the DFE, and the DFE is also configured to simultaneously process the digitized versions of the downconverted baseband signals received from each of the plurality of receiving chains to estimate the time delay associated with the signal received through each of the plurality of receiving chains.

[0415] Example 138. As a receiver of Example 137, the DFE is configured to simultaneously process digitized versions of down-converted baseband signals received from each of the multiple receiving chains by utilizing the correlation of signals received from each of the multiple receiving chains.

[0416] Example 139. As a receiver of Example 137 or Example 138, the DFE is configured to process digitized versions of down-converted baseband signals received from each of a plurality of receiving chains simultaneously with each other to estimate the signal received through each of the plurality of receiving chains, along with an estimate of the time delay associated with the signal received through each of the plurality of receiving chains.

[0417] Example 140. As a receiver of any one of Examples 137 to 139, the correlation of the signal received through each of the plurality of receiving chains and the estimate of the time delay associated with the signal received through each of the plurality of receiving chains are used to suppress quantization noise associated with one or more ADCs associated with one or more of the plurality of receiving chains.

[0418] Example 141. As a receiver of any one of Examples 137 to 140, the received signal has a frequency within the mm-Wave frequency range.

[0419] Example 142. As a receiver of any one of Examples 137 to 141, at least one ADC included in each of the receiving chains of the plurality of receiving chains includes a successive approximation (SAR) ADC.

[0420] Example 143. A receiver comprising a digital front end (DFE) and a plurality of receiving chains, wherein each receiving chain of the plurality of receiving chains is configured to receive a signal and downconvert the signal into a baseband signal, and each receiving chain of the plurality of receiving chains includes at least one ADC configured to output a digitized version of the downconverted baseband signal to the DFE, and the DFE is further configured to detect a blocker signal received in a direction different from the direction of the main beam associated with the signal by performing a sectored scan to analyze the signal energy represented by the digitized version of the downconverted baseband signal from each of the plurality of receiving chains in parallel and determining whether the analyzed signal energy exceeds a threshold energy level.

[0421] Example 144. As the receiver of Example 143, the DFE is further configured to perform a sectored scan for each of the eight quadrants of space.

[0422] Example 145. As a receiver of Example 143 or Example 144, the DFE is further configured to calculate a digitally estimated blocker signal by using at least one MSB (most significant bits) of a digitized version of a downconverted baseband signal output from at least one ADC associated with each of a plurality of receiving chains during a sectored scan.

[0423] Example 146....

Claims

Claim 1 A transceiver comprising a plurality of digital transceiver portions connected to a common digital front end (DFE) and a processor circuit, wherein each digital transceiver portion of the plurality of digital transceiver portions is configured to operate according to the same communication protocol using data communicated with the common DFE, and each digital transceiver portion includes a transmission path circuit connected to an antenna—the transmission path circuit is configured to convert digital transmission data received from the common DFE into an analog transmission signal transmitted through the antenna—a DC-DC converter connected to each digital transceiver portion—the DC-DC converter is configured to provide a supply voltage—and one or more feedback components configured to provide a feedback measurement value regarding the operation of each digital transceiver portion, and the processor circuit is configured to independently adjust the supply voltage provided by the DC-DC converter for each connected digital transceiver portion based on the feedback measurement value. Claim 2 In claim 1, the processor circuit is configured to change the amplifier bias setting of an amplifier associated with the transmission path circuit by adjusting the supply voltage provided by the DC-DC converter of at least one each connected digital transceiver portion. Claim 3 In claim 2, the processor circuit is configured to track the modulation envelope of the analog transmission signal transmitted through the antenna by adjusting the supply voltage provided by the DC-DC converter of at least one connected digital transceiver portion to change the amplifier bias setting of the amplifier. Claim 4 A transceiver according to claim 1, wherein one or more feedback components are configured to measure forward power and reverse power within the transmission path circuit associated with the analog transmission signal transmitted through the antenna, and the processor circuit is configured to (i) track the voltage standing wave ratio (VSWR) between the transmission path circuit and the antenna using the measured forward power and reverse power, and (ii) change the amplifier bias setting of the amplifier associated with the transmission path circuit based on the tracked VSWR. Claim 5 A transceiver according to claim 1, wherein each digital transceiver portion of the plurality of digital transceiver portions further comprises a digital front-end (DFE) portion corresponding to each digital transceiver portion in the transmission path circuit—each DFE portion is configured to apply a digital pre-distortion (DPD) parameter to the digital transmission data, and the processor circuit is configured to adjust the DPD parameter independently for each digital transceiver portion based on the feedback measurement value. Claim 6 A transceiver according to claim 4, wherein each digital transceiver portion of the plurality of digital transceiver portions further comprises a digital front-end (DFE) portion corresponding to each digital transceiver portion in the transmission path circuit—each DFE portion is configured to apply DPD parameters to the digital transmission data, and the processor circuit is configured to adjust the DPD parameters independently of each other for each digital transceiver portion based on the tracked VSWR. Claim 7 A transceiver according to any one of claims 1 to 5, wherein the one or more feedback components are configured to measure the junction temperature of an amplifier associated with the transmission path circuit, and the processor circuit is configured to change the amplifier bias setting of the amplifier based on the measured junction temperature by adjusting the supply voltage provided by the DC-DC converter of at least one each connected digital transceiver part. Claim 8 In claim 2, the processor circuit is configured to change the amplifier bias setting by adjusting the supply voltage provided by the DC-DC converter of at least one connected digital transceiver part so that the analog transmission signal transmitted through the antenna has a magnitude according to a stored codebook value. Claim 9 A transceiver according to claim 1, wherein each digital transceiver portion of the plurality of digital transceiver portions further includes a digital front-end (DFE) portion separated from the common DFE, and the DFE portion corresponding to the common DFE and each digital transceiver portion is configured to perform different functions for the same communication protocol. Claim 10 A transceiver according to any one of claims 1 to 5, further comprising a receiving path circuit connected to the antenna, wherein the processor circuit is configured to change the amplifier bias setting of an amplifier associated with the receiving path circuit by adjusting the supply voltage provided by the DC-DC converter of at least one each connected digital transceiver portion. Claim 11 A transceiver according to claim 2, wherein each digital transceiver portion of the plurality of digital transceiver portions is connected to a different respective antenna element in a phase antenna array, and the processor circuit is configured to perform amplitude tapering across the different respective antenna elements of the phase antenna array by adjusting the supply voltage provided by the DC-DC converter of each connected digital transceiver portion and independently adjusting the bias conditions of the amplifier associated with each connected digital transceiver portion. Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 A wireless device comprising: a plurality of digital transceiver portions connected to a common digital front end (DFE)—each digital transceiver portion of the plurality of digital transceiver portions is configured to operate according to the same communication protocol using data communicated with the common DFE, provide a supply voltage through a DC-DC converter connected to each, and provide a feedback measurement value regarding the operation of each digital transceiver portion—and a processor circuit configured to independently adjust the supply voltage provided by each DC-DC converter of each digital transceiver portion based on the feedback measurement value from each digital transceiver portion. Claim 17 A wireless device according to claim 16, wherein the processor circuit is configured to change the amplifier bias setting of an amplifier associated with a transmission path circuit included in each digital transceiver part by adjusting the supply voltage provided by each DC-DC converter of each digital transceiver part. Claim 18 A wireless device according to claim 16, wherein the processor circuit is configured to change the amplifier bias setting of an amplifier associated with a receiving path circuit included in each digital transceiver part by adjusting the supply voltage provided by each DC-DC converter of each digital transceiver part. Claim 19 A wireless device according to claim 17, wherein the processor circuit is configured to track the modulation envelope of a transmission signal associated with each digital transceiver part by changing the amplifier bias setting of the amplifier associated with the transmission path circuit included in each digital transceiver part. Claim 20 A wireless device according to any one of claims 16 to 19, wherein one or more feedback components included in each digital transceiver part are configured to measure forward power and reverse power within a transmission path circuit associated with each digital transceiver part, and the processor circuit is configured to (i) track a voltage standing wave ratio (VSWR) using the measured forward power and reverse power, and (ii) change the amplifier bias setting of an amplifier associated with the transmission path circuit included in each digital transceiver part based on the tracked VSWR. Claim 21 A wireless device according to any one of claims 16 to 19, wherein each digital transceiver portion of the plurality of digital transceiver portions further comprises a digital front-end (DFE) portion within a transmission path circuit included in each digital transceiver portion—each DFE portion is configured to apply a digital pre-distortion (DPD) parameter to digital transmission data received from the common DFE—and the processor circuit is configured to adjust the DPD parameter independently for each digital transceiver portion based on the feedback measurement. Claim 22 A wireless device according to claim 20, wherein each digital transceiver portion of the plurality of digital transceiver portions further comprises a digital front-end (DFE) portion within a transmission path circuit included in each digital transceiver portion—each DFE portion is configured to apply digital pre-distortion (DPD) parameters to digital transmission data received from the common DFE—and the processor circuit is configured to adjust the DPD parameters independently of each other for each digital transceiver portion based on the tracked VSWR. Claim 23 A wireless device according to any one of claims 16 to 19, wherein one or more feedback components included in each digital transceiver part are configured to measure the junction temperature of an amplifier associated with a transmission path circuit included in each digital transceiver part, and the processor circuit is configured to independently change the amplifier bias setting of the amplifier by adjusting the supply voltage provided by the DC-DC converter for each digital transceiver part based on the measured junction temperature. Claim 24 A wireless device according to any one of claims 16 to 19, wherein the processor circuit is configured to independently adjust the supply voltage provided by each DC-DC converter included in each digital transceiver part, thereby changing the amplifier bias setting of the amplifier associated with the transmission path circuit included in each digital transceiver part so that the transmission signal has a size according to the stored codebook size value. Claim 25 delete

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