Low-power power on reset circuit

Abstract

A power-on reset circuit is disclosed, comprising: a first resistor portion including a plurality of P-type MOSFETs and having a resistance value determined by a preset reference voltage; and a second resistor portion including a plurality of N-type MOSFETs and having a resistance value determined by the reference voltage, wherein a power supply voltage is applied to one end of the first resistor portion and the other end of the first resistor portion is connected to one end of the second resistor portion, and a reset signal is output at the connection node between the first resistor portion and the second resistor portion.

Description

Technology Field

[0001] The present invention relates to a low-power power-on reset (POR, hereinafter also referred to as 'POR') circuit, and more specifically, to a power-on reset circuit that generates a reset signal based on the magnitude of a power supply voltage. Background Technology

[0003] Generally, a power-on reset circuit is a device for maintaining digital logic in a reset state during the time period while the supplied power voltage rises to the operating voltage level of digital logic, such as a processor or system-on-chip, or for switching digital logic to a reset state in advance before the power voltage decreases to a level below the operating voltage level.

[0004] The requirements for a POR circuit are broadly two: first, to ensure a reset when the power supply is lower than the operating voltage, and second, to have low power consumption.

[0005] FIG. 1 is a diagram illustrating an example of a conventional power-on reset circuit. As shown in FIG. 1, the conventional power-on reset circuit has a structure in which the level of the reset output is determined based on the capacitor voltage formed by the charging of the capacitor (C). Consequently, a problem arises in which the fluctuation of the reset output level increases depending on operating conditions, operating environment, etc.

[0007] The matters described above as background technology are intended only to enhance understanding of the background of the present invention and should not be construed as an acknowledgment that they constitute prior art already known to those skilled in the art. Prior art literature

[0009] Korean Published Patent No. 10-2013-0062911 (June 13, 2013) Korean Published Patent No. 10-2003-0052365 (June 27, 2003) The problem to be solved

[0010] Accordingly, the present invention aims to solve the technical problem of providing a power-on reset circuit that can be implemented in a small size with minimal fluctuation in the reset level.

[0012] The problems to be solved by the present invention are not limited to those described above, and other problems and advantages of the present invention not mentioned can be understood from the following description and will become more clearly known through the embodiments of the present invention. Furthermore, a person skilled in the art to which the present invention pertains will readily understand that the problems and advantages of the present invention can be realized by the means and combinations thereof set forth in the claims. means of solving the problem

[0014] As a means to solve the above technical problem, the present invention is,

[0015] A first resistor comprising a plurality of P-type MOSFETs, wherein the resistance value is determined by a preset reference voltage;

[0016] It includes a plurality of N-type MOSFETs and a second resistor whose resistance value is determined by the reference voltage,

[0017] A power-on reset circuit is provided, characterized in that a power supply voltage is applied to one end of the first resistor, the other end of the first resistor is connected to one end of the second resistor, and a reset signal is output at the connection node between the first resistor and the second resistor.

[0018] In an embodiment of the present invention, the resistance value of the first resistor is determined by the ON resistance of the plurality of P-type MOSFETs, and the resistance value of the second resistor can be determined by the ON resistance of the plurality of N-type MOSFETs.

[0019] In an embodiment of the present invention, the first resistor may be a pseudo resistor composed of the plurality of P-type MOSFETs.

[0020] In an embodiment of the present invention, the first resistor comprises a first P-type MOSFET and a second P-type MOSFET, wherein the source and the bulk are connected to each other and the reference voltage is applied to the gate in common, and the power supply voltage is applied to the drain of the first P-type MOSFET and the drain of the second P-type MOSFET can be connected to the connection node.

[0021] In an embodiment of the present invention, the second resistor may be a pseudo-resistor composed of the plurality of N-type MOSFETs.

[0022] In an embodiment of the present invention, the second resistor may be a pseudo-resistor composed of the plurality of N-type MOSFETs.

[0023] In an embodiment of the present invention, the second resistor comprises a first N-type MOSFET and a second N-type MOSFET, wherein the source and the bulk are connected to each other and the reference voltage is applied to the gate in common, and the drain of the first N-type MOSFET may be connected to the connection node.

[0024] In an embodiment of the present invention, the second resistor is formed by sequentially connecting the source of one of the plurality of N-type MOSFETs and the drain of another to form a stack, and the gates of the plurality of N-type MOSFETs may have the reference voltage applied in common. Effects of the invention

[0026] According to the above power-on reset circuit, it has the effect of enabling stable operation by reducing the size and decreasing the fluctuation range of the reset output level depending on operating conditions or operating environment.

[0028] The effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0030] The following drawings attached to this specification illustrate preferred embodiments of the present invention and serve to facilitate a better understanding of the technical concept of the present invention together with the detailed description of the invention provided below; therefore, the present invention should not be interpreted as being limited only to the matters described in the following drawings. Figure 1 is a circuit diagram of a conventional power-on reset circuit. FIG. 2 is a block diagram of a power-on reset circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a power-on reset circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram of a power-on reset circuit according to another embodiment of the present invention. Specific details for implementing the invention

[0031] Hereinafter, a low-power power-on reset circuit according to various embodiments of the present invention will be described in detail with reference to the attached drawings.

[0032] Specific structural or functional descriptions of the embodiments described below are disclosed merely for illustrative purposes and may be modified and implemented in various forms. Accordingly, the embodiments are not limited to specific disclosed forms, and the scope of this specification includes modifications, equivalents, or substitutions that fall within the technical concept.

[0033] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0034] When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or joined to that other component, or that there may be other components in between.

[0035] The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0036] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0037] FIG. 2 is a block diagram of a power-on reset circuit according to an embodiment of the present invention.

[0038] Referring to FIG. 2, it may be configured to include a first resistor (11) comprising a plurality of P-type MOSFETs and whose resistance value is determined by a preset reference voltage (REF), and a second resistor (11) comprising a plurality of N-type MOSFETs and whose resistance value is determined by the reference voltage (REF).

[0039] A power supply voltage is applied to one end of the first resistor (11), and the other end of the first resistor (11) is connected to one end of the second resistor (12), and the connection node (OUT) between the first resistor (11) and the second resistor (12) can be an output terminal where a reset signal is output.

[0040] The resistance value of the first resistor (11) can be determined by the ON resistance of a plurality of P-type MOSFETs included in the first resistor (11), and the resistance value of the second resistor (12) can be determined by the ON resistance of a plurality of N-type MOSFETs included in the second resistor (12).

[0041] In this way, in one embodiment of the present invention, the level of a reset signal can be determined and output by the ratio of the resistance value of the first resistor (11) and the resistance value of the second resistor (12) determined by the reference voltage (REF).

[0042] FIG. 3 is a circuit diagram of a power-on reset circuit according to an embodiment of the present invention.

[0043] Referring to FIG. 3, the first resistor (11) of the power-on reset circuit according to an embodiment of the present invention can be implemented with a first P-type MOSFET (P1) and a second P-type MOSFET (P2) that constitute a pseudo resistor, and the second resistor (12) can also be implemented with a first N-type MOSFET (N1) and a second N-type MOSFET (N2) that constitute a pseudo resistor.

[0044] Each of the first P-type MOSFET (P1) and the second P-type MOSFET (P2) constituting the first resistor section (11) may have their sources and bulk connected to each other, and a reference voltage (REF) may be applied to their gates in common. The sources of each of the first P-type MOSFET (P1) and the second P-type MOSFET (P2) may be connected to each other. Additionally, a power supply voltage (VDD) may be applied to the drain of the first P-type MOSFET (P1), and the drain of the second P-type MOSFET (P2) may be connected to a connection node (OUT) that is connected to the second resistor section (12).

[0045] Similarly, the first N-type MOSFET (N1) and the second N-type MOSFET (N2) constituting the second resistor (12) each have their sources and bulk connected to each other, and a reference voltage (REF) can be applied to their gates in common. The sources of the first N-type MOSFET (N1) and the second N-type MOSFET (N2) can be connected to each other. Additionally, the drain of the first N-type MOSFET (N1) can be connected to a connection node (OUT) connected to the first resistor (11).

[0046] In the circuit structure of the embodiment shown in FIG. 3, the reference voltage (REF) may be a constant voltage value provided by a circuit such as an external bandgap reference. The reference voltage (REF) may be applied to the gate of a MOSFET constituting a pseudo-resistor provided in the first resistor part (11) and the second resistor part (12) and used to determine the resistance value of the pseudo-resistor.

[0047] The pseudoresistors can be implemented such that the sources and bulks of the first P-type MOSFET (P1) and the second P-type MOSFET (P2), respectively, are connected to each other, and the sources and bulks of the first N-type MOSFET (N1) and the second N-type MOSFET (N2), respectively, are connected to each other so that the MOSFETs can operate in the weak inversion region. The resistance values ​​of the pseudoresistors constituting the first resistor section (11) and the second resistor section (12) can be determined according to the physical properties of the MOSFETs constituting each.

[0048] A reset signal may be output at a connection node (OUT) that outputs a reset signal based on the resistance values ​​of the first resistor (11) and the second resistor (12). For example, when the power supply voltage (VDD) decreases to a specific level, the connection node (OUT) that outputs the reset signal may output a signal corresponding to a low level, and when the power supply voltage (VDD) gradually increases to a specific level, the connection node (OUT) that outputs the reset signal may output a signal corresponding to a high level. The level at which the signal output from the node (OUT) is switched may be determined by the ratio of the resistance values ​​of the first resistor (11) and the second resistor (12), and the resistance values ​​of the first resistor (11) and the second resistor (12) may be appropriately tuned by the MOSFET design of the pseudo-resistors constituting each.

[0049] FIG. 4 is a circuit diagram of a power-on reset circuit according to another embodiment of the present invention.

[0050] The embodiment shown in FIG. 4 has a circuit structure in which the configuration of the second resistor (12) is changed compared to the embodiment shown in FIG. 3.

[0051] Referring to FIG. 4, the first resistor (11) of the power-on reset circuit according to another embodiment of the present invention can be implemented with a first P-type MOSFET (P1) and a second P-type MOSFET (P2) that constitute a pseudo resistor, just like in the embodiment of FIG. 3, and the second resistor (12) can also be implemented with a first N-type MOSFET (N1) and a second N-type MOSFET (N2) that constitute a pseudo resistor.

[0052] Each of the first P-type MOSFET (P1) and the second P-type MOSFET (P2) constituting the first resistor section (11) may have their sources and bulk connected to each other, and a reference voltage (REF) may be applied to their gates in common. The sources of each of the first P-type MOSFET (P1) and the second P-type MOSFET (P2) may be connected to each other. Additionally, a power supply voltage (VDD) may be applied to the drain of the first P-type MOSFET (P1), and the drain of the second P-type MOSFET (P2) may be connected to a connection node (OUT) that is connected to the second resistor section (12).

[0053] Meanwhile, the second resistor (12) can be implemented in a stacked form of multiple N-type MOSFETs. That is, each of the multiple N-type MOSFETs (N1, Nn) (n is a natural number greater than or equal to 2) constituting the second resistor (12) has a stacked structure in which the drain and source are sequentially connected. The source of one N-type MOSFET can be connected to the drain of another N-type MOSFET, and the source of another N-type MOSFET can be connected to the drain of yet another N-type MOSFET in a sequential stacked structure. A reference voltage (REF) can be connected to the gates of the multiple N-type MOSFETs (N1, Nn) constituting the second resistor (12).

[0054] The circuit structure shown in FIG. 4 is very similar to the circuit of FIG. 3 described above. However, since the second resistor (12) is composed of stacked N-type MOSFETs, the resistance value of the second resistor (12) can be substantially the same as the on-resistance of all stacked N-type MOSFETs connected in series.

[0055] Similar to the embodiment illustrated in FIG. 3, the resistance value of the pseudo-resistor of the first resistor (11) can be determined by various physical properties of the MOSFET constituting it, and the pseudo-resistor can be implemented in a structure in which the source and bulk of each of the first P-type MOSFET (P1) and the second P-type MOSFET (P2) are connected to each other so that the MOSFET can operate in the weak inversion region. In addition, in the embodiment of FIG. 4, the reset signal output from the node (OUT) can be switched according to the level change of the power supply voltage (VDD), and the level at which the reset signal is switched can be determined by the ratio of the resistance values ​​of the first resistor (11) and the second resistor (12). The resistance values ​​of the first resistor (11) and the second resistor (12) can be appropriately tuned by the MOSFET design constituting each.

[0056] As described above, the power-on reset circuit according to various embodiments of the present invention can reduce the level variability of the reset signal in various aspects by utilizing the on-resistance of a MOSFET when generating a reset signal, and in particular by generating the on-resistance as a pseudo-resistance, and can reduce the circuit size and reduce current consumption. Explanation of the symbols

[0058] 11: First resistance section 12: Second resistance section P1, P2: P-type MOSFET N1, N2: N-type MOSFET

Claims

Claim 1 A power-on reset circuit comprising: a first resistor portion including a plurality of P-type MOSFETs and having a resistance value determined by a preset reference voltage; a second resistor portion including a plurality of N-type MOSFETs and having a resistance value determined by the reference voltage, wherein a power supply voltage is applied to one end of the first resistor portion and the other end of the first resistor portion is connected to one end of the second resistor portion, and a reset signal is output at a connection node between the first resistor portion and the second resistor portion, wherein the plurality of P-type MOSFETs of the first resistor portion include a first P-type MOSFET and a second P-type MOSFET, wherein the source and bulk are connected to each other and the reference voltage is applied to the gate in common, and wherein the power supply voltage is applied to the drain of the first P-type MOSFET and the drain of the second P-type MOSFET is connected to the connection node. Claim 2 A power-on reset circuit according to claim 1, wherein the resistance value of the first resistor is determined by the ON resistance of the plurality of P-type MOSFETs, and the resistance value of the second resistor is determined by the ON resistance of the plurality of N-type MOSFETs. Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 A power-on reset circuit comprising: a first resistor portion including a plurality of P-type MOSFETs and having a resistance value determined by a preset reference voltage; a second resistor portion including a plurality of N-type MOSFETs and having a resistance value determined by the reference voltage, wherein a power supply voltage is applied to one end of the first resistor portion and the other end of the first resistor portion is connected to one end of the second resistor portion, and a reset signal is output at a connection node between the first resistor portion and the second resistor portion, wherein the plurality of N-type MOSFETs of the second resistor portion include a first N-type MOSFET and a second N-type MOSFET, wherein the source and bulk are connected to each other and the reference voltage is applied to the gate in common, and the drain of the first N-type MOSFET is connected to the connection node. Claim 8 A power-on reset circuit according to claim 1 or claim 2, wherein the second resistor is characterized in that the source of one of the plurality of N-type MOSFETs and the drain of another are sequentially connected to form a stack, and the gates of the plurality of N-type MOSFETs are commonly supplied with the reference voltage.

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