Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method for manufacturing a semiconductor device are disclosed. As a non-limiting example, various aspects of the present invention provide a stackable semiconductor device having a small size and a fine pitch and a method for manufacturing the same.

Description

Technology Field

[0001] Various embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Current semiconductor devices and methods for manufacturing semiconductor devices have problems such as being unsuitable due to excessively low sensitivity, high cost, reduced reliability, and excessively large package sizes. The limitations and disadvantages of conventional and prior art methods will become clear to those skilled in the art through a comparison of these approaches with the current methods described in the remainder of the invention with reference to the drawings. The problem to be solved

[0003] The problem to be solved by the present invention is to provide a new semiconductor device and manufacturing method that overcomes the limitations of conventional semiconductor devices and manufacturing methods. means of solving the problem

[0004] Various embodiments of the present invention provide a semiconductor device and a method for manufacturing a semiconductor device. As a non-limiting example, various embodiments of the present invention provide a semiconductor device capable of stacking with a small size and fine pitch, and a method for manufacturing the same.

[0005] A semiconductor device according to one embodiment of the present invention comprises: a substrate including an upper substrate surface, a lower substrate surface, and side end substrate surfaces extending between the upper substrate surface and the lower substrate surface; a semiconductor die including an upper die surface, a lower die surface, and a side end die surface extending between the upper die surface and the lower die surface, wherein the lower die surface is coupled to the upper substrate surface; a metal pillar including an upper pillar surface, a lower pillar surface, and a side end pillar surface extending between the upper pillar surface and the lower pillar surface, wherein the lower pillar surface is coupled to the upper substrate surface through an adhesive member and is located in an area of ​​the upper substrate surface other than the area covered by the semiconductor die; and a sealing material that seals at least a portion of the side end die surface and at least a portion of the side end pillar surface.

[0006] The above adhesive member includes solder.

[0007] Preferably, the upper filament is in the same plane as the upper die.

[0008] Preferably, the upper filament is flush with the upper surface of the sealing material.

[0009] The semiconductor device may further include an upper substrate surface, a lower upper substrate surface, and a side upper substrate surface extending between the upper upper substrate surface and the lower upper substrate surface.

[0010] The upper substrate may include a lower conductive pattern in which the metal pillar is integrally formed.

[0011] The metal pillar can be plated on the conductive pattern.

[0012] Preferably, the upper substrate is positioned directly on the metal pillar and includes a lower conductive pattern and an upper conductive pattern formed integrally with the metal pillar.

[0013] Preferably, the side die surface is in the same plane as each of the side substrate surfaces and each side upper substrate surface.

[0014] A method for manufacturing a semiconductor device according to another embodiment of the present invention comprises: a step of coupling a lower surface of a semiconductor die to an upper surface of a first substrate; a step of providing a second substrate, wherein the second substrate comprises a metal pillar protruding from the lower surface of the second substrate; and a step of coupling a lower surface of the metal pillar to an upper surface of the first substrate.

[0015] The step of bonding the lower surface of the metal pillar to the upper surface of the first substrate may involve bonding the lower surface of the metal pillar to the upper surface of the first substrate through an adhesive member.

[0016] The above adhesive member may include soldering.

[0017] Preferably, the second substrate includes an insulating member, and after the step of bonding the bottom surface of the metal pillar, the step of removing at least a portion of the insulating member is included.

[0018] Preferably, the second substrate includes a seed layer on the upper surface of the insulating member, and after the step of bonding the lower surface of the metal pillar to the upper surface of the first substrate, the step of removing the seed layer is included.

[0019] The second substrate provided above may include a bottom conductive pattern on which the metal pillar is plated.

[0020] After the step of joining the bottom surface of the metal pillar, the method may include the step of removing the bottom conductive pattern.

[0021] A method for manufacturing a semiconductor device according to another embodiment of the present invention comprises: a step of bonding a bottom surface of a semiconductor die to a top surface of a first substrate; a step of forming a second substrate, wherein the second substrate comprises a metal pillar protruding from the second substrate, an adhesive member on the surface of the metal pillar, and an insulating member surrounding at least a portion of the metal pillar; and a step of bonding the adhesive member to the top surface of the first substrate.

[0022] The method may include the step of forming the metal pillar by plating the metal pillar on at least a portion of the conductive pattern of the second substrate.

[0023] The method may include the step of forming the adhesive member by patterning a temporary material on at least a portion of the insulating member and forming the adhesive member on the surface of the metal pillar. Effects of the invention

[0024] Various embodiments of the present invention provide a semiconductor device capable of stacking with a small size and fine pitch, and a method for manufacturing the same.

[0025] In an exemplary semiconductor device of the present invention, metal pillars having a fine pitch are disposed on the top surface of a substrate and exposed to the outside of a sealant, thereby enabling the realization of a fine pitch and reducing the overall size, while simultaneously allowing another semiconductor device (or vice versa) to be stacked on top of the semiconductor device. Brief explanation of the drawing

[0026] FIG. 1 illustrates a cross-sectional view of a semiconductor device according to various embodiments of the present invention. FIG. 2 shows a cross-sectional view of a semiconductor device according to various embodiments of the present invention. FIGS. 3a to 3f are drawings illustrating a method for manufacturing a semiconductor device according to various embodiments of the present invention. FIGS. 4a to 4i are drawings illustrating a method for manufacturing a semiconductor device according to various embodiments of the present invention. FIGS. 5a to 5f are drawings illustrating methods for manufacturing semiconductor devices in various embodiments of the present invention. Specific details for implementing the invention

[0027] Various aspects of the present invention described below are disclosed by describing the embodiments thereof. These embodiments are non-limiting, and the scope of the various aspects of the present invention disclosed should not be inevitably limited by the specific attributes of the embodiments presented herein. In the description below, the terms “by example,” “for example,” and “exemplary” are non-limiting and are generally equivalent to expressions such as “by example and as non-limiting,” “for example, and not limited thereto,” etc.

[0028] As used herein, "and / or" means one or more items in the list connected by "and / or". For example, "x and / or y" means any element of the three-element set {(x), (y), (x, y)}. That is, "x and / or y" means "one or both of x and y". As another example, "x, y, and / or z" means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. That is, "x, y and / or z" means one or more of "x, y, and z". As used herein, “eg,” and “for example” establish one or more non-definite examples, cases, or diagrams.

[0029] The terms used herein are merely for describing specific embodiments and are not intended to limit the invention. As used herein, the singular form is intended to include the plural form unless otherwise evidently presented. As used herein, terms such as “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” etc. refer to features, integers, steps, actions, components, and / or parts, and it will be understood that the presence or addition of one or more of features, integers, steps, actions, components, parts, and / or groups thereof is not excluded.

[0030] Although terms such as first, second, etc. may be used herein to describe various components, it will be understood that these components should not be limited to these terms. These terms are used to distinguish one component from another. Thus, for example, the first component, first part, or first section described below may be referred to as the second component, second part, or second section without departing from the teachings of the present invention. Similarly, various spatial terms such as "upper," "lower," "side," "top," "bottom," etc., may be used to distinguish one component from another in a relative manner. However, components may be positioned in other ways; for example, without departing from the teachings of the present invention, it should be understood that a semiconductor device may be positioned sideways such that the "top" surface faces horizontally and its "side" surface faces vertically.

[0031] Furthermore, the terms combined, connected, and attached include the meanings of direct or indirect connection, connection, and attachment (e.g., through intermediate components) unless explicitly indicated otherwise. For example, if component A is combined with component B, component A may be indirectly connected to component B through an intermediate signal distribution structure, or component A may be directly connected to component B (e.g., directly attached, directly soldered, or directly bonded via metal-to-metal bonding).

[0032] In the drawings, dimensions of structures, floor areas, etc. (e.g., absolute and / or relative dimensions) may be exaggerated for clarity. These dimensions generally represent exemplary implementations, but are not limited thereto. For example, if structure A is depicted as being larger than area B, this represents an exemplary implementation and, unless otherwise noted, does not require that structure A be generally larger than structure B. Additionally, similar reference numerals in the drawings may refer to similar components throughout the detailed description.

[0033] Various embodiments of the present invention provide a semiconductor device comprising a substrate, a semiconductor die coupled to one surface of the substrate, metal pillars coupled to one surface of the substrate, and an encapsulant that seals and insulates the semiconductor die and the metal pillars and exposes the metal pillars. The metal pillars may be formed vertically, for example, along a hole in the encapsulant.

[0034] Various aspects of the present invention provide a method for manufacturing a semiconductor device comprising the steps of: providing a carrier substrate comprising a metal pillar and an insulating element surrounding the metal pillar; coating and patterning a photoresist on one surface of the insulating element; performing plating on the metal pillar; bonding the metal pillar to a substrate; removing the photoresist and the carrier substrate; and forming a sealant that seals the metal pillar.

[0035] Various embodiments of the present invention provide a method for manufacturing a semiconductor device, the method comprising the steps of: providing a seed layer and a photoresist on one side of a carrier substrate; forming a metal pillar by performing plating in the pattern of the photoresist; removing the photoresist; bonding the metal pillar to a substrate; forming a sealant that seals the metal pillar; and removing the carrier substrate.

[0036] Various embodiments of the present invention provide, for example, a semiconductor device comprising fine-pitch metal pillars on the top surface of a substrate, wherein the metal pillars are exposed outside a sealant so as to enable the stackable semiconductor device to have a small size and a fine-pitch pattern spacing. Additionally, the semiconductor device may include, for example, an upper substrate coupled to the metal pillars.

[0037] Various embodiments of the present invention are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice them.

[0038] FIG. 1 shows a cross-sectional view of a semiconductor device according to various embodiments of the present invention. A semiconductor device (100) according to one embodiment may include, for example, a substrate (110), a semiconductor die (120), metal pillars (130), a sealant (140), and conductive balls (150).

[0039] The substrate (110) may be formed, for example, generally as a printed circuit board (PCB) or a lead frame. Additionally, the substrate (110) may be formed as a built-up substrate made of silicon substrate in a semiconductor process. Although not individually illustrated, the substrate (110) may include one or more conductive layers (e.g., metal, etc.) such that electrically coupled pads formed on the top and bottom surfaces of the substrate allow a semiconductor die (120) or metal pillar (130) placed above to be electrically connected to a conductive ball (150) placed below. The conductive layers of such a substrate (110) may include, for example, copper (Cu), aluminum (Al), alloys thereof, etc. However, the scope of the invention is not limited thereto. For additionally enhanced connectivity, a metal such as gold (Au) may additionally be applied to the pads.

[0040] The semiconductor die (120) may include, for example, an integrated circuit chip separated from a semiconductor wafer. The semiconductor die (120) may include any one of various types of electrical circuits, for example, a central processing unit (CPU), digital signal processors (DSP), a network processor, a power management unit, an audio processor, an RF circuit, a wireless-based System on Chip (SoC), a sensor, an application-specific integrated circuit, etc.

[0041] A semiconductor die (120) may, for example, input and / or output an electrical signal to and / or from a first surface (e.g., a bottom surface) through a conductive pad (121). The conductive pad (121) may generally comprise aluminum (Al) and / or other conductive materials. Additionally, the conductive pad (121) of the semiconductor die (120) may be electrically connected to a ball (or pad or other interconnecting structure) formed on the top surface of the substrate (110) through a conductive adhesive element (120a) (e.g., solder, conductive epoxy, etc.). Direct metal-to-metal (e.g. solderless) heterogeneous metal bonding may also be utilized. The semiconductor die (120) may, for example, include a passivation layer that insulates areas other than the region where the conductive pad (121) is exposed. Although one conductive pad (121) has been described, a different number of such conductive pads may be presented.

[0042] The semiconductor die (120) may include, for example, a second surface (e.g., a top surface) opposite to the first surface (e.g., a bottom surface). The second surface (122) may be exposed to the outside (e.g., exposed from the sealing material). The second surface (122) may be exposed to the outside of the sealing material (140) by having the same height as the top surface of the sealing material (140), for example. In this exemplary configuration, the semiconductor die (120) may be configured to facilitate heat dissipation from the semiconductor die (120) to the outside.

[0043] A metal pillar (130) protrudes from the top surface of the substrate (110). The metal pillar (130) may be made of, for example, a metal (e.g., copper, etc.) and may be placed in an area other than the area where the semiconductor die (120) is located. The metal pillar (130) may be electrically connected to the substrate (110) through, for example, a conductive adhesive member (130a, including, for example, solder). Additionally, the metal pillar (130) may be exposed from the upper area of ​​the seal (140) (e.g., from the top surface). In some cases, the end (131) of the metal pillar (130) may extend further from the substrate (110) than the seal (140), for example, protrude from the top surface of the seal (140). When another semiconductor device is stacked on top of this semiconductor device (100), the semiconductor devices can be electrically connected to each other through a metal pillar (130).

[0044] In an exemplary embodiment, the metal pillar (130) has a width ranging from, for example, about 10 μm to 15 μm. Thus, compared to using soldering bumps with a diameter of about 350 μm, the metal pillar (130) can be implemented on the substrate (110) with a fine pitch, thereby reducing the overall size of the semiconductor device (100) including the substrate (110). Additionally, many metal pillars (130) can be placed on the substrate (110) of the same small size (and / or various sizes), and more degrees of freedom can be obtained in designing the semiconductor device (100).

[0045] A sealing material (140) may be formed, for example, on a first surface (e.g., top surface) of a substrate (110) to surround the semiconductor die (120) and the metal pillar (130) (e.g., to surround and / or contact the sides thereof). The sealing material (140) may be made of any various material (e.g., a general resin, etc.) and protects the semiconductor die (120) and the metal pillar (130) from external impact while fixing the positions of the semiconductor die (120) and the metal pillar (130).

[0046] A conductive ball (150, or any of various interconnected structures, e.g., conductive bumps, conductive posts, or pillars, etc.) may be formed under the substrate (110) (e.g., on the bottom surface of the substrate (110) of FIG. 1). The conductive ball (150) may be made of solder, e.g., and may be connected to interconnected structures (e.g., pads, traces, balls, bumps, etc.) on the bottom surface of the substrate (110). The conductive ball (150) functions to subsequently be connected to an external circuit to provide a path for inputting and / or outputting electrical signals to and / or from the substrate (110).

[0047] As described above, in an exemplary semiconductor device (100), metal pillars (130) having a fine pitch are disposed (formed) on the upper surface of a substrate (110) and exposed to the outside of a sealant (140), thereby enabling the realization of a fine pitch and reducing the overall size, while simultaneously enabling stacking another semiconductor device (or vice versa) on the semiconductor device (100).

[0048] In an exemplary embodiment, another substrate or interposer may be laminated (or formed) on the surface (top side) of the semiconductor die (120) and / or sealant (140). An example of such an embodiment is shown in FIG. 2 and described below.

[0049] FIG. 2 shows a cross-sectional view of a semiconductor device according to various embodiments of the present invention. In one embodiment, the semiconductor device (200) includes, for example, a substrate (110), a semiconductor die (120), a metal pillar (130), an upper substrate (230), a sealant (140), and a conductive ball (150). Components having the same function as in another semiconductor device (100) in one embodiment of FIG. 1 are indicated by the same reference numerals, and the following description generally focuses on the differences between the semiconductor device (100) according to one embodiment of FIG. 1 and the semiconductor device (200) according to another embodiment of FIG. 2.

[0050] An upper substrate (230) is positioned along the upper surface of the sealing material (140). Additionally, the upper substrate (230) includes a plurality of conductive patterns (231) (or parts thereof) exposed from the lower surface of the upper substrate (230) to the upper surface of the sealing material (140). The upper substrate (230) may be electrically connected to a semiconductor device stacked thereon through the conductive patterns (231) (or parts thereof) exposed from the upper surface of the upper substrate (230) (or parts thereof). Additionally, in one embodiment, the conductive patterns (231) may be electrically connected to a metal pillar (130) located in various areas of the semiconductor device (200), for example, areas other than the area where the semiconductor die (120) is positioned. For example, the upper substrate (230) may be electrically connected to the substrate (110) through the metal pillar (130).

[0051] As described above, a semiconductor device (200) according to one embodiment may be formed to have a fine pitch pattern (e.g., conductors, lands, traces, pads, etc.) by providing a metal pillar (130) on a sealing material (400) without performing a laser drilling process (or removal process). Additionally, a semiconductor device (200) according to one embodiment may be configured to provide another semiconductor device stacked (or vice versa) on the semiconductor device (200) by, for example, providing an upper substrate (230) connected to the metal pillar (130).

[0052] Hereinafter, an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention is described. For example, the manufacturing method according to one embodiment may be used to manufacture some or all of the embodiments of the semiconductor device or a part of the configuration thereof according to the embodiment described herein.

[0053] FIGS. 3a through 3f illustrate exemplary manufacturing methods of different semiconductor devices according to various aspects of the present invention.

[0054] Referring to FIG. 3a, a method for manufacturing a semiconductor device according to one embodiment of various aspects of the present invention may include the step of providing (or forming) a metal pillar (130) and an insulating member (20) covering the metal pillar (130) on a carrier substrate (10). The carrier substrate (10) may include, for example, a metal, a dielectric material, a semiconductor material, etc. The insulating member (20) may be formed, for example, by molding, but the scope of the present invention is not limited thereto. For example, the insulating member (20) may be formed by a method such as spin coating, vapor deposition, or printing. Additionally, the insulating member (20) may be patterned on the carrier substrate (20), and, for example, electroplating or electroless plating may be performed using the carrier substrate (10) as a seed layer, thereby forming the metal pillar (130). The metal pillar (130) can be made of, for example, copper (Cu), aluminum (Al), etc. The metal pillar (130) can be formed by plating the metal pillar (130) on, for example, on a seed layer, on a conductive pattern (e.g., pad, land, trace, etc.) of a carrier substrate (10), on a seed layer, etc.

[0055] Referring to FIG. 3b, a photoresist (30) (or a photoresist layer) is formed (e.g., formed by coating) and patterned on an insulating member (20), and electroplating or electroless plating is performed on an area exposed by the pattern of the photoresist (30) to increase the height of the metal pillar (130). Such plating may be, for example, the same material as the metal pillar (130) and / or a different material. Additionally, a conductive adhesive member (130a) may be additionally formed on the metal pillar (130) (e.g., formed with or without adding metal to the metal pillar (130)). The conductive adhesive member (130a) may be made of, for example, a general soldering material, but the invention is not limited thereto.

[0056] Referring to FIG. 3c, the photoresist (30) (or photoresist layer) and the carrier substrate (10) are removed. The photoresist (30) is removed, for example, by a general ashing process, and the carrier substrate (10) can be removed by grinding (e.g., strip-grinding, etc.), by peeling off the adhesive tape if an interface is formed between the photoresist (30) and the carrier substrate (10), or by a chemical / mechanical planarization process, etc. Accordingly, the conductive adhesive member (130a) formed on the metal pillar (130) and the metal pillar (130) (or part thereof) are exposed.

[0057] Referring to FIG. 3d, the metal pillar (130) is coupled to the substrate (110) while the conductive adhesive member (130a) is inverted so that it faces downward. In one embodiment of the present invention, the substrate (110) may be in a state where the semiconductor die (120) is coupled to the substrate prior to the metal pillar (130), and the conductive adhesive member (130a) is aligned with a pattern (e.g., trace, pad, land, etc.) formed on the substrate (110), so that the metal pillar (130) can be coupled to the substrate (110). Such coupling may be performed, for example, by thermocompressing bonding, mass reflow, direct metal-to-metal (e.g., soldering) bonding, conductive adhesive, etc.

[0058] Referring to FIG. 3e, a sealant (140) (or sealing material) can fill the area between the insulating member (20) and the substrate (110) to seal the semiconductor die (120) and the metal filler (130). The sealant (140) may be formed to seal internal components from at least one side (e.g., from the side). Additionally, although not separately illustrated, an individual underfill may be optionally formed prior to the sealant (140) to surround the conductive pad (121) of the semiconductor die (120).

[0059] Additionally, referring to FIG. 3e, after forming the seal (140), the insulating member (20) can be removed. The insulating member (20) can be removed, for example, by grinding (e.g., strip-grinding), etching, chemical / mechanical planarization, etc. Thus, the top surface of the semiconductor die (120) can be exposed from the top of the seal (140) (e.g., from the top surface). In this case, the metal pillar (130) (e.g., its end) can be exposed from the top of the seal (140) and / or, for example, may protrude upward from the top surface of the seal (140) due to a difference in physical properties when the seal (20) is removed.

[0060] Referring to FIG. 3f, a conductive ball (150) (or other interconnected structures, e.g., pillars, posts, bumps, etc.) is formed on the bottom surface of the substrate (110). The conductive ball (150) is formed along a pattern on the bottom surface of the substrate (110) (e.g., traces, lands, pads, underbump metallization layers, etc.) to provide a connection path to an external circuit.

[0061] Hereinafter, another processing method for a semiconductor device according to one embodiment of the present invention is described. For example, the method according to one embodiment may be used to manufacture some or all of the embodiments of the semiconductor device or a part of the configuration thereof according to the embodiment described herein.

[0062] FIGS. 4a through 4i illustrate a method for manufacturing a semiconductor device according to various aspects of the present invention. The method according to the above embodiments may share some or all features of the exemplary method illustrated in FIGS. 3a through 3f, for example.

[0063] Referring to FIGS. 4a and 4b, an exemplary method for manufacturing a semiconductor device according to various embodiments of the present invention comprises the step of forming a seed layer (11) and a photoresist (12) (or a photoresist layer) on the surface of a carrier substrate (10). The seed layer (11) may be formed of a metal, such as copper (Cu), or a metal sheet, for example, but the scope of the present invention is not limited thereto.

[0064] Referring to FIG. 4c, a pattern is formed with a photoresist (12), for example, through masking. The pattern can be implemented to expose an area corresponding to a metal pillar (130) to be formed later, for example.

[0065] Referring to FIG. 4d, electroplating is performed using a seed layer (11) as a seed to form a plating layer (13). The plating layer (13) may be formed inside and / or near the pattern (12a) of the photoresist (12), for example, on an area of ​​the seed layer (11) exposed by the pattern (12a) of the photoresist (12). Note that the plating layer (13) may be formed in the form of any various conductive pattern (e.g., pads, lands, traces, etc.). The plating layer (13) may also be formed, for example, by being integrated with the conductor on which the plating layer (13) is plated.

[0066] Referring to FIG. 4e, grinding (e.g., strip-grinding, etc.) or general thinning may be performed on the photoresist (12) and the plating layer (13). Additionally, the plating layer (13) resulting from the grinding may form a metal pillar (13). However, this step is performed optionally. If this step is not performed, the plating layer (13) may be identical to a metal pillar (130).

[0067] Referring to FIG. 4f, the photoresist (12) is removed. As described above, the photoresist (12) can be removed, for example, by ashing, thereby exposing the seed layer (11) and the metal pillar (130).

[0068] Referring to FIG. 4g, a conductive adhesive member (130a) is formed below the metal pillar (130), and the metal pillar (130) and the substrate (110) can be joined together through the conductive adhesive member (130a). Note that the conductive adhesive member (130a) can be formed on the metal pillar (130) as described with reference to FIG. 3, such as being formed on the substrate (110) before the metal pillar (130) is attached. Here, the semiconductor die (120) can be joined to the substrate (110) prior to the metal pillar (130). The conductive adhesive member (130a) can be aligned with a pattern (e.g., trace, pad, land, etc.) formed on the substrate (110) to join the metal pillar (130) and the substrate (110) together.

[0069] Referring to FIG. 4h, a sealant (140), e.g., a molding material, a general dielectric material, etc., may be formed to fill the area between the seed layer (11) and the substrate (110) to seal, e.g., the semiconductor die (120) and the metal filler (130) (e.g., the sides thereof). The sealant (140) may be formed to seal internal components, e.g., from at least one side. Additionally, although not individually illustrated, an individual underfill may be optionally formed prior to the sealant (140) to surround the conductive pad (121) of the semiconductor die (1200).

[0070] Also, referring to FIG. 4h, after forming the seal (140), the carrier substrate (10) and the seed layer (11) can be removed. The insulating member (20) can be removed, for example, by grinding (e.g., strip-grinding), etching, chemical / mechanical planarization process, general planarization process, etc. Thus, the top surface (122) of the semiconductor die (120) can be exposed from the top of the seal (140) (e.g., from the top surface). In this case, the metal pillar (130) (e.g. its top surface) can also be exposed from the top of the seal (140) and / or, for example, may be formed protruding upward from the surface of the seal due to a difference in physical properties when the insulating member (20) is removed.

[0071] Referring to FIG. 4i, a conductive ball (150) (or other interconnected structures, e.g., pillars, posts, bumps, etc.) may be formed on the bottom surface of the substrate (110). The conductive ball (150) may be formed to correspond to a pattern formed on the bottom surface of the substrate (110) (e.g., traces, lands, pads, underbump metallization layers, etc.) to provide a connection path to an external circuit.

[0072] Hereinafter, a method for processing a semiconductor device according to another embodiment of the present invention is described. For example, the method according to one embodiment may be used to manufacture a semiconductor device according to the embodiment described herein, or some or all of the embodiments of a part of the device.

[0073] FIGS. 5a through 5f illustrate a method for manufacturing a semiconductor device according to various aspects of the present invention. The method according to the above embodiments may share some or all features of the exemplary method and / or exemplary method illustrated in FIGS. 3a through 3f, for example.

[0074] Referring to FIG. 5a, an exemplary method for manufacturing a semiconductor device according to various embodiments of the present invention may include the steps of providing (or forming) a conductive pattern (231) (e.g., a trace, land, pad, etc.), providing a metal pillar (130) on a carrier substrate (10), and providing an insulating member (20) covering the conductive pattern (231) and the metal pillar (130). The insulating member (20) may be formed, for example, by molding, but the scope of the present invention is not limited thereto. For example, the insulating member (20) may be formed by spin coating, vapor deposition, printing, etc.

[0075] Additionally, in an exemplary embodiment, the insulating member (20) is first patterned on the carrier substrate (10), and, for example, using the carrier substrate (10) as a seed layer, electroplating and electroless plating may be performed to form a conductive pattern (231). Then, after the patterning step of the insulating member (20), a plated metal pillar (130) is formed, for example, using the conductive pattern (231) (e.g., pad, land, trace, etc.) and / or the carrier substrate (10) as a seed layer. The conductive layer (13) may be formed, for example, by being integrated with the conductor on which the conductive layer (13) is plated.

[0076] Referring to FIG. 5b, a photoresist (30) (or a photoresist layer) is formed (or coated, etc.) on an insulating member (20), and electroplating or electroless plating is performed on an area exposed by a pattern of the photoresist (30) to increase the height of the metal pillar (130). Such plating may be, for example, a material such as the metal pillar (130) and / or another material. Additionally, a conductive adhesive member (130a) may be additionally formed on the metal pillar (130) (for example, with and / or without adding metal to the metal pillar (130)). The conductive adhesive member (130a) may be made of, for example, a general soldering material, but the scope of the invention is not limited thereto.

[0077] Referring to FIG. 5c, the photoresist (30) (or photoresist layer) and the carrier substrate (10) are removed. The photoresist (30) can be removed, for example, by a general ashing process, and the carrier substrate (10) can be removed by grinding (e.g., strip-grinding, etc.), or by peeling off the adhesive tape if an adhesive tape is formed as an interface between the photoresist (30) and the carrier substrate (10), or by a chemical / mechanical planarization process, etc. Accordingly, the conductive adhesive member (130a) formed on the metal pillar (130) and the metal pillar (130) (or part thereof) are exposed. In this way, an upper substrate (230) having a conductive pattern (231) and a metal pillar (130) according to one embodiment can be formed. At this stage, a portion of the insulating member (20) may be removed to further expose the metal pillar (130). In an embodiment according to one embodiment, if the thickness of the insulating member (20) is reduced and the thickness of the photoresist (30) is increased, a significant portion of the metal pillar (130) may be exposed by removing the photoresist (30).

[0078] Referring to FIG. 5d, the metal pillar (130) is bonded to the substrate (110) while the conductive adhesive member (130a) is inverted so that it faces downward. In one embodiment of the present invention, the substrate (110) may be in a state where the semiconductor die (120) is bonded to the substrate prior to the metal pillar (130), and the conductive adhesive member (130a) is aligned with a pattern (e.g., trace, pad, land, etc.) formed on the substrate (110), so that the metal pillar (130) and the substrate (110) can be bonded to each other. This bonding may be performed, for example, by thermocompressing bonding, mass reflow, direct metal-to-metal (e.g., soldering) bonding, conductive adhesive, etc.

[0079] Referring to FIG. 5d, the conductive pattern (231) of the upper substrate (230) is exposed in the upper direction. Thus, a semiconductor device stacked in a subsequent step can be easily electrically connected to the conductive pattern (231).

[0080] Referring to FIG. 5e, a sealant (140) (or sealing material) can fill the area between the upper substrate (230) and the substrate (11) to seal the semiconductor die (120) and the metal filler (130). The sealant (140) can be formed to seal internal components from at least one side (e.g., from the side). Additionally, although not separately illustrated, an individual underfill may be optionally formed prior to the sealant (140) to surround the conductive pad (121) of the semiconductor die 91200.

[0081] Referring to FIG. 5f, a conductive ball (150) (or other interconnected structures, e.g., pillars, posts, bumps, etc.) is formed on the bottom surface of the substrate (110). The conductive ball (150) is formed along a pattern on the bottom surface of the substrate (110) (e.g., traces, lands, pads, underbump metallization layers, etc.) to provide a connection path to an external circuit.

[0082] Although semiconductor devices and manufacturing methods according to various aspects of the present invention have been described by reference to specific supporting examples and / or embodiments, it will be readily understood by those skilled in the art that such description is not limited to the specific embodiments described above, and that the present invention includes all embodiments, examples, and implementations within the scope of the appended claims.

[0083] The foregoing description includes various aspects of electronic device assemblies and methods of assembling the same, which are illustrated in numerous drawings. For clarity regarding the drawings, not all features of the assemblies according to each embodiment are shown. An assembly and / or method according to any of the embodiments provided herein may share all or some of its features with all other assemblies and / or methods provided herein.

[0084] In summary, various embodiments according to the present invention provide a semiconductor device and a method for manufacturing a semiconductor device. As a non-limiting example, various embodiments of the present invention provide a stackable semiconductor device having a small size and fine pitch and a method for manufacturing the same. Although the foregoing description has been described with reference to specific embodiments and examples, it will be understood by those skilled in the art that various modifications may be made and replaced with equivalents without departing from the scope of the invention. Furthermore, many modifications may be made to adapt to specific situations or materials to the teachings of the present invention without departing from the scope of the invention. Accordingly, the present invention is not limited to the specific example(s) disclosed, but is intended to include all examples that fall within the scope of the appended claims.

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: a step of coupling the bottom side of a semiconductor die to the upper side of a substrate; a step of providing an assembly comprising a metal and a plurality of metal pillars extending from the metal; a step of coupling the assembly to the substrate, wherein a first pillar end of each of the plurality of metal pillars is attached to the upper side of the substrate at a lateral outer position of the upper region of the substrate covered by the semiconductor die; a step of forming a seal between the metal and the upper side of the substrate, wherein the seal surrounds the semiconductor die and the lateral pillar side of each of the plurality of metal pillars; and a step of removing the metal of the assembly to expose a second pillar end for each of the plurality of metal pillars from the seal. Claim 2 A method according to claim 1, wherein the step of joining the assembly to a substrate comprises joining the first pillar end of each of the plurality of metal pillars to the upper side of the substrate with an adhesive member. Claim 3 In paragraph 2, the method wherein the adhesive member comprises solder. Claim 4 A method according to claim 1, wherein the assembly comprises a carrier, and the method comprises the step of removing the carrier of the assembly together with the metal. Claim 5 In claim 1, the method wherein the metal comprises copper. Claim 6 A method according to claim 1, wherein the assembly comprises an insulating member, and the method comprises the step of removing the insulating member of the assembly together with the metal. Claim 7 In claim 6, a method in which, before removing the insulating member, the insulating member contacts the upper side of the sealing material and the upper side of the semiconductor die. Claim 8 A method according to claim 1, wherein the sealant comprises a mold material. Claim 9 A method according to claim 1, wherein the removal of the metal of the assembly comprises the step of grinding the metal of the assembly. Claim 10 A method according to claim 1, further comprising the step of forming an interconnected structure on the bottom side of the substrate. Claim 11 A method for manufacturing a semiconductor device, comprising the steps of: joining the bottom side of a semiconductor die to the upper side of a substrate; providing an assembly comprising a metal and a plurality of metal pillars extending from the metal; joining the assembly to the substrate, wherein the first pillar end of each of the plurality of metal pillars is attached to the upper side of the substrate using an adhesive member; forming a seal between the metal and the upper side of the substrate, wherein the seal surrounds the semiconductor die and the side pillar side of each of the plurality of metal pillars laterally; and removing the metal of the assembly to expose the second pillar end for each of the plurality of metal pillars from the seal. Claim 12 In claim 11, the method wherein the adhesive member comprises solder. Claim 13 In paragraph 11, the method wherein the metal comprises copper. Claim 14 In claim 11, the method wherein the sealant comprises a mold material. Claim 15 In claim 11, the step of removing the metal of the assembly is the metal of the assembly second A method including a grinding step. Claim 16 A method according to claim 11, further comprising the step of forming an interconnected structure on the bottom side of the substrate. Claim 17 A substrate having an upper substrate side, a lower substrate side, and a side substrate side extending between the upper and lower substrate sides; a semiconductor die having an upper die side, a lower die side, and a side die side extending between the upper and lower die sides - the lower die side is coupled to the upper substrate side -; a plurality of metal pillars each comprising a first pillar end, a second pillar end opposite to the first pillar end, and a side pillar side extending between the first pillar end and the second pillar end - the first pillar end is coupled to the upper substrate side by an adhesive member, and each of the plurality of metal pillars is laterally disposed outside the area of ​​the upper substrate side covered by the semiconductor die -; at least a portion of the upper substrate side, at least a portion of the side die side, at least a portion of the side pillar side of each of the plurality of metal pillars, and a mold material in direct contact with the adhesive member - the second pillar end of each of the plurality of metal pillars is exposed from the mold material -; A semiconductor device comprising: an interconnected structure coupled to the lower substrate side. Claim 18 In claim 17, the above adhesive member comprises solder, a semiconductor device. Claim 19 A semiconductor device according to claim 17, wherein each of the plurality of metal pillars comprises a copper pillar no wider than 15 μm. Claim 20 A semiconductor device according to claim 17, wherein the upper die side is exposed from the mold material.

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