Semiconductor device and semiconductor package

Abstract

One embodiment of the present invention comprises a first semiconductor chip having a flat upper surface provided by the first bonding layer, and a first substrate and a first bonding layer disposed on the first substrate; A semiconductor package is provided that includes a second semiconductor chip having a flat lower surface provided by the second bonding layer and contacting the upper surface of the first semiconductor chip, wherein the first bonding layer comprises a first outermost insulating layer providing the upper surface, a first inner insulating layer stacked below the first outermost insulating layer, first outer marks spaced apart from each other and disposed within the first outermost insulating layer, and first inner marks spaced apart from the first outer marks within the first inner insulating layer, wherein the second bonding layer comprises a second outermost insulating layer providing the lower surface, a second inner insulating layer stacked on the second outermost insulating layer, second outer marks spaced apart from each other and disposed within the second outermost insulating layer, and second inner marks spaced apart from the second outer marks within the second inner insulating layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor chip and a semiconductor package. Background Technology

[0003] As the demand for high capacity, thinness, and miniaturization of electronic products increases, various types of semiconductor packages are being developed. Recently, direct bonding technology, which joins semiconductor chips without adhesive films (e.g., NCF) or connection bumps (e.g., solder balls), is being developed as a method to integrate more components (e.g., semiconductor chips) into the package structure. The problem to be solved

[0005] One of the problems that the present invention aims to solve is to provide a semiconductor chip in which the dishing of the alignment structure is controlled during the planarization process.

[0006] One of the problems that the present invention aims to solve is to provide a semiconductor package in which void generation is minimized and yield is improved during direct bonding. means of solving the problem

[0008] As a means of solving the above-mentioned problem, one embodiment of the present invention comprises a first semiconductor chip having a flat upper surface provided by the first bonding layer, comprising a first substrate and a first bonding layer disposed on the first substrate; A semiconductor package is provided that includes a second semiconductor chip having a flat lower surface provided by the second bonding layer and contacting the upper surface of the first semiconductor chip, wherein the first bonding layer comprises a first outermost insulating layer providing the upper surface, a first inner insulating layer stacked below the first outermost insulating layer, first outer marks spaced apart from each other and disposed within the first outermost insulating layer, and first inner marks spaced apart from the first outer marks within the first inner insulating layer, wherein the second bonding layer comprises a second outermost insulating layer providing the lower surface, a second inner insulating layer stacked on the second outermost insulating layer, second outer marks spaced apart from each other and disposed within the second outermost insulating layer, and second inner marks spaced apart from the second outer marks within the second inner insulating layer.

[0010] Additionally, the semiconductor package comprises: a first semiconductor chip having an upper surface provided by the first bonding layer, comprising a first substrate and a first bonding layer disposed on the first substrate; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip, comprising a second substrate and a second bonding layer disposed below the second substrate, and having a lower surface provided by the second bonding layer and in contact with the upper surface of the first semiconductor chip, wherein the first bonding layer provides the upper surface and includes first external marks and a first external pad electrically insulated from each other, and the second bonding layer provides the lower surface and includes second external marks and a second external pad electrically insulated from each other, and the difference between the width of the first external marks and the width of the first external pad and the difference between the width of the second external marks and the width of the second external pad are each about 20% or less.

[0012] Additionally, the semiconductor package comprises: a first semiconductor chip having an upper surface provided by the first bonding layer, comprising a first substrate and a first bonding layer disposed on the first substrate; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip, comprising a second substrate and a second bonding layer disposed below the second substrate, and having a lower surface provided by the second bonding layer and in contact with the upper surface of the first semiconductor chip, wherein the first bonding layer comprises a first alignment structure having first external marks providing the upper surface and first internal marks disposed staggered with respect to the first external marks below the first external marks, and a first pad structure having a first external pad electrically insulated from the first external marks, wherein the first alignment structure has a planar area larger than the planar area of ​​the first external pad projected onto a plane parallel to the upper surface of the first semiconductor chip.

[0014] Additionally, the semiconductor chip comprises: a substrate; a circuit layer disposed on the substrate and including a wiring structure and an interlayer insulating layer surrounding the wiring structure; and a bonding layer disposed on the circuit layer and including a pad structure electrically connected to the wiring structure, an alignment structure spaced apart from the pad structure, and an insulating material layer surrounding the pad structure and the alignment structure, wherein the bonding layer has a front surface provided by the pad structure, the alignment structure, and the insulating material layer, and a rear surface located opposite to the front surface, wherein the insulating material layer includes an outermost insulating layer providing the front surface and one or more inner insulating layers stacked between the outermost insulating layer and the circuit layer, and wherein the alignment structure includes external marks disposed within the outermost insulating layer and spaced apart from each other in a first direction parallel to the front surface, and one or more inner marks disposed in the one or more inner insulating layers in a second direction perpendicular to the front surface and staggered with the external marks. Effects of the invention

[0016] According to embodiments of the present invention, by introducing a plurality of staggered alignment marks, a semiconductor chip in which dishing of the alignment structure is controlled during a planarization process can be provided.

[0017] According to embodiments of the present invention, a semiconductor package can be provided in which void generation is minimized and yield is improved during direct bonding by using a semiconductor chip in which dishing of the alignment structure is controlled. Brief explanation of the drawing

[0019] FIG. 1a is a cross-sectional view illustrating a semiconductor chip according to one embodiment of the present invention, and FIG. 1b is a plan view illustrating the front surface of the semiconductor chip of FIG. 1a. Figure 2 is a partial enlarged view illustrating area 'A' of Figure 1a. FIG. 3 is a plan view illustrating various planar shapes of alignment structures according to exemplary variations. FIG. 4 is a partial enlarged view illustrating a modified example of a semiconductor chip according to one embodiment of the present invention. FIG. 5 is a partial enlarged view illustrating a modified example of a semiconductor chip according to one embodiment of the present invention. FIG. 6 is a partial enlarged view illustrating a modified example of a semiconductor chip according to one embodiment of the present invention. FIG. 7 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIGS. 8a and 8b are partial enlarged views illustrating variations of the semiconductor package of FIG. 7, respectively. FIG. 9 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. Figure 10 is a partial enlarged view illustrating area 'C' of Figure 9. FIG. 11 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the present invention. FIGS. 12a to 12c are partial enlarged views illustrating a part of the manufacturing process of a semiconductor chip according to one embodiment of the present invention in the order of process, and FIG. 12d is a partial enlarged view illustrating dishing that occurred on an alignment structure of a comparative example by a planarization process. FIG. 13 is a cross-sectional view illustrating a part of the manufacturing process of a semiconductor package according to one embodiment of the present invention. FIG. 14a is a partial enlarged view illustrating region 'D' of FIG. 13, and FIG. 14b is a partial enlarged view illustrating a void that occurred between alignment structures of a comparative example during the bonding process of a semiconductor chip. Specific details for implementing the invention

[0020] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0022] FIG. 1a is a cross-sectional view illustrating a semiconductor chip (100) according to one embodiment of the present invention, FIG. 1b is a plan view illustrating the front surface (FS) of the semiconductor chip (100) of FIG. 1a, FIG. 2 is a partial enlarged view illustrating region 'A' of FIG. 1a, and FIG. 3 is a plan view illustrating various planar shapes of an alignment structure (AS) according to exemplary variations. FIG. 1a illustrates a cross-sectional view along line II' of FIG. 1b. FIG. 1b illustrates the planar shape of the alignment structure (AS) and the pad structure (PS) viewed through an insulating material layer ('IL' of FIG. 1a) (not shown).

[0024] Referring to FIGS. 1a and 1b, a semiconductor chip (100) of one embodiment may include a substrate (110), a circuit layer (120), and a bonding layer (BL). The bonding layer (BL) may provide a flat surface for bonding and joining (e.g., hybrid bonding, direct bonding, etc.) with an external device (e.g., semiconductor chip, semiconductor substrate, etc.). For example, the bonding layer (BL) is shown as providing a front surface (FS) of the semiconductor chip (100), but is not limited thereto. According to an embodiment, the bonding layer (BL) may be disposed on a second surface (S2) of a substrate (110) to provide a rear surface (BS) of a semiconductor chip (100), or may be disposed on a first surface (S1) and a second surface (S2) of a substrate (110) respectively to provide both a front surface (FS) and a rear surface (BS) of a semiconductor chip (100) (e.g., the embodiment of FIG. 7 and 9).

[0025] The present invention forms a plurality of layers of an alignment structure (AS) used as an alignment key or alignment mark between semiconductor chips (100) stacked in a vertical direction (Z-axis direction) during a direct bonding process of a semiconductor chip (100), and configures the marks (hereinafter "external marks") (AMa) that provide a direct bonding surface (hereinafter "external marks") to have a size similar to that of a pad (hereinafter "external pad") of a signal or power pad structure (PS), thereby controlling dishing and erosion occurring on the external marks (AMa) during the flattening process of the bonding layer (BL). As a result, the flatness of the bonding surface provided by the bonding layer (BL), for example, the front surface (FS) of FIG. 1a, is improved, and the reliability of the bonding surface during direct bonding can be ensured. In addition, marks that do not provide a direct bonding surface (hereinafter, "internal marks") (AMb) are arranged to overlap with the spacing between external marks (AMa) in the vertical direction (Z-axis direction), thereby providing a planar surface that can be combined with external marks (AMa) to ensure visibility of the alignment structure (AS).

[0026] For example, as illustrated in FIG. 1a, the alignment structure (AS) is electrically insulated from the pad structure (PS) and may include external marks (AMa) providing a front surface (FS) and internal marks (AMb) positioned staggered with respect to the external marks (AMa) on the external marks (AMa). The internal marks (AMb) may be positioned with a central axis staggered with respect to the external marks (AMa) and may be located between the external marks (AMa) that are spaced apart from each other. The external marks (AMa) may have a width similar to that of the external pads (Pa) providing the front surface (FS). Thus, the dishing and erosion of the external marks (AMa) after the flattening process of the front surface (FS) can be controlled to a level similar to that of the external pads (Pa). Additionally, the staggered external marks (AMa) and internal marks (AMb) may be utilized as overlay measurement marks.

[0027] For example, as illustrated in FIG. 1b, the external marks (AMa) and internal marks (AMb) form a group and may have a predetermined shape on a plane parallel to the front surface (FS) of the semiconductor chip (100). That is, since the alignment structure (AS) introduced in the present invention has a planar shape in which the external marks (AMa) and internal marks (AMb) are projected onto a plane parallel to the front surface (FS), it may have a planar area larger than the planar area of ​​the pad structure (PS) or the external pad (Pa) on the same plane. Accordingly, the alignment structure (AS) may have a planar area capable of ensuring sufficient visibility during the detection process of reflected light, diffracted light, etc., by the external marks (AMa) and internal marks (AMb). For example, the planar shape of the alignment structure (AS) projected onto the XY plane may have a maximum diameter of about 10 μm or more. Meanwhile, in FIG. 1b, the alignment structure (AS) is shown as being placed on the outer edge of the semiconductor chip (110), for example, within the scribe area, but is not limited thereto.

[0029] Hereinafter, with reference to FIG. 2, each component constituting a semiconductor chip (100) of one embodiment will be described in detail.

[0031] The substrate (110) has a first surface (S1) and a second surface (S2) facing each other and may be a semiconductor wafer comprising a semiconductor element such as silicon or germanium, or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The substrate (110) may have an active surface (e.g., the first surface (S1)) having an impurity-doped active region and an inactive surface opposite thereto (e.g., the second surface (S2)). In FIG. 1a, the second surface (S2) of the substrate (110) is shown as providing a back surface (BS) of the semiconductor chip (100), but a protective layer (not shown) providing a back surface (BS) of the semiconductor chip (100) may be formed on the second surface (S2) of the substrate (110). The above protective layer (not shown) may be made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, but depending on the embodiment, it may be made of an insulating polymer.

[0033] A circuit layer (120) is disposed on a first surface (S1) of a substrate (110) and may include an interlayer insulating layer (121) and a wiring structure (125). The interlayer insulating layer (121) may include FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma) oxide, PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD) oxide, or a combination thereof. At least a portion of the interlayer insulating layer (121) surrounding the wiring structure (125) may be composed of a low dielectric layer. The interlayer insulating layer (121) can be formed using a chemical vapor deposition (CVD), a flowable-CVD process, or a spin coating process. The wiring structure (125) can be formed as a multilayer structure including wiring patterns and vias made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof. A barrier film (not shown) comprising titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) may be disposed between the wiring pattern or / and vias and the interlayer insulating layer (121). Individual components (115) constituting an integrated circuit may be disposed on a first surface (S1) of the substrate (110). In this case, the wiring structure (125) can be electrically connected to individual elements (115) by an interconnection part (113) (e.g., a contact plug).Individual devices (115) may include various active and / or passive devices such as FETs like planar FET or FinFET, memory devices such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, RRAM, logic devices such as AND, OR, NOT, system LSI, CIS, MEMS.

[0035] A bonding layer (BL) is disposed on a substrate (110) and may include a pad structure (PS), an alignment structure (AS), and an insulating material layer (IL) surrounding them. For example, the bonding layer (BL) may be a front bonding layer (130) disposed on a first surface (S1) (or active surface) or a circuit layer (120) of the substrate (110). The front bonding layer (130) may include a front pad structure (133) electrically connected to a wiring structure (125), a front alignment structure (135) electrically insulated from the front pad structure (133), and a front insulating material layer (131) surrounding them. The front insulating material layer (131), the front pad structure (133), and the front alignment structure (135) may provide a flat front surface (FS) or bottom surface of the semiconductor chip (100).

[0036] Hereinafter, for convenience of explanation, the "front bonding layer (130)", "front pad structure (133)", "front alignment structure (135)", and "front insulating material layer (131)" may be referred to as the "bonding layer (BL)", "pad structure (PS)", "alignment structure (AS)", and "insulating material layer (IL)", respectively, so as not to be confused with the bonding layer ('BL1' or '150') (see FIG. 7 and 9) placed on the back surface (BS) of the semiconductor chip (100). Additionally, each component of the front pad structure (133), front alignment structure (135), and front insulating material layer (131) may also be understood as identical to the corresponding components of the pad structure (PS), alignment structure (AS), and insulating material layer (IL).

[0037] The insulating material layer (IL) may include an outermost insulating layer (ILa) providing a front surface (FS), and one or more inner insulating layers (ILb) laminated between the outermost insulating layer (ILa) and the circuit layer (120). For example, the front insulating material layer (131) may include a front outermost insulating layer (131a) and a front inner insulating layer (131b). The insulating material layer (IL) may include, for example, silicon oxide (SiO) or silicon carbonitride (SiCN). Depending on the embodiment, the outermost insulating layer (ILa) and the inner insulating layer (ILb) may include different types of materials. For example, the outermost insulating layer (ILa) may include silicon carbonitride (SiCN), and the inner insulating layer (ILb) may include silicon oxide (SiO). The outermost insulating layer (ILa) may provide a bonding surface for bonding and joining with an external device (e.g., a semiconductor chip, a semiconductor substrate, etc.).

[0038] The pad structure (PS) may include an outer pad (Pa) disposed within the outermost insulating layer (ILa) and one or more inner pads (Pb) disposed within one or more inner insulating layers (ILb). For example, the front pad structure (133) may include a front outer pad (133a) and a front inner pad (133b). The pad structure (PS) is electrically connected to the wiring structure (125) of the circuit layer (120) to receive power or signals from an external device or to transmit signals from the circuit layer (120) to the outside. The flattening process of the front (FS) may be performed by taking into account the width (d3) of the outer pad (Pa) to control the dishing of the outer pad (Pa). The pad structure (PS) may include, for example, any one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), or an alloy thereof.

[0039] The alignment structure (AS) may include external marks (AMa) spaced apart from each other in a first direction (X-axis direction) parallel to the front (FS) and arranged within an outermost insulating layer (ILa), and one or more internal marks (AMb) arranged alternately with the external marks (AMa) in a second direction (Z-axis direction) perpendicular to the front (FS) within one or more internal insulating layers (ILb). For example, the front alignment structure (135) may include front external marks (135a) and front internal marks (135b). The alignment structure (AS) may include, for example, any one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), or an alloy thereof.

[0040] The outer marks (AMa) may have a width (d1) that is substantially the same as the width (d3) of the outer pad (Pa) of the pad structure (PS) in the first direction (X-axis direction). For example, the difference between the width (d1) of the outer marks (AMa) and the width (d3) of the outer pad (Pa) may be about 20% or less, or about 10% or less. If the width (d3) of the outer pad (Pa) is about 2 µm, the width (d1) of the outer marks (AMa) may be in the range of about 1.6 µm to about 2.4 µm or in the range of about 1.8 µm to about 2.2 µm. Thus, after the flattening process of the front surface (FS), dishing similar to that of the outer pad (Pa) may be formed on the outer marks (AMa).

[0041] The outer marks (AMa) are spaced apart from each other, for example, in a first direction (X-axis direction), and the spaced-out area between the outer marks (AMa) can be filled by the outermost insulating layer (ILa). The width (sd) of the spaced-out area between the outer marks (AMa) can be formed to a level similar to the width (d1) of the outer marks (AMa), for example. However, embodiments of the present invention are not limited thereto, and the width (sd) between the outer marks (AMa) can be formed at a spacing distance that minimizes erosion in the densely packed area of ​​the outer marks (AMa) during the flattening process of the front surface (FS).

[0042] The internal marks (AMb) may be arranged to overlap the spacing between the external marks (AMa) in the vertical direction (Z-axis direction). For example, the internal marks (AMb) may have a width (d2) equal to or greater than the width (sd) (or spacing distance) between the external marks (AMa) so that the internal insulation layer (ILb) is not located within the spacing between the external marks (AMa). Thus, the external marks (AMa) and the internal marks (AMb) may form a group to form the planar shape of the alignment structure (AS), and may have a planar area larger than the planar area of ​​the pad structure (PS) or the external pad (Pa).

[0044] Hereinafter, with reference to FIG. 3, the alignment structure (AS) is described in terms of its planar shape. FIG. 3 illustrates the planar shape of the alignment structure (AS) projected onto a plane (e.g., XY plane) parallel to the front surface (FS) of FIG. 1a.

[0045] As illustrated in FIG. 3, the alignment structure (AS) may have various planar shapes. For example, on the XY plane, the outer marks (AMa) may form a first pattern (PT1) and a second pattern (PT2) that is spaced apart from the first pattern (PT1) and continuously surrounds the perimeter of the first pattern (PT1), and the inner marks (AMb) may form a third pattern (PT3) that is continuously extended between the first pattern (PT1) and the second pattern (PT2). In this case, the line width of each of the first pattern (PT1) and the second pattern (PT2) may be substantially the same as the width (d1) of the outer marks (AMa), and the line width of the third pattern (PT3) may be substantially the same as the width (d2) of the inner marks (AMb). The planar shape formed by the first pattern (PT1), the second pattern (PT2), and the third pattern (PT3) may have a planar area that can ensure sufficient visibility during the detection process of the alignment structure (AS). For example, on the XY plane, the maximum diameter (D) of the alignment structure (AS) composed of the first pattern (PT1), the second pattern (PT2), and the third pattern (PT3) may be about 10 μm or more.

[0047] FIG. 4 is a partial enlarged view illustrating a modified example of a semiconductor chip according to one embodiment of the present invention. FIG. 4 illustrates a region ('Aa') corresponding to 'A' in FIG. 2 in the semiconductor chip (100a) of the modified example.

[0049] Referring to FIG. 4, a semiconductor chip (100a) according to a modified example may have the same or similar features as described with reference to FIG. 1a through 3, except that the planar area of ​​the external marks (AMa) exposed on the front surface (FS) is smaller than the planar area of ​​the internal marks (AMb) embedded in the internal insulating layer (ILb). While the alignment structure (AS) shown in FIG. 2 and 3 is configured such that the planar area of ​​the surface (e.g., bottom) of the external marks (AMa) facing the front surface (FS) is larger than the planar area of ​​the surface (e.g., bottom) of the internal marks (AMb) facing the same direction, the alignment structure (AS) of the present modified example may be configured such that the planar area of ​​the surface (e.g., bottom) of the external marks (AMa) facing the front surface (FS) is smaller than the planar area of ​​the surface (e.g., bottom) of the internal marks (AMb). For example, the front alignment structure (135) may be configured such that the planar area of ​​the surface (e.g., bottom) of the front outer marks (135a) facing the front (FS) is smaller than the planar area of ​​the surface (e.g., bottom) of the front inner marks (135b). In this case, the area of ​​the outer marks (AMa) affected by the flattening process of the front (FS) can be minimized, and the width (sd) between the outer marks (AMa) within the area of ​​the alignment structure (AD) can be made wider to minimize erosion caused by the flattening process.

[0051] FIG. 5 is a partial enlarged view illustrating a modified example of a semiconductor chip according to one embodiment of the present invention. FIG. 5 illustrates a region ('Ab') corresponding to 'A' in FIG. 2 in the semiconductor chip (100b) of the modified example.

[0053] Referring to FIG. 5, a semiconductor chip (100b) according to a modified example may have the same or similar features as described with reference to FIG. 1a through 4, except that the width (d2) of the internal marks (AMb) is greater than the width (sd) between the external marks (AMa). The internal marks (AMb) of this modified example may be formed to have a width (d2) greater than the width (sd) between the external marks (AMa), taking into account the alignment error with the external marks (AMa). For example, the front internal marks (135b) may be formed to have a width (d2) greater than the width (sd) between the front external marks (135a). In this case, the process margin of the alignment structure (AS) is increased, and a planar area capable of ensuring visibility of the alignment structure (AS) can be more easily secured.

[0055] FIG. 6 is a partial enlarged view illustrating a modified example of a semiconductor chip according to one embodiment of the present invention. FIG. 6 illustrates a region ('Ac') corresponding to 'A' in FIG. 2 in the semiconductor chip (100c) of the modified example.

[0057] Referring to FIG. 6, a semiconductor chip (100c) according to a modified example may have the same or similar features as described with reference to FIG. 1a through 4, except that the internal mark (AMb) is formed in a shape that covers the space between the external marks (AMa) and at least some of the external marks (AMa). The internal mark (AMb) of the modified example may have a planar area or width (d2) capable of covering both the space between the external marks (AMa) and the external mark (AMa) located in the center. For example, the front internal mark (135b) may have a width (d2) capable of covering the space between the front external marks (AMa) and the front external mark (AMa) located in the center. In this case, the process margin of the alignment structure (AS) is increased, and a planar area capable of ensuring the visibility of the alignment structure (AS) can be more easily secured.

[0059] FIG. 7 is a cross-sectional view illustrating a semiconductor package (1000A) according to an embodiment of the present invention, and FIG. 8a and 8b are partial enlarged views illustrating modified examples of the semiconductor package of FIG. 7, respectively. FIG. 8a and 8b each illustrate a region corresponding to 'B' in FIG. 7 in the semiconductor packages (1000Aa, 1000Ab) of the modified examples.

[0061] Referring to FIG. 7, a semiconductor package (1000A) of one embodiment may include a first semiconductor chip (100A) and a second semiconductor chip (100B) stacked in a vertical direction (Z-axis direction). In this embodiment, the first semiconductor chip (100A) and the second semiconductor chip (100B) may form a bonding surface (BS) formed by directly bonding and joining a first bonding layer (BL1) providing a flat upper surface (USa) of the first semiconductor chip (100) and a second bonding layer (BL2) providing a flat lower surface (LSb) of the second semiconductor chip (100B) without a separate connecting member (e.g., metal pillar, solder bump, adhesive film, etc.).

[0062] Here, the first bonding layer (BL1) may include a first insulating material layer (IL1), a first pad structure (PS1), and a first alignment structure (AS1), and the second bonding layer (BL2) may include a second insulating material layer (IL2), a second pad structure (PS2), and a second alignment structure (AS2). The first bonding layer (BL1) and the second bonding layer (BL2) have the same or similar features as the bonding layer (BL) described with reference to FIGS. 1a through 6, and are designated with reference numbers similar to each component of the bonding layer (BL).

[0063] The first semiconductor chip (100A) and the second semiconductor chip (100B) include components identical or similar to the semiconductor chip (100) described with reference to FIGS. 1a to 2, so redundant descriptions and reference numbers are omitted thereafter. A connection pad (CP) and a bump structure (BP) may be disposed on the lower surface (LSa) of the first semiconductor chip (100A). The connection pad (CP) is electrically connected to an integrated circuit inside the first semiconductor chip (100A), and the bump structure (BP) may electrically connect the connection pad (CP) to an external device. The bump structure (BP) may include, for example, a solder ball, but depending on the embodiment, it may have a structure combining a metal pillar and a solder ball. Depending on the embodiment, a lower bonding layer for direct bonding may be formed on the lower surface (LSa) of the first semiconductor chip (100A), similar to the second bonding layer (BL2).

[0064] The first semiconductor chip (100A) and the second semiconductor chip (100B) may be chiplets that constitute a Multi-Chip Module (MCM). In this case, the number of second semiconductor chips (100B) stacked vertically or horizontally on the first semiconductor chip (100A) may be two or more. For example, the second semiconductor chip (100B) on the first semiconductor chip (100A) may include an I / O, CPU, GPU, FPGA (Field Programmable Gate Array) chip, etc., and the first semiconductor chip (100A) may be an active interposer that performs the function of an I / O chip, and in this case, it may include an I / O element, DC / DC converter, sensor, test circuit, etc. inside. For example, the first semiconductor chip (100A) may be a logic chip including, for example, a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific semiconductor (ASIC), etc., and the second semiconductor chip (100B) may be a memory chip such as a DRAM, SRAM, PRAM, MRAM, FeRAM, or RRAM.

[0066] Referring together with FIG. 8a, an exemplary modified semiconductor package (1000Aa) may include a first semiconductor chip (100A) having a flat upper surface (USa) provided by the back bonding layer (150) disposed on a first substrate ('110' located at the bottom) and a second semiconductor chip (100B) having a flat lower surface (LSb) provided by the front bonding layer (130) disposed on the upper surface (USa) of the first semiconductor chip (100A) and disposed below a second substrate ('110' located at the top) and provided by the front bonding layer (130) and in contact with the upper surface (USa) of the first semiconductor chip (100A). Here, the back bonding layer (150) may be understood to correspond to the first bonding layer (BL1), and the front bonding layer (130) may correspond to the second bonding layer (BL2).

[0067] The rear bonding layer (or first bonding layer) (150) may include a rear insulating material layer (151), a rear pad structure (153), and a rear alignment structure (155).

[0068] The rear insulating material layer (151) may include an outermost rear insulating layer (or a first outermost insulating layer) (151a) that provides an upper surface (USa) of the first semiconductor chip (100A), and one or more rear inner insulating layers (or a first inner insulating layer) (151b) stacked below the outermost rear insulating layer (151a). The rear insulating material layer (151) may include a material that can be bonded to the front insulating material layer (131) of the second semiconductor chip (100B), for example, silicon oxide (SiO) or silicon carbonitride (SiCN). According to an embodiment, the outermost rear insulating layer (151a) and the rear inner insulating layer (151b) may include different types of materials. For example, the outermost rear insulating layer (151a) may include silicon carbonitride (SiCN), and the rear inner insulating layer (151b) may include silicon oxide (SiO). The outermost rear insulating layer (151a) can provide a bonding surface (BS) for bonding and joining with the second semiconductor chip (100B).

[0069] The rear pad structure (153) may include a rear outer pad (or first outer pad) (153a) disposed within the outermost rear insulating layer (151a), and one or more rear inner pads (or first inner pads) (153b) disposed within one or more rear inner insulating layers (151b). The rear outer pad (153a) is exposed on the upper surface (USa) of the first semiconductor chip (100A) and may be bonded and coupled with the front outer pad (or second outer pad) (133a) of the second semiconductor chip (100B). The rear outer pad (153a) may include a material that can be bonded and coupled with the front outer pad (or second outer pad) (133a), for example, any one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), or an alloy thereof. The rear pad structure (153) can be electrically connected to a wiring structure (not shown) of the first semiconductor chip (100A) through a through electrode (140). The through electrode (140) may include a via plug (145) and a side insulating film (141) surrounding the side of the via plug (145). The side insulating film (141) may electrically isolate the via plug (145) from the second substrate (110). The via plug (145) may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu) and may be formed by a plating process, a PVD process, or a CVD process. The side insulating film (141) may include a metal compound such as tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN) and may be formed by a PVD process or a CVD process.

[0070] The rear alignment structure (155) may include rear outer marks (or first outer marks) (155a) spaced apart from each other and rear inner marks (or first inner marks) (155b) spaced apart from the rear outer marks (155a) within the rear inner insulation layer (151b). The rear outer marks (155a) may have a width substantially equal to the width of the rear outer pad (153a) in the first direction (X-axis direction). For example, the difference between the width of the rear outer pad (153a) and the width of the rear outer marks (155a) may be about 20% or less, or about 10% or less. Accordingly, after the flattening process of the upper surface (USa) of the first semiconductor chip (100A), dishing similar to that of the rear outer pad (153a) can be formed on the rear outer marks (155a). Additionally, the rear outer marks (155a) are spaced apart from each other, for example, in a first direction (X-axis direction), and the spaced-out area between the rear outer marks (155a) can be filled by the outermost rear insulating layer (151a). The width of the spaced-out area between the rear outer marks (155a) can be formed as a spacing distance that minimizes erosion in the dense area of ​​the rear outer marks (155a) during the flattening process of the upper surface (USa) of the first semiconductor chip (100A). The rear outer marks (155a) may include a material that can be bonded to the front outer marks (or second outer marks) (135a) of the second semiconductor chip (100B), for example, any one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), or an alloy thereof.

[0071] The rear internal marks (155b) may be arranged to overlap the spacing between the rear external marks (155a) in a direction perpendicular to the upper surface (USa) of the first semiconductor chip (100A) (Z-axis direction). For example, the rear internal marks (155b) may have a width equal to or greater than the width (or spacing distance) between the rear external marks (155a) so that the rear internal insulating layer (151b) is not located within the spacing between the rear external marks (155a). Thus, the rear external marks (155a) and the rear internal marks (155b) may form a group to form the planar shape of the rear alignment structure (155), and may have a planar area larger than the planar area of ​​the rear pad structure (153) or the rear external pad (153a). For example, the upper surface of the rear outer marks (155a) and the upper surface of the rear inner marks (155b) facing the lower surface (LSb) of the second semiconductor chip (100B) can be combined to form a rear alignment structure (155) having a predetermined planar shape. According to an embodiment, the upper surface of the rear outer marks (155a) may have a smaller planar area than the upper surface of the rear inner marks (155b) (see embodiment of FIG. 4).

[0072] The front bonding layer (or second bonding layer) (130) may include a front insulating material layer (131), a front pad structure (133), and a front alignment structure (135).

[0073] The front insulating material layer (131) may include an outermost front insulating layer (or second outermost insulating layer) (131a) that provides a lower surface (LSba) of the second semiconductor chip (100B), and one or more front inner insulating layers (or second inner insulating layers) (131b) laminated on the outermost front insulating layer (131a). The front insulating material layer (131) may include a material that can be bonded and coupled with the rear insulating material layer (151) of the second semiconductor chip (100A), for example, silicon oxide (SiO) or silicon carbonitride (SiCN). The outermost front insulating layer (131a) may provide a bonding surface (BS) for bonding and coupling with the first semiconductor chip (100A).

[0074] The front pad structure (133) may include a front outer pad (or second outer pad) (133a) disposed within the outermost front insulating layer (131a), and one or more front inner pads (or second inner pads) (133b) disposed within one or more front inner insulating layers (131b). The front outer pad (133a) may include a material that can be bonded to the rear outer pad (153a), for example, any one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), or an alloy thereof.

[0075] The front alignment structure (135) may include front outer marks (or second outer marks) (135a) spaced apart from each other and front inner marks (or second inner marks) (135b) arranged in an alternating manner with the front outer marks (135a) within the front inner insulation layer (131b). Since the front outer marks (135a) and front inner marks (135b) have the same or similar characteristics as the rear outer marks (155a) and rear inner marks (155b) of the rear alignment structure (155) described above, redundant descriptions below are omitted.

[0077] Referring to FIG. 8b, an exemplary modified semiconductor package (1000Ab) may have the same or similar features as described with reference to FIG. 7 and 8a, except that the first front bonding layer (130A) of the first semiconductor chip (100A) and the second front bonding layer (130B) of the second semiconductor chip (100B) are bonded to provide a bonding surface (BS). Here, the first front bonding layer (130A) may be understood to correspond to the first bonding layer (BL1), and the second front bonding layer (130B) may correspond to the second bonding layer (BL2). The first front bonding layer (130A) comprises a first front insulating material layer (131A) including a first front outermost insulating layer (131Aa) and a first front inner insulating layer (131Ab), a first front pad structure (133A) including a first front outer pad (131Aa) and a first front inner pad (131Ab), and a first front alignment structure (135A) including first front outer marks (135Aa) and a first front inner marks (135Ab), and the second front bonding layer (130B) comprises a second front insulating material layer (131B) including a second front outermost insulating layer (131Ba) and a second front inner insulating layer (131Bb), a second front pad structure (133B) including a second front outer pad (131Ba) and a second front inner pad (131Bb), and a second front outer It may include a second front alignment structure (135B) including marks (135Ba) and second front internal marks (135Bb). Each component of the first front bonding layer (130A) and the second front bonding layer (130B) has the same or similar features as described with reference to FIGS. 7 and 8a, so redundant descriptions are omitted.

[0079] FIG. 9 is a cross-sectional view illustrating a semiconductor package (1000B) according to one embodiment of the present invention, and FIG. 10 is a partial enlarged view illustrating region 'C' of FIG. 9.

[0081] Referring to FIGS. 9 and 10, a semiconductor package (1000B) of one embodiment has the same or similar features as described with reference to FIGS. 7 to 8b, except that it includes a chip structure (CS) and a molding member (90) disposed on a first semiconductor chip (100A), so redundant description is omitted. The chip structure (CS) may include a plurality of directly bonded semiconductor chips, for example, a second semiconductor chip (100B), a third semiconductor chip (100C), a fourth semiconductor chip (100D), and a fifth semiconductor chip (100E). For example, as shown in FIG. 10, a bonding surface (BS) provided by a rear bonding layer (150) and a front bonding layer (130) may be formed between the third semiconductor chip (100C) and the fourth semiconductor chip (100D), and between the fourth semiconductor chip (100D) and the fifth semiconductor chip (100E), respectively. According to an embodiment, the chip structure (CS) may include more or fewer semiconductor chips than shown in the drawing. For example, the chip structure (CS) may include three or fewer or five or more semiconductor chips.

[0082] For example, the first semiconductor chip (100A) may be a buffer chip or a control chip comprising a plurality of logic elements and / or memory elements. The first semiconductor chip (100A) may transmit signals from the second to fifth semiconductor chips (100B, 100C, 100D, 100E) stacked on top thereof to the outside, and may also transmit signals and power from the outside to the second to fifth semiconductor chips (100B, 100C, 100D, 100E). The second to fifth semiconductor chips (100B, 100C, 100D, 100E) may be memory chips comprising volatile memory elements such as DRAM, SRAM, or non-volatile memory elements such as PRAM, MRAM, FeRAM, or RRAM. In this case, the semiconductor package (1000B) of the present embodiment can be used for HBM (High Bandwidth Memory) products or EDP (Electro Data Processing) products, etc.

[0083] The first to fifth semiconductor chips (100A, 100B, 100C, 100D, 100E) include components identical or similar to the semiconductor chip (100) shown in FIGS. 1a to 2, except that they further include a through electrode (140) for forming an inter-electrical connection path; therefore, reference numerals and repeated descriptions of identical components have been omitted. However, the fifth semiconductor chip (100E) placed at the top does not have a through electrode (140) and may have a relatively large thickness.

[0084] The molding member (90) is disposed on the first semiconductor chip (100A) and can seal at least a portion of each of the second to fifth semiconductor chips (100B, 100C, 100D, 100E). The molding member (90) may be formed to expose the upper surface of the fifth semiconductor chip (100E) disposed at the top. However, according to an embodiment, the molding member (90) may be formed to cover the upper surface of the fifth semiconductor chip (100E). The molding member (90) may include, for example, EMC (Epoxy Mold Compound), but the material of the molding member (90) is not particularly limited.

[0086] FIG. 11 is a cross-sectional view illustrating a semiconductor package (10000) according to one embodiment of the present invention.

[0088] Referring to FIG. 11, a semiconductor package (10000) of one embodiment may include a package substrate (500), an interposer substrate (600), and at least one package structure (1000). Additionally, the semiconductor package (10000) may further include a logic chip or processor chip (700) disposed adjacent to the package structure (1000) on the interposer substrate (600). The package structure (1000) may have the same or similar features as the semiconductor package (1000B) described with reference to FIG. 9 and 10.

[0090] The package substrate (500) is a support substrate on which an interposer substrate (600), a logic chip (700), and a package structure (1000) are mounted, and may be a semiconductor package substrate including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, etc. The body of the package substrate (500) may include different materials depending on the type of substrate. For example, if the package substrate (500) is a printed circuit board, it may be in the form of a body copper foil laminate or a form in which wiring layers are additionally laminated on one or both sides of the copper foil laminate.

[0092] The interposer substrate (600) may include a substrate (610), an interconnect structure (620), and through-vias (640). The package structure (1000) and the processor chip (700) may be stacked on the package substrate (500) via the interposer substrate (600). The interposer substrate (600) may electrically connect the package structure (1000) and the processor chip (700) to each other.

[0093] The substrate (610) may be formed from, for example, any one of silicon, organic, plastic, and glass substrates. If the substrate (610) is a silicon substrate, the interposer substrate (600) may be referred to as a silicon interposer. If the substrate (610) is an organic substrate, the interposer substrate (600) may be referred to as a panel interposer. A lower protective layer (603) and a lower pad (605) may be disposed on the lower surface of the substrate (610). The lower pad (605) may be connected to a through-via (640). A package structure (1000) and a processor chip (700) may be electrically connected to the package substrate (500) through a bump structure (BP) disposed on the lower pad (605).

[0094] An interconnect structure (620) is disposed on the upper surface of a substrate (710) and may include an interlayer insulating layer (621) and a single-layer or multilayer wiring structure (622). If the interconnect structure (620) is composed of a multilayer wiring structure, wiring patterns of different layers may be connected to each other through contact vias. The interposer substrate (600) may be used for the purpose of converting or transmitting input electrical signals between a package substrate (500) and a package structure (1000) or a processor chip (700). Accordingly, the interconnect structure (620) may not include components such as active or passive components. Additionally, according to an embodiment, the interconnect structure (620) may be disposed below a through-via (640). For example, the positional relationship between the interconnect structure (620) and the through-via (640) may be relative.

[0095] The through-via (640) may extend from the upper surface of the substrate (610) to the lower surface and penetrate the substrate (610). Additionally, the through-via (640) may extend into the interior of the interconnect structure (620) and be electrically connected to the wiring structure (622). If the substrate (610) is silicon, the through-via (640) may be referred to as a TSV. According to an embodiment, the interposer substrate (600) may contain only the interconnect structure and may not include the through-via.

[0097] The logic chip or processor chip (700) may include, for example, a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc. Depending on the type of components included inside the Logic chip (800), the semiconductor package (10000) may be referred to as a server-oriented semiconductor package or a mobile-oriented semiconductor package, etc.

[0099] Meanwhile, the semiconductor package (10000) may further include an internal sealing material that covers the side and top surfaces of the package structure (1000) and the processor chip (700) on the interposer substrate (600). Additionally, the semiconductor package (10000) may further include an external sealing material that covers the interposer substrate (600) and the internal sealing material on the package substrate (500). The external sealing material and the internal sealing material may be formed together and may not be distinguishable. According to an embodiment, the semiconductor package (10000) may further include a heat dissipation structure that covers the package structure (1000) and the processor chip (700) on the package substrate (500).

[0101] FIGS. 12a to 12c are partial enlarged views illustrating a part of the manufacturing process of a semiconductor chip according to one embodiment of the present invention in the order of process, and FIG. 12d is a partial enlarged view illustrating dishing that occurred on an alignment structure of a comparative example by a planarization process.

[0103] Referring to FIG. 12a, for example, an internal insulating layer (ILb), an internal pad (Pb), and internal marks (AMb) can be formed on a circuit layer (120). The internal insulating layer (ILb) may include, for example, silicon oxide. The internal insulating layer (ILb) may be formed using a chemical vapor deposition (CVD), a flowable-CVD process, or a spin coating process. The internal pad (Pb) and internal marks (AMb) may be formed by filling the etched area of ​​the internal insulating layer (ILb) with a metal such as copper (Cu). The etched area of ​​the internal insulating layer (ILb) may be formed using a photolithography process. The internal pad (Pb) and internal marks (AMb) may be formed by performing a planarization process, such as a chemical mechanical polishing (CMP) process, after a plating process.

[0105] Referring to FIG. 12b, an outermost insulating layer (ILa) and a plating layer (PL) can be formed on an inner insulating layer (ILb). The outermost insulating layer (ILa) may include, for example, silicon oxide or silicon carbonitride. The outermost insulating layer (ILa) may include a first trench (T1) and a second trench (T2) etched by a photolithography process. The width (Td1) of the first trench (T1) may be formed to be substantially the same as the width (Td2) of the second trench (T2). For example, the difference between the width (Td1) of the first trench (T1) and the width (Td2) of the second trench (T2) may be about 20% or less. The plating layer (PL) may be formed to fill the first trench (T1) and the second trench (T2) by a plating process. A barrier film (not shown) and a seed film (not shown) may be disposed on the lower part of the plating layer (PL). The barrier film (not shown) and the seed film (not shown) may extend along the inner walls of the first trench (T1) and the second trench (T2). The barrier film (not shown) may include, for example, Ti / TiN, and the seed film (not shown) may include, for example, Cu.

[0107] Referring to FIG. 12c, a front surface (FS) can be formed by the outermost insulating layer (ILa), the outer pad (Pa), and the outer marks (AMa). A barrier film (not shown) and a seed film (not shown) may be disposed on the side and bottom surfaces of the outer pad (Pa) and the outer marks (AMa). The front surface (FS) may be formed, for example, by performing a CMP process. Due to dishing that occurs during the CMP process, the outer marks (AMa) may have a first recessed surface (RS1), and the outer pad (Pa) may have a second recessed surface (RS2). The present invention can minimize the difference in dishing that occurs on the outer marks (AMa) and the outer pad (Pa) after the CMP process by forming the width of the outer marks (AMa) to a level substantially equal to the width of the outer pad (Pa). For example, the depth (dp1) from the front surface (FS) to the first recess surface (RS1) may be substantially the same level as the depth (dp2) from the front surface (FS) to the second recess surface (RS2). In this specification, "substantially the same level" or "substantially the same" is a concept that includes process tolerances, etc., and does not mean physically completely identical.

[0109] On the other hand, referring to FIG. 12d, the alignment structure (AS') of the comparative example, which has a width greater than the width of the outer pad (Pa), may have a relatively larger dishing depth after the CMP process. The alignment structure (AS') of the comparative example may be a single layer having a width of, for example, about 10 μm or more, to ensure visibility. In this case, after the CMP process, the depth (dp1') from the front surface (FS) to the recess surface (RS1') of the comparative example may be formed to be greater than the depth (dp2) from the front surface (FS) to the second recess surface (RS2), and this difference may cause voids in the direct bonding process and reduce the process yield.

[0111] FIG. 13 is a cross-sectional view illustrating a part of the manufacturing process of a semiconductor package according to one embodiment of the present invention, FIG. 14a is a partial enlarged view illustrating region 'D' of FIG. 13, and FIG. 14b is a partial enlarged view illustrating a void that occurred between alignment structures (AS1', AS2') of a comparative example during the bonding process of a semiconductor chip.

[0113] Referring to FIG. 13, a semiconductor chip (100) can be placed on a base wafer (100W). The base wafer (100W) may include components for a first semiconductor chip (100A), such as FIG. 7. The semiconductor chip (100) can be placed on the base wafer (100W) using a pick-and-place device (10). The upper surface of the base wafer (100W) provided by the first bonding layer (BL1) and the lower surface of the semiconductor chip (100) provided by the second bonding layer (BL2) can be bonded together. At this time, the first pad structure (PS1) and the second pad structure (PS2) providing the bonding surface, and the first alignment structure (AS1) and the second alignment structure (AS2) can be bonded by applying pressure in a thermal atmosphere higher than room temperature, for example, about 200°C to about 300°C. Here, the temperature of the thermal atmosphere is not limited to about 200°C to about 300°C and can vary.

[0115] Referring to FIG. 14a, the first alignment structure (AS1) and the second alignment structure (AS2) each have first recessed surfaces (RS1) at a level similar to the second recessed surfaces (RS2) of the first pad structure (PS1) and the second pad structure (PS2), so that a bonding surface (BS) can be formed between the first alignment structure (AS1) and the second alignment structure (AS2) without void formation, along with the joining and bonding of the first pad structure (PS1) and the second pad structure (PS2). That is, a bonding surface (BS) between the first alignment structure (AS1) and the second alignment structure (AS2) can be formed without the need to provide an additional thermal atmosphere after the joining and bonding of the first pad structure (PS1) and the second pad structure (PS2).

[0117] On the other hand, referring to FIG. 14b, the first alignment structure (AS1') and the second alignment structure (AS2') of the comparative example may each have first recessed surfaces (RS1') that are recessed more significantly than the second recessed surfaces (RS2) of the first pad structure (PS1) and the second pad structure (PS2). In this case, even after the first pad structure (PS1) and the second pad structure (PS2) are completely joined and bonded, a void (VD) may remain between the first alignment structure (AS1') and the second alignment structure (AS2') of the comparative example, and consequently, the reliability of the bonding surface (BS) may be reduced.

[0119] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

Claims

Claim 1 A first semiconductor chip comprising a first substrate and a first bonding layer disposed on the first substrate, and having a flat upper surface provided by the first bonding layer; and disposed on the upper surface of the first semiconductor chip, comprising a second substrate and a second bonding layer disposed below the second substrate, and comprising a second semiconductor chip having a flat lower surface provided by the second bonding layer and in contact with the upper surface of the first semiconductor chip, wherein the first bonding layer comprises a first outermost insulating layer providing the upper surface, a first inner insulating layer stacked below the first outermost insulating layer, first external marks disposed within the first outermost insulating layer and spaced apart from each other, and first internal marks disposed within the first inner insulating layer and staggered with the first external marks, wherein the second bonding layer comprises a second outermost insulating layer providing the lower surface, a second inner insulating layer stacked on the second outermost insulating layer, second external marks disposed within the second outermost insulating layer and spaced apart from each other, and second internal marks disposed within the second inner insulating layer and staggered with the second external marks, and parallel to the upper surface of the first semiconductor chip A semiconductor package in which the first external marks projected onto a first plane include a first pattern and a second pattern spaced apart from the first pattern and surrounding the perimeter of the first pattern, the first internal marks projected onto the first plane include a third pattern extended between the first pattern and the second pattern, the second external marks projected onto a second plane parallel to the lower surface of the second semiconductor chip include a fourth pattern and a fifth pattern spaced apart from the fourth pattern and surrounding the perimeter of the fourth pattern, and the second internal marks projected onto the second plane include a sixth pattern extended between the fourth pattern and the fifth pattern. Claim 2 In claim 1, the first external marks are each in contact with the second external marks, forming a semiconductor package. Claim 3 A semiconductor package according to claim 1, wherein the first internal marks are arranged to overlap with the first spacing between the first external marks in a direction perpendicular to the upper surface of the first semiconductor chip, and the second internal marks are arranged to overlap with the second spacing between the second external marks in a direction perpendicular to the lower surface of the second semiconductor chip. Claim 4 A semiconductor package according to claim 3, wherein the first internal marks have a width equal to or greater than the width of the first spaced space in a direction parallel to the upper surface of the first semiconductor chip, and the second internal marks have a width equal to or greater than the width of the second spaced space in a direction parallel to the lower surface of the second semiconductor chip. Claim 5 A semiconductor package according to claim 1, wherein the upper surface of the first external marks and the upper surface of the first internal marks facing the lower surface of the second semiconductor chip are combined with each other to form a first alignment structure having a predetermined planar shape. Claim 6 A semiconductor package according to claim 5, wherein the lower surface of the second external marks facing the upper surface of the first semiconductor chip and the lower surface of the second internal marks are combined to form a second alignment structure having a planar shape corresponding to the first alignment structure. Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 A semiconductor package comprising: a first substrate and a first bonding layer disposed on the first substrate, the first semiconductor chip having an upper surface provided by the first bonding layer; and a second semiconductor chip disposed on the upper surface of the first semiconductor chip, comprising a second substrate and a second bonding layer disposed below the second substrate, the second semiconductor chip having a lower surface provided by the second bonding layer and in contact with the upper surface of the first semiconductor chip, wherein the first bonding layer comprises a first alignment structure having first external marks providing the upper surface and first internal marks disposed staggered with respect to the first external marks below the first external marks, and a first pad structure having a first external pad electrically insulated from the first external marks, wherein the first alignment structure has a planar area larger than the planar area of ​​the first external pad projected onto a plane parallel to the upper surface of the first semiconductor chip. Claim 13 In claim 12, on the plane, the first alignment structure is a semiconductor package having a planar shape in which the first external marks and the first internal marks are combined with each other. Claim 14 In claim 13, the planar shape projected onto a plane parallel to the upper surface of the first semiconductor chip is a semiconductor package having a maximum diameter of 10 μm or more. Claim 15 In claim 12, the second bonding layer comprises a second alignment structure having second external marks providing the lower surface and second internal marks arranged alternately with the second external marks on the second external marks, and a second pad structure having a second external pad electrically insulated from the second external marks, wherein the second alignment structure has a planar area larger than the planar area of ​​the second external pad projected on a plane parallel to the lower surface of the second semiconductor chip. Claim 16 In claim 15, the second alignment structure is a semiconductor package having a planar shape corresponding to the first alignment structure. Claim 17 A substrate; a circuit layer disposed on the substrate and comprising a wiring structure and an interlayer insulating layer surrounding the wiring structure; and a bonding layer comprising a pad structure disposed on the circuit layer and electrically connected to the wiring structure, an alignment structure spaced apart from the pad structure, and an insulating material layer surrounding the pad structure and the alignment structure, wherein the bonding layer has a front surface provided by the pad structure, the alignment structure, and the insulating material layer, and a rear surface located opposite to the front surface, wherein the insulating material layer comprises an outermost insulating layer providing the front surface and one or more inner insulating layers laminated between the outermost insulating layer and the circuit layer, wherein the alignment structure comprises external marks disposed within the outermost insulating layer and spaced apart from each other in a first direction parallel to the front surface, and one or more inner marks disposed in the one or more inner insulating layers in a second direction perpendicular to the front surface and staggered with the external marks, wherein the external marks projected onto a plane parallel to the front surface include a first pattern and a second pattern spaced apart from the first pattern and continuously surrounding the perimeter of the first pattern, and the inner marks projected onto the plane between the first pattern and the second pattern A semiconductor chip including a third pattern that is continuously extended. Claim 18 In claim 17, the semiconductor chip having one or more layers of internal marks having a width equal to or greater than the spacing distance of the external marks in the first direction. Claim 19 In claim 17, the pad structure comprises an outer pad disposed within the outermost insulating layer and one or more inner pads disposed within one or more inner insulating layers, and the outer marks have a width equal to the width of the outer pad in the first direction, on a semiconductor chip. Claim 20 delete

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