Semiconductor device, semiconductor package, and memory system
Patent Information
- Authority / Receiving Office
- KR · KR
- Patent Type
- Patents
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2021-11-16
- Publication Date
- 2026-08-03
Smart Images
Figure R1020210157518_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a semiconductor device, a semiconductor package, and a memory system. Background Technology
[0003] A semiconductor device includes pads that are connected to other external semiconductor devices, and the pads may be connected to an input / output circuit included in the semiconductor device that includes at least one of a transmitter and a receiver. The semiconductor device can exchange signals with other semiconductor devices through the pads. Generally, signals are exchanged by physically connecting the pads of different semiconductor devices directly; however, recently, there has been an active trend in research on methods for semiconductor devices to exchange signals with each other by forming coils on the pads and utilizing the electromagnetic induction phenomenon caused by the current flowing through the coils. The problem to be solved
[0005] One of the objectives of the technical concept of the present invention is to provide a semiconductor device, a semiconductor package, and a memory system that can improve integration density and performance by using a via structure that penetrates the center of a coil pattern for transmitting and receiving signals to connect the input / output circuits of different semiconductor devices to each other and by transmitting and receiving signals different from the coil pattern through the via structure. means of solving the problem
[0007] A semiconductor device according to one embodiment of the present invention comprises a semiconductor substrate, a device region having a plurality of elements formed on the semiconductor substrate, and a wiring region disposed on the device region having an interlayer insulating layer, a plurality of wiring patterns disposed within the interlayer insulating layer, and a via structure extending in a direction perpendicular to the upper surface of the semiconductor substrate within the interlayer insulating layer, wherein at least some of the plurality of elements provide a first input / output circuit for transmitting and receiving a first signal and a second input / output circuit for transmitting and receiving a second signal different from the first signal, and at least some of the plurality of wiring patterns are coil patterns providing an inductor circuit, wherein the coil pattern is connected to the first input / output circuit and the via structure penetrates the center of the coil pattern and is connected to the second input / output circuit.
[0009] A semiconductor package according to one embodiment of the present invention comprises a package substrate and a first semiconductor device and a second semiconductor device stacked in a direction perpendicular to the upper surface of the package substrate, wherein each of the first semiconductor device and the second semiconductor device comprises a semiconductor substrate, a plurality of via structures penetrating the semiconductor substrate, a coil pattern surrounding at least one of the plurality of via structures in a direction parallel to the upper surface of the semiconductor substrate, and an input / output circuit connected to the at least one of the plurality of via structures and the coil pattern, wherein the at least one via structure provides a transmission path for a first signal, and the coil pattern provides a transmission path for a second signal different from the first signal.
[0011] A memory system according to one embodiment of the present invention comprises a printed circuit board, a host device disposed on the printed circuit board, and a plurality of memory devices disposed on the printed circuit board and stacked together, and a memory package connected to the host device, wherein at least some of the plurality of memory devices comprise a plurality of through silicon vias and a plurality of coil patterns surrounding at least one of the plurality of through silicon vias, and the plurality of memory devices exchange signals with the host device through the plurality of through silicon vias and the plurality of coil patterns. Effects of the invention
[0013] According to one embodiment of the present invention, some signals are transmitted and received between semiconductor devices by electromagnetic induction caused by current flowing through a coil pattern connected to a pad, and the semiconductor devices can exchange signals other than the signal transmitted to the coil pattern through a via structure penetrating the center of the coil pattern. Therefore, since more signals can be exchanged within a limited area of the semiconductor device, the integration density and performance of the semiconductor device, semiconductor package, and memory system can be improved.
[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing
[0016] FIG. 1 is a simplified block diagram showing a system including a semiconductor device according to one embodiment of the present invention. FIGS. 2a and FIGS. 2b are drawings provided to explain the operation of a semiconductor device according to an embodiment of the present invention. FIGS. 3 and FIGS. 4 are drawings that simply illustrate a semiconductor device according to one embodiment of the present invention. FIGS. 5 to 9 are drawings that simply illustrate a semiconductor package according to one embodiment of the present invention. FIG. 10 is a drawing provided to explain the operation of a semiconductor device according to one embodiment of the present invention. FIG. 11 is a simplified diagram of a semiconductor device according to one embodiment of the present invention. FIG. 12 is a simplified diagram of a semiconductor device according to one embodiment of the present invention. FIGS. 13 and FIGS. 14 are drawings that simply illustrate a semiconductor package according to one embodiment of the present invention. FIGS. 15 and 16 are simplified drawings illustrating coil patterns included in semiconductor devices according to one embodiment of the present invention. FIG. 17 is a drawing provided to explain the operation of semiconductor devices according to one embodiment of the present invention. FIGS. 18 and 19 are drawings that simply illustrate a semiconductor package according to one embodiment of the present invention. FIG. 20 is a simplified diagram of a memory system according to one embodiment of the present invention. Specific details for implementing the invention
[0017] Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings.
[0019] FIG. 1 is a simplified block diagram showing a system including a semiconductor device according to one embodiment of the present invention.
[0020] Referring to FIG. 1, a system (1) according to one embodiment of the present invention includes a first semiconductor device (10) and a second semiconductor device (20), and the first semiconductor device (10) and the second semiconductor device (20) may be connected to communicate with each other. The first semiconductor device (10) may include an internal circuit (11) and an input / output circuit (12), a plurality of coil patterns (13, 14), and a plurality of pads (15, 16). The second semiconductor device (20) may include an internal circuit (21) and an input / output circuit (22), a plurality of coil patterns (23, 24), and a plurality of pads (25, 26).
[0021] In one embodiment, the internal circuit (11) of the first semiconductor device (10) and the internal circuit (21) of the second semiconductor device (20) may have different structures and may perform different functions. For example, if the first semiconductor device (10) is an application processor, the internal circuit (11) may include a CPU, GPU, DSP, NPU, memory interface, display interface, power circuit, etc. If the second semiconductor device (20) is a memory device connected to the application processor, the internal circuit (11) may include a memory cell array in which memory cells are arranged and peripheral circuits that control the memory cell array.
[0022] The first semiconductor device (10) and the second semiconductor device (20) can exchange signals through a plurality of coil patterns (13, 14, 23, 24). For example, the plurality of coil patterns (13, 14, 23, 24) may be inductor circuits provided by wiring patterns inside the first semiconductor device (10) and the second semiconductor device (20). The first semiconductor device (10) and the second semiconductor device (20) can exchange signals by utilizing the electromagnetic induction phenomenon between a pair of coil patterns (13, 14, 23, 24) that are coupled to each other.
[0023] Additionally, the first semiconductor device (10) and the second semiconductor device (20) can also exchange signals with each other through a plurality of pads (15, 16, 25, 26). For example, the first semiconductor device (10) and the second semiconductor device (20) can be stacked together, and the plurality of pads (15, 16) included in the first semiconductor device (10) can be connected to the plurality of pads (25, 26) included in the second semiconductor device (20) through via structures. The first semiconductor device (10) and the second semiconductor device (20) can exchange signals with each other through via structures.
[0024] In one embodiment illustrated in FIG. 1, some of the pads (16, 26) among the plurality of pads (15, 16, 25, 26) may be placed at the center of the coil patterns (13, 14, 23, 24). Via structures connecting some of the pads (16, 26) to each other may penetrate the center of the coil patterns (13, 14, 23, 24).
[0025] Some of the pads (16, 26) can transmit signals just like the other pads (15, 26). In one embodiment, when the first semiconductor device (10) is an application processor and the second semiconductor device (20) is a memory device, the first semiconductor device (10) can transmit power supply voltage required for the operation of the second semiconductor device (20) along with signals such as a data signal, a system clock signal, and a data strobe signal to the second semiconductor device (20). For example, the first semiconductor device (10) and the second semiconductor device (20) can exchange data signals through coil patterns (13, 14, 23, 24). Meanwhile, the first semiconductor device (10) can supply power supply voltage to the second semiconductor device (20) through some of the pads (16, 26) placed at the center of the coil patterns (13, 14, 23, 24).
[0026] However, this is merely one embodiment, and the first semiconductor device (10) and the second semiconductor device (20) may exchange signals other than the power supply voltage through some pads (16, 26) placed at the center of the coil patterns (13, 14, 23, 24). In this way, in one embodiment of the present invention, some pads (16, 26) are placed at the center of the coil patterns (13, 14, 23, 24), and some pads (16, 26) are connected to via structures to be used as a signal transmission path. Accordingly, a signal transmission path between the semiconductor devices (10, 20) can be effectively secured, and the integration density of each of the semiconductor devices (10, 20) can be improved.
[0028] FIGS. 2a and FIGS. 2b are drawings provided to explain the operation of a semiconductor device according to an embodiment of the present invention.
[0029] Referring to FIGS. 2a and 2b, a first semiconductor device (30) and a second semiconductor device (40) according to one embodiment of the present invention can exchange signals with each other by utilizing the electromagnetic induction phenomenon caused by the current flowing through the coil patterns (32, 42). In the embodiments illustrated in FIGS. 2a and 2b, the first semiconductor device (30) is shown transmitting a signal and the second semiconductor device (40) is shown receiving a signal, but it is of course possible that, conversely, the second semiconductor device (40) transmits a signal and the first semiconductor device (30) receives a signal.
[0030] Referring to FIGS. 2a and 2b, a transmitting circuit (31) may be connected to a coil pattern (32) in a first semiconductor device (30), and a receiving circuit (41) may be connected to a coil pattern (42) in a second semiconductor device (40). Referring to FIG. 2a, the transmitting circuit (31) may apply a first current (I1) flowing in a first direction to the coil pattern (32). When the first current (I1) flows through the coil pattern (32), an electromagnetic induction phenomenon occurs within the coil patterns (32, 42) coupled to each other as shown in FIG. 2a, and a voltage may be induced at both ends of the coil pattern (42) of the second semiconductor device (40). Additionally, a second current (I2) may flow through the coil pattern (42) in a first direction.
[0031] Next, referring to FIG. 2b, the transmitting circuit (31) can apply a first current (I1) flowing in a second direction opposite to the first direction to the coil pattern (32). For example, in the embodiments illustrated in FIG. 2a and FIG. 2b, the first direction may be counterclockwise and the second direction may be clockwise. When the first current (I1) flows in the second direction to the coil pattern (32), an electromagnetic induction phenomenon occurs within the coil patterns (32, 42) coupled to each other as illustrated in FIG. 2b, and a voltage may be induced across the ends of the coil pattern (42) of the second semiconductor device (40). Additionally, a second current (I2) flowing in the second direction may be induced to the coil pattern (42).
[0032] The receiving circuit (41) of the second semiconductor device (40) can determine the data included in the signal transmitted by the first semiconductor device (30) based on the voltage induced in the coil pattern (42). For example, when the first semiconductor device (30) intends to transmit data '0', it may apply a voltage to both ends of the coil pattern (32) so that a first current (I1) flows in a first direction in the coil pattern (32). Conversely, when the first semiconductor device (30) intends to transmit data '1', it may apply a voltage to both ends of the coil pattern (32) so that a first current (I1) flows in a second direction in the coil pattern (32).
[0033] The voltage induced in the coil pattern (42) of the second semiconductor device (40) may vary depending on the direction of the first current (I1) flowing in the coil pattern (32) of the first semiconductor device (30). Accordingly, the receiving circuit (41) of the second semiconductor device (40) can determine the data included in the signal transmitted by the first semiconductor device (30) based on the voltage induced in the coil pattern (42).
[0035] FIGS. 3 and FIGS. 4 are drawings that simply illustrate a semiconductor device according to one embodiment of the present invention.
[0036] First, referring to FIG. 3, a semiconductor device (50) according to one embodiment of the present invention may include an internal circuit (51), a transmitter (Tx) and a receiver (Rx), and a plurality of coil patterns (52, 53). The plurality of coil patterns (52, 53) may include a first coil pattern (52) connected to the output terminal of the transmitter (Tx) and a second coil pattern (53) connected to the input terminal of the receiver (Rx).
[0037] The internal circuit (51) may include a plurality of circuits for implementing the functions of the semiconductor device (50). For example, if the semiconductor device (50) is a memory device, the internal circuit (51) may include a power circuit, a decoder circuit, a page buffer, a memory cell array, etc. If the semiconductor device (50) is an application processor, the internal circuit (51) may include a core, a GPU, a DSP, a memory controller, a power circuit, etc.
[0038] The internal circuit (51) can output a signal to another external semiconductor device through the transmitter (Tx) and the first coil pattern (52). The internal circuit (51) can output a desired signal by controlling the direction of the current flowing through the first coil pattern (52) through the transmitter (Tx). Depending on the current flowing through the first coil pattern (52), an induced voltage may be generated in the coil pattern included in another semiconductor device adjacent to the semiconductor device (50). In one embodiment, the internal circuit of the other semiconductor device may receive the signal output by the semiconductor device (50) by comparing the induced voltage with a predetermined reference voltage.
[0039] Additionally, the internal circuit (51) can receive a signal from another external semiconductor device through the receiver (Rx) and the second coil pattern (53). Due to the current flowing through the coil pattern of the other external semiconductor device, an induced voltage may be generated in the second coil pattern (53). The receiver (Rx) can compare the induced voltage generated in the second coil pattern (53) with a predetermined reference voltage, and the internal circuit (51) can receive a signal output by the other semiconductor device.
[0040] In one embodiment illustrated in FIG. 3, a first coil pattern (52) may be connected to a transmitter (Tx) and a second coil pattern (53) may be connected to a receiver (Rx). On the other hand, in a semiconductor device (60) according to one embodiment illustrated in FIG. 4, a single coil pattern (62) may be connected to the output terminal of the transmitter (Tx) and the input terminal of the receiver (Rx). Therefore, in one embodiment illustrated in FIG. 4, the semiconductor device (60) may include a first switch (SW1) and a second switch (SW2) so that the coil pattern (62) is not simultaneously connected to the transmitter (Tx) and the receiver (Rx).
[0041] The first switch (SW1) may be a transmission switch connected between the output terminal of the transmitter (Tx) and the coil pattern (62). Meanwhile, the second switch (SW2) may be a reception switch connected between the input terminal of the receiver (Rx) and the coil pattern (62). Each of the first switch (SW1) and the second switch (SW2) is turned on and turned off by an internal circuit (61), and the first switch (SW1) and the second switch (SW2) may not be turned on simultaneously.
[0042] When the internal circuit (61) wants to output a signal to another semiconductor device, it can turn on the first switch (SW1) and turn off the second switch (SW2) to connect the coil pattern (62) to the output terminal of the transmitter (Tx). On the other hand, when receiving a signal from another semiconductor device, the internal circuit (61) can turn off the first switch (SW1) and turn on the second switch (SW2) to connect the coil pattern (62) to the input terminal of the receiver (Rx).
[0044] FIGS. 5 to 9 are drawings that simply illustrate a semiconductor package according to one embodiment of the present invention.
[0045] Referring to FIG. 5, a semiconductor package (100) according to one embodiment of the present invention includes a first semiconductor device (110) and a second semiconductor device (120), and the first semiconductor device (110) and the second semiconductor device (120) may be stacked together. Each of the first semiconductor device (110) and the second semiconductor device (120) may include an input / output circuit (111, 112, 121, 122), a coil pattern (113, 123) connected to the first input / output circuit (111, 121), and a via structure (130) connected to the second input / output circuit (112, 122).
[0046] The input / output circuits (111, 112, 121, 122) of the first semiconductor device (110) and the second semiconductor device (120), respectively, may include a transmitter, a receiver, and a sampling circuit, etc. Meanwhile, the coil pattern (113, 123) may be connected to the output terminal of the transmitter and the input terminal of the receiver included in the first input / output circuit (111, 121), and the coil pattern (113) of the first semiconductor device (110) may be aligned with the coil pattern (123) of the second semiconductor device (120).
[0047] Accordingly, an induced voltage may be generated in the coil pattern (123) of the second semiconductor device (120) due to the current flowing through the coil pattern (113) of the first semiconductor device (110), and conversely, an induced voltage may be generated in the coil pattern (113) of the first semiconductor device (110) due to the current flowing through the coil pattern (123) of the second semiconductor device (120). In one embodiment illustrated in FIG. 5, each of the coil patterns (113, 123) is simply illustrated, but the shape and number of turns of the coil patterns (113, 123) can be varied in various ways, unlike those illustrated in FIG. 5.
[0048] Referring to FIG. 5, the semiconductor package (100) may include a via structure (130) that penetrates the center of the coil pattern (113, 123). The via structure (130) may extend in a direction in which the first semiconductor device (110) and the second semiconductor device (120) are stacked. Additionally, the via structure (130) may provide a signal transmission path between the first semiconductor device (110) and the second semiconductor device (120). In other words, the first semiconductor device (110) and the second semiconductor device (120) may exchange signals through the via structure (130). In one embodiment, the via structure (130) is connected to a second input / output circuit (112, 122), and a transmitter and a receiver included in the second input / output circuit (112, 122) may output a signal or receive a signal through the via structure (130).
[0049] For example, the via structure (130) may be a through silicon via (TSV) that penetrates a semiconductor substrate included in the first semiconductor device (110). Additionally, the via structure (130) may be formed of a material having low resistivity to efficiently transmit signals. As shown in FIG. 5, by arranging the via structure (130) to penetrate the center of the coil pattern (113, 123) and designing the first semiconductor device (110) and the second semiconductor device (120) to exchange signals through the via structure (130), the integration density of each of the first semiconductor device (110) and the second semiconductor device (120) can be improved.
[0050] In one embodiment, the signal transmitted through the coil pattern (113, 123) and the signal transmitted through the via structure (130) may be different from each other. For example, the first semiconductor device (110) and the second semiconductor device (120) may exchange data signals, data strobe signals, etc. through the coil pattern (113, 123), and may exchange power signals through the via structure (130). However, this is merely one embodiment, and the signal transmitted through the coil pattern (113, 123) and the signal transmitted through the via structure (130) may be modified in various ways.
[0052] Next, referring to FIG. 6, a semiconductor package (100A) according to one embodiment of the present invention includes a first semiconductor device (110) and a second semiconductor device (120), and the first semiconductor device (110) and the second semiconductor device (120) may be stacked together. Each of the first semiconductor device (110) and the second semiconductor device (120) may include an input / output circuit (111, 112, 121, 122), a coil pattern (113, 123) connected to the first input / output circuit (111, 121), and a plurality of via structures (141-144: 140) connected to the second input / output circuit (112, 122). Signal transmission and reception between the first semiconductor device (110) and the second semiconductor device (120) by the operation of the first input / output circuit (111, 121) and the coil pattern (113, 123) can be understood by referring to the explanation above with reference to FIG. 5.
[0053] Referring to FIG. 6, a semiconductor package (100A) may include a plurality of via structures (140) penetrating the center of a coil pattern (113, 123). The plurality of via structures (140) are connected to a second input / output circuit (112, 122), and the second input / output circuit (112, 122) may include a plurality of transmitters and a plurality of receivers connected to the plurality of via structures (140). Each of the plurality of via structures (140) may be arranged along one direction or arranged in a matrix form. The plurality of via structures (140) may have the same cross-sectional area and may be formed of a material having high conductivity.
[0054] In one embodiment illustrated in FIG. 6, a plurality of via structures (140) adjacent to each other and surrounded by coil patterns (113, 123) can provide a transmission path for the same type of signal. For example, the plurality of via structures (140) can provide transmission paths for a plurality of data signals. Also, as previously described, the signal exchanged between the first semiconductor device (110) and the second semiconductor device (120) through the coil patterns (113, 123) may be different from the signal exchanged through the plurality of via structures (140).
[0056] Meanwhile, referring to FIG. 7, a semiconductor package (100B) according to one embodiment of the present invention includes a first semiconductor device (110) and a second semiconductor device (120) that are stacked together, and each of the first semiconductor device (110) and the second semiconductor device (120) may include an input / output circuit (111, 112, 121, 122), a coil pattern (113, 123) connected to the first input / output circuit (111, 121), and a plurality of via structures (151-155: 150), etc. Signal transmission and reception by operation of the first input / output circuit (111, 121) and the coil pattern (112, 122) may be as described above with reference to FIG. 5.
[0057] Referring to FIG. 7, the semiconductor package (100A) may include a plurality of via structures (150) penetrating the center of the coil pattern (113, 123). The plurality of via structures (150) may have the same cross-sectional area.
[0058] In one embodiment illustrated in FIG. 7, at least one via structure (155) among a plurality of via structures (150) may be formed of a material different from the remaining via structures (151-154). For example, at least one via structure (155) may be formed of a first material having ferromagnetic properties, and the remaining via structures (151-154) may be formed of a second material having a lower resistivity than the first material. Thus, the remaining via structures (151-154) may have superior conductivity compared to at least one via structure (155).
[0059] The first semiconductor device (110) and the second semiconductor device (120) can exchange signals with each other through the coil pattern (113, 123) and the remaining via structures (151-154). At least one via structure (155) formed of a ferromagnetic material may not be connected to the second input / output circuit (121, 122), unlike the remaining via structures (151-154). Since at least one via structure (155) formed of a ferromagnetic material is positioned to penetrate the center of the coil pattern (113, 123), the coupling coefficient can be improved without increasing the cross-sectional area of the coil pattern (113, 123). Therefore, the signal transmission efficiency through the coil pattern (113, 123) can be improved without reducing the integration density of the first semiconductor device (110) and the second semiconductor device (120).
[0060] In one embodiment illustrated in FIG. 7, at least one via structure (155) formed of a ferromagnetic material may be disposed between the remaining via structures (151-154), and the remaining via structures (151-154) may be distributed in equal numbers on both sides of the at least one via structure (155). However, this is merely one embodiment, and the arrangement order and shape of the via structure (155) formed of a first material having ferromagnetic properties and the via structures (151-154) formed of a second material having low resistivity may be varied. Additionally, depending on the embodiment, the number of via structures (155) having ferromagnetic properties may also vary.
[0062] Referring to FIG. 8, a semiconductor package (100C) according to one embodiment of the present invention may include a first semiconductor device (110) and a second semiconductor device (120) that are stacked together. Each of the first semiconductor device (110) and the second semiconductor device (120) includes an input / output circuit (111, 112, 121, 122) and a coil pattern (113, 123) connected to the first input / output circuit (111, 121), and the signal transmission and reception between the first semiconductor device (110) and the second semiconductor device (120) through the coil pattern (113, 123) may be as described above.
[0063] Referring to FIG. 8, the semiconductor package (100C) may include a plurality of via structures (161-165: 160) penetrating the center of the coil pattern (111, 121). As described with reference to FIG. 7, at least one via structure (165) among the plurality of via structures (150) may be formed of a first material having ferromagnetic properties, and the remaining via structures (151-154) may be formed of a second material having excellent conductivity. The remaining via structures (151-154) formed of the second material may be connected to a second input / output circuit (112, 122).
[0064] In one embodiment illustrated in FIG. 8, at least one via structure (165) formed of the first material may have a relatively large cross-sectional area compared to the remaining via structures (161-164). Thus, the coupling coefficient of the coil pattern (113, 123) can be increased more significantly, and the signal transmission efficiency through the coil pattern (113, 123) can be improved more significantly.
[0065] Meanwhile, in a semiconductor package (100D) according to an embodiment illustrated in FIG. 9, among a plurality of via structures (171-175: 170), a via structure (175) formed of a ferromagnetic material may have a smaller cross-sectional area compared to the remaining via structures (171-174) formed of a material having high conductivity. Accordingly, as many via structures (171-174) as possible can be arranged in the area formed inside the coil pattern (113, 123) and utilized as a signal transmission path, and the integration density of each of the first semiconductor device (110) and the second semiconductor device (120) can be improved.
[0067] As described with reference to FIGS. 5 through 9, the first semiconductor device (110) and the second semiconductor device (120) can transmit signals through coil patterns (113, 123), as well as exchange signals with each other through via structures (130, 140, 150, 160, 170) arranged to penetrate the center of the coil patterns (113, 123). For example, a power signal may be transmitted between the first semiconductor device (110) and the second semiconductor device (120) through the via structures (130, 140, 150, 160, 170), or a signal other than the power signal may be transmitted. Hereinafter, this will be described in more detail with reference to FIG. 10.
[0069] FIG. 10 is a drawing provided to explain the operation of a semiconductor device according to one embodiment of the present invention.
[0070] In one embodiment illustrated in FIG. 10, the semiconductor device may exchange a data strobe signal (DQS) and data signals (DQ0-DQ3) with another semiconductor device. For convenience of explanation, referring together with FIG. 6, the first semiconductor device (110) may be a memory device, and the second semiconductor device (120) may be a host for the memory device. The second semiconductor device (120) may transmit the data strobe signal (DQS) to the first semiconductor device (110) and exchange data signals (DQ0-DQ3) with the first semiconductor device (110). In one embodiment, the first semiconductor device (110) may sample the data signals (DQ0-DQ3) received from the second semiconductor device (120) at the rising edge and / or falling edge of the data strobe signal (DQS) received from the second semiconductor device (120).
[0071] For example, referring to FIG. 6 and FIG. 10 together, a data strobe signal (DQS) can be transmitted from the second semiconductor device (120) to the first semiconductor device (110) by electromagnetic induction between coil patterns (112, 122). Meanwhile, a transmission path for data signals (DQ0-DQ3) can be provided by via structures (140). For example, a first via structure (141) can provide a transmission path for the first data signal (DQ0), a second via structure (142) can provide a transmission path for the second data signal (DQ1), a third via structure (143) can provide a transmission path for the third data signal (DQ2), and a fourth via structure (144) can provide a transmission path for the third data signal (DQ3).
[0072] Via structures (140) can generally be assigned to each of the data signals (DQ0-DQ3), such as a transmission path connecting multiple semiconductor devices. The second semiconductor device (120) can transmit a data strobe signal (DQS) to the first semiconductor device (110) through coil patterns (112, 122), and at the same time transmit the data signals (DQ0-DQ3) to the first semiconductor device (110) through the via structures (140) as illustrated in FIG. 10. The first semiconductor device (110) may include an input terminal connected to the via structures (140), a receiver, and a sampling circuit that operates in synchronization with the data strobe signal (DQS). The output terminal of the receiver is connected to the input terminal of the sampling circuit, and the sampling circuit can sample data signals (DQ0-DQ3) at the rising edge and / or falling edge of the data strobe signal (DQS).
[0074] FIG. 11 is a simplified diagram of a semiconductor device according to one embodiment of the present invention.
[0075] Referring to FIG. 11, a semiconductor device (200) according to one embodiment of the present invention may include a plurality of input / output circuits (210, 220), a plurality of coil patterns (230), and a plurality of via structures (240). Some of the input / output circuits (210) among the plurality of input / output circuits (210, 220) may be connected to the coil patterns (230), and the remaining input / output circuits (220) may be connected to the via structures (240). The input / output circuits (210, 220) may be connected to the coil patterns (230) and via structures (240) through wiring patterns (215, 225).
[0076] Each of the input / output circuits (210, 220) may include at least one of a transmitter and a receiver. For example, if the semiconductor device (200) is a memory device, the input / output circuit processing the data signal may include both a transmitter and a receiver to exchange data signals with another external semiconductor device. On the other hand, the input / output signal processing the data strobe signal or clock signal may include only a receiver that receives the data strobe signal or clock signal from another external semiconductor device.
[0077] In one embodiment illustrated in FIG. 11, a plurality of coil patterns (230) and a plurality of via structures (240) may be arranged in the center of the semiconductor device (200). However, this is only one embodiment, and the plurality of coil patterns (230) and a plurality of via structures (240) may be arranged adjacent to the edge of the semiconductor device (200), or may be distributed in the center and at the edge of the semiconductor device (200).
[0078] Additionally, each of the plurality of coil patterns (230) may be arranged to surround each of the plurality of via structures (240). In other words, the plurality of via structures (240) may be arranged in an area formed at the center of the plurality of coil patterns (230). By arranging each of the plurality of coil patterns (230) to surround each of the plurality of via structures (240) and transmitting and receiving signals through the coil patterns (230) and the via structures (240), an input / output path capable of transmitting and receiving many signals can be arranged in a limited area of the semiconductor device (200), and the integration density can be improved.
[0079] As previously explained, the coil patterns (230) can be aligned with coil patterns included in other semiconductor devices. For example, the semiconductor device (200) can be stacked with other semiconductor devices, so that the coil patterns (230) may overlap with the coil patterns of other semiconductor devices in the stacking direction. Input / output circuits (210) connected to the coil patterns (230) can output a signal by changing the polarity of the induced voltage induced in the coil patterns of other semiconductor devices by controlling the direction of the current flowing through each of the coil patterns (230). Additionally, the input / output circuits (210) can receive a signal depending on the polarity of the induced voltage induced in each of the coil patterns (230).
[0080] At least one of the plurality of via structures (240) may be a through silicon via penetrating a semiconductor substrate included in the semiconductor device (200). Accordingly, the plurality of via structures (240) may be formed across the device region and wiring region included in the semiconductor device (200). Meanwhile, the plurality of coil patterns (230) may be provided by some of the plurality of wiring patterns formed in the wiring region.
[0082] FIG. 12 is a simplified diagram of a semiconductor device according to one embodiment of the present invention.
[0083] Referring to FIG. 12, a semiconductor device (300) according to one embodiment of the present invention may include a device region (301) and a wiring region (302). The device region (TRA) may include a semiconductor substrate (305) and a plurality of devices (310) formed on the semiconductor substrate (305). Meanwhile, the wiring region (302) may include a plurality of interlayer insulating layers (320) formed on the semiconductor substrate (305), and a plurality of wiring patterns (330) covered by the plurality of interlayer insulating layers (320).
[0084] A plurality of elements (310) may include transistors formed on a semiconductor substrate (305). For example, each of the plurality of elements (310) may include a source / drain region (311) and a gate structure (315). The gate structure (315) may include a gate insulating layer (312), a gate electrode layer (313), a gate spacer (314), etc. A contact (CNT) is connected to the source / drain region (311) and the gate structure (315), and the contact (CNT) may be connected to at least one of a plurality of wiring patterns (330).
[0085] Multiple wiring patterns (330) may be distributed among multiple wiring layers, and the number of wiring layers may vary. For example, wiring patterns (330) placed in the bottom wiring layer may be connected to multiple elements (310) through contacts (CNT). The thickness and width of each of the multiple wiring patterns (330) may vary depending on the wiring layers. For example, the thickness and width of the wiring patterns (330) placed in the top wiring layer may be greater than the thickness and width of the wiring patterns (330) placed in the bottom wiring layer.
[0086] The wiring area (302) includes a passivation layer (340) disposed on the uppermost wiring layer, and at least some of the wiring patterns (330) disposed on the uppermost wiring layer may be exposed to the outside by the passivation layer (340) to provide pads (345). In one embodiment illustrated in FIG. 12, the pads (345) are shown disposed at the edge of the semiconductor device (300), but alternatively, the pads (345) may be disposed at the center of the semiconductor device (300).
[0087] Meanwhile, some of the plurality of wiring patterns (330) may provide a coil pattern (335). The coil pattern (335) may be a pattern provided for the purpose of the semiconductor device (300) exchanging signals with another external semiconductor device. The coil pattern (335) may be positioned to overlap with the coil pattern included in the other semiconductor device when the semiconductor device (300) is stacked and packaged with another semiconductor device.
[0088] In order for the coil pattern (335) to efficiently exchange signals with the coil pattern of another semiconductor device, it is necessary to increase the inductance of the coil pattern (335) and the coupling coefficient between the coil pattern of the other semiconductor device. In one embodiment illustrated in FIG. 12, the inductance of the coil pattern (335) can be increased by forming the coil pattern (335) using some of the wiring patterns (330) of the uppermost wiring layer formed with a relatively large width and thickness. Meanwhile, the semiconductor device (310) connected to the coil pattern (335) may be a device included in an input / output circuit that processes signals transmitted and received through the coil pattern (335).
[0090] FIGS. 13 and FIGS. 14 are drawings that simply illustrate a semiconductor package according to one embodiment of the present invention.
[0091] First, referring to FIG. 13, a semiconductor package (400) according to one embodiment of the present invention may include a package substrate (405) and a plurality of semiconductor devices (410) stacked on the package substrate (405). Each of the plurality of semiconductor devices (410) may be an integrated circuit chip and may include a plurality of coil patterns (411) and a plurality of via structures (412) disposed in a portion of the area.
[0092] In one embodiment illustrated in FIG. 13, a plurality of coil patterns (411) and a plurality of via structures (412) are shown to be arranged in the center of each of the plurality of semiconductor devices (410); however, alternatively, the plurality of coil patterns (411) and a plurality of via structures (412) may be arranged adjacent to the edges of each of the plurality of semiconductor devices (410). The plurality of coil patterns (411) and a plurality of via structures (412) can provide signal transmission paths between the plurality of semiconductor devices (410).
[0093] Each of the plurality of semiconductor devices (410) may include a semiconductor substrate, a device region in which semiconductor devices formed on the semiconductor substrate are disposed, and a wiring region in which a plurality of wiring patterns connected to the semiconductor devices are disposed on the device region. A plurality of coil patterns (411) may be provided by some of the plurality of wiring patterns in the wiring region. When the plurality of semiconductor devices (410) are stacked together, the plurality of coil patterns (411) disposed in the wiring region of different semiconductor devices (410) may be aligned and overlapped with each other.
[0094] Multiple via structures (412) may extend from a wiring region to a device region and may be through silicon vias penetrating a semiconductor substrate. In the direction in which multiple semiconductor devices (410) are stacked, via structures (412) placed at the same location in different semiconductor devices (410) may be connected to each other.
[0096] Referring to FIG. 14, a semiconductor package (500) according to one embodiment of the present invention may include a package substrate (505) and a plurality of semiconductor devices (510, 520), etc., stacked on the package substrate (505). The package substrate (505) includes a plurality of bumps (503) formed on the lower surface and may be electrically connected to another semiconductor package through the plurality of bumps (503).
[0097] A plurality of semiconductor devices (510, 520) include a first semiconductor device (510) and a second semiconductor device (520), and the first semiconductor device (510) may include a first element region (511) and a first wiring region (512). Meanwhile, the second semiconductor device (520) may include a second element region (521) and a second wiring region (522).
[0098] Meanwhile, the first semiconductor device (510) may include first coil patterns (515) and first via structures (516), and the second semiconductor device (520) may include second coil patterns (525) and second via structures (526). As illustrated in FIG. 14, the first via structures (516) and the second via structures (526) may be connected to each other through microbumps (535) formed between the first semiconductor device (510) and the second semiconductor device (520). Additionally, the second via structures (526) may be connected to the package substrate (505) through microbumps (535) formed between the second semiconductor device (520) and the package substrate (505). A protective layer (530) may be further disposed between the first semiconductor device (510) and the second semiconductor device (520), and between the second semiconductor device (520) and the package substrate (505) to protect the microbumps (535) from external shocks, etc.
[0099] Referring to FIG. 14, each of the first via structures (516) and the second via structures (526) is formed across the device region (511, 521) and the wiring region (512, 522), and thus can penetrate the semiconductor substrate included in the device region (511, 521). Additionally, the first via structures (516) may be surrounded by first coil patterns (515), and the second via structures (526) may be surrounded by second coil patterns (525).
[0100] At least some of the first via structures (516) and the second via structures (526) may provide a signal transmission path through which a signal is actually transmitted. Some of the first via structures (516) and the second via structures (526) providing the signal transmission path may be connected to at least one of the semiconductor devices placed in the device regions (511, 521) through the wiring regions (512, 522).
[0101] For example, the first coil patterns (515) and the second coil patterns (525) may provide a signal transmission path for the first semiconductor device (510) and the second semiconductor device (520) to exchange data signals and clock signals. Meanwhile, at least one of the first via structures (516) and the second via structures (526) may provide a power transmission path through which a power supply voltage is transmitted between the first semiconductor device (510) and the second semiconductor device (520). For example, a power supply voltage supplied externally to the package substrate (505) may be input to the first semiconductor device (510) and the second semiconductor device (520) through at least one of the first via structures (516) and the second via structures (526). Additionally, according to embodiments, some of the first via structures (516) and the second via structures (526) may provide a transmission path for a signal different from the coil patterns (515, 525).
[0102] In one embodiment illustrated in FIG. 14, via structures (516, 526) are shown being disposed one by one at the center of each of the coil patterns (515, 525), but alternatively, two or more via structures (516, 526) may be disposed at the center of each of the coil patterns (515, 525). In one embodiment, the arrangement of the coil patterns (515, 525) and via structures (516, 526) may be varied depending on the cross-sectional area of each of the via structures (516, 526), the space formed at the center of each of the coil patterns (515, 525), etc.
[0104] FIGS. 15 and 16 are simplified drawings illustrating coil patterns included in semiconductor devices according to one embodiment of the present invention.
[0105] First, referring to FIG. 15, the coil patterns (600) included in semiconductor devices according to one embodiment of the present invention may include a first coil pattern (610) and a second coil pattern (620). The first coil pattern (610) may be included in a first semiconductor device, and the second coil pattern (620) may be included in a second semiconductor device that is stacked with the first semiconductor device. The first coil pattern (610) and the second coil pattern (620) may be arranged parallel to each other and may overlap each other.
[0106] The first coil pattern (610) and the second coil pattern (620) may have the same structure. For example, the first coil pattern (610) may include a coil section (611), a first lead line (612), and a second lead line (613). The second coil pattern (620) may include a coil section (621), a first lead line (622), and a second lead line (623). In each of the first coil pattern (610) and the second coil pattern (620), one of the first lead line (612, 622) and the second lead line (613, 623) may be placed at the same height as the coil section (611), and the other may be placed at a different height from the coil section (611). In one embodiment illustrated in FIG. 15, the coil portion (611) of the first coil pattern (610) and the coil portion (621) of the second coil pattern (620) may have the same number of turns.
[0107] The first lead line (612) and the second lead line (613) of the first coil pattern (610) can be connected to the input / output circuit of the first semiconductor device. Likewise, the first lead line (622) and the second lead line (623) of the second coil pattern (620) can be connected to the input / output circuit of the second semiconductor device. When a signal is transmitted from the first semiconductor device to the second semiconductor device, the direction of the current flowing through the first coil pattern (610) may change depending on the voltage applied to each of the first lead line (612) and the second lead line (613), and the polarity of the induced voltage induced in the second coil pattern (620) may change. Depending on the polarity of the induced voltage, the second semiconductor device can determine the data of the signal received from the first semiconductor device.
[0108] Meanwhile, the via structure (630) can penetrate the center of the coil portion (611) of the first coil pattern (610) and the center of the coil portion (621) of the second coil pattern (620). As previously described, the via structure (630) can provide a transmission path for signals other than those transmitted and received using electromagnetic induction of the first coil pattern (610) and the second coil pattern (620). For example, the via structure (630) may be formed of a material having ferromagnetic properties to increase the coupling coefficient between the first coil pattern (610) and the second coil pattern (620).
[0110] Next, referring to FIG. 16, the coil patterns (600A) included in the semiconductor devices according to one embodiment of the present invention may include a first coil pattern (610A) and a second coil pattern (620A). The structure of each of the first coil pattern (610A) and the second coil pattern (620A) is similar to that described above with reference to FIG. 15, and the via structure (630A) may penetrate the center of the first coil pattern (610A) and the second coil pattern (620A).
[0111] However, in one embodiment illustrated in FIG. 16, the number of turns of the first coil pattern (610A) may differ from the number of turns of the second coil pattern (620A). Referring to FIG. 16, the number of turns of the first coil pattern (610A) may be greater than the number of turns of the second coil pattern (620A). However, this is only one embodiment, and the number of turns of the second coil pattern (620A) may be greater than the number of turns of the first coil pattern (610A).
[0113] FIG. 17 is a drawing provided to explain the operation of semiconductor devices according to one embodiment of the present invention.
[0114] Referring to FIG. 17, a semiconductor package (700) according to one embodiment of the present invention may include a first semiconductor device (710) and a second semiconductor device (720). The first semiconductor device (710) may include a first coil pattern (711), a second coil pattern (712), an internal circuit (713), a first input / output circuit (714), and a second input / output circuit (715), etc. The first coil pattern (711) may be connected to the internal circuit (713) through a first transmitter (Tx1), and the second coil pattern (712) may be connected to the internal circuit (713) through a first receiver (Rx1).
[0115] The second semiconductor device (720) may have a structure similar to that of the first semiconductor device (710). The second semiconductor device (720) may include a first coil pattern (721), a second coil pattern (722), an internal circuit (723), a first input / output circuit (724), and a second input / output circuit (725), etc. The first coil pattern (721) may be connected to the internal circuit (723) through a second receiver (Rx2), and the second coil pattern (722) may be connected to the internal circuit (723) through a second transmitter (Tx2). In one embodiment, if the first semiconductor device (710) and the second semiconductor device (720) are semiconductor devices of the same type, the internal circuit (713) of the first semiconductor device (710) may be the same as the internal circuit (723) of the second semiconductor device (720).
[0116] Referring to FIG. 17, the first coil pattern (711) of the first semiconductor device (710) is coupled with the first coil pattern (721) of the second semiconductor device (720), and the second coil pattern (712) of the first semiconductor device (710) can be coupled with the second coil pattern (722) of the second semiconductor device (720). When the first semiconductor device (710) and the second semiconductor device (720) are stacked, the first coil patterns (711, 721) overlap each other, and the second coil patterns (712, 722) can overlap each other.
[0117] The internal circuit (713) of the first semiconductor device (710) can control the direction of the current flowing through the first coil pattern (711) via the first transmitter (Tx1), thereby changing the polarity of the induced voltage induced in the first coil pattern (721) of the second semiconductor device (720). The second receiver (Rx2) of the second semiconductor device (720) can compare the induced voltage of the first coil pattern (721) with a reference voltage, and the internal circuit (723) can receive the data that the first semiconductor device (710) intends to transmit to the first transmitter (Tx1) based on the output of the second receiver (Rx2).
[0118] Likewise, the internal circuit (723) of the second semiconductor device (720) can control the direction of the current flowing through the second coil pattern (722) via the second transmitter (Tx2), thereby changing the polarity of the induced voltage induced in the second coil pattern (712) of the first semiconductor device (710). The first receiver (Rx1) of the first semiconductor device (710) can compare the induced voltage of the second coil pattern (712) with a reference voltage, and the internal circuit (713) can receive data that the second semiconductor device (720) intends to transmit to the second transmitter (Tx2) based on the output of the first receiver (Rx1).
[0119] Meanwhile, a first via structure (701) may be disposed at the center of the first coil patterns (711, 721), and a second via structure (702) may be disposed at the center of the second coil patterns (712, 722). The first via structure (701) may be connected to the first input / output circuit (714) of the first semiconductor device (710) and the first input / output circuit (724) of the second semiconductor device (720). The second via structure (702) may be connected to the second input / output circuit (715) of the first semiconductor device (710) and the second input / output circuit (725) of the second semiconductor device (720). According to an embodiment, unlike as illustrated in FIG. 17, a plurality of via structures may be disposed at the center of each of the first coil patterns (711, 721) and the center of the second coil patterns (712, 722).
[0120] Each of the first via structure (701) and the second via structure (702) can provide a transmission path for signals different from the first coil patterns (711, 721) and the second coil patterns (712, 722). For example, if the first semiconductor device (710) is a semiconductor device operating as a host and the second semiconductor device (720) is a memory device such as a DRAM, the first semiconductor device (710) can output a data signal to the second semiconductor device (720) through the first coil pattern (711) and receive a data signal from the second semiconductor device (720) through the second coil pattern (712). Additionally, the second semiconductor device (720) can operate by receiving a power supply voltage from the first semiconductor device (710) through the first via structure (701) and the second via structure (702).
[0122] FIGS. 18 and 19 are drawings that simply illustrate a semiconductor package according to one embodiment of the present invention.
[0123] First, referring to FIG. 18, a semiconductor package (800) according to one embodiment of the present invention may include a package substrate (805) and a plurality of semiconductor devices (810-850) stacked on the package substrate (805). The package substrate (805) may be mounted on a system substrate, etc. through a plurality of bumps (503) formed on its lower surface and may be electrically connected to another semiconductor package.
[0124] At least one of the plurality of semiconductor devices (810-850) may be different from the other semiconductor devices. In one embodiment illustrated in FIG. 18, the first to fourth semiconductor devices (810-840) may be semiconductor devices of the same type, and the fifth semiconductor device (850) may be a semiconductor device of a different type from the first to fourth semiconductor devices (810-840). For example, each of the first to fourth semiconductor devices (810-840) may be memory chips, and the fifth semiconductor device (850) may be a controller chip that controls the memory chips.
[0125] The fifth semiconductor device (850) can be mounted on a package substrate (805) through a plurality of microbumps (853). According to an embodiment, an interposer substrate may be disposed between the fifth semiconductor device (850) and the package substrate (805).
[0126] The first to fourth semiconductor devices (810-840) may be implemented as memory devices having the same capacity and may have the same structure. Referring to the first semiconductor device (810) as an example, the first semiconductor device (810) includes a device region (811) and a wiring region (812), and a plurality of coil patterns (815) may be formed in the wiring region (812). Additionally, the first semiconductor device (810) may include a plurality of via structures (816) penetrating the device region (811) and the wiring region (812). The plurality of via structures (816) of the first semiconductor device (810) may be connected to a plurality of via structures (826) of the second semiconductor device (820) through a plurality of microbumps (813) on the bottom surface. A protective layer (870) for protecting microbumps (813, 823, 833, 843) may be formed between multiple semiconductor devices (810-850).
[0127] Among the first to fourth semiconductor devices (810-840), the via structures (846) of the fourth semiconductor device (840) that is positioned closest to the package substrate (805) can be connected to the via structures (856) of the fifth semiconductor device (850). The via structures (856) of the fifth semiconductor device (850) can be connected to the package substrate (805) through some of the plurality of microbumps (853). Additionally, at least some of the via structures (856) of the fifth semiconductor device (850) may be connected to semiconductor elements inside the fifth semiconductor device (850).
[0128] In each of the plurality of semiconductor devices (810-850), the plurality of via structures (816, 826, 836, 846, 856) may be surrounded by the plurality of coil patterns (815, 825, 835, 845, 855). As previously described, the plurality of semiconductor devices (810-850) can transmit and receive signals to and from each other through the plurality of coil patterns (815, 825, 835, 845, 855) and the plurality of via structures (816, 826, 836, 846, 856). Thus, as many signal transmission paths between the plurality of semiconductor devices (810-850) as possible can be placed in a limited area, and the integration density of the semiconductor package (800) can be improved.
[0130] Next, referring to FIG. 19, a semiconductor package (900) according to one embodiment of the present invention may include a first semiconductor device (910) and a second semiconductor device (920). The structure of each of the semiconductor devices (910, 920) included in the semiconductor package (900) may be similar to that described above with reference to FIG. 18. Referring to the first semiconductor device (910) as an example, it includes a device region (911) and a wiring region (912), and a plurality of coil patterns (915) may be disposed in the wiring region (912). In addition, the first semiconductor device (910) may include a plurality of via structures (916) penetrating the plurality of coil patterns (915).
[0131] However, in one embodiment illustrated in FIG. 19, the first semiconductor device (910) and the second semiconductor device (920) may be stacked so that the wiring region (912) of the first semiconductor device (910) and the wiring region (922) of the second semiconductor device (920) are adjacent to each other. In other words, wiring regions (912, 922) may be arranged between device regions (911, 921). Between adjacent wiring regions (912, 922), a plurality of via structures (916, 926) may be connected to each other through a plurality of microbumps (935). To protect the plurality of microbumps (935) from external shocks, a protective layer (930) may be inserted between the wiring regions (912, 922).
[0132] Also, referring to FIG. 19, a plurality of via structures (916, 926) penetrating a plurality of coil patterns (915, 925) may not extend to device regions (911, 921). Since wiring regions (912, 922) are disposed between device regions (911, 921) including a semiconductor substrate, the plurality of via structures (916, 926) may not be formed in the form of through silicon vias penetrating the semiconductor substrate. However, if another semiconductor device is disposed on top of the first semiconductor device (910) or another semiconductor device is disposed below the second semiconductor device (920), at least some of the plurality of via structures (916, 926) may be formed as through silicon vias penetrating to the device regions (911, 921). Alternatively, in order to connect a plurality of via structures (916) to a pad formed on the device region (911) of the first semiconductor device (910), or to connect a plurality of via structures (926) to a pad formed below the device region (921) of the second semiconductor device (920), at least some of the plurality of via structures (916, 926) may be formed as through silicon vias.
[0134] FIG. 20 is a simplified diagram of a memory system according to one embodiment of the present invention.
[0135] Referring to FIG. 20, a memory system (1000) according to one embodiment of the present invention may include at least one memory package (1100) and a host device (1200). The memory package (1100) may include a plurality of memory devices (1110-1170).
[0136] Each of the plurality of memory devices (1110-1170) may include a peripheral circuit region (PERI) and a cell region (CELL). A plurality of memory cells may be placed in the cell region (CELL). In the peripheral circuit region (PERI), a wordline decoder connected to a plurality of memory cells via wordlines, a sense amplifier circuit connected to a plurality of memory cells via bitlines, and a logic circuit for writing data to a plurality of memory cells or reading data from a plurality of memory cells may be placed.
[0137] Multiple memory devices (1110-1170) can be connected to a host device (1200) through wiring patterns (1020) formed on a printed circuit board (1010). The host device (1200) can be implemented as a central processing unit, a graphics processing unit, a system-on-chip, etc., and can control the operation of the multiple memory devices (1110-1170).
[0138] Meanwhile, each of the plurality of memory devices (1110-1170) may include a plurality of via structures (1030) formed as through silicon vias and a plurality of coil patterns (1040) formed around the plurality of via structures (1030). The plurality of memory devices (1110-1170) and the host device (1200) can exchange signals with each other through the plurality of via structures (1030) and the plurality of coil patterns (1040).
[0139] In one embodiment illustrated in FIG. 20, a host device (1200) and a memory package (1100) are placed at different locations on a printed circuit board (1010) and thus can be connected to each other by wiring patterns (1020) of the printed circuit board (1010). However, depending on the embodiments, the host device (1200) may be mounted directly on the printed circuit board (1010) and the memory package (1100) may be stacked on top of the host device (1200). When the memory package (1100) is stacked on top of the host device (1200), the host device (1200) may include at least one through silicon via connecting the memory package (1100) and the printed circuit board (1010).
[0141] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols
[0143] 10, 20, 30, 40, 50, 60, 100, 100A, 100B, 100C, 100D, 200, 300, 410, 510, 520, 710, 720: Semiconductor device 13, 14, 23, 24, 32, 42, 52, 53, 62, 113, 123, 230, 335, 411, 515, 525, 610, 620, 711, 712, 721, 722: Coil pattern 130, 140, 150, 160, 170, 240, 412, 516, 526, 630, 701, 702: via structure 301, 511, 521: Device area 302, 512, 522: Wiring area 400, 500, 700, 800, 900, 1100: Memory Package 405, 505, 805: Package substrate
Claims
Claim 1 A semiconductor device comprising: a semiconductor substrate; a device region having a plurality of elements formed on the semiconductor substrate; and a wiring region disposed on the device region, comprising an interlayer insulating layer, a plurality of wiring patterns disposed within the interlayer insulating layer, and a via structure extending in a direction perpendicular to the upper surface of the semiconductor substrate within the interlayer insulating layer; wherein at least some of the plurality of elements provide a first input / output circuit for transmitting and receiving a first signal and a second input / output circuit for transmitting and receiving a second signal different from the first signal, and at least some of the plurality of wiring patterns are coil patterns providing an inductor circuit, wherein the coil pattern is connected to the first input / output circuit, and the via structure penetrates the center of the coil pattern, is connected to the second input / output circuit, and is electrically isolated from the coil pattern. Claim 2 A semiconductor device according to claim 1, wherein the first signal is a data signal and the second signal is a power supply voltage signal. Claim 3 A semiconductor device according to claim 1, wherein the first signal is a clock signal and the second signal is a data signal transmitted and received by the second input / output circuit in synchronization with the first signal. Claim 4 A semiconductor device according to claim 1, wherein the via structure comprises a plurality of via structures, the second input / output circuit comprises a plurality of second transmitters that output different signals, and the plurality of via structures are each connected to the plurality of second transmitters. Claim 5 A semiconductor device according to claim 1, wherein the via structure comprises a plurality of via structures, and the second input / output circuit comprises a plurality of second transmitters that output different signals, and at least one of the plurality of via structures is separated from the plurality of second transmitters, and the remaining via structures among the plurality of via structures are each connected to the plurality of second transmitters. Claim 6 A semiconductor device according to claim 5, wherein at least one via structure comprises a first material, and the remaining via structures comprise a second material different from the first material. Claim 7 A semiconductor device according to claim 5, wherein, in one direction parallel to the upper surface of the semiconductor substrate, the at least one via structure is disposed between the remaining via structures. Claim 8 A semiconductor package comprising: a package substrate; and a first semiconductor device and a second semiconductor device stacked in a direction perpendicular to the upper surface of the package substrate; wherein each of the first semiconductor device and the second semiconductor device comprises a semiconductor substrate, a plurality of via structures penetrating the semiconductor substrate, a coil pattern surrounding at least one of the plurality of via structures in a direction parallel to the upper surface of the semiconductor substrate and electrically isolated from the at least one via structure, and an input / output circuit connected to the at least one of the plurality of via structures and the coil pattern, wherein the at least one via structure provides a transmission path for a first signal and the coil pattern provides a transmission path for a second signal different from the first signal. Claim 9 In claim 8, each of the first semiconductor device and the second semiconductor device comprises a first coil pattern, a second coil pattern, a transmitter having an output terminal connected to the first coil pattern, and a receiver having an input terminal connected to the second coil pattern, wherein the first coil pattern of the first semiconductor device is coupled to the second coil pattern of the second semiconductor device, and the second coil pattern of the first semiconductor device is coupled to the first coil pattern of the second semiconductor device. Claim 10 A memory system comprising: a printed circuit board; a host device disposed on the printed circuit board; and a memory package disposed on the printed circuit board and including a plurality of memory devices stacked together and connected to the host device; wherein at least some of the plurality of memory devices include a plurality of through silicon vias and a plurality of coil patterns surrounding at least one of the plurality of through silicon vias, wherein the plurality of through silicon vias are electrically isolated from the plurality of coil patterns, and the plurality of memory devices exchange signals with the host device through the plurality of through silicon vias and the plurality of coil patterns.