Image sensor including stakced chips
The stacked chip configuration with three-dimensional transistors and pixel isolation structure in image sensors enhances integration density and performance, enabling high-resolution imaging by optimizing pixel arrangement and transistor design.
KR102999290B1Active Publication Date: 2026-08-05SAMSUNG ELECTRONICS CO LTD
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Patent Information
- Application Number
- KR1020210185008
- Authority / Receiving Office
- KR · KR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2021-12-22
- Publication Date
- 2026-08-05
- Estimated Expiration
- 2041-12-22
AI Technical Summary
Technical Problem
Existing image sensors face challenges in increasing integration density and improving performance by effectively arranging pixel circuits on multiple chips.
Method used
The image sensor is designed with a stacked chip configuration, where pixel circuits are divided and arranged between an upper and lower chip, incorporating three-dimensional transistors with a gate-all-around structure, and a pixel isolation structure to minimize pixel size and enhance resolution.
Benefits of technology
This configuration allows for a higher pixel density and improved performance by reducing pixel size and integrating high-performance transistors, enabling high-resolution image generation.
✦ Generated by Eureka AI based on patent content.
Abstract
An image sensor is provided. The image sensor comprises a first lower chip; and an upper chip bonded to the first lower chip on the first lower chip. The first lower chip and the upper chip share a plurality of pixels, and each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, and a transmission gate disposed within the upper chip; and a plurality of lower transistors disposed within the first lower chip, wherein the first lower transistor among the plurality of lower transistors includes a plurality of first channel layers stacked vertically, and a first gate that spans the plurality of first channel layers and surrounds each of the plurality of first channel layers.
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