Semiconductor devices

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a first base active region on a substrate; a second base active region adjacent to the first base active region on the substrate; a single first active region extending in a vertical direction and extending in a first direction intersecting the vertical direction on the first base active region; a plurality of second active regions extending in the vertical direction and each extending in the first direction on the second base active region; a device isolation region; a first gate structure extending in a second direction intersecting the first active region; a second gate structure extending in the second direction intersecting the plurality of second active regions; a first source / drain region connected to the first active region on the first active region; a second source / drain region connected to the plurality of second active regions on the plurality of second active regions; and a first contact plug electrically connected to the first source / drain region on the first source / drain region. and a second contact plug electrically connected to the second source / drain region on the second source / drain region, wherein the device isolation region comprises: a first device isolation region disposed on the first base active region and disposed on the side of the first active region; a second device isolation region disposed on the second base active region and disposed on the sides of the plurality of second active regions; and a third device isolation region disposed on the substrate between the first and second base active regions, and the first contact plug may include a first region vertically overlapping with the first source / drain region and a second region vertically overlapping with the device isolation region without vertically overlapping with the first source / drain region.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In manufacturing semiconductor devices with fine patterns to meet the trend of high integration, it is required to implement patterns with fine widths or fine spacing. In addition, efforts are being made to develop semiconductor devices equipped with a channel of a three-dimensional structure to overcome the limitations of operating characteristics resulting from the size reduction of planar MOSFETs (metal oxide semiconductor FETs).

[0004] delete Prior art literature

[65535] Published Patent Application No. 10-2021-0151277 The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises: a first base active region on a substrate; a second base active region adjacent to the first base active region on the substrate; a single first active region extending in a vertical direction and extending in a first direction intersecting the vertical direction on the first base active region; a plurality of second active regions extending in the vertical direction and each extending in the first direction on the second base active region; a device isolation region; a first gate structure extending in a second direction intersecting the first active region; a second gate structure extending in the second direction intersecting the plurality of second active regions; a first source / drain region connected to the first active region on the first active region; a second source / drain region connected to the plurality of second active regions on the plurality of second active regions; and a first contact plug electrically connected to the first source / drain region on the first source / drain region. and a second contact plug electrically connected to the second source / drain region on the second source / drain region, wherein the device isolation region comprises: a first device isolation region disposed on the first base active region and disposed on the side of the first active region; a second device isolation region disposed on the second base active region and disposed on the sides of the plurality of second active regions; and a third device isolation region disposed on the substrate between the first and second base active regions, and the first contact plug may include a first region vertically overlapping with the first source / drain region and a second region vertically overlapping with the device isolation region without vertically overlapping with the first source / drain region.

[0009] A semiconductor device according to exemplary embodiments comprises: a substrate; a single first active region extending in a vertical direction on the substrate and extending in a first direction perpendicular to the vertical direction; a plurality of second active regions extending in the vertical direction on the substrate and each extending in the first direction; a device isolation region on the sides of the first and second active regions; a first gate structure extending in a second direction intersecting the first active region; a second gate structure extending in the second direction intersecting the plurality of second active regions; a first source / drain region connected to the first active region on the first active region; a second source / drain region connected to the plurality of second active regions on the plurality of second active regions; and a first contact plug electrically connected to the first source / drain region on the first source / drain region. and a second contact plug electrically connected to the second source / drain region on the second source / drain region, wherein the first contact plug includes a first region that overlaps vertically with the first source / drain region and a second region that overlaps vertically with the device isolation region without overlapping vertically with the first source / drain region, and the upper surface of the first active region may be positioned at a different level from the upper surface of at least one of the plurality of second active regions. Effects of the invention

[0011] According to embodiments, a semiconductor device comprising a single first active region and a plurality of second active regions adjacent to the first active region can be provided. A semiconductor device with improved electrical characteristics and reliability can be provided by providing a first contact plug that is connected to a single first source / drain region on the single first active region and includes a region that overlaps vertically with a device isolation region without vertically overlapping with the first source / drain region.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments. FIGS. 2a to 2c are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. FIG. 3 is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIGS. 4a to 4c are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. FIG. 5a is a plan view illustrating a semiconductor device according to exemplary embodiments. FIG. 5b is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIG. 6a is a plan view illustrating a semiconductor device according to exemplary embodiments. FIG. 6b is a cross-sectional view illustrating a semiconductor device according to exemplary embodiments. FIGS. 7a to 12 are cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments. FIG. 2a to 2c are cross-sectional views illustrating a semiconductor device according to exemplary embodiments.

[0018] FIGS. 2a to 2c each show cross-sections of the semiconductor device of FIG. 1 cut along the cutting lines I-I', II-II', and III-III'.

[0019] For convenience of explanation, only the major components of the semiconductor device are shown in Fig. 1.

[0020] Referring to FIGS. 1 to 2c, a semiconductor device (100) comprises a substrate (101), a first base active region (103A) on the substrate (101), a first base active region (103B) adjacent to the first base active region (103A) on the substrate (101), active regions (105) including a single first active region (105A) and a plurality of second active regions (105B), a device isolation region (110), a gate structure (160) including a first gate structure (160A) extending in a second direction (y) intersecting the first active region (105A) and a second gate structure (160B) extending in a second direction (y) intersecting the plurality of second active regions (105B), source / drain regions (150) disposed on the active regions (105) at least on one side of the gate structure (160), and a connection to the source / drain regions (150). It may include contact plugs (180). The semiconductor device (100) may further include an interlayer insulating layer (190), a gate isolation pattern (195), and a buried insulating layer (200). The gate structure (160) may include a gate dielectric layer (162), a gate spacer layer (164), a gate electrode (165), and a gate capping layer (166).

[0021] In the semiconductor device (100), active regions (105) may be formed as fin structures protruding from the upper surface of the substrate (101). According to an exemplary embodiment, each of the active regions (105) may be a PMOSFET region or an NMOSFET region.

[0022] A semiconductor device (100) may include a first transistor region (TR1) in which a first active region (105A), a first source / drain region (150A), and a first gate structure (160A) are disposed, and second transistor regions (TR2) in which a second active region (105B), second source / drain regions (150B), and a second gate structure (160B) are disposed. Either one of the first and second transistor regions (TR1, TR2) may be an NMOS transistor region, and the other may be a PMOS transistor region.

[0024] The substrate (101) may have an upper surface extending in the x and y directions. The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer, etc.

[0025] According to an exemplary embodiment, the substrate (101) may include a first base active region (103A) and a second base active region (103B). Active regions (105) may be arranged protruding from the upper surface of the substrate (101) on the first base active region (103A) and the second base active region (103B).

[0027] The active regions (105) may include a single first active region (105A) extending in the vertical direction (z) and extending in the vertical direction (z) and the first direction (x) on the first base active region (103A), and a plurality of second active regions (105B) extending in the vertical direction (z) and each extending in the first direction (x) on the second base active region (103B). The active regions (105) are defined by the device isolation region (110) within the substrate (101) and may be arranged to extend in the first direction, e.g., the x direction. The active regions (105) may have a structure protruding from the substrate (101). The upper end of the active regions (105) may be arranged to protrude to a predetermined height from the upper surface of the device isolation region (110). The active regions (105) may be formed as part of the substrate (101) or may include an epitaxial layer grown from the substrate (101). However, on both sides of the gate structure (160), the active regions (105) on the substrate (101) may be partially recessed, and a source / drain region (150) may be disposed on the recessed active regions (105). The active regions (105) may include impurities or doped regions containing impurities. The first active region (105A) and the second active regions (105B) may have different conductivity types. When the first active region (105A) has a first conductivity type, the second active regions (105B) may have a second conductivity type different from the first conductivity type. The first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type.

[0028] According to exemplary embodiments, in a cross-section along the second direction (y), the uppermost part of the first active region (105A) may be located at a higher level than the uppermost part of at least one of the plurality of second active regions (105B). However, this is not limited thereto, and the uppermost part of the first active region (105A) may be located at substantially the same level as the uppermost part of the plurality of second active regions (105B).

[0030] The device isolation region (110) can define active regions (105) on the substrate (101). The device isolation region (110) may include a first device isolation region (110A) disposed on a first base active region (103A) and disposed on the side of the first active region (105A), a second device isolation region (110B) disposed on a second base active region (103B) and disposed on the sides of a plurality of second active regions (105B), and a third device isolation region (110C) disposed on the substrate (101) between the first and second base active regions (103A, 103B).

[0031] The device isolation region (110) may be formed, for example, by a shallow trench isolation (STI) process. According to embodiments, the third device isolation region (110C) may further include a region that extends deeper with a step below the substrate (101). For example, the bottom of the third device isolation region (110C) may be positioned at a lower level than the bottom of the first and second device isolation regions (110A, 110B). Since the third device isolation region (110C) is formed after the first and second device isolation regions (110A, 110B) are formed, the third device isolation region (110C) may penetrate at least a portion of the first and second device isolation regions (110A, 110B). The device isolation region (110) may expose a portion of the upper part of the active regions (105). According to embodiments, the device isolation region (110) may have a curved upper surface having a higher level as it is adjacent to the active regions (105). The device isolation region (110) may be made of an insulating material. The device isolation region (110) may be, for example, an oxide, a nitride, or a combination thereof.

[0033] A gate structure (160) may be positioned to extend in one direction, for example, in the y-direction, above an active region (105). Channel regions of transistors may be formed in the active regions (105) intersecting the gate structure (160). The gate structure (160) may include first and second gate structures (160A, 160B). Each of the first and second gate structures (160A, 160B) may include a gate electrode (165), a gate dielectric layer (162) between the gate electrode (165) and the active regions (105), gate spacer layers (164) on the sides of the gate electrode (165), and a gate capping layer (166) on the upper surface of the gate electrode (165).

[0034] The gate dielectric layer (162) may be disposed between each of the active regions (105) and the gate electrode (165), and may be disposed to cover at least some of the faces of the gate electrode (165). For example, the gate dielectric layer (162) may be disposed to surround all faces except the top face of the gate electrode (165). The gate dielectric layer (162) may extend between the gate electrode (165) and the gate spacer layer (164), but is not limited thereto. The gate dielectric layer (162) may comprise an oxide, a nitride, or a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The above high dielectric constant material is, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It may be any one of ), and praseodymium oxide (Pr2O3). According to the embodiments, the gate dielectric layer (162) may be made of multiple layers.

[0035] The gate electrode (165) may be disposed extending in a second direction (y) above the active regions (105). The gate electrode (165) may include a conductive material. For example, it may include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon.

[0036] The gate electrode (165) may be composed of two or more multilayers. Gate spacer layers (164) may be disposed on both sides of the gate electrode (165). The gate spacer layers (164) may insulate the source / drain region (150) from the gate electrode (165). The gate spacer layers (164) may be formed into a multilayer structure according to the embodiments. The gate spacer layers (164) may include at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0037] A gate capping layer (166) may be disposed on top of a gate electrode (165). The gate capping layer (166) may be disposed to extend in a second direction, e.g., the y-direction, along the upper surface of the gate electrode (165). The sides of the gate capping layer (166) may be surrounded by gate spacer layers (164). The upper surface of the gate capping layer (166) may be substantially co-planar with the upper surface of the gate spacer layers (164), but is not limited thereto. The gate capping layer (166) may be composed of oxides, nitrides, and oxynitrides, and specifically may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0039] Source / drain regions (150) may be disposed on active regions (105). The source / drain regions (150) may include a first source / drain region (150A) connected to the first active region (105A) on the first active region (105A), and a second source / drain region (150B) connected to the second active regions (105B) on the plurality of second active regions (105B).

[0040] Source / drain regions (150) may be provided as source or drain regions of a transistor. Source / drain regions (150) may be disposed by partially recessing the upper portion of the active region (105), but the recessing and the depth of the recess may vary in the embodiments. Source / drain regions (150) may include a plurality of epitaxial layers, but are not limited thereto. Source / drain regions (150) may be semiconductor layers including silicon (Si) and / or germanium (SiGe). Source / drain regions (150) may include impurities of different types and / or concentrations. For example, source / drain regions (150) may include n-type doped silicon (Si) and / or p-type doped silicon germanium (SiGe). In exemplary embodiments, the source / drain regions (150) may include multiple regions containing elements and / or doping elements of different concentrations. The source / drain regions (150) may have a cross-section along the y-direction that is circular, elliptical, pentagonal, hexagonal, or similar in shape. However, in the embodiments, the source / drain regions (150) may have various shapes, for example, any one of polygonal, circular, and rectangular shapes.

[0041] According to an exemplary embodiment, the second source / drain regions (150B) may be connected to or merged with each other on two or more adjacent second active regions (105B) along the y direction to form one second source / drain region (150B).

[0043] The contact plugs (180) may include a first contact plug (180A) electrically connected to the first source / drain area (180A) on the first source / drain area (180A), and a second contact plug (180B) electrically connected to the second source / drain area (150B) on the second source / drain area (150B).

[0044] The first contact plug (180A) may include a first region (180Aa) that overlaps vertically with the first source / drain region (150A) and a second region (180Ab) that overlaps vertically with the device isolation region (110) without overlapping vertically with the first source / drain region (180A). According to an exemplary embodiment, in the first contact plug (180A), the lowest part of the second region (180Ab) may be located at a higher level than the lowest part of the first region (180Aa).

[0045] The first contact plug (180A) may include an extension (180Ae) on the second region (180Ab). According to an exemplary embodiment, the extension (180Ae) may extend to a level lower than the level where the maximum width along the second direction (y) of the first source / drain region (150A) is located. Specifically, the lowest part of the extension (180Ae) may be located at a level lower than the upper part of the first active region (150A).

[0046] The first contact plug (180A) may include a recessed region. As shown in FIG. 2c, in a cross-section along the second direction (y), the lowest part of the first contact plug (180A) may be located at a lower level than the lowest part of the second contact plug (180B). According to an exemplary embodiment, in a cross-section along the second direction (y), at least a portion of the first contact plug (180A) may extend to a level lower than the upper part of the first source / drain region (150A). According to an exemplary embodiment, the lowest part of the extension (180Ae) may be located at a level lower than the upper part of the first active region (105A), but is not limited thereto.

[0047] The first contact plug (180A) may include a first part (180A_1) and a second part (180A_2) in which a portion of the upper part of the first contact plug (180A) is recessed. Specifically, the first part (180A_1) is a portion covered by a mask pattern and whose height is not reduced during the recessing process of the first contact plug (180A), and the second part (180A_2) may correspond to a portion whose height is reduced by being exposed to an etching atmosphere during the recessing process. As a result, the upper surface of the second part (180A_2) may be located at a lower level than the upper surface of the first part (180A_1).

[0048] Contact plugs (180) can penetrate at least a portion of the interlayer insulation layer (190) to contact source / drain regions (150) and can apply an electrical signal to the source / drain regions (150). Contact plugs (180) can be placed on the source / drain regions (150) and, depending on the embodiments, may be placed to have a longer length along the y-direction than the source / drain regions (150). Contact plugs (180) may have inclined sides such that the width of the lower portion becomes narrower than the width of the upper portion according to the aspect ratio, but are not limited thereto. Contact plugs (180) may be placed to recess the source / drain regions (150) to a predetermined depth.

[0049] The first and second contact plugs (180A, 180B) may include first and second metal-semiconductor compound layers (182A, 182B) located at the bottom, first and second barrier layers (184A, 184B) disposed along the sidewalls, and first and second plug conductive layers (186A, 186B). The first and second metal-semiconductor compound layers (182A, 182B) may be, for example, metal silicide layers. The first and second barrier layers (184A, 184B) may include metal nitrides, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The first and second plug conductive layers (186A, 186B) may comprise a metallic material such as, for example, aluminum (Al), tungsten (W), or molybdenum (Mo). In exemplary embodiments, the first and second contact plugs (180A, 180B) may be positioned to penetrate at least a portion of the source / drain regions (150). In exemplary embodiments, the number and arrangement of the conductive layers constituting the first and second contact plugs (180A, 180B) may vary. Additionally, wiring structures such as contact plugs may be further positioned on the gate electrode (165), and wiring structures connected to the first and second contact plugs (180A, 180B) may be further positioned on the first and second contact plugs (180A, 180B).

[0051] The interlayer insulating layer (190) may be disposed to cover source / drain regions (150), a gate structure (160), and a device isolation region (110). The interlayer insulating layer (190) may include, for example, at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0053] A gate isolation pattern (195) may be placed on a device isolation region (110) between active regions (105). The gate isolation pattern (195) may be placed between the end portion of the first gate structure (160A) and the end portion of the second gate structure (160B) to separate the first and second gate structures (160A, 160B) from each other. In an exemplary embodiment, the gate isolation pattern (195) may be a line shape extending in the x-direction in a plane, but is not limited thereto. The gate isolation pattern (195) may comprise at least one of silicon nitride, silicon oxide, silicon oxynitride, or a nitride-based material. The gate isolation pattern (195) may comprise the same material as the gate spacer layers (164), but is not limited thereto.

[0055] The buried insulating layer (200) may be positioned to cover at least a portion of the first contact plug (180A). The buried insulating layer (200) may be positioned on a second portion (180A_2) of the first contact plug (180A). The buried insulating layer (200) may be substantially the same material as the interlayer insulating layer (190).

[0057] In the description of the following embodiments, descriptions that overlap with the descriptions above with reference to FIGS. 1 to 2c are omitted.

[0059] FIG. 3 is a cross-sectional view illustrating a semiconductor device (100a) according to exemplary embodiments. FIG. 3 illustrates a cross-sectional view of an embodiment modified from the semiconductor device (100) of FIG. 1, cut along the cutting line III-III'.

[0061] The upper surface of the first active region (105A) may be positioned at a different level from the upper surface of at least one of the plurality of second active regions (105B). According to exemplary embodiments, in a cross-section along the second direction (y), the uppermost part of the first active region (105A) may be located at the same or lower level as the uppermost part of at least one of the plurality of second active regions (105B). However, it is not limited thereto.

[0063] FIGS. 4a to 4c are cross-sectional views illustrating a semiconductor device (100b) according to exemplary embodiments. FIGS. 4a to 4c each illustrate cross-sections obtained by cutting an embodiment modified from the semiconductor device (100) of FIG. 1 along the cutting lines I-I', II-II', and III-III'.

[0065] Referring to FIGS. 4a to 4c, the semiconductor device (100) of FIGS. 2a to 2c may further include a channel structure (140).

[0066] The channel structure (140) may include first to third channel layers (141, 142, 143), which are two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active regions (105), for example, in the z-direction, on the active regions (105). Accordingly, the active regions (105) have a fin structure, and a gate electrode (165) may be disposed between the active regions (105) and the lowest channel layer (141), between the plurality of channel layers (141, 142, 143), and on top of the uppermost channel layer (143). Accordingly, the semiconductor device (100) is a Gate-All-Around type field-effect transistor (MBCFET) formed by the plurality of channel layers (141, 142, 143), source / drain regions (150), and gate structures (160). TM It can be a transistor with a (Multi-Bridge Channel FET) structure.

[0067] The first to third channel layers (141, 142, 143) may be connected to source / drain regions (150) and spaced apart from the upper surface of the active regions (105). The first to third channel layers (141, 142, 143) may have a width equal to or similar to that of the active region (105) in the y direction and a width equal to or similar to that of the gate structure (160) in the x direction. However, according to embodiments, the first to third channel layers (141, 142, 143) may have a reduced width such that their sides are located below the gate structure (160) in the x direction.

[0068] The first to third channel layers (141, 142, 143) may be made of a semiconductor material and may include, for example, silicon (Si). The first to third channel layers (141, 142, 143) may be made of, for example, the same material as the substrate (101). The number and shape of the channel layers (141, 142, 143) forming a channel structure (140) may vary in the embodiments. For example, according to the embodiments, the channel structure (140) may further include a channel layer disposed on the upper surface of the active regions (105).

[0069] Source / drain regions (150) may be placed on both sides of multiple channel layers (141, 142, 143).

[0070] The gate structure (160) may be arranged to extend in one direction, e.g., in the y-direction, intersecting the active region (105) and the plurality of channel layers (141, 142, 143) on top of the active region (105) and the plurality of channel layers (141, 142, 143). Channel regions of transistors may be formed in the active region (105) and the plurality of channel layers (141, 142, 143) intersecting the gate structure (160).

[0072] FIG. 5a is a plan view illustrating a semiconductor device (100c) according to exemplary embodiments. FIG. 5b is a cross-sectional view illustrating a semiconductor device (100c) according to exemplary embodiments. FIG. 5b illustrates cross-sections of the semiconductor device (100c) of FIG. 5a cut along the cutting line III-III'.

[0074] Referring to FIGS. 5a and 5b, the shape of the first contact plug (180A) in the embodiments of FIGS. 2a through 2c may be formed asymmetrically. In a cross-section along the second direction (y), at least a portion of the first contact plug (180A) may extend to a level lower than the uppermost portion of the first source / drain region (150A). According to an exemplary embodiment, in a cross-section along the second direction (y), the lowermost portion of the first contact plug (180A) may be positioned at a level lower than the lower portion of the first source / drain region (150A) in a direction close to the second source / drain regions (150B). A semiconductor device (100c) with improved performance can be provided by reducing the parasitic capacitance between the first contact plug (180A) and the gate electrode (165) of the first gate structure (160A) through a buried insulating layer (200) that penetrates at least a portion of the first contact plug (180A).

[0076] FIG. 6a is a plan view illustrating a semiconductor device (100d) according to exemplary embodiments. FIG. 6b is a cross-sectional view illustrating a semiconductor device (100d) according to exemplary embodiments. FIG. 6b illustrates cross-sections of the semiconductor device (100d) of FIG. 6a cut along the cutting line III-III'. Descriptions that overlap with FIG. 5a and FIG. 5b are omitted.

[0078] Referring to FIGS. 6a and 6b, the shape of the first contact plug (180A) may be formed asymmetrically in the embodiments of FIGS. 2a to 2c. According to an exemplary embodiment, in a cross-section along the second direction (y), the first contact plug (180A) may have an extension (180Ae) on one side of the first source-drain region (150A). The lowest part of the extension (180Ae) may be positioned at a level lower than the lower part of the first source / drain region (150A). According to an exemplary embodiment, unlike the embodiments of FIGS. 2a to 2c, the first contact plug (180A) may be formed without a recessed region.

[0080] FIGS. 7a to 12 are cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device (100) according to exemplary embodiments. FIGS. 7a to 12 describe an embodiment of a method for manufacturing the semiconductor device (100) of FIGS. 1 to 2c. FIGS. 7a, 9a, 10a, and 11a illustrate cross-sections corresponding to FIG. 2a, FIGS. 7b, 8, 9b, and 10b illustrate cross-sections corresponding to FIG. 2b, and FIGS. 9c, 11b, and 12 illustrate cross-sections corresponding to FIG. 2c. Overlapping drawings are omitted while proceeding with the process of the semiconductor device (100).

[0081] Referring to FIGS. 7a and 7b, preliminary active regions (105') can be formed on the substrate (101).

[0082] Preliminary active regions (105') can be formed by etching at least a portion of the substrate (101) to form a first trench defining preliminary active regions (105').

[0083] The preliminary active regions (105') may be regions defined by the first trench. The preliminary active regions (105') may be regions formed by removing a portion of the substrate (101) to protrude onto the upper surface of the substrate (101). The preliminary active regions (105') may be shaped to protrude in the z-direction, which is a direction perpendicular to the substrate (101), and may be formed of the same material as the substrate (101). The preliminary active regions (105') may be formed in the shape of a line extending in one direction, for example, in the x-direction, and may be spaced apart from each other in the y-direction.

[0084] In the area where a portion of the substrate (101) has been removed, an insulating material may be buried, and then a preliminary device isolation area (109) may be formed through a planarization process. The preliminary device isolation area (109) may be formed to cover the side of the preliminary active areas (105'). By the planarization process, the upper surface of the preliminary device isolation area (109) may be co-planar with the upper surface of the preliminary active areas (105'). The preliminary device isolation area (109) may include silicon oxide.

[0086] Referring to FIG. 8, a device isolation region (110) can be formed. Active regions (105) can be formed by etching at least a portion of the substrate (101), preliminary active regions (105'), and preliminary device isolation region (109) to form a second trench defining the active regions (105). The active regions (105) may be the region defined by the second trench. In the region where at least a portion of the substrate (101), preliminary active regions (105'), and preliminary device isolation region (109) has been removed, an insulating material is filled and a planarization process is performed to form the device isolation region (110). By the planarization process, the upper surface of the active regions (105) and the device isolation region (110) may form a co-surface. Since the third device isolation region (110C) is formed after the first and second device isolation regions (110A, 110B) are formed, the third device isolation region (110C) can penetrate at least a portion of the first and second device isolation regions (110A, 110B). Since the third device isolation region (110C) penetrates at least a portion of the substrate (101), the lowest part of the third device isolation region (110C) can be located at a lower level than the lowest part of the first and second device isolation regions (110A, 110B). By removing at least a portion of the preliminary active regions (105') while forming the third device isolation region (110C), a single first active region (105A) and a plurality of second active regions (105B) can be formed.

[0087] According to an exemplary embodiment, the active regions (105) may include a single first active region (105a) and a plurality of second active regions (105B) spaced apart from each other in the y direction. The first active region (105A) and the plurality of second active regions (105B) may have different conductivity types. In an exemplary embodiment, the first active region (105A) may have an N-type conductivity type, and at least one of the plurality of second active regions (105B) may have a P-type conductivity type.

[0089] Referring to FIGS. 9a through 9c, the insulating material may be partially removed so that the active regions (105) protrude. Next, a sacrificial gate structure (170) and a gate spacer layer (164) may be formed on the active regions (105). Next, source / drain regions (150) and an interlayer insulating layer (190) may be formed.

[0090] First, a device isolation region (110) can be formed by removing a portion of the insulating material so that the active regions (105) protrude. The first and second device isolation regions (110A, 110B) can be formed to cover a portion of the side of the active regions (105). The upper surface of the first and second device isolation regions (110A, 110B) can be formed lower than the upper surface of the active regions (105). The device isolation region (110) may include silicon oxide.

[0091] The sacrificial gate structure (170) may be a sacrificial structure formed in a region where a gate dielectric layer (162) and a gate electrode (165) are disposed on top of active regions (105) through a subsequent process as in FIG. 2a. The sacrificial gate structure (170) may include first and second sacrificial gate layers (172, 175) that are sequentially stacked, and a mask pattern layer (176). The first and second sacrificial gate layers (172, 175) may be patterned using the mask pattern layer (176). The first and second sacrificial gate layers (172, 175) may each be an insulating layer and a conductive layer. For example, the first sacrificial gate layer (172) may include silicon oxide, and the second sacrificial gate layer (175) may include polysilicon. The mask pattern layer (176) may include silicon nitride. The sacrifice gate structures (170) may have a line shape that extends in one direction intersecting the active regions (105). The sacrifice gate structures (170) may extend in the y direction, for example, and be spaced apart from each other in the x direction.

[0092] A gate spacer layer (164) can be formed on both side walls of the sacrificial gate structures (170). The gate spacer layer (164) can be formed by forming a film of uniform thickness along the top and side surfaces of the sacrificial gate structures (170) and the active regions (105), and then performing anisotropic etching. The gate spacer layer (164) may be made of a low dielectric constant material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0093] Next, a portion of the active regions (105) may be removed to form a recessed region, and then an epitaxial layer of source / drain regions (150) may be formed to fill the recessed region. When a portion of the active regions (105) is removed, the top of the first active region (105A) may be positioned at a higher level than the top of a plurality of second active regions (105B). The source / drain regions (150) may be formed by an epitaxial growth process. The source / drain regions (150) may be formed by repeating epitaxial growth and etching processes. The source / drain regions (150) may contain impurities by in-situ doping. The top surface of the source / drain regions (150) may be positioned at a height level substantially the same as or higher than the bottom surface of the gate structures (160), but is not limited thereto.

[0094] The interlayer insulating layer (190) can be formed by forming an insulating film covering the sacrificial gate structure (170) and source / drain regions (150) and performing a flattening process.

[0096] Referring to FIGS. 10a and 10b, the sacrificial gate structure (170) can be removed and a gate structure (160) can be formed within the gap regions. Additionally, a gate separation pattern (195) can be formed.

[0097] First, gap regions can be formed by removing the sacrifice gate structure (170).

[0098] Next, a gate structure (160) can be formed within the gap regions. A gate dielectric layer (162) can be formed to conformally cover the gap regions. A gate electrode (165) can be formed to fill the gap regions. The gate electrode (165) and the gate spacer layer (164) can be removed from the top of the gap regions to a predetermined depth. A gate capping layer (166) can be formed in the gap regions where the gate electrode (165) and the gate spacer layer (164) have been removed. Accordingly, a gate structure (160) comprising the gate dielectric layer (162), the gate spacer layer (164), the gate electrode (165), and the gate capping layer (166) can be formed.

[0099] An opening may be formed between the first and second gate structures (160A, 160B), and a gate separation pattern (195) may be formed within the opening. The gate separation pattern (195) may be formed by filling the opening with an insulating material and performing a flattening process so that the upper surface of the gate capping layer (166) is exposed. The gate separation pattern (195) may include silicon nitride or a nitride-based material. However, the order of formation of the gate structure (160) and the gate separation pattern (195) is not limited thereto.

[0101] Referring to FIGS. 11a and 11b, first and second contact holes (CH1, CH2) that expose source / drain regions (150) can be formed. The lower surfaces of the first and second contact holes (CH1, CH2) can be recessed into the source / drain regions (150). The first contact hole (CH1) can be formed on the side of the first source / drain region (150A) up to a level lower than the top of the first active regions (105A).

[0103] Referring to FIG. 12, first and second contact plugs (180A, 180B) can be formed. First, a material forming the first and second barrier layers (184A, 184B) is deposited within the first and second contact holes (CH1, CH2), and then a process such as a silicide process is performed to form the first and second metal-semiconductor compound layers (182A, 182B) on the upper surfaces of the first and second source / drain regions (150A, 150B).

[0104] Next, a conductive material can be deposited to fill the first and second contact holes (CH1, CH2) to form the first and second plug conductive layers (186A, 186B). By this step, a first preliminary contact plug (180A') and a second contact plug (180B) can be formed, comprising the first and second metal-semiconductor compound layers (182A, 182B), the first and second barrier layers (184A, 184B), and the first and second plug conductive layers (186A, 186B).

[0105] Next, referring to FIG. 2c, a first contact plug (180A) capable of reducing parasitic capacitance can be formed by etching a portion of the upper part of the first preliminary contact plug (180A'). A buried insulating layer (200) can be buried in the area where the first preliminary contact plug (180A') was etched, and a semiconductor device (100) can be provided through a planarization process.

[0107] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0109] 100: Semiconductor device 101: Substrate 105: Active regions 110: Device isolation region 140: Channel structure 141, 142, 143: First to third channel layers 150A, 150B: 1st and 2nd source / drain areas 160: Gate structure 164: Gate spacer layer 162: Gate dielectric layer 165: Gate electrode 170: Sacrifice Gate Structure 180: Contact Plugs 190: Interlayer insulation layer 200: Embedded insulation layer

Claims

Claim 1 A first base active region on a substrate; a second base active region adjacent to the first base active region on the substrate; a single first active region extending in a vertical direction and extending in a first direction intersecting the vertical direction on the first base active region; a plurality of second active regions extending in the vertical direction and each extending in the first direction on the second base active region; a device isolation region; a first gate structure extending in a second direction intersecting the first active region; a second gate structure extending in the second direction intersecting the plurality of second active regions; a first source / drain region connected to the first active region on the first active region; a second source / drain region connected to the plurality of second active regions on the plurality of second active regions; and a first contact plug electrically connected to the first source / drain region on the first source / drain region. A semiconductor device comprising a second contact plug electrically connected to the second source / drain region on the second source / drain region, wherein the device isolation region comprises: a first device isolation region disposed on the first base active region and disposed on the side of the first active region; a second device isolation region disposed on the second base active region and disposed on the sides of the plurality of second active regions; and a third device isolation region disposed on the substrate between the first and second base active regions, wherein the first contact plug comprises a first region vertically overlapping the first source / drain region, a second region vertically overlapping the device isolation region without vertically overlapping the first source / drain region, and extension portions extending from the second region to both sides of the first source / drain region, and the first source / drain region is a semiconductor device located between the extension portions. Claim 2 A semiconductor device according to claim 1, wherein the first contact plug comprises a first part and a second part in which a portion of the upper part of the first contact plug is recessed, and the upper surface of the second part is located at a lower level than the upper surface of the first part. Claim 3 A semiconductor device according to claim 2, further comprising a buried insulating layer on the second portion of the first contact plug. Claim 4 A semiconductor device according to claim 1, wherein the lowest part of the first contact plug is located at a lower level than the upper part of the first active region. Claim 5 In claim 1, the semiconductor device wherein the lowest part of the second region in the first contact plug is located at a lower level than the lowest part of the first region. Claim 6 A semiconductor device according to claim 1, wherein the uppermost portion of the first active region is located at a higher level than the uppermost portion of at least one of the plurality of second active regions. Claim 7 A semiconductor device according to claim 1, further comprising a plurality of channel layers spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate on the active regions. Claim 8 A substrate; a single first active region extending in a vertical direction on the substrate and extending in a first direction perpendicular to the vertical direction; a plurality of second active regions extending in the vertical direction on the substrate and each extending in the first direction; a device isolation region on the sides of the first and second active regions; a first gate structure extending in a second direction intersecting the first active region; a second gate structure extending in the second direction intersecting the plurality of second active regions; a first source / drain region connected to the first active region on the first active region; a second source / drain region connected to the plurality of second active regions on the plurality of second active regions; and a first contact plug electrically connected to the first source / drain region on the first source / drain region. A semiconductor device comprising a second contact plug electrically connected to the second source / drain region on the second source / drain region, wherein the first contact plug comprises a first region vertically overlapping the first source / drain region, a second region vertically overlapping the device isolation region without vertically overlapping the first source / drain region, and extension portions extending from the second region to both sides of the first source / drain region, wherein the first source / drain region is located between the extension portions, and the upper surface of the first active region is disposed at a different level from the upper surface of at least one of the plurality of second active regions. Claim 9 A semiconductor device according to claim 8, wherein the upper surface of the first active region is positioned at a lower level than the upper surface of at least one of the plurality of second active regions. Claim 10 A semiconductor device according to claim 8, further comprising a gate separation pattern disposed between the end portion of the first gate structure and the end portion of the second gate structure to separate the first and second gate structures from each other.

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