Semiconductor device and semiconductor package including the same

Abstract

The present invention relates to a semiconductor device and a semiconductor package including the same. The semiconductor device may include a substrate, an insulating layer on the lower surface of the substrate, a through-via penetrating the substrate such that the sidewall of the insulating layer protrudes outwardly from the sidewall of the substrate, a wiring structure provided within the insulating layer, and a dummy pattern disposed on the upper surface of the insulating layer exposed by the substrate.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a semiconductor package including the same, and more specifically, to a semiconductor device with improved reliability and a semiconductor package including the same. Background Technology

[0002] With the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In response to this trend, recent packaging technology is moving toward integrating multiple semiconductor chips within a single package.

[0003] Recently, the demand for portable devices in the electronics market has been rapidly increasing, leading to a continuous demand for the miniaturization and lightweighting of electronic components mounted on these products. To achieve this miniaturization and lightweighting, not only is technology required to reduce the individual size of mounted components, but also semiconductor packaging technology to integrate multiple individual components into a single package. In particular, semiconductor packages handling high-frequency signals are required to achieve not only miniaturization but also superior electrical characteristics. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved reliability.

[0005] The technical problem that the present invention aims to solve is to provide a semiconductor package including a semiconductor device with improved reliability.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to the present invention may include a substrate, an insulating layer on the lower surface of the substrate, a through-via penetrating the substrate such that the sidewall of the insulating layer protrudes outwardly from the sidewall of the substrate, a wiring structure provided within the insulating layer, and a dummy pattern disposed on the upper surface of the insulating layer exposed by the substrate.

[0008] A semiconductor substrate according to the present invention comprises a substrate, an insulating layer disposed on the lower surface of the substrate, a through-via penetrating the substrate, a wiring structure provided within the insulating layer, and a first connection pad adjacent to the lower surface of the insulating layer, wherein the sidewall of the insulating layer protrudes outwardly from the sidewall of the substrate, and the angle between the lower surface of the insulating layer and the sidewall of the insulating layer may be an acute angle.

[0009] A semiconductor package according to the present invention comprises a package substrate, a first semiconductor chip on the package substrate, and external terminals on the lower surface of the package substrate, wherein the first semiconductor chip comprises a substrate, an insulating layer on the lower surface of the substrate, a through-via penetrating the substrate, a wiring structure provided within the insulating layer, the wiring structure comprises a conductive via penetrating a portion of the insulating layer and a conductive pattern electrically connected to the conductive via, and the insulating layer may comprise a stepped portion provided protruding outward from the substrate, and a dummy pattern disposed on the stepped portion. Effects of the invention

[0010] According to the present invention, a semiconductor device may be provided having a dummy pattern disposed on the upper surface of an insulating layer protruding outward from a substrate. Accordingly, according to a semiconductor package including said semiconductor device, a bonding defect of the connection pads between adjacently stacked semiconductor chips can be prevented. Ultimately, the bonding efficiency of adjacently stacked semiconductor chips can be improved, thereby providing a semiconductor package with improved reliability. Brief explanation of the drawing

[0011] FIG. 1 is a plan view of a semiconductor package including a semiconductor device according to some embodiments of the present invention. FIG. 2 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. Figure 3 is an enlarged view of area A of Figure 2. FIG. 4 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. FIG. 5 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. FIG. 6 is a plan view of a semiconductor package including a semiconductor device according to some embodiments of the present invention. FIG. 7 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 6. FIG. 8 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 6. FIGS. 9, FIGS. 10, FIGS. 11, FIGS. 13, FIGS. 15, and FIGS. 16 are cross-sectional views for illustrating a method for manufacturing a semiconductor package including a semiconductor device according to some embodiments of the present invention. Figure 12 is an enlarged view of area B of Figure 11. Figure 14 is an enlarged view of area C of Figure 13. Specific details for implementing the invention

[0012] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0013] FIG. 1 is a plan view of a semiconductor package including a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view along I-I' of FIG. 1, illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention. FIG. 3 is an enlarged view of area A of FIG. 2.

[0014] Referring to FIGS. 1, 2, and 3, the semiconductor package (1) may include a first semiconductor chip (100) and a package substrate (500).

[0015] The above package substrate (500) may be, for example, a printed circuit board (PCB). The above package substrate (500) may include a single insulating layer or multiple insulating layers stacked together. The above package substrate (500) may include package substrate pads (510) and terminal pads (520). The above package substrate pads (510) may be adjacent to the upper surface of the package substrate (500), and the above terminal pads (520) may be adjacent to the lower surface of the package substrate (500). The above package substrate pads (510) may be exposed on the upper surface of the package substrate (500). The package substrate pads (510) and the terminal pads (520) may be electrically connected by internal wiring (not shown) within the package substrate (500). The package substrate pads (510) and the terminal pads (520) may comprise a conductive metal material. The package substrate pads (510) and the terminal pads (520) may comprise, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti). In this specification, electrical connection of two components may include the components being connected directly or indirectly through another conductive component.

[0016] External terminals (550) may be provided on the lower surface of the package substrate (500). The external terminals (550) may be disposed on the lower surface of the terminal pads (520) and electrically connected to the terminal pads (520). The external terminals (550) may be connected to an external device. Accordingly, external electrical signals may be transmitted to and received on the package substrate pads (510) through the external terminals (550). The external terminals (550) may include, for example, at least one of solder balls, bumps, and pillars. The external terminals (550) may include a conductive metal material. The external terminals (550) may include, for example, at least one of tin (Sn), lead (Pb), silver (Ag), zinc (Zn), nickel (Ni), gold (Au), copper (Cu), aluminum (Al), and bismuth (Bi).

[0017] The first semiconductor chip (100) may be provided on the package substrate (500) and mounted on the upper surface of the package substrate (500). The first semiconductor chip (100) may include a substrate (110) and an insulating layer (120). The first semiconductor chip (100) may be, for example, a semiconductor chip including a memory chip, a logic chip, or a combination thereof. In this specification, a semiconductor device may refer to the first semiconductor chip (100).

[0018] The substrate (110) may include a semiconductor material such as, for example, silicon, germanium, or silicon-germanium. As an example, the substrate (110) may be a chip-level substrate. The sidewalls (110s) of the substrate (110) may be substantially perpendicular to the upper surface of the package substrate (500) (or the upper surface of the substrate (110)).

[0019] The insulating layer (120) may be disposed on the lower surface of the substrate (110). The insulating layer (120) may include an insulating material. The insulating layer (120) may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The insulating layer (120) may include a single layer or a plurality of stacked layers. The sidewalls (120s) of the insulating layer (120) may intersect with the upper surface of the package substrate (500). The angle (θ) between the lower surface (120b) of the insulating layer (120) and the sidewalls (120s) of the insulating layer (120) may be an acute angle. The angle (θ) between the lower surface (120b) of the insulating layer (120) and the sidewalls (120s) of the insulating layer (120) may be, for example, 20 degrees or more and less than 90 degrees. For example, the width of the upper portion of the insulating layer (120) may be smaller than the width of the lower portion of the insulating layer (120). A portion of the upper surface (120a) of the insulating layer (120) may be exposed by the substrate (110). The width of the insulating layer (120) may increase as it extends toward the lower surface (120b) of the insulating layer (120). The side wall (120s) of the insulating layer (120) may protrude further outward than the side wall (110s) of the substrate (110). That is, the side wall (120s) of the insulating layer (120) may be misaligned rather than aligned with the side wall (110s) of the substrate (110). The width (W1) of the substrate (110) may be smaller than the width (W2) of the uppermost part of the insulating layer (120) (i.e., the minimum width of the insulating layer (120)). The difference between the width (W2) of the uppermost part of the insulating layer (120) and the width (W1) of the substrate (110) may be, for example, 10 μm to 130 μm.As the side wall (120s) of the insulating layer (120) protrudes further outward than the side wall (110s) of the substrate (110), a step (ST) may be formed between the upper surface (120a) of the insulating layer (120) and the side wall (110s) of the substrate (110). In this specification, width may refer to a distance measured in a direction parallel to the upper surface of the package substrate (500).

[0020] A wiring structure (130) may be provided within the insulating layer (120). The wiring structure (130) may include conductive patterns (131) and conductive vias (135). The wiring structure (130) may be provided in multiple numbers. The conductive vias (135) may penetrate a portion of the insulating layer (120) and be electrically connected to the conductive patterns (131). The conductive patterns (131) and the conductive vias (135) may include a conductive metallic material. The conductive patterns (131) and the conductive vias (135) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti). The insulating layer (120) may cover the conductive patterns (131) and the conductive vias (135).

[0021] First connection pads (140) may be provided within the insulating layer (120). The first connection pads (140) may be disposed adjacent to the lower surface (120b) of the insulating layer (120). The first connection pads (140) may be electrically connected to the wiring structures (130). Each of the first connection pads (140) may be electrically connected to the corresponding conductive via (135). The first connection pads (140) may comprise a conductive metallic material. The first connection pads (140) may comprise, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0022] A through-via (150) may be provided within the substrate (110). The through-via (150) may penetrate the substrate (110). The through-via (150) may be electrically connected to the wiring structure (130). The through-via (150) may be provided in multiple numbers. The through-via (150) may include a conductive metallic material. The through-via (150) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti). Although not illustrated, an insulating film and / or a barrier film may be further interposed between the through-via (150) and the substrate (110).

[0023] A pad insulating layer (115) may be provided on the upper surface of the substrate (110). The pad insulating layer (115) may include an insulating material. The pad insulating layer (115) may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a polymer.

[0024] Second connection pads (160) may be disposed adjacent to the upper surface of the substrate (110). The second connection pads (160) may be provided within the pad insulating layer (115). Each of the second connection pads (160) may contact the corresponding through-via (150) and may be electrically connected. The second connection pads (160) may comprise a conductive metal material. The second connection pads (160) may comprise, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0025] A dummy pattern (170) may be provided on the upper surface (120a) of the insulating layer (120). The dummy pattern (170) may be placed on the side wall of the substrate (110). The dummy pattern (170) may cover at least a portion of the upper surface (120a) of the insulating layer (120). In detail, the dummy pattern (170) may be placed on the upper surface (120a) of the insulating layer (120) that protrudes further outward than the substrate (110). The dummy pattern (170) may be placed on the upper surface (120a) of the insulating layer (120) exposed by the substrate (110). The dummy pattern (170) may be placed on the stepped portion (ST). For example, the dummy pattern (170) may have an upwardly convex shape. The dummy pattern (170) may include at least one of a conductive metal material, an insulating material, and a semiconductor material. The dummy pattern (170) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), silicon (Si), silicon oxide, and silicon nitride.

[0026] According to the present invention, a semiconductor device may be provided in which the dummy pattern (170) is disposed on an upper surface of the insulating layer (120) that protrudes outward from the substrate (110). Accordingly, the dummy pattern (170) may not be disposed on the upper surface of the substrate (110), the upper surface of the pad insulating layer (115), and / or the lower surface (120b) of the insulating layer (120).

[0028] FIG. 4 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 1. Hereinafter, content that overlaps with what has been previously described is omitted.

[0029] Referring to FIGS. 1 and FIGS. 4, the semiconductor package (2) may include a package substrate (500), a first semiconductor chip (100), and a second semiconductor chip (200).

[0030] The above package substrate (500) may include package substrate pads (510) and terminal pads (520). External terminals (550) may be provided on the lower surface of the package substrate (500). The description of the package substrate (500) and the external terminals (550) is the same as previously described with reference to FIGS. 1 and FIGS. 2.

[0031] The second semiconductor chip (200) may be provided on the package substrate (500) and mounted on the upper surface of the package substrate (500). The second semiconductor chip (200) may include a base substrate (210) and a base insulating layer (220). The second semiconductor chip (200) may include a semiconductor chip of a different type from the first semiconductor chip (100). The second semiconductor chip (200) may be a logic chip or a buffer chip and may perform a different function from the semiconductor chip (100).

[0032] The base substrate (210) may include a semiconductor material such as, for example, silicon, germanium, or silicon-germanium. As an example, the base substrate (210) may be a chip-level substrate. The sidewalls of the base substrate (210) may be substantially perpendicular to the upper surface of the package substrate (500).

[0033] The base insulating layer (220) may be disposed on the lower surface of the base substrate (210). The base insulating layer (220) may include an insulating material. The base insulating layer (220) may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The base insulating layer (220) may include a single layer or a plurality of stacked layers. The sidewalls of the base insulating layer (220) may be substantially perpendicular to the upper surface of the package substrate (500). For example, the sidewalls of the base insulating layer (220) may be aligned with the sidewalls of the base substrate (210).

[0034] Wiring patterns (230) may be provided within the base insulating layer (220). The wiring patterns (230) may penetrate a portion of the base insulating layer (220). The wiring patterns (230) may include a conductive metal material. The wiring patterns (230) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti). The base insulating layer (220) may cover the wiring patterns (230).

[0035] First chip pads (240) may be provided within the base insulating layer (220). The first chip pads (240) may be disposed adjacent to the lower surface of the base insulating layer (220). The first chip pads (240) may be electrically connected to the wiring patterns (230). The first chip pads (240) may include a conductive metal material. The first chip pads (240) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0036] A chip via (250) may be provided within the base substrate (210). The chip via (250) may penetrate the base substrate (210). The chip via (250) may be electrically connected to the wiring patterns (230). The chip via (250) may be provided in multiple numbers. The chip via (250) may include a conductive metal material. The chip via (250) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti). Although not illustrated, an insulating film and / or a barrier film may be further interposed between the chip via (250) and the base substrate (210).

[0037] A chip pad insulating layer (215) may be provided on the upper surface of the base substrate (210). The chip pad insulating layer (215) may include an insulating material. The chip pad insulating layer (215) may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a polymer.

[0038] Second chip pads (260) may be disposed adjacent to the upper surface of the base substrate (210). The second chip pads (260) may be provided within the chip pad insulating layer (215). Each of the second chip pads (260) may be electrically connected to the corresponding chip via (250). The second chip pads (260) may include a conductive metal material. The second chip pads (260) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0039] First connection terminals (270) may be provided on the lower surface of the second semiconductor chip (200). The first connection terminals (270) may be interposed between the package substrate (500) and the second semiconductor chip (200). The first connection terminals (270) may be disposed on the lower surface of the first chip pads (240) and electrically connected to the first chip pads (240). The first connection terminals (270) may be connected to the package substrate (500). The first connection terminals (270) may include, for example, at least one of a solder ball, a bump, and a pillar. The first connection terminals (270) may include a conductive metal material. The first connection terminals (270) may include, for example, at least one of tin (Sn), lead (Pb), silver (Ag), zinc (Zn), nickel (Ni), gold (Au), copper (Cu), aluminum (Al), and bismuth (Bi).

[0040] A first underfill film (430) may be interposed between the package substrate (500) and the second semiconductor chip (200). The first underfill film (430) may fill the space between the first connection terminals (270) and seal the first connection terminals (270). The first underfill film (430) may include an insulating polymer such as an epoxy-based polymer.

[0041] The first semiconductor chip (100) may be placed on the second semiconductor chip (200). The first semiconductor chip (100) may be provided in multiple numbers and may be vertically stacked on the second semiconductor chip (200). The first semiconductor chips (100) may form a chip stack. The first semiconductor chips (100) may include High Bandwidth Memory (HBM) chips. The first semiconductor chips (100) may include, for example, DRAM chips. The first semiconductor chip (100) may include a substrate (110), a pad insulating layer (115), and an insulating layer (120). A dummy pattern (170) may be placed on the upper surface (120a) of the insulating layer (120), which protrudes further outward than the substrate (110). The description of the first semiconductor chip (100) and the dummy pattern (170) is the same as that previously described with reference to FIGS. 1 to 3.

[0042] The adjacent first semiconductor chips (100) can be electrically connected through first and second connection pads (140, 160). Among the adjacent first semiconductor chips (100), the first connection pad (140) of the upper first semiconductor chip (100) and the second connection pad (160) of the lower first semiconductor chip (100) can be in direct contact and electrically connected. Among the adjacent first semiconductor chips (100), the insulating layer (120) of the upper first semiconductor chip (100) and the pad insulating layer (115) of the lower first semiconductor chip (100) can be in direct contact. The lowest first semiconductor chip (100) and the second semiconductor chip (200) can be electrically connected through the first connection pad (140) and the second chip pad (260). The first connection pad (140) of the first semiconductor chip (100) at the bottom and the second chip pad (260) of the second semiconductor chip (200) can be in direct contact and electrically connected. The insulating layer (120) of the first semiconductor chip (100) at the bottom and the chip pad insulating layer (215) of the second semiconductor chip (200) can be in direct contact. However, in some embodiments, the first semiconductor chip (100) at the top may not include a through-via (150) and a second connection pad (160). The number of stacked first semiconductor chips (100) is not limited to that shown in FIG. 4 and can be varied in many ways.

[0043] Generally, if the sidewalls of the insulating layer and the substrate are aligned, a dummy pattern can be placed on the lower surface of the insulating layer. In this case, due to the dummy pattern, it is difficult to bond the pads between adjacently stacked semiconductor devices, which may reduce bonding efficiency.

[0044] According to the present invention, a semiconductor device may be provided having the dummy pattern (170) disposed on the upper surface (120a) of the insulating layer (120) that protrudes outward from the substrate (110). In this case, the dummy pattern (170) may not be disposed on the upper surface of the substrate (110), the upper surface of the pad insulating layer (115), and / or the lower surface (120b) of the insulating layer (120). Accordingly, according to the semiconductor package including the semiconductor device, a bonding failure of the first and second connection pads (140, 160) between adjacently stacked first semiconductor chips (100) can be prevented. Ultimately, the bonding efficiency of the adjacently stacked first semiconductor chips (100) can be improved, thereby providing a semiconductor package with improved reliability.

[0046] FIG. 5 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view taken along I-I' of FIG. 1. Hereinafter, content that overlaps with what has been previously described is omitted.

[0047] Referring to FIGS. 1 and 5, the semiconductor package (3) may further include a molding film (700) and a heat dissipation structure (750) in addition to the package substrate (500), the first semiconductor chip (100), and the second semiconductor chip (200). The second semiconductor chip (200) may be mounted on the package substrate (500). The description of the package substrate (500) is the same as described above with reference to FIGS. 1 and 2, and the description of the second semiconductor chip (200) is the same as described above with reference to FIG. 4.

[0048] The first semiconductor chips (100) may be vertically stacked on the second semiconductor chip (200). The description of the first semiconductor chip (100) is the same as previously described with reference to FIGS. 1 to 3. However, in some embodiments, a dummy pattern (170) may not be provided on the upper surface (120a) of the insulating layer (120).

[0049] The molding film (700) may be provided on the package substrate (500). The molding film (700) may cover the upper surface of the package substrate (500), the second semiconductor chip (200), and the first semiconductor chips (100). In some embodiments, the molding film (700) may expose the upper surface of the uppermost first semiconductor chip (100). However, it is not limited thereto, and unlike what is illustrated, the molding film (700) may cover the upper surface of the uppermost first semiconductor chip (100). The molding film (700) may include an insulating polymer, for example, an epoxy-based polymer.

[0050] A heat dissipation structure (750) may be provided on the package substrate (500). The heat dissipation structure (750) may be disposed on the upper surface of the uppermost first semiconductor chip (100). The heat dissipation structure (750) may be in contact with the upper surface of the uppermost first semiconductor chip (100). The heat dissipation structure (750) may include a heat slug or a heat sink. The heat dissipation structure (750) may include a material with high thermal conductivity, such as metal.

[0052] FIG. 6 is a plan view of a semiconductor package including a semiconductor device according to some embodiments of the present invention. FIG. 7 is a cross-sectional view along I-I' of FIG. 6, illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention. Hereinafter, details that overlap with those previously described are omitted.

[0053] Referring to FIGS. 6 and 7, the semiconductor package (4) may further include a third semiconductor chip (300) and an interposer substrate (600) in addition to the first semiconductor chip (100), the second semiconductor chip (200), and the package substrate (500).

[0054] The above package substrate (500) may be provided. The above package substrate (500) may include package substrate pads (510) and terminal pads (520). External terminals (550) may be provided on the lower surface of the above package substrate (500). The description of the above package substrate (500) and the external terminals (550) is the same as that described above with reference to FIGS. 1 and FIGS. 2.

[0055] The interposer substrate (600) may be disposed on the package substrate (500). The interposer substrate (600) may include a substrate layer (601) and a wiring layer (602) on the substrate layer (601).

[0056] The substrate layer (601) may include a plurality of through electrodes (660) and lower pads (670). For example, the substrate layer (601) may be a silicon (Si) substrate. The through electrodes (660) may be disposed within the substrate layer (601) and may penetrate the substrate layer (601). Each of the through electrodes (660) may be electrically connected to a corresponding substrate wiring (630) among the substrate wirings (630) to be described later. The lower pads (670) may be disposed adjacent to the lower surface of the substrate layer (601). The lower pads (670) may be electrically connected to the through electrodes (660). The plurality of through electrodes (660) and the lower pads (670) may include a conductive metal material, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0057] The wiring layer (602) may include upper pads (610), internal wiring (620), substrate wiring (630), and a wiring insulation layer (605). The wiring insulation layer (605) may cover the upper pads (610), the internal wiring (620), and the substrate wiring (630). The upper pads (610) may be adjacent to the upper surface of the wiring layer (602), and the substrate wiring (630) may be adjacent to the lower surface of the wiring layer (602). The upper pads (610) may be exposed on the upper surface of the wiring layer (602). The internal wiring (620) may be disposed within the wiring insulation layer (605) and may be electrically connected to the upper pads (610) and the substrate wiring (630). The upper pads (610), the internal wiring (620), and the substrate wiring (630) may include a conductive metal material and, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0058] Substrate bumps (650) may be interposed between the package substrate (500) and the interposer substrate (600). The package substrate (500) and the interposer substrate (600) may be electrically connected by the substrate bumps (650). Each of the lower pads (670) may be electrically connected to a corresponding package substrate pad (510) through a corresponding one of the substrate bumps (650). The substrate bumps (650) may include, for example, at least one of solder balls, bumps, and pillars. The substrate bumps (650) may include a conductive metal material. The substrate bumps (650) may include, for example, at least one of tin (Sn), lead (Pb), silver (Ag), zinc (Zn), nickel (Ni), gold (Au), copper (Cu), aluminum (Al), and bismuth (Bi). The pitch of the substrate bumps (650) may be smaller than the pitch of the external terminals (550).

[0059] A substrate underfill film (410) may be interposed between the package substrate (500) and the interposer substrate (600). The substrate underfill film (410) may fill the space between the substrate bumps (650) and seal the substrate bumps (650). The substrate underfill film (410) may include an insulating polymer, for example, an epoxy-based polymer.

[0060] The second semiconductor chip (200) may be mounted on the interposer substrate (600). The first semiconductor chips (100) may be vertically stacked on the second semiconductor chip (200). Each of the first semiconductor chips (100) may include a substrate (110) and an insulating layer (120). A dummy pattern (170) may be placed on the upper surface (120a) of the insulating layer (120), which protrudes further outward than the substrate (110). The description of the first semiconductor chip (100) and the dummy pattern (170) is the same as described above with reference to FIGS. 1 to 3, and the description of the second semiconductor chip (200) is the same as described above with reference to FIG. 4.

[0061] The third semiconductor chip (300) may be mounted on the interposer substrate (600). The third semiconductor chip (300) may be horizontally spaced apart from the first and second semiconductor chips (100, 200). The third semiconductor chip (300) may be a different type of semiconductor chip from the first and second semiconductor chips (100, 200). The third semiconductor chip (300) may include a logic chip, a buffer chip, or a system-on-chip (SOC). For example, the third semiconductor chip (300) may be an ASIC chip or an application processor (AP) chip. An ASIC chip may include an application-specific integrated circuit (ASIC). The third semiconductor chip (300) may include a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU).

[0062] The third semiconductor chip (300) may include third chip pads (310) adjacent to its lower surface. The third chip pads (310) may be electrically connected to corresponding upper pads (610) of the interposer substrate (600). The third chip pads (310) may include a conductive metal material. The third chip pads (310) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0063] First connection terminals (270) may be interposed between the interposer substrate (600) and the second semiconductor chip (200). The first connection terminals (270) may be positioned on the lower surface of the first chip pads (240) and electrically connected to the interposer substrate (600). Each of the first chip pads (240) may be electrically connected to the upper pad (610) through a corresponding one of the first connection terminals (270). By means of the first connection terminals (270), the interposer substrate (600) and the second semiconductor chip (200) may be electrically connected.

[0064] Second connection terminals (350) may be provided on the lower surface of the third semiconductor chip (300). The second connection terminals (350) may be interposed between the interposer substrate (600) and the third semiconductor chip (300). The second connection terminals (350) may be disposed on the lower surface of the third chip pads (310) and electrically connected to the interposer substrate (600). Each of the third chip pads (310) may be electrically connected to the upper pad (610) through a corresponding one of the second connection terminals (350). The interposer substrate (600) and the third semiconductor chip (300) may be electrically connected by the second connection terminals (350). The second connection terminals (350) may include, for example, at least one of a solder ball, a bump, and a pillar. The second connection terminal (350) may include a conductive metal material. The second connection terminal (350) may include, for example, at least one of tin (Sn), lead (Pb), silver (Ag), zinc (Zn), nickel (Ni), gold (Au), copper (Cu), aluminum (Al), and bismuth (Bi).

[0065] A first underfill film (430) may be interposed between the interposer substrate (600) and the second semiconductor chip (200). The first underfill film (430) may fill the space between the first connection terminals (270) and seal the first connection terminals (270). A second underfill film (420) may be interposed between the interposer substrate (600) and the third semiconductor chip (300). The second underfill film (420) may fill the space between the second connection terminals (350) and seal the second connection terminals (350). The first underfill film (430) and the second underfill film (420) may include an insulating polymer, for example, an epoxy-based polymer.

[0066] A molding film (700) may be provided on the interposer substrate (600). The molding film (700) may cover the upper surface of the interposer substrate (600), the first semiconductor chips (100), the second semiconductor chip (200), and the third semiconductor chip (300).

[0068] FIG. 8 is a drawing for illustrating a semiconductor package including a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view along I-I' of FIG. 6. Hereinafter, content that overlaps with what has been previously described is omitted.

[0069] Referring to FIGS. 6 and 8, the semiconductor package (5) may further include a heat dissipation structure (750) in addition to the first semiconductor chips (100), the second semiconductor chip (200), the third semiconductor chip (300), the package substrate (500), and the interposer substrate (600). The interposer substrate (600) may be placed on the package substrate (500). The second semiconductor chip (200) may be mounted on the interposer substrate (600). The first semiconductor chips (100) may be vertically stacked on the second semiconductor chip (200). The third semiconductor chip (300) may be mounted on the interposer substrate (600). The third semiconductor chip (300) may be horizontally spaced apart from the second semiconductor chip (200). The description of the first semiconductor chips (100) and the package substrate (500) is the same as described above with reference to FIGS. 1 to 3, the description of the second semiconductor chip (200) is the same as described above with reference to FIG. 4, and the description of the third semiconductor chip (300) and the interposer substrate (600) is the same as described above with reference to FIGS. 6 and 7. However, in some embodiments, a dummy pattern (170) may not be provided on the upper surface (120a) of the insulating layer (120) of the first semiconductor chip (100).

[0070] A molding film (700) is provided on the interposer substrate (600) to cover the upper surface of the interposer substrate (600), the first semiconductor chips (100), the second semiconductor chip (200), and the third semiconductor chip (300). The molding film (700) may expose the upper surface of the first semiconductor chip (100) at the top.

[0071] A heat dissipation structure (750) may be provided on the interposer substrate (600). The heat dissipation structure (750) may be disposed on the upper surface of the uppermost first semiconductor chip (100) and the upper surface of the third semiconductor chip (300). The heat dissipation structure (750) may be in contact with at least one of the upper surface of the uppermost first semiconductor chip (100) and the upper surface of the third semiconductor chip (300). The heat dissipation structure (750) may include a heat slug or a heat sink. The heat dissipation structure (750) may include a material with high thermal conductivity, such as metal.

[0073] FIGS. 9, 10, 11, 13, 15, and 16 are cross-sectional views illustrating a method for manufacturing a semiconductor package including a semiconductor device according to some embodiments of the present invention. FIG. 12 is an enlarged view of region B of FIG. 11. FIG. 14 is an enlarged view of region C of FIG. 13. Hereinafter, content that overlaps with what has been previously described is omitted.

[0074] Referring to FIG. 9, a first carrier substrate (800) may be provided. An adhesive layer (810) may be formed on the first carrier substrate (800). The adhesive layer (810) may be, for example, a polymer layer.

[0075] A preliminary semiconductor device (100P) may be formed on the first carrier substrate (800). The preliminary semiconductor device (100P) may be a wafer-level substrate. The preliminary semiconductor device may include a substrate (110), a pad insulating layer (115), and an insulating layer (120). The substrate (110) may be, for example, a semiconductor wafer. The substrate (110) may include a semiconductor material such as, for example, silicon, germanium, or silicon-germanium. The insulating layer (120) may be disposed on the lower surface of the substrate (110). The insulating layer (120) may include an insulating material. The insulating layer (120) may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The pad insulating layer (115) may be disposed on the upper surface of the substrate (110). The pad insulating layer (115) may include an insulating material. The pad insulating layer (115) may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a polymer.

[0076] Wiring structures (130) may be provided within the insulating layer (120). The wiring structures (130) may include a conductive metal material. The wiring structures (130) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0077] First connection pads (140) may be provided within the insulating layer (120). The first connection pads (140) may be disposed adjacent to the lower surface (120b) of the insulating layer (120). The first connection pads (140) may include a conductive metal material. The first connection pads (140) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0078] A through-via (150) may be provided within the substrate (110). The through-via (150) may penetrate the substrate (110). The through-via (150) may include a conductive metal material. The through-via (150) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0079] Second connection pads (160) may be disposed adjacent to the upper surface of the substrate (110). The second connection pads (160) may be provided within the pad insulating layer (115). The second connection pads (160) may include a conductive metal material. The second connection pads (160) may include, for example, at least one of copper (Cu), aluminum (Al), tungsten (W), and titanium (Ti).

[0080] Referring to FIG. 10, a photoresist pattern (PR) may be formed on the substrate (110). The photoresist pattern (PR) may cover a portion of the upper surface of the pad insulating layer (115). The photoresist pattern (PR) may define an area where a subsequent dicing process is to be performed. The photoresist pattern (PR) may expose an area where a subsequent dicing process is to be performed.

[0081] Referring to FIGS. 11 and 12, a first dicing process may be performed on the upper surface of the preliminary semiconductor device (100P). The first dicing process may, for example, include cutting a portion of the preliminary semiconductor device (100P) using plasma. By the first dicing process, the substrate (110) may be recessed to form a first trench (TR1) that exposes a portion of the insulating layer (120). The width (W3) of the first trench (TR1) may be, for example, 80 μm to 150 μm. After the first dicing process is performed, the photoresist pattern (PR) may be removed. However, in some embodiments, the photoresist pattern (PR) may be removed after the second dicing process described later is performed.

[0082] Referring to FIGS. 13 and 14, a second dicing process may be performed on the upper surface of the preliminary semiconductor device (100P). The second dicing process may, for example, include cutting the preliminary semiconductor device (100P) using a laser or a blade. By the second dicing process, the insulating layer (120) may be recessed to form a second trench (TR2) that exposes a portion of the adhesive layer (810). Forming the second trench (TR2) may include recessing a portion of the bottom surface of the first trench (TR1). For example, the upper width of the second trench (TR2) may be greater than the lower width, and the inner wall of the second trench (TR2) may have an incline. The width (W4) of the uppermost part of the second trench (TR2) may be smaller than the width (W3) of the first trench (TR1). The width (W4) of the uppermost part of the second trench (TR2) may be, for example, 20 μm to 80 μm.

[0083] By the second dicing process, a dummy pattern (170) may be formed on the bottom surface of the first trench (TR1). The dummy pattern (170) may be formed on the upper surface (120a) of the insulating layer (120) exposed by the first trench (TR1). For example, the dummy pattern (170) may be formed by at least one residue of the insulating layer (120), the wiring structure (130), the first connection pad (140), and the substrate (110) that can be removed by the second dicing process, accumulating on the upper surface (120a) of the insulating layer (120).

[0084] By the first and second dicing processes above, the preliminary semiconductor device (100P) can be cut so that the first semiconductor chips (100) can be separated. However, in some embodiments, the dummy pattern (170) may be removed differently from what is shown.

[0085] Referring to FIG. 15, a second carrier substrate (850) may be formed on the upper surface of the pad insulating layer (115). The second carrier substrate (850) may cover the upper surface of the pad insulating layer (115). The first semiconductor chips (100) may be inverted so that the second carrier substrate (850) faces downward and the first carrier substrate (800) faces upward.

[0086] Referring to FIG. 16, the first carrier substrate (800) and the adhesive layer (810) can be removed. The diced first semiconductor chips (100) can be separated from the second carrier substrate (850). By the above-described process, the semiconductor device of the present invention can be manufactured.

[0087] Referring again to FIGS. 1 and FIGS. 2, a package substrate (500) may be provided. The package substrate (500) may include package substrate pads (510) and terminal pads (520). A first semiconductor chip (100) separated from the second carrier substrate (850) may be mounted on the package substrate (500). Mounting the first semiconductor chip (100) may include contacting a corresponding first connection pad (140) on a corresponding package substrate pad (510). By the above-described process, a semiconductor package including a semiconductor element of the present invention may be manufactured.

[0088] According to the present invention, a first dicing process can be performed on the substrate (110) to form the first trench (TR1), and then a second dicing process can be performed to form the second trench (TR2) having a width smaller than that of the first trench (TR1). As a result, semiconductor devices can be manufactured in which the dummy pattern (170) is placed on the upper surface (120a) of the insulating layer (120) that protrudes outward from the substrate (110). That is, residues generated by the dicing process can be prevented from accumulating on the upper surface of the substrate (110) or on the upper surface of the pad insulating layer (115). Accordingly, in a subsequent packaging process, a bonding defect between the first and second connecting pads (140, 160) between adjacently stacked first semiconductor chips (100) can be prevented. Ultimately, the bonding efficiency of the first semiconductor chips (100) stacked adjacently can be improved, thereby providing a semiconductor package with improved reliability.

[0090] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor device comprising: a semiconductor substrate; an insulating layer on the lower surface of the semiconductor substrate, wherein the sidewalls of the insulating layer protrude outwardly from the sidewalls of the semiconductor substrate so as to be offset from each other, and a portion of the upper surface of the insulating layer facing the semiconductor substrate is exposed by the semiconductor substrate; a through-via penetrating the semiconductor substrate; a wiring structure provided within the insulating layer; a first connection pad adjacent to the lower surface of the insulating layer; and a dummy pattern disposed on the portion of the upper surface of the insulating layer exposed by the semiconductor substrate. Claim 2 A semiconductor device according to claim 1, wherein the dummy pattern comprises a conductive metal material, and the conductive metal material comprises at least one of copper, aluminum, tungsten, and titanium. Claim 3 A semiconductor device according to claim 1, wherein the dummy pattern comprises an insulating material, and the insulating material comprises at least one of silicon, silicon oxide, and silicon nitride. Claim 4 delete Claim 5 A semiconductor device according to claim 1, wherein the angle between the lower surface of the insulating layer and the side wall of the insulating layer is 20 degrees or more and less than 90 degrees. Claim 6 In claim 5, the sidewall of the semiconductor substrate is a semiconductor device perpendicular to the upper surface of the semiconductor substrate. Claim 7 A semiconductor device according to claim 1, wherein the difference between the width of the uppermost portion of the insulating layer and the width of the semiconductor substrate is 10 μm to 130 μm. Claim 8 A semiconductor device according to claim 1, wherein the width of the insulating layer increases from the upper surface of the insulating layer to the lower surface of the insulating layer. Claim 9 A semiconductor device comprising: a semiconductor substrate; an insulating layer disposed on a lower surface of the semiconductor substrate, wherein the insulating layer has an upper surface facing the semiconductor substrate and a sidewall intersecting the upper surface; a through-via penetrating the semiconductor substrate; a wiring structure provided within the insulating layer; a first connection pad adjacent to the lower surface of the insulating layer; and a dummy pattern, wherein the sidewall of the insulating layer protrudes outwardly from the sidewall of the semiconductor substrate, the dummy pattern is disposed on the upper surface of the insulating layer and the sidewall of the semiconductor substrate, and the angle between the lower surface of the insulating layer and the sidewall of the insulating layer is an acute angle. Claim 10 A semiconductor package comprising: a package substrate; a first semiconductor chip on the package substrate; and external terminals on the lower surface of the package substrate, wherein the first semiconductor chip comprises: a semiconductor substrate; an insulating layer on the lower surface of the semiconductor substrate; a through-via penetrating the semiconductor substrate; a wiring structure provided within the insulating layer, wherein the wiring structure comprises a conductive via penetrating a portion of the insulating layer and a conductive pattern electrically connected to the conductive via; a step portion provided such that the insulating layer protrudes outward from the semiconductor substrate; and a dummy pattern disposed on the step portion, wherein the dummy pattern is disposed on the sidewall of the semiconductor substrate on the insulating layer, and the dummy pattern has an upwardly convex shape. Claim 11 In claim 1, the dummy pattern is a semiconductor device disposed on the upper surface of the insulating layer and on the sidewall of the semiconductor substrate.

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