Semiconductor package

Abstract

A semiconductor package comprises a substrate; a lower semiconductor chip on the substrate; a first upper semiconductor chip provided on the upper surface of the lower semiconductor chip and including upper pads; and bonding wires connected to the substrate and the upper pads, wherein, in a planar view, the first upper semiconductor chip has: a first overhang region spaced apart from the lower semiconductor chip and adjacent to a first side of the first upper semiconductor chip; a second overhang region spaced apart from the lower semiconductor chip and adjacent to a second side of the first upper semiconductor chip; and a first corner overhang region spaced apart from the lower semiconductor chip, wherein the corner region is adjacent to a corner where the first side and the second side of the first upper semiconductor chip meet, and the upper pads include: first upper pads on the upper surface of the first overhang region; and second upper pads on the upper surface of the second overhang region, wherein the number of the first upper pads is smaller than the number of the second upper pads, and the upper pads may be spaced apart from the first corner overhang region of the first upper semiconductor chip.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, specifically a semiconductor package including bonding wires. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board and electrically connecting them using bonding wires or bumps. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor package with improved reliability and electrical characteristics. means of solving the problem

[0004] According to embodiments of the present invention, a semiconductor package comprises a substrate; a lower semiconductor chip on the substrate; a first upper semiconductor chip provided on the upper surface of the lower semiconductor chip and including upper pads; and bonding wires connected to the substrate and the upper pads, wherein, in a planar view, the first upper semiconductor chip has: a first overhang region spaced apart from the lower semiconductor chip and adjacent to a first side of the first upper semiconductor chip; a second overhang region spaced apart from the lower semiconductor chip and adjacent to a second side of the first upper semiconductor chip; and a first corner overhang region spaced apart from the lower semiconductor chip, wherein the corner region is adjacent to a corner where the first side and the second side of the first upper semiconductor chip meet, and the upper pads include: first upper pads on the upper surface of the first overhang region; and second upper pads on the upper surface of the second overhang region, wherein the number of the first upper pads is smaller than the number of the second upper pads, and the upper pads may be spaced apart from the first corner overhang region of the first upper semiconductor chip.

[0005] According to embodiments of the present invention, a semiconductor package may comprise: a substrate including first substrate pads and second substrate pads; a lower semiconductor chip disposed on the substrate and including lower pads; a first upper semiconductor chip disposed on the lower semiconductor chip and including upper pads; first bonding wires connected to the lower pads and the first substrate pads; second bonding wires connected to the upper pads and the second substrate pads; and a molding film provided on the upper surface of the substrate and covering the lower semiconductor chip, the first upper semiconductor chip, the first bonding wires, and the second bonding wires. The first upper semiconductor chip is spaced apart from the lower pads, and in a planar view, the first upper semiconductor chip comprises: a first mounting region that overlaps with the lower semiconductor chip; and a first overhang region spaced apart from the lower semiconductor chip and between a first side of the lower semiconductor chip and a first side of the first upper semiconductor chip. A second overhang region spaced apart from the lower semiconductor chip and between the second side of the lower semiconductor chip and the second side of the first upper semiconductor chip; and a first corner overhang region spaced apart from the lower semiconductor chip, wherein the corner overhang region is adjacent to the corner where the first side and the second side of the first upper semiconductor chip meet, and the upper pads include: first upper pads on the upper surface of the first overhang region; and second upper pads on the upper surface of the second overhang region, wherein the number of the second upper pads is smaller than the number of the first upper pads, and the upper pads may not be provided on the corner overhang region of the first upper semiconductor chip.

[0006] According to embodiments of the present invention, a semiconductor package comprises: a substrate; a first semiconductor chip disposed on the substrate and having a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, wherein the first semiconductor chip includes first chip pads on an upper surface; a second semiconductor chip provided on the first semiconductor chip and having a first sidewall, a second sidewall opposite to the first sidewall, a third sidewall, and a fourth sidewall opposite to the third sidewall, wherein the second semiconductor chip includes second chip pads on an upper surface; and first bonding wires connected to the first chip pads. The apparatus includes second bonding wires connected to the second chip pads, wherein the first chip pads are adjacent to the first side, the third side, and the fourth side of the first semiconductor chip in a planar view, and the maximum gap between the first chip pads and the first side of the first semiconductor chip is smaller than the minimum gap between the first chip pads and the second side of the first semiconductor chip, and the second chip pads are arranged adjacent to the second sidewall, the third sidewall, and the fourth sidewall of the second semiconductor chip in a planar view, and the maximum gap between the second chip pads and the second sidewall of the second semiconductor chip is smaller than the minimum gap between the second chip pads and the second sidewall of the second semiconductor chip, and the first sidewall of the second semiconductor chip can be vertically aligned with the first side of the first semiconductor chip. Effects of the invention

[0007] According to the present invention, semiconductor chips can be stacked. Bonding wires can be disposed on the upper surfaces of the semiconductor chips. The arrangement of the pads of the semiconductor chips can be controlled so that damage to the semiconductor chips during the bonding wire formation process can be prevented. Alternatively, the arrangement of the pads of the semiconductor chips can be controlled so that the occurrence of an electrical short circuit between the bonding wires can be prevented. The semiconductor package can exhibit improved reliability and electrical characteristics. The manufacturing process efficiency of the semiconductor package can be improved. Brief explanation of the drawing

[0008] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments. FIG. 1b is a plan view illustrating the arrangement of a first upper semiconductor chip and a second upper semiconductor chip of a semiconductor package according to embodiments. FIG. 1c is a plan view for illustrating the arrangement of a second upper semiconductor chip and a third upper semiconductor chip of a semiconductor package according to embodiments. Figure 1d is a cross-section taken along the line I-I' of Figure 1a. Figure 1e is a cross-section taken along the line II-II' of Figure 1a. Figure 1f is a cross-section taken along the line III-III' of Figure 1a. FIGS. 2a to 2c are drawings for illustrating semiconductor packages according to embodiments. FIG. 3a is a plan view for illustrating the arrangement of a first upper semiconductor chip and a second upper semiconductor chip according to embodiments. FIG. 3b is a plan view for illustrating the arrangement of the first upper semiconductor chip and the second upper semiconductor chip according to embodiments. FIG. 4a is a plan view of a semiconductor package according to embodiments. FIG. 4b is a plan view of a first semiconductor chip according to embodiments. FIG. 4c is a plan view of a second semiconductor chip according to embodiments. Figure 4d is a cross-section taken along the line A-A' of Figure 4a. Figure 4e is a cross-section cut along the line B-B' of Figure 4a. Figure 4f is a cross-section cut along the line C-C' of Figure 4a. FIGS. 5A, FIGS. 5B, and FIGS. 5C are drawings for illustrating semiconductor packages according to embodiments. Specific details for implementing the invention

[0009] In this specification, the same reference numerals throughout the text may refer to the same components. A semiconductor package according to the concept of the present invention is described.

[0011] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments, and is a drawing for explaining the arrangement of a lower semiconductor chip and a first upper semiconductor chip. FIG. 1b is a plan view for explaining the arrangement of a first upper semiconductor chip and a second upper semiconductor chip of a semiconductor package according to embodiments. FIG. 1c is a plan view for explaining the arrangement of a second upper semiconductor chip and a third upper semiconductor chip of a semiconductor package according to embodiments. FIG. 1d is a cross-section cut along line I-I' of FIG. 1a. FIG. 1e is a cross-section cut along line II-II' of FIG. 1a. FIG. 1f is a cross-section cut along line III-III' of FIG. 1a. FIG. 1d corresponds to the cross-section cut along line I-I' of FIG. 1b and line I-I' of FIG. 1c. FIG. 1e corresponds to the cross-section cut along line II-II' of FIG. 1b and line II-II' of FIG. 1c. Figure 1f corresponds to a cross-section cut along the line III-III' of Figure 1b and the line III-III' of Figure 1c.

[0012] Referring to FIGS. 1a through 1f, the semiconductor package (1) may include a substrate (500), a lower semiconductor chip (100), a first upper semiconductor chip (210), first bonding wires (BW1), and second bonding wires (BW2).

[0013] The substrate (500) may include first substrate pads (511), second substrate pads (512), third substrate pads (513), fourth substrate pads (514), lower substrate pads (520), and conductive patterns (530). For example, the substrate (500) may be a printed circuit board (PCB). As shown in FIG. 1d, the first substrate pads (511), second substrate pads (512), and third substrate pads (513) may be provided on the upper surface of the substrate (500). The first substrate pads (511), second substrate pads (512), and third substrate pads (513) may be spaced apart from each other. Conductive patterns (530) are provided within the substrate (500) and may be connected to first substrate pads (511), second substrate pads (512), third substrate pads (513), or fourth substrate pads (514). The conductive patterns (530) may include vias and wirings. Electrical connection of two components includes the components being connected directly or indirectly through other conductive components. Electrical connection to the substrate (500) may mean being electrically connected to any one of the first substrate pads (511), second substrate pads (512), third substrate pads (513), and fourth substrate pads (514). Lower substrate pads (520) may be provided on the lower surface of the substrate (500). The lower substrate pads (520) may be electrically connected to the first substrate pads (511), the second substrate pads (512), the third substrate pads (513), or the fourth substrate pads (514) through the conductive patterns (530). The first to fourth substrate pads (511, 512, 513, 514), the conductive patterns (530), and the lower substrate pads (520) may include a metal such as aluminum, copper, tungsten, and / or titanium.

[0014] The first direction (D1) may be parallel to the upper surface of the substrate (500). The second direction (D2) may be parallel to the upper surface of the substrate (500) and substantially perpendicular to the first direction (D1). The third direction (D3) may be substantially perpendicular to the upper surface of the substrate (500). The fourth direction (D4) may be parallel to the upper surface of the substrate (500) and intersect the first direction (D1) and the second direction (D2). The fourth direction (D4) may be a diagonal direction in a planar view.

[0015] The semiconductor package (1) may further include solder balls (600). The solder balls (600) may be provided on the lower surface of the substrate (500). For example, the solder balls (600) may be connected to the lower surfaces of the lower substrate pads (520). The solder balls (600) may include a metal such as a solder material. The solder material may include, for example, tin (Sn), silver (Ag), zinc (Zn), and / or an alloy thereof.

[0016] A lower semiconductor chip (100) may be placed on the upper surface of a substrate (500). The lower semiconductor chip (100) may include a memory chip, for example, a DRAM. As another example, the lower semiconductor chip (100) may be, for example, a logic chip or a buffer chip.

[0017] As shown in FIG. 1a, the lower semiconductor chip (100) may have a first side (100s1), a second side (100s2), a third side (100s3), and a fourth side (100s4). The second side (100s2) of the lower semiconductor chip (100) may be adjacent to the first side (100s1). The third side (100s3) of the lower semiconductor chip (100) may be opposite to the first side (100s1). The third side (100s3) of the lower semiconductor chip (100) may be parallel to the second direction (D2). The fourth side (100s4) of the lower semiconductor chip (100) may be opposite to the second side (100s2) and adjacent to the first side (100s1) and the third side (100s3). The fourth side (100s4) of the lower semiconductor chip (100) can be parallel to the first direction (D1).

[0018] The lower semiconductor chip (100) may have a first edge region (ER1), a second edge region (ER2), a mounting region, and a corner region (CR) in a planar view. The first edge region (ER1) of the lower semiconductor chip (100) may be adjacent to the third side (100s3) of the substrate (500) in a planar view. The second edge region (ER2) of the lower semiconductor chip (100) may be adjacent to the fourth side (100s4). The corner region (CR) of the lower semiconductor chip (100) may be adjacent to the corner where the third side (100s3) and the third side (100s3) meet. The corner region (CR) of the lower semiconductor chip (100) may be provided between the third side (100s3) of the lower semiconductor chip (100) and the second edge region (ER2), and between the fourth side (100s4) of the lower semiconductor chip (100) and the first edge region (ER1).

[0019] The lower semiconductor chip (100) may include lower integrated circuits and a plurality of lower pads. The lower integrated circuits may be provided within the lower semiconductor chip (100). The lower pads may include first lower pads (111) and second lower pads (112). The first and second lower pads (111, 112) may be chip pads or rewiring pads of the lower semiconductor chip (100). The first lower pads (111) and the second lower pads (112) may be electrically connected to the lower integrated circuits.

[0020] The first lower pads (111) may be provided on the upper surface of the first edge region (ER1) of the lower semiconductor chip (100). The first lower pads (111) may be adjacent to the third side (100s3) of the lower semiconductor chip (100). The first lower pads (111) may be aligned along the second direction (D2). The second lower pads (112) may be provided on the upper surface of the second edge region (ER2) of the lower semiconductor chip (100). The second lower pads (112) may be positioned adjacent to the fourth side (100s4) of the lower semiconductor chip (100). The second lower pads (112) may be provided in plurality, and the plurality of second lower pads (112) may be aligned along the first direction (D1). As the second lower pad (112) is provided, the first lower pads (111) may not be provided on the corner region (CR) of the lower semiconductor chip (100).

[0021] The number of second lower pads (112) may be smaller than the number of first lower pads (111). For example, the number of second lower pads (112) may be 1% to 50% of the number of first lower pads (111). The size of the second lower pads (112) may be substantially the same as the first lower pads, but is not limited thereto. The first and second lower pads (111, 112) may comprise a metal such as aluminum, copper, nickel, and / or an alloy thereof. Unlike what is illustrated, the lower semiconductor chip (100) may include a single number of second lower pads (112). Hereinafter, for convenience, a plurality of second lower pads (112) are described, but the present invention is not limited thereto.

[0022] The second edge region (ER2) of the lower semiconductor chip (100) may include a pad region (PR) and a blank region (BR). The blank region (BR) of the lower semiconductor chip (100) may be adjacent to the first side (100s1) of the lower semiconductor chip (100) in a planar view. For example, the blank region (BR) of the lower semiconductor chip (100) may be provided between a first imaginary line and the first side (100s1) of the lower semiconductor chip (100). The first imaginary line may pass through the midpoint of the fourth side (100s4) of the lower semiconductor chip (100) and may be parallel to the second direction (D2). The pad region (PR) of the lower semiconductor chip (100) may be provided between the blank region (BR) and the corner region (CR). The pad area (PR) of the lower semiconductor chip (100) can be provided between the first virtual line and the corner area (CR) of the lower semiconductor chip (100).

[0023] Referring to FIGS. 1a and 1d, first bonding wires (BW1) may be provided on the upper surface of the lower semiconductor chip (100). First and second lower pads (111, 112) may be connected to the first substrate pads (511) through the first bonding wires (BW1). The lower semiconductor chip (100) may be connected to the substrate (500) through the first bonding wires (BW1). In this specification, connecting to the semiconductor chip may include connecting to the integrated circuits of the semiconductor chip. The first bonding wires (BW1) may include a metal such as gold (Au). The second lower pads (112) may be provided on the pad region (PR) of the lower semiconductor chip (100), but may not be provided on the blank region (BR). Accordingly, the bonding process between the second bonding wires (BW2) and the first lower pads (111) and the bonding process between the second bonding wires (BW2) and the second lower pads (112) can be easily performed.

[0024] An upper semiconductor chip may be placed on the upper surface of a lower semiconductor chip (100). The upper semiconductor chip may be a first upper semiconductor chip (210). The first upper semiconductor chip (210) may include a memory chip, for example, a DRAM. As another example, the first upper semiconductor chip (210) may be a logic chip or a buffer chip, for example. The first upper semiconductor chip (210) may be a chip of the same type as the lower semiconductor chip (100). The first upper semiconductor chip (210) may have the same size and the same storage capacity as the lower semiconductor chip (100). As another example, the first upper semiconductor chip (210) may be a chip of a different type from the lower semiconductor chip (100) and may have a different size from the lower semiconductor chip (100).

[0025] The first upper semiconductor chip (210) may have a first side (210s1), a second side (210s2), a third side, and a fourth side. The second side (210s2) of the first upper semiconductor chip (210) may be adjacent to the first side (210s1). The third side of the first upper semiconductor chip (210) may be opposite to the first side (210s1). The fourth side of the first upper semiconductor chip (210) may be opposite to the second side (210s2). The first side (210s1) and the third side of the first upper semiconductor chip (210) may be parallel to the second direction (D2). The second side (210s2) and the fourth side of the first upper semiconductor chip (210) may be parallel to the first direction (D1).

[0026] The first upper semiconductor chip (210) can be shifted in a fourth direction (D4) from the lower semiconductor chip (100). Accordingly, the first upper semiconductor chip (210) can expose the first lower pads (111) and the second lower pads (112).

[0027] The first upper semiconductor chip (210) may have a mounting area (R30), a first overhang area (R10), a second overhang area (R20), and a corner overhang area (COR1) in a planar view. The mounting area (R30) of the first upper semiconductor chip (210) may overlap with the lower semiconductor chip (100) in a planar view. The mounting area (R30) of the first upper semiconductor chip (210) may be named the first mounting area.

[0028] From a planar perspective, the first overhang region (R10) of the first upper semiconductor chip (210) may be spaced apart from the lower semiconductor chip (100). The first overhang region (R10) of the first upper semiconductor chip (210) may be provided between the first side (100s1) of the lower semiconductor chip (100) and the first side (210s1) of the first upper semiconductor chip (210). The second overhang region (R20) of the second upper semiconductor chip (220) may be spaced apart from the lower semiconductor chip (100). The second overhang region (R20) of the second upper semiconductor chip (220) may be provided between the second side (100s2) of the lower semiconductor chip (100) and the second side (210s2) of the second upper semiconductor chip (220).

[0029] From a planar perspective, the corner overhang region (COR1) of the first upper semiconductor chip (210) is spaced apart from the lower semiconductor chip (100) and may be adjacent to the corner of the first upper semiconductor chip (210). The corner of the first upper semiconductor chip (210) may be the part where the first side (210s1) and the second side (210s2) of the first upper semiconductor chip (210) meet. The corner overhang region (COR1) of the first upper semiconductor chip (210) may be provided between the first overhang region (R10) and the second side (210s2) of the first upper semiconductor chip (210), and between the second overhang region (R20) and the first side (210s1) of the first upper semiconductor chip (210). A corner overhang region (COR1) of the first upper semiconductor chip (210) may be provided between a virtual extension line of the first side (100s1) of the lower semiconductor chip (100) and the first side (210s1) of the first upper semiconductor chip (210), and between a virtual extension line of the second side (100s2) of the lower semiconductor chip (100) and the second side (210s2) of the first upper semiconductor chip (210). The corner overhang region (COR1) of the first upper semiconductor chip (210) may be named the first corner overhang region.

[0030] The first upper semiconductor chip (210) may include first upper integrated circuits and upper pads. The first upper integrated circuits may be provided within the first upper semiconductor chip (210). The upper pads may include first upper pads (211) and second upper pads (212). The first upper pads (211) and the second upper pads (212) may be chip pads and / or rewiring pads of the first upper semiconductor chip (210). The first lower pads (111) and the second lower pads (112) are provided on the upper surface of the first upper semiconductor chip (210) and may be electrically connected to the lower integrated circuits.

[0031] The first upper pads (211) may be provided on the first overhang region (R10) of the first upper semiconductor chip (210). They may be adjacent to the first side (210s1) of the first upper semiconductor chip (210). The first upper pads (211) may be aligned along the second direction (D2). The second upper pad (212) may be provided on the first overhang region (R10) of the first upper semiconductor chip (210). The second upper pad (212) may be adjacent to the second side (210s2) of the first upper semiconductor chip (210). The second upper pad (212) may be provided in plurality, and the plurality of second upper pads (212) may be aligned along the first direction (D1). As the second upper pad (212) is provided, the first upper pads (211) may not be provided on the corner overhang region (COR1) of the first upper semiconductor chip (210). Unlike what is illustrated, the first upper semiconductor chip (210) may include a single number of second upper pads (212). Hereinafter, for convenience, a plurality of second upper pads (212) are described, but the present invention is not limited thereto.

[0032] The number of second upper pads (212) may be smaller than the number of first upper pads (211). For example, the number of second upper pads (212) may be 1% to 50% of the number of first upper pads (211). The spacing between the second upper pads (212) may be the same as or different from the spacing between the first upper pads (211). The size of the second upper pads (212) may be substantially the same as the size of the first upper pads (211), but is not limited thereto. The first and second upper pads (211, 212) may comprise a metal such as aluminum, copper, nickel, and / or an alloy thereof.

[0033] Placing the first upper semiconductor chip (210) may include preparing a first upper semiconductor chip (210) of the same type as the lower semiconductor chip (100), rotating the first semiconductor chip (310) symmetrically 180 degrees with respect to the lower semiconductor chip (100), and shifting the first upper semiconductor chip (210) with respect to the lower semiconductor chip (100). Accordingly, the number and size of the first upper pads (211) of the first upper semiconductor chip (210) may be substantially the same as the number and size of the first lower pads (111) of the lower semiconductor chip (100), respectively. The number and size of the second upper pads (212) may be substantially the same as the number and size of the second lower pads (112) of the lower semiconductor chip (100), respectively. However, the present invention is not limited thereto.

[0034] Second bonding wires (BW2) may be provided on the upper surface of the first upper semiconductor chip (210). The second bonding wires (BW2) may be connected to the second substrate pads (512) and the first and second upper pads (211, 212). Accordingly, the first upper semiconductor chip (210) may be electrically connected to the substrate (500) through the second bonding wires (BW2). The second bonding wires (BW2) may be spaced apart from the lower semiconductor chip (100) and may be electrically isolated. The second bonding wires (BW2) may include a metal such as gold (Au).

[0035] In the process of forming the second bonding wires (BW2), the ends of the second bonding wires (BW2) may come into contact with the first upper pads (211). Accordingly, pressure or force may be applied to the upper surface of the first upper semiconductor chip (210). When the first upper pads (211) are placed on the upper surface of the corner overhang region (COR1) of the first upper semiconductor chip (210), the first upper pads (211) of the corner overhang region (COR1) of the first upper semiconductor chip (210) may be aligned in a second direction (D2) with the first upper pads (211) of the first overhang region (R10). From a planar perspective, the gap between the lower semiconductor chip (100) and the first upper pads (211) on the first overhang region (R10) of the first upper semiconductor chip (210) may be relatively small. From a planar perspective, the gap between the first upper pads (211) and the lower semiconductor chip (100) on the corner overhang region (COR1) of the first upper semiconductor chip (210) may be larger than the gap between the first upper pads (211) and the lower semiconductor chip (100) on the first overhang region (R10) of the first upper semiconductor chip (210). Accordingly, in the process of forming the second bonding wires (BW2), it may be difficult for the lower semiconductor chip (100) to sufficiently support the first upper pads (211) on the corner overhang region (COR1) of the second upper semiconductor chip (220). During the formation process of the second bonding wires (BW2), the corner overhang region (COR1) of the first upper semiconductor chip (210) may be bent downward by the force applied to the first upper pads (211) on the corner overhang region (COR1) of the first upper semiconductor chip (210), and the corner overhang region (COR1) of the first upper semiconductor chip (210) may be damaged. For example, a crack may occur on the corner overhang region (COR1) of the first upper semiconductor chip (210).

[0036] According to the embodiments, since the second upper pads (212) are provided, the first upper pads (211) and the second bonding wires (BW2) may not be provided on the corner overhang region (COR1) of the first upper semiconductor chip (210). Accordingly, cracks are prevented from occurring on the corner overhang region (COR1) of the first upper semiconductor chip (210), and the reliability and durability of the first upper semiconductor chip (210) can be improved.

[0037] From a planar perspective, the gap between the second upper pads (212) and the lower semiconductor chip (100) may be substantially the same as the gap between the first upper pads (211) and the lower semiconductor chip (100). In the process of forming the second bonding wires (BW2), the first overhang region (R10) and the second overhang region (R20) of the first upper semiconductor chip (210) may not be bent. Accordingly, the occurrence of cracks on the first overhang region (R10) and the second overhang region (R20) of the first upper semiconductor chip (210) may be prevented.

[0038] The second overhang region (R20) of the first upper semiconductor chip (210) may include a first pad region (PR1) and a first blank region (BR1). The first blank region (BR1) of the first upper semiconductor chip (210) may be adjacent to the third side of the first upper semiconductor chip (210) in a planar view. The first blank region (BR1) of the first upper semiconductor chip (210) may be provided between a second imaginary line and the third side of the first upper semiconductor chip (210). The second imaginary line may pass through the midpoint of the second side (210s2) of the first upper semiconductor chip (210) and may be parallel to the second direction (D2). The first pad region (PR1) of the first upper semiconductor chip (210) may be provided between the first blank region (BR1) and the corner overhang region (COR1) of the first upper semiconductor chip (210). A first pad region (PR1) of the first upper semiconductor chip (210) may be provided between the second virtual line and the corner overhang region (COR1). Second upper pads (212) may be provided on the first pad region (PR1) of the first upper semiconductor chip (210) but may not be provided on the first blank region (BR1). Accordingly, the bonding process between the second bonding wires (BW2) and the first upper pads (211) and the bonding process between the second bonding wires (BW2) and the second upper pads (212) can be easily performed.

[0039] The first upper semiconductor chip (210) may not include metal pads on its lower surface. The second bonding wires (BW2) may not be provided on the lower surface of the first upper semiconductor chip (210).

[0040] As shown in FIGS. 1b and 1d, the semiconductor package (1) may further include a second upper semiconductor chip (220). The second upper semiconductor chip (220) may be placed on the upper surface of the first upper semiconductor chip (210). The second upper semiconductor chip (220) may include a memory chip, for example, such as a DRAM. As another example, the second upper semiconductor chip (220) may be, for example, a logic chip or a buffer chip. The second upper semiconductor chip (220) may be a chip of the same type as the first upper semiconductor chip (210). The second upper semiconductor chip (220) may have the same size and the same storage capacity as the first upper semiconductor chip (210). As another example, the second upper semiconductor chip (220) may be a chip of a different type from the first upper semiconductor chip (210) and may have a different size from the first upper semiconductor chip (210).

[0041] The second upper semiconductor chip (220) may have a first side (220s1), a second side (220s2), a third side, and a fourth side. The second side (220s2) of the second upper semiconductor chip (220) may be adjacent to the first side (220s1). The third side of the second upper semiconductor chip (220) may be opposite to the first side (220s1). The fourth side of the second upper semiconductor chip (220) may be opposite to the second side (220s2). The first side (220s1) and the third side of the second upper semiconductor chip (220) may be parallel to the second direction (D2). The second side (220s2) and the fourth side of the second upper semiconductor chip (220) may be parallel to the first direction (D1).

[0042] The second upper semiconductor chip (220) can be shifted in the opposite direction of the fourth direction (D4) from the first upper semiconductor chip (210). Accordingly, the second upper semiconductor chip (220) can expose the first upper pads (211) and the second upper pads (212).

[0043] From a planar perspective, the second upper semiconductor chip (220) may have a mounting area (R31), a first overhang area (R11), a second overhang area (R21), and a corner overhang area (COR2). The mounting area (R31) of the second upper semiconductor chip (220) may overlap with the first upper semiconductor chip (210). The mounting area (R31) of the second upper semiconductor chip (220) may be named the second mounting area. The first overhang area (R11) of the second upper semiconductor chip (220) may be spaced apart from the first upper semiconductor chip (210) from a planar perspective. The first overhang area (R11) of the second upper semiconductor chip (220) may be adjacent to the first side (220s1) of the second upper semiconductor chip (220). For example, the first overhang region (R11) of the second upper semiconductor chip (220) may be provided between the third side of the first upper semiconductor chip (210) and the first side (220s1) of the second upper semiconductor chip (220). The first overhang region (R11) of the second upper semiconductor chip (220) may be named the third overhang region. The second overhang region (R21) of the second upper semiconductor chip (220) may be spaced apart from the first upper semiconductor chip (210) in a planar view. The second overhang region (R21) of the second upper semiconductor chip (220) may be adjacent to the second side (220s2) of the second upper semiconductor chip (220). For example, the second overhang region (R21) of the second upper semiconductor chip (220) may be provided between the fourth side of the first upper semiconductor chip (210) and the second side (220s2) of the second upper semiconductor chip (220). The second overhang region (R21) of the second upper semiconductor chip (220) may be named the fourth overhang region.

[0044] The corner overhang region (COR2) of the second upper semiconductor chip (220) is spaced apart from the first upper semiconductor chip (210) in a planar view and may be adjacent to the corner of the second upper semiconductor chip (220). The corner of the second upper semiconductor chip (220) may be the part where the first side (220s1) and the second side (220s2) of the second upper semiconductor chip (220) meet. The corner overhang region (COR2) of the second upper semiconductor chip (220) may be provided between the first overhang region (R11) and the second side (220s2) of the second upper semiconductor chip (220), and between the second overhang region (R21) and the first side (220s1) of the second upper semiconductor chip (220). The corner overhang region (COR2) of the second upper semiconductor chip (220) may be provided between the virtual extension line of the third side of the first upper semiconductor chip (210) and the first side (220s1) of the second upper semiconductor chip (220), and between the virtual extension line of the fourth side of the first upper semiconductor chip (210) and the second side (220s2) of the second upper semiconductor chip (220). The corner overhang region (COR2) of the second upper semiconductor chip (220) may be named the second corner overhang region.

[0045] The second upper semiconductor chip (220) may include second upper integrated circuits and conductive pads. The second upper integrated circuits may be provided within the second upper semiconductor chip (220). The conductive pads may include first conductive pads (221) and second conductive pads (222). The first conductive pads (221) and the second conductive pads (222) are provided on the upper surface of the second upper semiconductor chip (220) and may be electrically connected to the second upper integrated circuits. The first conductive pads (221) and the second conductive pads (222) may be chip pads and / or rewiring pads of the second upper semiconductor chip (220). The first conductive pads (221) may be provided on the upper surface of the first overhang region (R11) of the second upper semiconductor chip (220). The first conductive pads (221) may be aligned along the second direction (D2). A second conductive pad (222) may be provided on the upper surface of the second overhang region (R21) of the second upper semiconductor chip (220). A plurality of second conductive pads (222) may be provided, and a plurality of second conductive pads (222) may be aligned along a first direction (D1). As the second conductive pad (222) is provided, the first conductive pads (221) may not be provided on the corner region (CR) of the second upper semiconductor chip (220).

[0046] The spacing between the second conductive pads (222) may be the same as or different from the spacing between the first conductive pads (221). The size of the second conductive pad (222) may be substantially the same as the size of the first conductive pads (211), but is not limited thereto. The first and second conductive pads (221, 222) may comprise a metal such as aluminum, copper, nickel, and / or an alloy thereof. Unlike what is illustrated, the second upper semiconductor chip (220) may comprise a singular number of second conductive pads (222). For convenience of explanation, a plurality of second conductive pads (222) are described below, but the present invention is not limited thereto.

[0047] Placing the second upper semiconductor chip (220) may include preparing a second upper semiconductor chip (220) of the same type as the first upper semiconductor chip (210), rotating the second semiconductor chip (320) symmetrically with respect to the first upper semiconductor chip (210) by 180 degrees, and shifting the second upper semiconductor chip (220) with respect to the first upper semiconductor chip (210). Accordingly, the number and size of the first conductive pads (221) of the second upper semiconductor chip (220) may be substantially the same as the number and size of the first upper pads (211) of the first upper semiconductor chip (210). The number and size of the second conductive pads (222) may be substantially the same as the number and size of the second upper pads (212), respectively. However, the present invention is not limited thereto.

[0048] Third bonding wires (BW3) may be provided on the upper surface of the second upper semiconductor chip (220). The first and second conductive pads (221, 222) may be connected to the third substrate pads (513) through the third bonding wires (BW3). Accordingly, the second upper semiconductor chip (220) may be electrically connected to the substrate (500). The third bonding wires (BW3) may be spaced apart from the lower semiconductor chip (100) and the first upper semiconductor chip (210), and may be electrically isolated from the lower semiconductor chip (100) and the first upper semiconductor chip (210). The third bonding wires (BW3) may include a metal such as gold (Au).

[0049] In the process of forming the second bonding wires (BW2), the ends of the third bonding wires (BW3) may come into contact with the first conductive pads (221). When the first conductive pads (221) are placed on the upper surface of the corner overhang region (COR2) of the first upper semiconductor chip (210), the corner overhang region (COR2) of the second upper semiconductor chip (220) may bend downward during the process of forming the third bonding wires (BW3). In this case, the corner overhang region (COR2) of the second upper semiconductor chip (220) may be damaged. For example, damage to the corner overhang region (COR2) of the second upper semiconductor chip (220) may include the formation of a crack.

[0050] According to the embodiments, the second upper pads (212) and the third bonding wires (BW3) may not be provided on the corner overhang region (COR2) of the first upper semiconductor chip (210). Accordingly, damage to the corner overhang region (COR2) of the second upper semiconductor chip (220) is prevented, and the reliability and durability of the second upper semiconductor chip (220) may be improved.

[0051] From a planar perspective, the gap between the second conductive pads (222) and the lower semiconductor chip (100) may be substantially the same as the gap between the first conductive pads (221) and the lower semiconductor chip (100). In the process of forming the third bonding wires (BW3), the first overhang region (R11) and the second overhang region (R21) of the second upper semiconductor chip (220) may not be bent. Accordingly, the occurrence of cracks on the first overhang region (R11) and the second overhang region (R21) of the first upper semiconductor chip (210) may be further prevented.

[0052] The second overhang region (R20) of the second upper semiconductor chip (220) may include a second pad region (PR2) and a second blank region (BR2) in a planar view. The second blank region (BR2) of the second upper semiconductor chip (220) may be adjacent to the third side of the second upper semiconductor chip (220) in a planar view. The second blank region (BR2) may be provided between a third imaginary line and the third side of the second upper semiconductor chip (220). The third imaginary line may pass through the midpoint of the second side (220s2) of the second upper semiconductor chip (220) and may be parallel to the second direction (D2). The second pad region (PR2) of the second upper semiconductor chip (220) may be provided between the second blank region (BR2) and the corner overhang region (COR2) of the second upper semiconductor chip (220). The second pad region (PR2) of the second upper semiconductor chip (220) may be provided between the third virtual line and the corner overhang region (COR3) of the second upper semiconductor chip (220). The second conductive pads (222) may be provided on the second pad region (PR2) of the second upper semiconductor chip (220) but may not be provided on the second blank region (BR2). Accordingly, the bonding process between the third bonding wires (BW3) and the first and second conductive pads (221, 222) can be easily performed.

[0053] As shown in FIG. 1d, the first substrate pads (511) can be provided between the lower semiconductor chip (100) and the third substrate pads (513). Accordingly, the third bonding wires (BW3) can be spaced apart from the first bonding wires (BW1). An electrical short circuit between the first bonding wires (BW1) and the third bonding wires (BW3) can be prevented.

[0054] The second upper semiconductor chip (220) may not include metal pads on the lower surface. The third bonding wires (BW3) may not be provided on the lower surface of the second upper semiconductor chip (220).

[0055] Referring to FIGS. 1a, 1b, and 1d, the second upper semiconductor chip (220) may overlap with the lower semiconductor chip (100) in a planar view. The number and arrangement of the first conductive pads (221) may be substantially the same as the number and arrangement of the first lower pads (111). The number and arrangement of the second conductive pads (222) may be substantially the same as the number and arrangement of the second lower pads (112). However, the present invention is not limited thereto. As shown in FIGS. 1d through 1f, the sides of the second upper semiconductor chip (220) may be vertically aligned with the side walls of the lower semiconductor chip (100). In this specification, "vertical" may mean parallel to the third direction (D3).

[0056] As shown in FIG. 1c and FIG. 1d, the semiconductor package (1) may further include a third upper semiconductor chip (230). The third upper semiconductor chip (230) may be disposed on the upper surface of the second upper semiconductor chip (220). The third upper semiconductor chip (230) may include a memory chip, for example, a DRAM. As another example, the second upper semiconductor chip (220) may be, for example, a logic chip or a buffer chip.

[0057] The third upper semiconductor chip (230) may have a first side (230s1), a second side (230s2), a third side, and a fourth side. The second side (230s2) of the third upper semiconductor chip (230) may be adjacent to the first side (230s1). The third side of the third upper semiconductor chip (230) may be opposite to the first side (230s1). The fourth side of the third upper semiconductor chip (230) may be opposite to the second side (230s2). The first side (230s1) and the third side of the third upper semiconductor chip (230) may be parallel to the second direction (D2). The second side (230s2) and the fourth side of the third upper semiconductor chip (230) may be parallel to the first direction (D1).

[0058] The third upper semiconductor chip (230) can be shifted in the opposite direction of the fourth direction (D4) from the second upper semiconductor chip (220). Accordingly, the third upper semiconductor chip (230) can expose the first conductive pads (211) and the second conductive pads (212).

[0059] From a planar perspective, the third upper semiconductor chip (230) may have a mounting area (R32), a first overhang area (R12), a second overhang area (R22), and a corner overhang area (COR3). The mounting area (R32) of the third upper semiconductor chip (230) may overlap with the second upper semiconductor chip (220). The first overhang area (R12) of the third upper semiconductor chip (230) may be spaced apart from the second upper semiconductor chip (220). From a planar perspective, the first overhang area (R12) of the third upper semiconductor chip (230) may be provided between the third side of the second upper semiconductor chip (220) and the first side (230s1) of the third upper semiconductor chip (230). The second overhang area (R22) of the third upper semiconductor chip (230) may be spaced apart from the second upper semiconductor chip (220). The second overhang region (R22) of the third upper semiconductor chip (230) may be provided between the fourth side of the second upper semiconductor chip (220) and the second side (230s2) of the third upper semiconductor chip (230).

[0060] From a planar perspective, the corner overhang region (COR3) of the third upper semiconductor chip (230) is spaced apart from the second upper semiconductor chip (220) and may be adjacent to the corner of the third upper semiconductor chip (230). At the corner of the third upper semiconductor chip (230), the third side and the fourth side of the third upper semiconductor chip (230) may meet. The corner overhang region (COR3) of the third upper semiconductor chip (230) may be provided between the first overhang region (R12) and the second side (230s2) of the third upper semiconductor chip (230), and between the second overhang region (R22) and the first side (230s1) of the third upper semiconductor chip (230). The corner overhang region (COR3) of the third upper semiconductor chip (230) may be provided between the virtual extension line of the third side of the second upper semiconductor chip (220) and the first side (230s1) of the third upper semiconductor chip (230), and between the virtual extension line of the fourth side of the second upper semiconductor chip (220) and the second side (230s2) of the third upper semiconductor chip (230).

[0061] The third upper semiconductor chip (230) may include third upper integrated circuits, first bonding pads (231), and second bonding pads (232). The third upper integrated circuits may be provided within the third upper semiconductor chip (230). The first bonding pads (231) and the second bonding pad (232) may be provided on the upper surface of the third upper semiconductor chip (230) and may be electrically connected to the third upper integrated circuits. The first bonding pads (231) and the second bonding pad (232) may be chip pads or rewiring pads of the third upper semiconductor chip (230). The first bonding pads (231) may be provided on the upper surface of the first overhang region (R12) of the third upper semiconductor chip (230). The first bonding pads (231) may be adjacent to the first side (230s1) of the third upper semiconductor chip (230) and aligned along the second direction (D2). The second bonding pad (232) may be provided on the upper surface of the second overhang region (R22) of the third upper semiconductor chip (230). For example, the second bonding pad (232) may be provided in multiple numbers, and the multiple second bonding pads (232) may be aligned along the first direction (D1). As the second bonding pad (232) is provided, the first bonding pads (231) may not be provided on the corner overhang region (COR3) of the third upper semiconductor chip (230). The number of the second bonding pads (232) may be smaller than the number of the first bonding pads (231). For example, the number of second bonding pads (232) may be 1% to 50% of the number of first bonding pads (231). Unlike what is illustrated, the third upper semiconductor chip (230) may include a single number of second bonding pads (232). Hereinafter, for convenience, a plurality of second bonding pads (232) are described, but the present invention is not limited thereto.

[0062] The spacing between the second bonding pads (232) may be the same as or different from the spacing between the first bonding pads (231). The size of the second bonding pads (232) may be substantially the same as the size (231) of the first bonding pads, but is not limited thereto. The first and second bonding pads (231, 232) may comprise a metal such as aluminum, copper, nickel, and / or an alloy thereof.

[0063] The third upper semiconductor chip (230) may be a chip of the same type as the second upper semiconductor chip (220). The third upper semiconductor chip (230) may have the same size and the same storage capacity as the second upper semiconductor chip (220). Placing the third upper semiconductor chip (230) may include preparing a third upper semiconductor chip (230) of the same type as the second upper semiconductor chip (220), rotating the third upper semiconductor chip (230) 180 degrees symmetrically with respect to the second upper semiconductor chip (220), and shifting the third upper semiconductor chip (230) with respect to the second upper semiconductor chip (220). Accordingly, the number and size of the first bonding pads (231) of the third upper semiconductor chip (230) may be substantially the same as the number and size of the first conductive pads (221) of the second upper semiconductor chip (220), respectively. The number and size of the second bonding pads (232) may be substantially the same as the number and size of the second conductive pads (222), respectively. As another example, the third upper semiconductor chip (230) may be a different type of chip from the second upper semiconductor chip (220) and may have a different size from the second upper semiconductor chip (220).

[0064] Referring to FIGS. 1b through 1f, the third upper semiconductor chip (230) may overlap with the first upper semiconductor chip (210) in a planar view. The number and arrangement of the first bonding pads (231) may be substantially the same as the number and arrangement of the first upper pads (211). The number and arrangement of the second bonding pads (232) may be substantially the same as the number and arrangement of the second upper pads (212). However, the present invention is not limited thereto. As shown in FIGS. 1d through 1f, the sides of the third upper semiconductor chip (230) may be vertically aligned with the side walls of the first upper semiconductor chip (210).

[0065] Fourth bonding wires (BW4) may be provided on the upper surface of the third upper semiconductor chip (230). The fourth bonding wires (BW4) may be connected to the fourth substrate pads (514) and the first and second bonding pads (231, 232). Accordingly, the third upper semiconductor chip (230) may be electrically connected to the substrate (500). The fourth bonding wires (BW4) may be spaced apart from the lower semiconductor chip (100), the first upper semiconductor chip (210), and the second upper semiconductor chip (220). The fourth bonding wires (BW4) may include a metal such as gold (Au).

[0066] According to the embodiments, the first bonding pads (231) and the fourth bonding wires (BW4) may not be provided on the corner overhang region (COR3) of the third upper semiconductor chip (230). Accordingly, damage to the corner overhang region (COR3) of the third upper semiconductor chip (230) is prevented, and the reliability and durability of the third upper semiconductor chip (230) may be improved.

[0067] From a planar perspective, the gap between the second bonding pads (232) and the second upper semiconductor chip (220) may be substantially the same as the gap between the first bonding pads (231) and the second upper semiconductor chip (220). In the process of forming the fourth bonding wires (BW4), the first overhang region (R12) and the second overhang region (R22) of the third upper semiconductor chip (230) may not be bent. Accordingly, the occurrence of cracks on the first overhang region (R12) and the second overhang region (R22) of the third upper semiconductor chip (230) may be further prevented.

[0068] As shown in FIG. 1c, the second overhang region (R22) of the third upper semiconductor chip (230) may include a third pad region (PR3) and a third blank region (BR3) in a planar view. The third blank region (BR3) of the third upper semiconductor chip (230) may be adjacent to the third side of the third upper semiconductor chip (230) in a planar view. The third blank region (BR3) may be provided between the fourth imaginary line of the third upper semiconductor chip (230) and the third side of the third upper semiconductor chip (230). The fourth imaginary line may pass through the midpoint of the second side (230s2) and be parallel to the second direction (D2). The third pad region (PR3) of the third upper semiconductor chip (230) may be provided between the third blank region (BR3) and the corner overhang region (COR3) of the third upper semiconductor chip (230). The third pad region (PR3) may be provided between the fourth virtual line and the corner overhang region (COR3) of the third upper semiconductor chip (230). The second bonding pads (232) may be provided on the third pad region (PR3) of the third upper semiconductor chip (230) but may not be provided on the third blank region (BR3). Accordingly, the bonding process of the fourth bonding wires (BW4) and the first and second bonding pads (231, 232) can be easily performed.

[0069] As shown in FIG. 1d, the second substrate pads (512) can be provided between the lower semiconductor chip (100) and the fourth substrate pads (514). Accordingly, the fourth bonding wires (BW4) are spaced apart from the second bonding wires (BW2), and an electrical short circuit between the second bonding wires (BW2) and the fourth bonding wires (BW4) can be prevented.

[0070] The third upper semiconductor chip (230) may not include metal pads on the lower surface. The fourth bonding wires (BW4) may not be provided on the lower surface of the third upper semiconductor chip (230).

[0071] The semiconductor package (1) may further include a molding film (400). The molding film (400) is provided on the upper surface of the substrate (500) to cover the lower semiconductor chip (100), the first upper semiconductor chip (210), the second upper semiconductor chip (220), and the third upper semiconductor chip (230). The molding film (400) may seal the first to fourth bonding wires (BW1, BW2, BW3, BW4). The outer walls of the molding film (400) may be vertically aligned with the side walls of the substrate (500). The molding film (400) may include an insulating polymer such as an epoxy-based molding compound.

[0072] The semiconductor package (1) may further include adhesive layers (410). The adhesive layers (410) may be provided on the lower surface of the lower semiconductor chip (100), the lower surface of the first upper semiconductor chip (210), the lower surface of the second upper semiconductor chip (220), and the lower surface of the third upper semiconductor chip (230). The adhesive layers (410) may be die attach films. The adhesive layers (410) may include, for example, an insulating polymer. The adhesive layers (410) may include a material different from the molding film (400).

[0074] FIG. 2a is a cross-section of a semiconductor package according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1a, line I-I' of FIG. 1b, and line I-I' of FIG. 1c. FIG. 2b is a drawing for explaining a semiconductor package according to embodiments, corresponding to a cross-section cut along line II-II' of FIG. 1a, line II-II' of FIG. 1b, and line II-II' of FIG. 1c. FIG. 2c is a drawing for explaining a semiconductor package according to embodiments, corresponding to a cross-section cut along line III-III' of FIG. 1a, line III-III' of FIG. 1b, and line III-III' of FIG. 1c. Hereinafter, in the description of FIG. 2a to 2c, FIG. 1a to 1c will be referred to together.

[0075] Referring to FIGS. 2a to 2c, a semiconductor package (1A) may include a substrate (500), solder balls (600), a lower semiconductor chip (100), a plurality of first upper semiconductor chips (210), a plurality of second upper semiconductor chips (220), a third upper semiconductor chip (230), first bonding wires (BW1), second bonding wires (BW2), third bonding wires (BW3), fourth bonding wires (BW4), a molding film (400), and adhesive layers (410). The substrate (500), solder balls (600), lower semiconductor chip (100), first to third upper semiconductor chips (210, 220, 230), first to fourth bonding wires (BW1, BW2, BW3, BW4), molding film (400), and adhesive layers (410) may be substantially the same as those described above in the examples of FIGS. 1a to 1e.

[0076] However, the semiconductor package (1A) may include a plurality of first upper semiconductor chips (210) and a plurality of second upper semiconductor chips (220). The first upper semiconductor chips (210) and the second upper semiconductor chips (220) may be stacked alternately with each other. Second bonding wires (BW2) may be disposed on the second upper semiconductor chips (220) to be connected to the first upper pads (211) and the second upper pads (212). Third bonding wires (BW3) may be disposed on the third upper semiconductor chip (230) to be connected to the first conductive pads (221) and the second conductive pads (222).

[0077] The number of first upper semiconductor chips (210) and the number of second upper semiconductor chips (220) can be varied. For example, the semiconductor package (1A) may include a single first upper semiconductor chip (210) but may not include second upper semiconductor chips (220) and third upper semiconductor chips (230).

[0079] FIG. 3a is a plan view illustrating the arrangement of a first upper semiconductor chip and a second upper semiconductor chip according to embodiments. FIG. 3b is a plan view illustrating the arrangement of a first upper semiconductor chip and a second upper semiconductor chip according to embodiments. Hereinafter, descriptions that overlap with those previously described are omitted.

[0080] Referring to FIGS. 3a and 3b, a second upper semiconductor chip (220) may be provided on a first upper semiconductor chip (210). The first upper semiconductor chip (210) may include first upper pads (211) and second upper pads (212). The second upper semiconductor chip (220) may include first conductive pads (221) and second conductive pads (222). For example, the second upper semiconductor chip (220) may be a semiconductor chip of a different type from the first upper semiconductor chip (210). The arrangement of the second conductive pads (222) may differ from the arrangement of the second upper pads (212).

[0081] As shown in FIG. 3a, the spacing (A2) between the second conductive pads (222) may differ from the spacing (A1) between the second upper pads (212). The spacing (A2) between the second conductive pads (222) may be smaller than the spacing (A1) between the second upper pads (212). Unlike what is shown, the spacing (A2) between the second conductive pads (222) may be larger than the spacing (A1) between the second upper pads (212).

[0082] As shown in FIG. 3b, the number of second conductive pads (222) may differ from the number of second upper pads (212). For example, the number of second conductive pads (222) may be greater than the number of second upper pads (212). Unlike what is shown, the number of second conductive pads (222) may be smaller than the number of second upper pads (212).

[0083] Unlike FIGS. 3a and 3b, the arrangement of the first conductive pads (221) may differ from the arrangement of the first upper pads (211). For example, the spacing between the first conductive pads (221) may differ from the spacing between the first upper pads (211). Or the number of the first conductive pads (221) may differ from the number of the first upper pads (211).

[0085] The arrangement of the second upper pads (212) and the second conductive pads (222) in FIGS. 3a and 3b may be applied to the arrangement of the second lower pads (112) and the second upper pads (212) described in the example of FIG. 1a, or to the arrangement of the second conductive pads (222) and the second bonding pads (232) in FIG. 1c. For example, the spacing between the second lower pads (112) in FIG. 1a may be different from the spacing between the second upper pads (212), or the number between the second lower pads (112) may be different from the number of the second upper pads (212). The spacing between the second conductive pads (222) in FIG. 1c may be different from the spacing between the second bonding pads (232), or the number between the second conductive pads (222) may be different from the number of the second bonding pads (232).

[0087] FIG. 4a is a plan view of a semiconductor package according to embodiments. FIG. 4b is a plan view of a first semiconductor chip according to embodiments. FIG. 4c is a plan view of a second semiconductor chip according to embodiments. FIG. 4d is a cross-section cut along the line A-A' of FIG. 4a. FIG. 4e is a cross-section cut along the line B-B' of FIG. 4a. FIG. 4f is a cross-section cut along the line C-C' of FIG. 4a.

[0088] Referring to FIGS. 4a through 4f, the semiconductor package (2) may include a substrate (500), solder balls (600), a first semiconductor chip (310), a second semiconductor chip (320), first bonding wires (BW1'), second bonding wires (BW2'), a molding film (400), and adhesive layers (410). The substrate (500), solder balls (600), molding film (400), and adhesive layer (410) may be substantially the same as those described in the examples of FIGS. 1a through 1e. The substrate (500) may include first substrate pads (511) and second substrate pads (512).

[0089] A first semiconductor chip (310) may be placed on a substrate (100). The first semiconductor chip (210) may be similar to the lower semiconductor chip (100) described in the examples of FIGS. 1a to 1e. For example, the first semiconductor chip (310) may be a memory chip. As another example, the first semiconductor chip (310) may be a logic chip or a buffer chip.

[0090] As shown in FIG. 4b, the first semiconductor chip (310) may have a first side (310s1), a second side (310s2), a third side (310s3), and a fourth side (310s4). The second side (310s2) of the first semiconductor chip (310) may be opposite to the first side (310s1). The third side (310s3) of the first semiconductor chip (310) may be adjacent to the first side (310s1). The fourth side (310s4) of the first semiconductor chip (310) may be opposite to the third side (310s3). The first side (310s1) and the second side (310s2) of the first semiconductor chip (310) may be parallel to the first direction (D1). The third side (310s3) and the fourth side (310s3) of the first semiconductor chip (310) may be parallel to the second direction (D2).

[0091] The first side (310s1) and the second side (310s2) of the first semiconductor chip (310) may be parallel to the short axis direction of the first semiconductor chip (310), and the third side (310s3) and the fourth side (310s3) of the first semiconductor chip (310) may be parallel to the long axis direction of the first semiconductor chip (310). However, the present invention is not limited thereto. For example, unlike what is illustrated, the first semiconductor chip (310) may have a square shape in a planar view.

[0092] The first semiconductor chip (310) may have a first region (R1) and a second region (R2) in a planar view. The first region (R1) of the first semiconductor chip (310) may be adjacent to the first side (310s1) of the first semiconductor chip (310) in a planar view. The second region (RR2) of the second semiconductor chip (320) may be adjacent to the second side (310s2) of the first semiconductor chip (310). The first region (R1) of the first semiconductor chip (310) may be provided between a first virtual centerline and the first side (310s1). The first virtual centerline may connect the midpoint of the third side (310s3) and the midpoint of the fourth side (310s4) of the first semiconductor chip (310). A second region (R2) of the first semiconductor chip (310) may be provided between the first virtual centerline and the second side (310s2). The area of ​​the second region (R2) of the first semiconductor chip (310) may be substantially the same as the area of ​​the first region (R1).

[0093] The first semiconductor chip (310) may include first integrated circuits and first chip pads (311). The first integrated circuits may be provided within the first semiconductor chip (310). The first chip pads (311) may be provided on the upper surface of the first semiconductor chip (310) and may be electrically connected to the first integrated circuits. The first chip pads (311) may be provided on a first region (R1) of the first semiconductor chip (310) but may be spaced apart from a second region (R2). The first chip pads (311) may not be provided on the second region (R2) of the first semiconductor chip (310). The first region (R1) of the first semiconductor chip (310) may be a pad region, and the second region (R2) of the first semiconductor chip (310) may be a blank region.

[0094] The first chip pads (311) may include a first group of first chip pads (311), a second group of first chip pads (311), and a third group of first chip pads (311). Some of the first chip pads (311) (e.g., the first group of first chip pads (311)) may be positioned adjacent to a third side (310s3) on a first region (R1) of the first semiconductor chip (310) and aligned along a second direction (D2). Some of the other first chip pads (311) (e.g., the second group of first chip pads (311)) may be positioned adjacent to a fourth side (310s4) on a first region (R1) of the first semiconductor chip (310) and aligned along a second direction (D2). The remaining of the first chip pads (311) (e.g., the first chip pads (311) of the third group) are arranged adjacent to the first side (310s1) of the first semiconductor chip (310) on the first region (R1) and can be aligned with each other along the first direction (D1).

[0095] The first chip pads (311) may not be placed adjacent to the second side (310s2) of the first semiconductor chip (310). For example, the maximum gap (B1) between the first chip pads (311) and the first side (310s1) of the first semiconductor chip (310) may be smaller than the minimum gap (B2) between the first chip pads (311) and the second side (310s2) of the first semiconductor chip (310).

[0096] As shown in FIG. 4a and FIG. 4, a second semiconductor chip (320) may be placed on the first semiconductor chip (310). The second semiconductor chip (320) may be a memory chip. As another example, the second semiconductor chip (320) may be a logic chip or a buffer chip.

[0097] As shown in FIG. 4c, the second semiconductor chip (320) may have a first sidewall (320s1), a second sidewall (320s2), a third sidewall (320s3), and a fourth sidewall (320s4). The second sidewall (320s2) of the second semiconductor chip (320) may be opposite to the first sidewall (320s1). The third sidewall (320s3) of the second semiconductor chip (320) may be adjacent to the first sidewall (320s1). The fourth sidewall (320s4) of the second semiconductor chip (320) may be opposite to the third sidewall (330s2). The first sidewall (320s1) and the second sidewall (320s2) of the second semiconductor chip (320) may be parallel to the first direction (D1). The third side (320s3) and the fourth side (320s3) of the second semiconductor chip (320) may be parallel to the second direction (D2).

[0098] The first sidewall (320s1) and the second sidewall (320s2) of the second semiconductor chip (320) may be parallel to the short axis direction of the second semiconductor chip (320), and the third sidewall (320s3) and the fourth sidewall (320s4) of the second semiconductor chip (320) may be parallel to the long axis direction of the second semiconductor chip (320), however, the present invention is not limited thereto. For example, the second semiconductor chip (320) may have a square shape in a planar view.

[0099] The second semiconductor chip (320) may have a first region (RR1) and a second region (RR2) in a planar view. The first region (RR1) of the second semiconductor chip (320) may be adjacent to the first sidewall (320s1) of the second semiconductor chip (320). The first region (RR1) of the second semiconductor chip (320) may be provided between the second virtual centerline and the first sidewall (320s1). The second virtual centerline may connect the midpoint of the third sidewall (320s3) and the midpoint of the fourth sidewall (320s4) of the second semiconductor chip (320). The second region (RR2) of the second semiconductor chip (320) may be adjacent to the second sidewall (320s2) of the second semiconductor chip (320). The second region (RR2) of the second semiconductor chip (320) may be provided between the second virtual centerline and the second sidewall (320s2). The area of ​​the second region (RR2) of the second semiconductor chip (320) may be substantially the same as the area of ​​the first region (RR1).

[0100] The second semiconductor chip (320) may include second integrated circuits and second chip pads (321). The second integrated circuits may be provided within the second semiconductor chip (320). The second chip pads (321) may be provided on the upper surface of the second semiconductor chip (320) and may be electrically connected to the second integrated circuits. The second chip pads (321) may be provided on a first region (RR1) of the second semiconductor chip (320) but may be spaced apart from a second region (R2). The second chip pads (321) may not be provided on a second region (RR2) of the second semiconductor chip (320). The first region (RR1) of the second semiconductor chip (320) may include a pad region, and the second region (RR2) of the second semiconductor chip (320) may be a blank region.

[0101] The second chip pads (321) may include a first group of second chip pads (321), a second group of second chip pads (321), and a third group of second chip pads (321). Some of the second chip pads (321) (e.g., the second chip pads (321) of the first group) may be positioned adjacent to the third sidewall (320s3) on the second region (RR2) of the second semiconductor chip (320) and may be aligned along the second direction (D2). Some of the other second chip pads (321) (e.g., the second chip pads (321) of the second group) may be positioned adjacent to the fourth sidewall (320s4) of the second semiconductor chip (320) on the second region (R2) and may be aligned along the second direction (D2). The remaining of the second chip pads (321) (e.g., the second chip pads (321) of the third group) are positioned adjacent to the second sidewall (320s2) of the second semiconductor chip (320) and can be aligned with each other along the second direction (D2).

[0102] The second chip pads (321) may not be adjacent to the first sidewall (320s1) of the second semiconductor chip (320). For example, the maximum gap between the second chip pads (321) and the second sidewall (320s2) of the first semiconductor chip (310) may be smaller than the minimum gap between the second chip pads (321) and the first sidewall (320s1) of the first semiconductor chip (310).

[0103] Unlike what is described, a number of second chip pads (321) may be adjacent to the second side wall (320s2) of the second semiconductor chip (320).

[0104] As shown in FIGS. 4a, 4d, 4e, and 4f, the second semiconductor chip (320) may have the same size as the first semiconductor chip (310). The second semiconductor chip (320) may be a chip of the same type as the first semiconductor chip (310) and may have the same storage capacity. For example, the number of the second chip pads (321) may be the same as the number of the first chip pads (311). The size of the second chip pads (321) may be substantially the same as the size of the first chip pads (311). However, the present invention is not limited thereto.

[0105] The second semiconductor chip (320) may be stacked on the upper surface of the first semiconductor chip (310). The first region (RR1) of the second semiconductor chip (320) may overlap with the second region (R2) of the first semiconductor chip (310) and may be spaced apart from the first region (R1) of the first semiconductor chip (310). The second region (RR2) of the second semiconductor chip (320) may overlap with the first region (R1) of the first semiconductor chip (310) and may be spaced apart from the second region (R2) of the first semiconductor chip (310). Accordingly, the second chip pads (321) may not overlap with the first chip pads (311) in a planar view. In a planar view, the arrangement of the second chip pads (321) may be 180 degrees rotationally symmetric with respect to the arrangement of the first chip pads (311).

[0106] First bonding wires (BW1') may be provided on the upper surface of the first region (R1) of the first semiconductor chip (310). The first bonding wires (BW1') may be connected to the first substrate pads (511) and the first chip pads (311). The first bonding wires (BW1') may be spaced apart from the upper surface of the second region (R2) of the first semiconductor chip (310).

[0107] The second bonding wires (BW2') may be provided on the upper surface of the first region (RR1) of the second semiconductor chip (320). The second bonding wires (BW2') may be connected to the second substrate pads (512) and the second chip pads (321). The second bonding wires (BW2') may be spaced apart from the upper surface of the second region (RR2) of the second semiconductor chip (320). The second bonding wires (BW2') may be spaced apart from the first semiconductor chip (310).

[0108] The closer the second bonding wires (BW2') are placed to the first bonding wires (BW1'), the higher the probability of an electrical short circuit occurring between the first bonding wires (BW1') and the second bonding wires (BW2').

[0109] According to the embodiments, since the second chip pads (321) are spaced apart from the first chip pads (311), the second bonding wires (BW2') can be spaced apart from the first bonding wires (BW1'). The occurrence of an electrical short circuit between the first bonding wires (BW1') and the second bonding wires (BW2') can be prevented. Additionally, since the first region (RR1) of the second semiconductor chip (320) is spaced apart from the first region (R1) of the first semiconductor chip (310), even if some process error occurs during the formation process of the first bonding wires (BW1') or the second bonding wires (BW2'), the second bonding wires (BW2') may not come into contact with the first bonding wires (BW1'). Accordingly, electrical short circuits between the first bonding wires (BW1') and the second bonding wires (BW2') can be further prevented, and the electrical characteristics and reliability of the semiconductor package (2) can be further improved.

[0110] The first sidewall (320s1), second sidewall (320s2), third sidewall (320s3), and fourth sidewall (320s4) of the second semiconductor chip (320) can be vertically aligned with the second side (310s2), first side (310s1), third side (310s3), and fourth side (310s4) of the first semiconductor chip (310), respectively. Since the first region (RR1) of the second semiconductor chip (320) is spaced apart from the second region (R2) of the first semiconductor chip (310), the second semiconductor chip (320) may not be shift-positioned relative to the first semiconductor chip (310). Accordingly, the semiconductor package (2) can be miniaturized.

[0111] Adhesive layers (410) may be provided on the lower surface of the first semiconductor chip (310) and the lower surface of the second semiconductor chip (320). The adhesive layers (410) may be die attach films. Any one of the adhesive layers (410) may be interposed between the first semiconductor chip (310) and the second semiconductor chip (320) and may be relatively thick. Any one of the adhesive layers (410) may further cover the ends of the first bonding wires (BW1').

[0112] A molding film (400) is provided on the upper surface of a substrate (500) to cover a first semiconductor chip (310) and a second semiconductor chip (320). The molding film (400) can seal the first and second bonding wires (BW1', BW2').

[0114] FIGS. 5A, FIGS. 5B, and FIGS. 5C are drawings for illustrating semiconductor packages according to embodiments. FIGS. 5A, FIGS. 5B, and FIGS. 5C correspond to cross-sections cut along the line AA' of FIG. 4A, the line B-B' of FIG. 4A, and the line C-C' of FIG. 4A, respectively.

[0115] Referring to FIGS. 5a through 5c, the semiconductor package (2A) may include a substrate (500), solder balls (600), a plurality of first semiconductor chips (310), a plurality of second semiconductor chips (320), first bonding wires (BW1'), second bonding wires (BW2'), a molding film (400), and adhesive layers (410). The first semiconductor chip (310) and the second semiconductor chip (320) may be substantially the same as those described in the examples of FIGS. 4a through 4f. However, the semiconductor package (2A) may include a plurality of first semiconductor chips (310) and a plurality of second semiconductor chips (320).

[0116] The first semiconductor chips (310) and the second semiconductor chips (320) can be stacked alternately. The first region (RR1) of each of the second semiconductor chips (320) may overlap with the second region (R2) of each of the first semiconductor chips (310) in a planar view and may be spaced apart from the first region (R1) of each of the first semiconductor chips (310). The first chip pads (311) of any one of the first semiconductor chips (310) may overlap with the first chip pads (311) of another of the first semiconductor chips (310) in a planar view. The first chip pads (311) of the first semiconductor chips (310) may be spaced apart from the second chip pads (321) of the second semiconductor chips (320) in a planar view.

[0117] The first sidewall (320s1), second sidewall (320s2), third sidewall (320s3), and fourth sidewall (320s4) of each of the second semiconductor chips (320) can be vertically aligned with the first side (310s1), second side (310s2), third side (310s3), and fourth side (310s4) of each of the first semiconductor chips (310). The first semiconductor chips (310) can be vertically aligned with each other. The second semiconductor chips (320) can be vertically aligned with each other.

[0118] First bonding wires (BW1') may be provided on the upper surface of the first region (R1) of each of the first semiconductor chips (310). The first bonding wires (BW1') may be connected to the first substrate pads (511) and the first chip pads (311).

[0119] Second bonding wires (BW2') may be provided on the upper surface of the first region (RR1) of each of the second semiconductor chips (320). The second bonding wires (BW2') may be connected to the second substrate pads (512) and the second chip pads (321). The second bonding wires (BW2') may be spaced apart from the first semiconductor chip (310) and the first bonding wires (BW1').

[0120] The number of first semiconductor chips (310) and the number of second semiconductor chips (320) can be varied.

[0122] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention.

Claims

Claim 1 A substrate; a lower semiconductor chip on the substrate; a first upper semiconductor chip provided on the upper surface of the lower semiconductor chip and comprising upper pads; and bonding wires connected to the substrate and the upper pads, wherein, in a planar view, the first upper semiconductor chip comprises: a first overhang region spaced apart from the lower semiconductor chip and adjacent to a first side of the first upper semiconductor chip; a second overhang region spaced apart from the lower semiconductor chip and adjacent to a second side of the first upper semiconductor chip; and a first corner overhang region spaced apart from the lower semiconductor chip, wherein the first corner overhang region is adjacent to the corner where the first side and the second side of the first upper semiconductor chip meet, and the upper pads comprise: first upper pads on the upper surface of the first overhang region; A semiconductor package comprising second upper pads on the upper surface of the second overhang region, wherein the number of first upper pads is smaller than the number of second upper pads, and the upper pads are spaced apart from the first corner overhang region of the first upper semiconductor chip, wherein the first overhang region is provided between the first side of the lower semiconductor chip and the first side of the first upper semiconductor chip, the second overhang region is provided between the second side of the lower semiconductor chip and the second side of the first upper semiconductor chip, and the first corner overhang region is provided between the first overhang region and the second side of the first upper semiconductor chip and between the second overhang region and the first side of the first upper semiconductor chip. Claim 2 A semiconductor package according to claim 1, wherein the number of the second upper pads is 1% to 50% of the number of the first upper pads. Claim 3 A semiconductor package according to claim 1, wherein the second overhang region of the first upper semiconductor chip comprises: a blank region adjacent to a third side of the first upper semiconductor chip; and a pad region between the blank region and the first corner overhang region, wherein the second upper pads are provided on the pad region but are spaced apart from the blank region, and the third side of the first upper semiconductor chip is opposite to the first side of the first upper semiconductor chip. Claim 4 In claim 3, the pad region of the first upper semiconductor chip is provided between a virtual line and the first corner overhang region of the first upper semiconductor chip, the virtual line passes through the midpoint of the second side of the first upper semiconductor chip, and the semiconductor package is parallel to the first side of the first upper semiconductor chip. Claim 5 delete Claim 6 In claim 1, the lower semiconductor chip further includes lower pads on its upper surface, and the lower pads are a semiconductor package exposed by the first upper semiconductor chip. Claim 7 In claim 6, the lower semiconductor chip in a planar view comprises: a first edge region adjacent to a third side of the lower semiconductor chip; a second edge region adjacent to a fourth side of the lower semiconductor chip; and a corner region spaced apart from the lower semiconductor chip, wherein the corner region is adjacent to the corner where the third side and the fourth side of the lower semiconductor chip meet, and the lower pads are provided on the first edge region and the second edge region of the lower semiconductor chip, and the semiconductor package spaced apart from the corner region. Claim 8 In claim 7, the lower pads comprise: first lower pads on the upper surface of the first edge region; and second lower pads on the upper surface of the second edge region, wherein the number of the second lower pads is smaller than the number of the first lower pads. Claim 9 A semiconductor package according to claim 1, further comprising a second upper semiconductor chip on the upper surface of the first upper semiconductor chip, wherein, in a planar view, the second upper semiconductor chip comprises: a mounting area overlapping with the first upper semiconductor chip; a third overhang area spaced apart from the first upper semiconductor chip and adjacent to a first side of the second upper semiconductor chip; a fourth overhang area spaced apart from the first upper semiconductor chip and adjacent to a second side of the second upper semiconductor chip; and a second corner overhang area spaced apart from the first upper semiconductor chip, wherein the second corner overhang area is adjacent to a corner where the first side and the second side of the second upper semiconductor chip meet, and the second upper semiconductor chip comprises conductive pads, wherein the conductive pads comprise: first conductive pads on the upper surface of the third overhang area; and second conductive pads on the upper surface of the fourth overhang area, and the number of the second conductive pads is smaller than the number of the first conductive pads. Claim 10 In claim 9, the challenge pads are a semiconductor package spaced apart from the second corner overhang region of the second upper semiconductor chip. Claim 11 A semiconductor package according to claim 9, wherein the number of the first conductive pads is the same as the number of the first upper pads, and the number of the second conductive pads is the same as the number of the second upper pads. Claim 12 In claim 9, the first upper semiconductor chip is shifted in one direction from the lower semiconductor chip in a planar view, and the second upper semiconductor chip is shifted in the opposite direction from the first upper semiconductor chip in a planar view. Claim 13 In claim 12, the above-mentioned one direction intersects the first direction and the second direction from a planar perspective, the first direction is parallel to the first side of the first upper semiconductor chip and the second direction is parallel to the second side of the first upper semiconductor chip, forming a semiconductor package. Claim 14 A substrate comprising first substrate pads and second substrate pads; a lower semiconductor chip disposed on the substrate and comprising lower pads; a first upper semiconductor chip disposed on the lower semiconductor chip and comprising upper pads; first bonding wires connected to the lower pads and the first substrate pads; second bonding wires connected to the upper pads and the second substrate pads; and a molding film provided on the upper surface of the substrate and covering the lower semiconductor chip, the first upper semiconductor chip, the first bonding wires, and the second bonding wires, wherein the first upper semiconductor chip is spaced apart from the lower pads, and in a planar view, the first upper semiconductor chip comprises: a first mounting region overlapping with the lower semiconductor chip; a first overhang region spaced apart from the lower semiconductor chip and between a first side of the lower semiconductor chip and a first side of the first upper semiconductor chip; and a second overhang region spaced apart from the lower semiconductor chip and between a second side of the lower semiconductor chip and a second side of the first upper semiconductor chip. A semiconductor package having a first corner overhang region spaced apart from the lower semiconductor chip, wherein the corner overhang region is adjacent to the corner where the first side and the second side of the first upper semiconductor chip meet, and the upper pads include: first upper pads on the upper surface of the first overhang region; and second upper pads on the upper surface of the second overhang region, wherein the number of the second upper pads is smaller than the number of the first upper pads, and the upper pads are not provided on the corner overhang region of the first upper semiconductor chip. Claim 15 In claim 14, a semiconductor package wherein the number of the second upper pads is 1% to 50% of the number of the first upper pads, Claim 16 In claim 14, the lower semiconductor chip in a planar view comprises: a first edge region adjacent to a third side of the lower semiconductor chip; a second edge region adjacent to a fourth side of the lower semiconductor chip; and a corner region spaced apart from the lower semiconductor chip, wherein the corner region is adjacent to the corner where the third side and the fourth side of the lower semiconductor chip meet, and the lower pads comprise: first lower pads on the upper surface of the first edge region; and second lower pads on the upper surface of the second edge region, wherein the number of the second lower pads is 1% to 50% of the number of the first lower pads, and the lower pads are a semiconductor package spaced apart from the corner region of the lower semiconductor chip. Claim 17 In claim 14, further comprising: a second upper semiconductor chip disposed on the upper surface of the first upper semiconductor chip; and a third bonding wire connected to the substrate and the second upper semiconductor chip, wherein, in a planar view, the second upper semiconductor chip comprises: a second mounting area overlapping with the first upper semiconductor chip; a third overhang area spaced apart from the first upper semiconductor chip and adjacent to the first side of the second upper semiconductor chip; a fourth overhang area spaced apart from the first upper semiconductor chip and adjacent to the second side of the second upper semiconductor chip; a second corner overhang area spaced apart from the first upper semiconductor chip, wherein the second corner overhang area is adjacent to the corner where the first side and the second side of the second upper semiconductor chip meet; and conductive pads, wherein the conductive pads comprise: first conductive pads on the upper surface of the third overhang area; A semiconductor package comprising second conductive pads on the upper surface of the fourth overhang region, wherein the number of second conductive pads is 1% to 50% of the number of first conductive pads. Claim 18 A substrate; a first semiconductor chip disposed on the substrate and having a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, wherein the first semiconductor chip includes first chip pads on an upper surface; a second semiconductor chip provided on the first semiconductor chip and having a first sidewall, a second sidewall opposite to the first sidewall, a third sidewall, and a fourth sidewall opposite to the third sidewall, wherein the second semiconductor chip includes second chip pads on an upper surface; and first bonding wires connected to the first chip pads; A semiconductor package comprising second bonding wires connected to the second chip pads, wherein the first chip pads are adjacent to the first side, the third side, and the fourth side of the first semiconductor chip in a planar view, the maximum gap between the second chip pads and the second sidewall of the second semiconductor chip is smaller than the minimum gap between the second chip pads and the second sidewall of the second semiconductor chip, and the first sidewall of the second semiconductor chip is vertically aligned with the first side of the first semiconductor chip. Claim 19 In claim 18, in a planar view, the first semiconductor chip has: a first region that overlaps with the first chip pads and is adjacent to the first side of the first semiconductor chip; and a second region that is spaced apart from the first chip pads and is adjacent to the second side of the first semiconductor chip; in a planar view, the second semiconductor chip has: a first region that overlaps with the second chip pads and is adjacent to the first sidewall of the second semiconductor chip; and a second region that is spaced apart from the second chip pads and is adjacent to the second sidewall of the second semiconductor chip; in a planar view, the first region of the second semiconductor chip is spaced apart from the first region of the first semiconductor chip, forming a semiconductor package. Claim 20 In claim 18, the number of the second chip pads is the same as the number of the first chip pads in the semiconductor package.

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