Method for manufacturing a package substrate for mounting semiconductor devices

Abstract

A method for manufacturing a package substrate for mounting a semiconductor device having an insulating layer and a wiring conductor, comprising: a first substrate forming process (a) for forming a substrate having a first metal layer, a first insulating resin layer, and a second metal layer, wherein the first metal layer has a thickness of 1 μm to 70 μm and is peelable, on one or both sides of a core resin layer; a first interlayer connection process (b) for connecting the second and first metal layers by forming a non-penetrating hole reaching the surface of the first metal layer and performing electrolytic and / or electroless copper plating on the inner wall thereof; a second substrate forming process (c) for forming a substrate by arranging a second insulating resin layer and a third metal layer and heating and pressing the first substrate; a second interlayer connection process (d) for connecting the second and third metal layers by forming a non-penetrating hole reaching the surface of the second metal layer and performing electrolytic and / or electroless copper plating on the inner wall thereof; and a peeling process (e) for peeling off the third substrate. and a wiring conductor forming process (f) for forming a wiring conductor by patterning the first and third metal layers.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a package substrate for mounting a semiconductor device. Background Technology

[0002] The high functionality and miniaturization of semiconductor packages, which are widely used in electronic devices, communication devices, and personal computers, have recently been accelerating even further. Along with this, there is a demand for thinning of printed circuit boards and package substrates for mounting semiconductor devices in semiconductor packages. Typically, printed circuit boards and package substrates for mounting semiconductor devices are manufactured by laminating a layer that forms a circuit pattern (hereinafter simply referred to as a "wiring conductor") and an insulating material on a support substrate.

[0003] A method for manufacturing a package substrate for mounting such a semiconductor device is disclosed, for example, by using a circuit forming substrate formed by forming a first insulating resin on the carrier surface of an ultra-thin copper foil to which a carrier foil is attached, forming a first wiring conductor by pattern electrolytic copper plating, additionally laminating a second insulating resin, and then forming a second wiring conductor (see, for example, Patent Document 1 below). Furthermore, a manufacturing technology related to these package substrates for mounting semiconductor devices is disclosed, which involves laminating a plurality of layers on a core substrate to form a laminate, and then separating the laminate from the core substrate to produce a semiconductor package substrate, etc. (see, for example, Patent Documents 2 to 4 below). Prior art literature

[0004] Japanese Published Patent Application No. 2005-101137, Japanese Published Patent Application No. 2014-220402, Japanese Published Patent Application No. 2012-099857, Japanese Published Patent Application No. 2011-119722 The problem to be solved

[0005] As a manufacturing technology related to package substrates for mounting semiconductor devices as described above, a method is known to use a circuit forming substrate formed by building up an insulating layer such as prepreg and a metal foil on both sides, centered on a copper-clad laminate in which a metal foil is installed on both sides of a core resin layer. When the circuit forming substrate has four layers of metal foil, it is also referred to as a "4-layer coreless shield plate." For example, the 4-layer coreless shield plate is subsequently transformed into a 6-layer coreless shield plate through a patterning process, and each substrate (laminated) formed on both sides is peeled off from the core resin layer.

[0006] Furthermore, recently, there has been an increasing demand for thinning of package substrates for mounting semiconductor devices, such as to a thickness of approximately 40 μm. Accompanying this thinning of package substrates, issues that were not previously problematic are beginning to emerge as new problems. For example, in the manufacturing process of package substrates, it is necessary to perform processes such as hole machining, desmearing, and plating on the intermediate product, the laminate. When hole machining is performed, the rigidity of the laminate is temporarily reduced until the hole is sealed by the plating process. Moreover, due to this reduction in rigidity, the likelihood of warping occurring in the laminate increases. In each process, it is necessary to transport the laminate to the next stage; however, if the thinned laminate is in a state of reduced rigidity, handling performance is compromised, such as the increased risk of breakage. Additionally, with the thinning of the substrate, the impact of substrate (laminated) warping on each process, such as alignment, becomes greater. As such, there are cases where the yield ultimately decreases due to various causes accompanying the thinning of the substrate.

[0007] To solve the problem described above, the present invention aims to provide a method for manufacturing a package substrate for mounting semiconductor devices with excellent yield. means of solving the problem

[0008] <1> A method for manufacturing a package substrate for mounting a semiconductor device having an insulating layer and a wiring conductor formed on the insulating layer,

[0009] A first substrate forming process (a) for forming a first substrate having, in this order, a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer on one or both sides of a core resin layer, and

[0010] A first interlayer connection process (b), wherein a non-penetrating hole reaching the surface of the first metal layer is formed on the surface of the first substrate, and electrolytic copper plating and / or electroless copper plating is performed on the inner wall of the non-penetrating hole to connect the second metal layer and the first metal layer, and

[0011] A second substrate forming process (c) for forming a second substrate by heating and pressing a laminate formed by arranging a second insulating resin layer and a third metal layer in this order on the surface of the second metal layer of the first substrate, and

[0012] A second interlayer connection process (d) for connecting the second metal layer and the third metal layer by forming a non-penetrating hole reaching the surface of the second metal layer on the surface of the second substrate, and performing electrolytic copper plating and / or electroless copper plating on the inner wall of the non-penetrating hole, and

[0013] A peeling process (e) for peeling off a third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer, and

[0014] A method for manufacturing a package substrate for mounting a semiconductor device, comprising a wiring conductor forming process (f) of patterning the first metal layer and the third metal layer of the third substrate to form the wiring conductor.

[0015] <2> The above first substrate formation process (a) is,

[0016] (i) the first metal layer is placed on one or both sides of the core resin layer and laminated by heating and pressing, and then the first insulating resin layer and the second metal layer are placed in this order on the surface of the first metal layer and the first substrate is formed by heating and pressing; or,

[0017] (ii) A method for manufacturing a package substrate for mounting a semiconductor device as described in <1>, wherein the first metal layer, the first insulating resin layer, and the second metal layer are arranged in this order on both sides of the core resin layer to form a laminate, and the laminate is heated and pressed in a batch to form a first substrate.

[0018] <3> A method for manufacturing a package substrate for mounting a semiconductor device as described in <1> or <2>, wherein the thickness of the third substrate is 5 μm to 100 μm.

[0019] <4> A method for manufacturing a package substrate for mounting a semiconductor device as described in any one of <1> to <3>, wherein the first metal layer comprises a thin layer, and the first substrate has the first metal layer arranged so as to contact the thin layer and the core resin layer.

[0020] <5> A method for manufacturing a package substrate for mounting a semiconductor device as described in any one of <1> to <4>, wherein the third metal layer comprises a carrier layer, and after the first substrate is heated and pressed in the second substrate forming process (c), the carrier layer is removed from the third metal layer.

[0021] <6> A method for manufacturing a package substrate for mounting a semiconductor device as described in any one of <1> to <5>, wherein at least one of the first metal layer, the second metal layer, and the third metal layer is a copper foil.

[0022] <7> A method for manufacturing a package substrate for mounting a semiconductor device as described in any one of <1> to <6>, wherein at least one of the core resin layer, the first insulating resin layer, and the second insulating resin layer is a prepreg formed by impregnating a resin into a substrate.

[0023] <8> A method for manufacturing a package substrate for mounting a semiconductor device as described in any one of <1> to <7>, wherein the film thickness of the core resin layer is 1 μm to 90 μm. Effects of the invention

[0024] According to the present invention, a method for manufacturing a package substrate for mounting semiconductor devices with excellent yield can be provided. Brief explanation of the drawing

[0025] FIG. 1 is a schematic diagram illustrating an embodiment of a method for manufacturing a package substrate for mounting a semiconductor device according to the present invention. Specific details for implementing the invention

[0026] The present invention will be described below by way of example with respect to embodiments. However, the embodiments of the present invention are not limited to the embodiments described below.

[0027] The method for manufacturing a package substrate for mounting a semiconductor device according to the present embodiment (hereinafter, it may be simply referred to as the "manufacturing method of the present embodiment") is,

[0028] A method for manufacturing a package substrate for mounting a semiconductor device having an insulating layer and a wiring conductor formed on the insulating layer,

[0029] A first substrate forming process (a) for forming a first substrate having, in this order, a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer on one or both sides of a core resin layer, and

[0030] A first interlayer connection process (b), wherein a non-penetrating hole reaching the surface of the first metal layer is formed on the surface of the first substrate, and electrolytic copper plating and / or electroless copper plating is performed on the inner wall of the non-penetrating hole to connect the second metal layer and the first metal layer, and

[0031] A second substrate forming process (c) for forming a second substrate by heating and pressing a laminate formed by arranging a second insulating resin layer and a third metal layer in this order on the surface of the second metal layer of the first substrate, and

[0032] A second interlayer connection process (d), wherein a non-penetrating hole reaching the surface of the second metal layer is formed on the surface of the second substrate, and electrolytic copper plating and / or electroless copper plating is performed on the inner wall of the non-penetrating hole to connect the second metal layer and the third metal layer, and

[0033] A peeling process (e) for peeling off a third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer, and

[0034] It includes a wiring conductor forming process (f) for forming the wiring conductor by patterning the first metal layer and the third metal layer of the third substrate.

[0035] In conventional manufacturing methods, in many cases, after forming a first substrate, a laminate comprising a first metal layer, a first insulating resin layer, a second metal layer, a second insulating resin layer, and a third metal layer is peeled off from both sides of the core substrate, and then a package substrate for mounting semiconductor devices is manufactured by performing hole processing, desmearing, plating, etc., on the peeled laminate. However, according to such conventional manufacturing methods, as the substrate becomes thinner, the handling properties of the laminate deteriorate, and warping of the laminate becomes more likely to occur. As a result, the yield of the final product, the package substrate for mounting semiconductor devices, decreases. These problems, such as reduced handling properties and warping, often manifest after the laminate is peeled off from the core substrate.

[0036] In contrast, according to the manufacturing method of the present embodiment, after forming a second substrate, the laminate is not peeled off from the core resin layer, and a non-penetrating hole is formed in the second substrate, and the inner wall is electrolytically copper-plated and / or electroless copper-plated to perform a second interlayer connection process to connect the second metal layer and the third metal layer. After that, the third substrate, which has the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order, is peeled off from the core resin layer. The third substrate, which is a laminate after peeling, is already in a state where each layer is connected, and there is no need to perform hole processing or the like, which reduces rigidity, on the laminate separated from the core resin layer. Therefore, according to the manufacturing method of the present embodiment, the burden placed on the third substrate after peeling is reduced, and thus, the reduction in handling performance due to the reduction in rigidity of the third substrate or damage to the substrate accompanying the occurrence of bending can be reduced.

[0037] The manufacturing method of the present embodiment is described in detail below.

[0038] [First substrate formation process (a)]

[0039] The first substrate forming process (a) is a process of forming a first substrate having, in this order, a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer on one or both sides of a core resin layer. The configuration of the first substrate (substrate for circuit formation) is described using FIG. 1. FIG. 1 is a schematic diagram for explaining an embodiment of the method for manufacturing a package substrate for mounting a semiconductor device according to the present invention. As shown in FIG. 1(A) and FIG. 1(B), the circuit forming substrate (first substrate) (1) has a first metal layer (3), a first insulating resin layer (4), and a second metal layer formed in order from the surface side of the core resin layer (2) on both sides of the core resin layer (2) (e.g., prepreg). Here, "substrate for circuit formation" refers to a laminate comprising a core resin layer, a metal foil, and a resin layer, in a state where patterning, etc., is not performed on the metal foil.

[0040] In the first substrate formation process (a), the method of forming the first substrate is not particularly limited, but, for example, it can be formed by any of the following processes (i) or (ii).

[0041] (i) the first metal layer is placed on one or both sides of the core resin layer and laminated by heating and pressing, and then the first insulating resin layer and the second metal layer are placed in this order on the surface of the first metal layer and the first substrate is formed by heating and pressing; or,

[0042] (ii) A laminate is formed in which the first metal layer, the first insulating resin layer, and the second metal layer are arranged in this order on both sides of the core resin layer, and the laminate is heated and pressed collectively to form a first substrate.

[0043] In the above (i), a press process (first press) is performed to form a copper-clad laminate (in which only the first metal layer is laminated on one or both sides of the core resin layer), and additionally, a first insulating resin layer and a second metal layer are laminated and a press process (second press) is performed. The method or conditions for laminating each layer are not particularly limited, but for example, a vacuum press may be performed on the laminate under conditions of a temperature of 220 ± 2 ℃, a pressure of 5 ± 0.2 MPa, and a holding time of 60 minutes. In addition, to obtain adhesion between each metal layer and the core resin layer or each insulating resin layer, a surface treatment may be performed on the surface of each metal layer. The above surface treatment is not particularly limited and may use known means appropriately, and for example, means using a copper surface treatment liquid may be used.

[0044] In the above (ii), a first metal layer, a first insulating resin layer, and a second metal layer are arranged in this order on both sides of the core resin layer to form a laminate, and then the laminate is heated and pressed in a batch to form a first substrate. Here, "forming the first substrate (circuit forming substrate) in a batch" means a process in which, in the first substrate forming process (a), a first metal layer, a first insulating resin layer, and a second metal layer are arranged in this order on both sides of the core resin layer to form a first substrate (circuit forming substrate) by heating and pressing (performing a press process), and the first substrate is formed by performing a press process once. That is, in (ii), a press process for forming a copper-clad laminate is not performed, and after laminating the first insulating resin layer and the second metal layer, a first substrate is formed by performing one press process.

[0045] (ii) In the above, the method or conditions for lamination to form the laminate are not particularly limited, but for example, the first substrate can be formed by performing vacuum pressing on the laminate under conditions of a temperature of 220 ± 2 ℃, a pressure of 5 ± 0.2 MPa, and a holding time of 60 minutes. In addition, to obtain adhesion between each metal layer and the core resin layer or each insulating resin layer, a surface treatment may be performed on the surface of each metal layer. The above surface treatment is not particularly limited and may use known means appropriately, for example, a means using a copper surface treatment liquid.

[0046] As described above, since forming a circuit forming substrate in batches allows for the omission of one press process, the manufacturing efficiency of the circuit forming substrate and the semiconductor device mounting package substrate using it can be improved.

[0047] (Core resin layer)

[0048] As for the core resin layer in the substrate forming process (a), although not specifically limited, for example, a prepreg in which an insulating resin material (insulating material) such as a thermosetting resin is impregnated into a substrate such as glass cloth, or an insulating film material, can be used.

[0049] The thickness of the core resin layer is not particularly limited. However, when forming the first substrate using the method of (ii) described above, the thickness of the core resin layer is preferably 1 μm to 90 μm, and more preferably 1 μm to 80 μm. If the thickness of the core resin layer is 1 μm to 90 μm (preferably 1 μm to 80 μm), the moldability of the resin is sufficient, and when the first substrate is formed in batches, it is possible to suppress the occurrence of wrinkles or irregularities on the metal layer of the third substrate surface that is peeled off from the core resin layer after the peeling process. Therefore, by forming the first substrate (substrate for circuit formation) in batches, production efficiency is increased, and additionally, the occurrence of wrinkles or irregularities on the metal layer that cause patterning defects is suppressed, so the yield of the package substrate for mounting semiconductor devices can be improved. The thickness of the core resin layer is more preferably 3 μm to 40 μm and particularly preferably 10 μm to 25 μm from the perspective of lamination moldability.

[0050] "Prepreg" is formed by impregnating or coating a substrate with an insulating material such as a resin composition.

[0051] The substrate is not particularly limited and well-known materials used in laminates for various electrical insulation materials may be appropriately used. Materials constituting the substrate may include, for example, inorganic fibers such as E glass, D glass, S glass, or Q glass; organic fibers such as polyimide, polyester, or tetrafluoroethylene; and mixtures thereof. The substrate is not particularly limited, but may appropriately be used in the form of, for example, woven fabric, nonwoven fabric, roving, chopped strand mat, surfacing mat, etc. The material and shape of the substrate are selected according to the intended use or performance of the molded article, and if necessary, a single material or two or more types of materials and shapes may be used.

[0052] The thickness of the substrate can be appropriately set according to the thickness of the core resin layer and is not particularly limited, but typically, a thickness of 10 μm to 30 μm can be used. In addition, as the substrate, a substrate surface-treated with a silane coupling agent or one mechanically opened can be used, and these substrates are preferred in terms of heat resistance, moisture resistance, and processability.

[0053] The above insulating material is not particularly limited, and a known resin composition used as an insulating material for printed circuit boards may be appropriately selected and used. As the above resin composition, a thermosetting resin having good heat resistance and chemical resistance may be used as a base. Examples of thermosetting resins are not particularly limited, but include phenol resin, epoxy resin, cyanate resin, maleimide resin, isocyanate resin, benzocyclobutene resin, vinyl resin, etc. One type of thermosetting resin may be used alone, or two or more types may be used in a mixture.

[0054] Among thermosetting resins, epoxy resins can be preferably used as insulating materials because they have excellent heat resistance, chemical resistance, and electrical properties, and are relatively inexpensive. Examples of epoxy resins include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A novolak type epoxy resin, diglycidyl etheride of biphenol, diglycidyl etheride of naphthalenediol, diglycidyl etheride of phenols, diglycidyl etheride of alcohols, and their alkyl substituents, halides, hydrogenated derivatives, etc. One type of epoxy resin may be used alone, or two or more types may be mixed and used. In addition, any curing agent used together with this epoxy resin can be used without limitation as long as it cures the epoxy resin, and examples include polyfunctional phenols, polyfunctional alcohols, amines, imidazole compounds, acid anhydrides, organic phosphorus compounds, and their halides. These epoxy resin curing agents may be used as a single type or as a mixture of two or more types.

[0055] The above cyanate resin is a resin that produces a cured product having a triazine ring as a repeating unit upon heating, and the cured product has excellent dielectric properties. For this reason, it is particularly desirable in cases where high-frequency characteristics are required. The cyanate resin is not particularly limited, but examples include 2,2-bis(4-cyanatophenyl)propane, bis(4-cyanatophenyl)ethane, 2,2-bis(3,5-dimethyl-4-cyanatophenyl)methane, 2,2-(4-cyanatophenyl)-1,1,1,3,3,3-hexafluoropropane, α,α'-bis(4-cyanatophenyl)-m-diisopropylbenzene, cyanate esters of phenol novolac and alkylphenol novolac. Among these, 2,2-bis(4-cyanatophenyl)propane is preferred because the balance between the dielectric properties and curability of the cured product is particularly good, and it is also inexpensive. Cyanate resins such as these cyanate ester compounds may be used as a single type or as a mixture of two or more types. In addition, some of the cyanate ester compounds may be oligomerized into a tripr or a pentamer in advance.

[0056] In addition, a curing catalyst or a curing accelerator may be used in combination with the cyanate resin. As a curing catalyst, metals such as manganese, iron, cobalt, nickel, copper, and zinc may be used, and specifically, organometallic salts such as 2-ethylhexanoate and octylate, or organometallic complexes such as acetylacetone complexes may be used. As for the curing catalyst, one type may be used alone, or two or more types may be used in combination.

[0057] In addition, it is preferable to use phenols as curing accelerators, and monofunctional phenols such as nonylphenol and paracumylphenol, difunctional phenols such as bisphenol A, bisphenol F, and bisphenol S, or polyfunctional phenols such as phenol novolac and cresol novolac may be used. One type of curing accelerator may be used alone, or two or more types may be used in combination.

[0058] In the resin composition used as the insulating material above, a thermoplastic resin may be blended considering dielectric properties, impact resistance, film processability, etc. The thermoplastic resin is not particularly limited, but examples include fluoropolymer resin, polyphenylene ether, modified polyphenylene ether, polyphenylene sulfide, polycarbonate, polyetherimide, polyetheretherketone, polyacrylate, polyamide, polyamideimide, polybutadiene, etc. The thermoplastic resin may be used as a single type or as a mixture of two or more types.

[0059] Among thermoplastic resins, it is useful to use a combination of polyphenylene ether and modified polyphenylene ether from the perspective that it can improve the dielectric properties of the cured product. Examples of polyphenylene ethers and modified polyphenylene ethers include, for instance, poly(2,6-dimethyl-1,4-phenylene) ether, an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and polystyrene, an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and styrene-butadiene copolymer, an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and styrene-maleic anhydride copolymer, an alloy polymer of poly(3,6-dimethyl-1,4-phenylene) ether and polyamide, and an alloy polymer of poly(2,6-dimethyl-1,4-phenylene) ether and styrene-butadiene-acrylonitrile copolymer. In addition, to impart reactivity or polymerization to polyphenylene ether, functional groups such as amine groups, epoxy groups, carboxyl groups, and styryl groups may be introduced to the ends of the polymer chain, or functional groups such as amine groups, epoxy groups, carboxyl groups, styryl groups, and methacryl groups may be introduced to the side chains of the polymer chain.

[0060] Among thermoplastic resins, polyamideimide resin is useful in terms of excellent moisture resistance and good adhesion to metal. The raw materials for polyamideimide resin are not particularly limited, but examples of acid components include trimellitic anhydride and trimellitic anhydride monochloride, and examples of amine components include metaphenylenediamine, paraphenylenediamine, 4,4'-diaminodiphenyl ether, 4,4'-diaminodiphenylmethane, bis[4-(aminophenoxy)phenyl]sulfone, 2,2'-bis[4-(4-aminophenoxyphenyl]propane, etc. Polyamideimide resin may be modified with siloxane to improve drying properties, in which case siloxane diamine may be used as the amino component. Considering film processability, it is preferable to use polyamideimide resin with a molecular weight of 50,000 or more.

[0061] Although the thermoplastic resins described above have been explained primarily as insulating materials used in prepregs, these thermoplastic resins are not limited to use as prepregs. For example, a film (film material) made using the thermoplastic resins described above may be used as a core resin layer in the circuit forming substrate.

[0062] In the resin composition used as an insulating material, inorganic fillers may be mixed. Inorganic fillers are not particularly limited, but examples include alumina, aluminum hydroxide, magnesium hydroxide, clay, talc, antimony trioxide, antimony pentoxide, zinc oxide, fused silica, glass powder, quartz powder, silage balloons, etc. These inorganic fillers may be used as a single type or as a mixture of two or more types.

[0063] The resin composition used as an insulating material may contain an organic solvent. The organic solvent is not particularly limited and may be used in combination as desired, including aromatic hydrocarbon solvents such as benzene, toluene, xylene, and trimethylbenzene; ketone solvents such as acetone, methyl ethyl ketone, and methyl isobutyl ketone; ether solvents such as tetrahydrofuran; alcohol solvents such as isopropanol and butanol; ether alcohol solvents such as 2-methoxyethanol and 2-butoxyethanol; and amide solvents such as N-methylpyrrolidone, N,N-dimethylformamide, and N,N-dimethylacetamide. In addition, when producing prepreg, the amount of solvent in the varnish is preferably in the range of 40 to 80 mass% relative to the total resin composition. In addition, the viscosity of the above varnish is preferably in the range of 20 to 100 cP (20 to 100 mPa·s).

[0064] A resin composition used as an insulating material may contain a flame retardant. As for the flame retardant, although not specifically limited, known conventional flame retardants may be used, such as bromine compounds including decabromodiphenyl ether, tetrabromobisphenol A, tetrabromophthalic anhydride, and tribromophenol; phosphorus compounds including triphenylphosphate, trixylenephosphate, and cresyldiphenylphosphate; metal hydroxides including magnesium hydroxide and aluminum hydroxide; red phosphorus and its modified products; antimony compounds including antimony trioxide and antimony pentoxide; and triazine compounds including melamine, cyanuric acid, and melamine cyanurate.

[0065] For a resin composition used as an insulating material, the curing agent, curing accelerator described above, or various other additives or fillers such as thermoplastic particles, coloring agents, UV impermeable agents, antioxidants, and reducing agents may be added as needed.

[0066] In this embodiment, the prepreg can be obtained as a prepreg in a semi-cured state (B-stage state) by impregnating or coating a substrate with a resin composition (including varnish) such that the amount of resin composition attached to the substrate described above is 20 to 90 mass% as the resin content in the prepreg after drying, and then heating and drying at a temperature of 100 to 200°C for 1 to 30 minutes. For such a prepreg, for example, the GHPL-830NS series and GHPL-830NSF series (product names) manufactured by Mitsubishi Gas Chemical can be used.

[0067] (First metal layer)

[0068] A metal foil having a thickness of 1 μm to 70 μm and capable of being peeled off from the core resin layer is used for the first metal layer. If the thickness of the first metal layer is less than 1 μm, the first to third substrates become molded defective, and if it exceeds 70 μm, surface defects occur. From the perspective of circuit formability, the thickness of the first metal layer is preferably 1 μm to 12 μm, and more preferably 2 μm to 5 μm.

[0069] As described below, the third substrate is peeled off from the interface between the core resin layer and the first metal layer during the peeling process. The surface roughness of the first metal layer when peeled off from the core resin layer during the peeling process (average roughness of 10 points (Rzjis) as shown in JISB0601:2001) is preferably 1 μm to 3 μm from the viewpoint of preventing pattern defects, more preferably 1 μm to 2 μm, and particularly preferably 1 μm to 1.5 μm. The surface roughness of the first metal layer can be measured, for example, by cutting a sample 5 × 5 cm and then using a microscope VR-3100 (manufactured by Keyence) to measure a 1 × 1 cm area.

[0070] For example, copper foil can be used as the first metal layer. Also, for example, a fillable type copper foil can be used. "Fillerable type" copper foil refers to an ultra-thin copper foil having a thin layer, wherein the thin layer is, for example, a peelable copper foil. When using a fillable type copper foil, the first metal layer is laminated so that the thin layer is in contact with the core resin layer.

[0071] As for the thin layer, for example, a layer containing at least a silicon compound may be provided, and, for example, it may be formed by applying a silicon compound formed by applying a silane compound alone or in combination with multiple others onto a copper foil or ultra-thin copper foil. Furthermore, the means for applying the silicon compound is not particularly limited, and known means such as coating may be used, for example. Anti-corrosion treatment may be performed (an anti-corrosion treatment layer may be formed) on the adhesive surface with the thin layer of the copper foil. The anti-corrosion treatment may be performed using any one of nickel, tin, zinc, chromium, molybdenum, cobalt, or an alloy thereof.

[0072] The thickness of the thin layer is not particularly limited, but from the perspective of removeability and peelability, 5 nm to 100 nm is preferred, 10 nm to 80 nm is more preferred, and 20 nm to 60 nm is particularly preferred.

[0073] (First insulating resin layer)

[0074] As the first insulating resin layer, the same material as the core resin layer described above (e.g., prepreg) may be used. Also, the thickness of the first insulating resin layer is not particularly limited as it is appropriately set according to preference, but for example, it can be 10 μm to 100 μm, 10 μm to 50 μm is preferred, and 10 μm to 30 μm is more preferred.

[0075] (Second metal layer)

[0076] For the second metal layer, for example, the same material as the first metal layer described above (e.g., copper foil) may be used. The thickness of the second metal layer is not particularly limited as it is appropriately set according to preference, but for example, it can be 2 μm to 70 μm, 2 μm to 18 μm is preferred, and 2 μm to 12 μm is more preferred.

[0077] In addition, for the second metal layer, for example, an ultra-thin copper foil with a carrier attached can be used. In this case, the second metal layer is arranged so that the copper foil, etc., comes into contact with the second insulating resin layer, and the carrier is peeled off after the first substrate is formed by heating and pressing.

[0078] [1st Interlayer Connection Process (b)]

[0079] The first interlayer connection process (b) is a process of forming a non-penetrating hole on the surface of the first substrate described above that reaches the surface of the first metal layer, and performing electrolytic copper plating and / or electroless copper plating on the inner wall of the non-penetrating hole to connect the second metal layer and the first metal layer. By undergoing the first interlayer connection process (b), as shown in FIG. 1(E), the first metal layer (3) and the second metal layer (5) in the first substrate (1) are interlayer connected via a copper plating film (5A), and electrical conductivity is ensured.

[0080] (Formation of non-penetrating holes)

[0081] In the first interlayer connection process (b), a non-penetrating hole reaching the surface of the first metal layer is formed on the surface of the first substrate. As shown in FIG. 1(C), the non-penetrating hole (6A) is formed on both sides of the first substrate (1).

[0082] The means for forming non-penetrating holes are not particularly limited, and known means such as a laser, such as a carbon dioxide laser, or a drill can be used. The number or size of the non-penetrating holes can be appropriately selected as desired. In addition, after forming the non-penetrating holes, desmearing treatment can be performed using an aqueous sodium permanganate solution, etc.

[0083] (Inter-floor connection)

[0084] In the first interlayer connection process (b), after forming a non-penetrating hole (6A), as shown in FIG. 1(D), electrolytic copper plating and / or electroless copper plating are performed to form a copper plating film (5A) on the inner wall of the non-penetrating hole, thereby electrically connecting the first metal layer (3) and the second metal layer (5). At this time, the thickness of the second metal layer on both sides of the first substrate may be increased by the electrolytic copper plating and / or electroless copper plating, and the layer thickness may be adjusted by adjusting the film thickness as described later. The method of performing electrolytic copper plating and / or electroless plating is not particularly limited, and known methods may be adopted. The copper plating may be either electrolytic copper plating or electroless plating, but it is preferable to perform both electrolytic copper plating and electroless plating.

[0085] (Adjusting film thickness)

[0086] In the first interlayer connection process (b), as shown in FIG. 1(E), after electrolytic / electroless copper plating treatment, if necessary, a known treatment such as etching treatment can be performed so that the second metal layer (5) becomes a desired thickness, thereby adjusting the film thickness.

[0087] The thickness of the second metal layer after adjustment is not particularly limited as it is appropriately set according to the desired, but, for example, it can be 2 μm to 30 μm, 2 μm to 20 μm is preferred, and 2 μm to 12 μm is more preferred.

[0088] (Patterning)

[0089] In the first interlayer connection process (b), if necessary, the second metal layer (5) is surface-lined, and then a pattern can be formed on the second metal layer (5) of the first substrate (1) as shown in FIG. 1 (F). The means for forming the pattern of the second metal layer is not particularly limited, but, for example, can be formed by the following process.

[0090] Patterning is not particularly limited, but for example, a front surface of the second metal layer can be formed, a dry film resist, etc. can be laminated, a negative type mask can be applied, a circuit pattern can be baked using an exposure machine, and the dry film resist can be developed with a developer to form an etching resist. After that, an etching treatment can be performed to remove copper in the portion without the etching resist using an aqueous ferric chloride solution, etc., and then the resist can be removed to form a pattern on the second metal layer.

[0091] The resist described above is not particularly limited, and known materials such as commercially available dry film resists can be appropriately selected and used. In addition, photolithography (including exposure, development, and removal of the resist) when forming a pattern on the second metal layer is not particularly limited and can be performed using known means and devices.

[0092] The pattern width of the second metal layer is not particularly limited and can be appropriately selected according to the application, but for example, it can be 5 to 100 μm, and preferably 10 to 30 μm.

[0093] [Second substrate formation process (c)]

[0094] The second substrate forming process (c) is a process of forming a second substrate by heating and pressing a laminate formed by arranging a second insulating resin layer and a third metal layer in this order on the surface of the second metal layer of the first substrate. By undergoing the second substrate forming process (c), as shown in FIG. 1(G), a second substrate (7) can be obtained in which the second insulating resin layer (8) and the third metal layer (9) are laminated on the second metal layer (5).

[0095] (Second insulating resin layer)

[0096] As the second insulating resin layer, the same material as the core resin layer described above (e.g., prepreg) may be used. Also, the thickness of the second insulating resin layer is not particularly limited as it is appropriately set according to preference, but for example, it can be 10 μm to 100 μm, 10 μm to 50 μm is preferred, and 10 μm to 30 μm is more preferred.

[0097] (Third metal layer)

[0098] For the third metal layer, for example, the same material as the first metal layer described above (e.g., copper foil) may be used. The thickness of the third metal layer is not particularly limited as it is appropriately set according to preference, but for example, it can be 2 μm to 70 μm, 2 μm to 18 μm is preferred, and 2 μm to 5 μm is more preferred.

[0099] In addition, for the third metal layer, for example, an ultra-thin copper foil with a carrier attached can be used. In this case, the third metal layer is arranged so that the copper foil, etc., comes into contact with the second insulating resin layer, and the carrier is peeled off after the second substrate is formed by heating and pressing.

[0100] (Lamination method / conditions)

[0101] The method or conditions for laminating the second insulating resin layer and the third metal layer to obtain the second substrate are not particularly limited, but for example, the second substrate can be formed by laminating the second insulating resin layer and the third metal layer onto the first substrate and then performing a vacuum press under conditions of a temperature of 220 ± 2 ℃, a pressure of 5 ± 0.2 MPa, and a holding time of 60 minutes. In addition, to obtain adhesion between the second metal layer and the second insulating resin layer, a surface treatment may be performed on the surface of the second metal layer.

[0102] [Second Interlayer Connection Process (d)]

[0103] The second interlayer connection process (d) is a process of forming a non-penetrating hole on the surface of the second substrate that reaches the surface of the second metal layer, and performing electrolytic copper plating and / or electroless copper plating on the inner wall of the non-penetrating hole to connect the second metal layer and the third metal layer. By undergoing the second interlayer connection process (d), as shown in FIG. 1(J), the second metal layer (5) and the third metal layer (9) in the second substrate (7) are interlayer connected via a copper plating film (9A), and electrical conductivity is ensured.

[0104] (Formation of non-penetrating holes)

[0105] In the second interlayer connection process (d), a non-through hole reaching the surface of the second metal layer is formed on the surface of the first substrate. As shown in FIG. 1(H), the non-through hole (6B) is formed on both sides of the second substrate (7).

[0106] As described above, the means for forming non-penetrating holes is not particularly limited, and known means such as a laser, such as a carbon dioxide laser, or a drill can be used. The number or size of the non-penetrating holes can be appropriately selected as desired. In addition, after forming the non-penetrating holes, a desmearing treatment can be performed using an aqueous sodium permanganate solution, etc.

[0107] (Inter-floor connection)

[0108] In the second interlayer connection process (d), after forming a non-penetrating hole (6B), as shown in FIG. 1(I), electrolytic copper plating and / or electroless copper plating are performed to form a copper plating film (9A) on the inner wall of the non-penetrating hole, and the second metal layer (5) and the third metal layer (9) are electrically connected. At this time, the thickness of the third metal layer on both sides of the second substrate may be increased by the electrolytic copper plating and / or electroless copper plating, and the film thickness may be adjusted by the film thickness adjustment described later. The method of performing electrolytic copper plating and / or electroless plating is not particularly limited, and known methods may be adopted. The copper plating may be either electrolytic copper plating or electroless plating, but it is preferable to perform both electrolytic copper plating and electroless plating.

[0109] (Adjusting film thickness)

[0110] In the second interlayer connection process (d), as shown in FIG. 1(J), after electrolytic / electroless copper plating treatment, if necessary, a known treatment such as etching treatment can be performed so that the thickness of the third metal layer (9) becomes a desired thickness, thereby adjusting the film thickness.

[0111] The thickness of the third metal layer after adjustment is not particularly limited as it is appropriately set according to the desired, but, for example, it can be 2 μm to 30 μm, 2 μm to 20 μm is preferred, and 2 μm to 12 μm is more preferred.

[0112] [Peeling process (e)]

[0113] The peeling process (e) is a process of peeling off a third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer. After the peeling process (e), as shown in FIG. 1(K), by separating the second substrate (7) at the interface between the core resin layer (2) and the first metal layer (3) disposed on both sides thereof, two third substrates (10) having the first metal layer (3), the first insulating resin layer (4), the second metal layer (5), the second insulating resin layer (8), and the third metal layer (9) in this order can be obtained.

[0114] The thickness of the third substrate is not particularly limited as it is appropriately set according to preference, but, for example, it can be 5 μm to 400 μm, 5 μm to 200 μm is preferred, and 5 μm to 100 μm is more preferred.

[0115] In the peeling process (e), it is preferable that the core resin layer be peeled off at the interface between the core resin layer and the first metal layer, but for example, if the first metal layer has a thin layer, a part thereof may be peeled off together with the core resin layer. Also, an embodiment in which the core resin layer is peeled off together with the thin layer at the interface between the thin layer of the first metal layer and the copper foil is included. If the thin layer remains on the first metal layer, the thin layer may be removed, for example, using a sulfuric acid-based or hydrogen peroxide-based etching solution. The sulfuric acid-based or hydrogen peroxide-based etching solution is not particularly limited and may use any that are used in the industry.

[0116] [Wiring conductor formation process (f)]

[0117] The wiring conductor forming process (f) is a process of forming the wiring conductor by patterning the first metal layer and the third metal layer of the third substrate. By undergoing the wiring conductor forming process (f), a package substrate (13) for mounting a semiconductor device can be obtained in which wiring conductors (12) are formed on both sides of an insulating layer (11), as shown in FIG. 1(L). In addition, the insulating layer (11) is composed of a first insulating resin layer (4) and a second insulating resin layer (8), and the wiring conductor (12) is formed by interlayer connecting the patterned first metal layer (3), second metal layer (5), and third metal layer (9) by electrolytic copper plating and / or electroless copper plating.

[0118] (Patterning)

[0119] In the wiring conductor forming process (f), if necessary, the front of the first metal layer (3) and the third metal layer (9) (see FIG. 1(K)) may be formed, then a dry film resist or the like may be laminated, and further a negative type mask may be applied, then the circuit pattern may be baked with an exposure machine, and the dry film resist may be developed with a developer to form an etching resist. After that, an etching treatment may be performed to remove copper in the parts without the etching resist using an aqueous ferric chloride solution or the like, and then the resist may be removed to form wiring conductors (12) on both sides of the insulating layer (11).

[0120] In addition, applicable interlayer connection methods in this embodiment include a method of applying chemical copper plating to a known laser-formed blind via (a method of forming a wiring circuit by laser processing and then performing patterning and interlayer connection by chemical copper plating), a method of performing interlayer connection by piercing the insulating layer with a metal bump (preferably a copper bump) formed by plating or etching a metal foil in the part to be the connection part, and furthermore, a method of printing bumps at a predetermined point by screen printing, etc., using a metal paste containing metal fillers such as solder, silver, and copper in an insulating resin, curing the paste by drying, and ensuring electrical conductivity between the inner and outer layers by applying heat and pressure.

[0121] In FIG. 1, which illustrates the exemplary embodiment, the package substrate (13) for mounting a semiconductor device has a three-layer structure, but the present invention is not limited to this and can form a package substrate for mounting a semiconductor device having an additional build-up structure such as a five-layer structure. For example, in the wiring conductor forming process (f), after forming the wiring conductor, an insulating resin layer and a metal layer are additionally laminated, and patterning and interlayer connection are repeated, thereby making it possible to manufacture a package substrate for mounting a semiconductor device having a build-up structure.

[0122] Method for manufacturing a package substrate for mounting semiconductor devices

[0123] In the method for manufacturing a package substrate for mounting a semiconductor device according to the present embodiment, after forming a package substrate for a semiconductor device as described above, a semiconductor device such as a bare chip can be mounted as desired.

[0124] The above semiconductor device is not particularly limited and any desired device may be appropriately used; for example, a bare chip having gold bumps formed by a gold wire ball bonding method on an aluminum electrode portion may be used. The semiconductor device may be mounted on the wiring conductors of a package substrate for mounting the semiconductor device by means of a bonding material. The above bonding material is not particularly limited as long as it has a conductive means, but for example, solder (e.g., solder balls, solder paste, etc.) may be used. In addition, the semiconductor device may be mounted by means of a bonding material after surface treatment is performed on the wiring conductors of the package substrate for mounting the semiconductor device. The above surface treatment is not particularly limited, but for example, the formation of a nickel layer or a gold plating layer may be used. In cases where solder is used as the above bonding material, a treatment such as reflow may be performed after mounting the semiconductor device on the wiring conductors. At this time, the temperature of the reflow is appropriately selected according to the melting point of the bonding material, but for example, it may be 260°C or higher.

[0125] In addition, although the above description was given as an example where each layer is formed on both sides of the core resin layer, the present invention is not limited to such a case and may have each layer on only one side of the core resin layer.

[0126] Examples

[0127] The manufacturing method of the present invention will be specifically described below through examples.

[0128] [Example 1]

[0129] A prepreg (core resin layer (2) in FIG. 1(A); thickness 0.100 mm: manufactured by Mitsubishi Gas Chemical, product name: GHPL-830NS ST56) prepared by impregnating a glass cloth (glass fiber) with a bismaleimide triazine resin (BT resin) to form a B stage was placed on both sides of the prepreg, and a copper foil (first metal layer (3) in FIG. 1(A); manufactured by JX Nikko Nisseki Metal Co., Ltd., product name: PCS) with a thin layer coated with a copper foil thickness of 8 μm was attached thereto was placed so that the thin layer surface was bonded to the prepreg, and a vacuum press was performed under conditions of a temperature of 220 ± 2 ℃, a pressure of 5 ± 0.2 MPa, and a holding time of 60 minutes to produce a copper-clad laminate with a copper foil surface roughness of 3 μm.

[0130] <First substrate formation process (a)>

[0131] On both sides of the obtained copper-clad laminate, a prepreg (the first insulating resin layer (4) in FIG. 1(A); thickness 0.017 mm; manufactured by Mitsubishi Gas Chemical, trade name: GHPL-830NS SF62) prepared as a B stage by impregnating a glass cloth (glass fiber) with bismaleimidetriazine resin (BT resin) is interposed, and a 2 μm copper foil (the second metal layer (5) in FIG. 1(A); manufactured by Mitsui Metal Mining Co., Ltd., trade name: MTEx) with an 18 μm carrier copper foil attached is laminated using a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 220 ± 2 ℃, and holding time 60 minutes, and then the 18 μm carrier copper foil is peeled off to form a first substrate (the circuit forming substrate (the 1. A substrate) (1)) was manufactured.

[0132] <1st Interlayer Connection Process (b)>

[0133] Next, non-penetrating holes (non-penetrating holes (6A) in FIG. 1(C)) were formed on both sides of the first substrate by processing one hole at a time using a carbon dioxide laser processing machine (manufactured by Hitachi Via Mechanics Co., Ltd., product name: LC-1C / 21) under conditions of beam irradiation diameter Φ0.21 mm, frequency 500 Hz, and pulse width 10 μs. Then, desmearing treatment was performed using an aqueous sodium permanganate solution at a temperature of 80 ± 5 ℃ and a concentration of 55 ± 10 g / ℓ.

[0134] In addition, after performing a plating treatment to achieve a thickness of 0.4 to 0.8 μm by electroless copper plating, a plating treatment to achieve a thickness of 8 μm was performed by electrolytic copper plating to form a copper plating film (copper plating film (5A) in FIG. 1(D)). As a result, the first and second metal layers are electrically connected by non-through holes through the copper plating film. Next, the front surface of the first substrate was treated, and a dry film resist (manufactured by Nichigo Morton Co., Ltd., product name: NIT225) was laminated at a temperature of 110 ± 10 ℃ and a pressure of 0.50 ± 0.02 MPa. After that, a negative type mask was applied, the circuit pattern was baked using a parallel exposure machine, the dry film resist was developed with a 1% sodium carbonate aqueous solution to form an etching resist, the copper in the parts without the etching resist was removed with a ferric chloride aqueous solution, and the dry film resist was removed with a sodium hydroxide aqueous solution to form a pattern on the second metal layer (5) (see FIG. 1(F)).

[0135] <Second substrate formation process (c)>

[0136] Next, the surface of the patterned second metal layer was conditioned using a copper surface conditioning solution (manufactured by MEC Co., Ltd., product name: CZ-8100), and a resin sheet (thickness 0.010 mm: manufactured by Mitsubishi Gas Chemical, product name: CRS-381NSI) that was applied to a 2 μm copper foil (manufactured by Mitsui Metal Mining Co., Ltd., product name: MTEx) with an 18 μm carrier copper foil attached to the surface of the second metal layer formed on both sides of the first substrate was laminated using a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 220 ± 2 ℃, and holding time 60 minutes, and then the 18 μm carrier copper foil was peeled off to produce a second substrate (the second substrate (7) in FIG. 1(G)).

[0137] <Second Interlayer Connection Process (d)>

[0138] Non-penetrating holes (non-penetrating holes (6B) in FIG. 1(H)) were formed on both sides of the second substrate by processing one hole at a time using a carbon dioxide laser processing machine (manufactured by Hitachi Via Mechanics Co., Ltd., product name: LC-1C / 21) under conditions of beam irradiation diameter Φ0.21 mm, frequency 500 Hz, and pulse width 10 μs. Subsequently, desmearing treatment was performed using an aqueous sodium permanganate solution at a temperature of 80 ± 5 ℃ and a concentration of 55 ± 10 g / ℓ.

[0139] In addition, after performing a plating treatment to achieve a thickness of 0.4 to 0.8 μm by electroless copper plating, a plating treatment to achieve a thickness of 8 μm by electrolytic copper plating was performed to form a copper plating film (copper plating film (9A) in FIG. 1(I)). Thus, the second and third metal layers are electrically connected by non-through holes through the copper plating film.

[0140] <Peeling Process (e)>

[0141] In the second substrate, a physical force is applied to the boundary between the copper foil (first metal layer (3)) to which the thin layer is attached and the prepreg (core resin layer (2)) to peel it off, thereby obtaining a third substrate (the third substrate (10) in FIG. 1(K)).

[0142] <Wiring conductor formation process (f)>

[0143] After forming guide holes on the third substrate using a router machine manufactured by Hitachi Via Mechanics Co., Ltd., the surface was etched to a depth of about 1 to 2 μm with a soft etching solution based on sulfuric acid peroxide, and a dry film resist (manufactured by Nichigo Morton Co., Ltd., product name: NIT225) was laminated at a temperature of 110 ± 10 ℃ and a pressure of 0.50 ± 0.02 MPa. Baking of the circuit pattern was performed using a parallel exposure machine based on the guide holes, the dry film resist was developed with a 1% sodium carbonate aqueous solution, and a pattern electrolytic copper plating of about 15 to 20 μm was performed in a copper sulfate plating line with a copper sulfate concentration of 60 to 80 g / ℓ and a sulfuric acid concentration of 150 to 200 g / ℓ. After that, the dry film resist was peeled off with an amine-based resist peeling solution, and a pattern was formed on the third metal layer to produce a package substrate for mounting a semiconductor device (a package substrate for mounting a semiconductor device (13) in which wiring conductors (12) are formed on both sides of the insulating layer (11) in FIG. 1(L)).

[0144] On the obtained package substrate for mounting a semiconductor device, solder resist formation treatment and gold plating finish were performed, and by cutting and processing to the package size, the package substrate for mounting a semiconductor device of Example 1 was obtained. The package substrate for mounting a semiconductor device of Example 1 had excellent handling properties, and the yield was 99% when manufactured multiple times.

[0145] [Example 2]

[0146] In the first substrate formation process (a) of Example 1, the first substrate (the circuit forming substrate (first substrate) (1) in FIG. 1(B)) was produced in the same manner as below, and a package substrate for mounting a semiconductor device of Example 2 was obtained.

[0147] On both sides of a prepreg (core resin layer (2) in FIG. 1(A); thickness 0.08 mm: manufactured by Mitsubishi Gas Chemical, product name: GHPL-830NS SH65) prepared as a B stage by impregnating a glass cloth (glass fiber) with bismaleimide triazine resin (BT resin), a copper foil (first metal layer (3) in FIG. 1(A); manufactured by JX Nikko Nisseki Metal Co., Ltd., product name: PCS, surface roughness Rz 3.7 μm) having a thin layer with a copper foil thickness of 8 μm coated and attached thereto is arranged so that the thin layer surface adheres to the prepreg, and then a prepreg (first insulating resin layer (4) in FIG. 1(A)); thickness 0.017 mm (manufactured by Mitsubishi Gas Chemical, product name: GHPL-830NS SF62) was interposed with a 2 μm copper foil (second metal layer (5) in FIG. 1(A); manufactured by Mitsui Metal Mining Co., Ltd., product name: MTEx) to which an 18 μm carrier copper foil was attached, and then the 2 μm copper foil was laminated using a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 220 ± 2 ℃, and holding time 60 minutes, and then the 18 μm carrier copper foil was peeled off to produce a second circuit board and a first substrate (circuit forming substrate (first substrate) (1)) in FIG. 1(B)).

[0148] The handling of the package substrate for mounting semiconductor devices in Example 2 was excellent, and the yield was 99% when manufactured multiple times.

[0149] [Comparative Example 1]

[0150] A prepreg (core resin layer: thickness 0.100 mm: manufactured by Mitsubishi Gas Chemical, product name: GHPL-830NS ST56) prepared by impregnating a glass cloth (glass fiber) with bismaleimide triazine resin (BT resin) to form a B stage was placed on both sides of the prepreg, and a copper foil (manufactured by JX Nikko Nisseki Metal Co., Ltd., product name: PCS) with a release layer coated with copper foil having a thickness of 2 μm was placed so that the thin layer surface was bonded to the prepreg, and a vacuum press was performed under conditions of a temperature of 220 ± 2 ℃, a pressure of 5 ± 0.2 MPa, and a holding time of 60 minutes to produce a copper-clad laminate with a copper foil surface roughness of 3 μm.

[0151] On both sides of the obtained copper-clad laminate, a prepreg (thickness 0.017 mm: manufactured by Mitsubishi Gas Chemical, product name: GHPL-830NS SF62) prepared by impregnating a glass cloth (glass fiber) with bismaleimide triazine resin (BT resin) to the B stage was interposed, and a 12 μm copper foil (manufactured by Mitsui Metal Mining Co., Ltd., product name: 3LC-VLP) was laminated using a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 220 ± 2 ℃, and holding time 60 minutes.

[0152] Next, a front treatment was performed on the surface of the obtained substrate, and a dry film resist (manufactured by Nichigo Morton Co., Ltd., product name: NIT225) was laminated at a temperature of 110 ± 10 ℃ and a pressure of 0.50 ± 0.02 MPa. After that, a negative type mask was applied, and a circuit pattern was baked using a parallel exposure machine. The dry film resist was developed with a 1% sodium carbonate aqueous solution to form an etching resist, and copper in the areas without the etching resist was removed with a ferric chloride aqueous solution, and the dry film resist was removed with a sodium hydroxide aqueous solution to form a circuit pattern.

[0153] The surface of the obtained substrate was conditioned using a copper surface conditioning solution (manufactured by MEC Co., Ltd., product name: CZ-8100), and a resin sheet (thickness 0.010 mm: manufactured by Mitsubishi Gas Chemical, product name: CRS-381NSI) prepared as a B stage, in which bismaleimidetriazine resin (BT resin) was applied to a 2 μm copper foil (manufactured by Mitsui Metal Mining Co., Ltd., product name: MTEx) with an 18 μm carrier copper foil attached, was laminated using a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 220 ± 2 ℃, and holding time 60 minutes, after which the 18 μm carrier copper foil was peeled off.

[0154] For the obtained substrate, physical force was applied to the boundary between the core resin layer and the PCS to peel it off.

[0155] I tried to form non-through holes on the substrate by processing one hole at a time on both sides of the substrate peeled from the core resin layer using a carbon dioxide laser processing machine (manufactured by Hitachi Via Mechanics Co., Ltd., product name: LC-1C / 21) under conditions of beam irradiation diameter Φ0.21 mm, frequency 500 Hz, and pulse width 10 μs, but the substrate was very thin and the substrate was damaged.

[0156] The disclosure of Japanese Patent Application No. 2018-234584, filed on December 14, 2018, is incorporated herein by reference in its entirety.

[0157] Furthermore, all documents, patent applications, and technical specifications described in the specification are incorporated by reference within this specification to the same extent that individual documents, patent applications, and technical specifications are incorporated by reference as they are specifically and individually described. Explanation of the symbols

[0158] 1 : Circuit forming substrate (first substrate) 2 : Core resin layer 3: First metal layer 4: First insulating resin layer 5: Second metal layer 5A, 9A: Copper plating film 6A, 6B: Non-penetrating holes 7 : Second substrate 8: Second insulating resin layer 9: Third metal layer 10: Third substrate 11: Insulating layer 12: Wiring conductor 13: Package substrate for mounting semiconductor devices

Claims

Claim 1 A method for manufacturing a package substrate for mounting a semiconductor device having an insulating layer and a wiring conductor formed on the insulating layer, comprising: a first substrate forming process (a) for forming a first substrate having, on one or both sides of a core resin layer, a first metal layer having a thickness of 1 μm to 70 μm and peelable from the core resin layer, a first insulating resin layer, and a second metal layer in that order; a first interlayer connection process (b) for forming a non-through hole reaching the surface of the first metal layer on the surface of the first substrate and performing electrolytic copper plating and / or electroless copper plating on the inner wall of the non-through hole to connect the second metal layer and the first metal layer; a second substrate forming process (c) for forming a second substrate by heating and pressing a laminate formed by arranging a second insulating resin layer and a third metal layer in that order on the surface of the second metal layer of the first substrate; and the second substrate A second interlayer connection process (d) for connecting the second metal layer and the third metal layer by forming a non-penetrating hole on the surface reaching the surface of the second metal layer and performing electrolytic copper plating and / or electroless copper plating on the inner wall of the non-penetrating hole; a peeling process (e) for peeling off a third substrate having the first metal layer, the first insulating resin layer, the second metal layer, the second insulating resin layer, and the third metal layer in this order from the core resin layer; and a wiring conductor forming process (f) for forming the wiring conductor by patterning the first metal layer and the third metal layer of the third substrate, wherein the first substrate forming process (a) forms a laminate in which the first metal layer, the first insulating resin layer, and the second metal layer are arranged in this order on both sides of the core resin layer, and heats and presses the laminate in a batch to form the first substrate Forming, wherein the film thickness of the core resin layer is 1 μm to 90 μm, and the second interlayer connection process (d) is,A method for manufacturing a package substrate for mounting a semiconductor device, comprising a process for adjusting the thickness of the third metal layer on both sides of the second substrate, wherein the core resin layer is a prepreg having a thickness of 20 μm to 35 μm, formed by impregnating a glass cloth with bis-maleimide triazine resin as a B stage. Claim 2 A method for manufacturing a package substrate for mounting a semiconductor device according to claim 1, wherein the thickness of the third substrate is 5 μm to 100 μm. Claim 3 A method for manufacturing a package substrate for mounting a semiconductor device according to claim 1 or 2, wherein the first metal layer comprises a thin layer, and the first substrate has the first metal layer arranged such that the thin layer and the core resin layer are in contact. Claim 4 A method for manufacturing a package substrate for mounting a semiconductor device according to claim 1 or 2, wherein the third metal layer comprises a carrier layer, and after the first substrate is heated and pressed in the second substrate forming process (c), the carrier layer is removed from the third metal layer. Claim 5 A method for manufacturing a package substrate for mounting a semiconductor device according to claim 1 or 2, wherein at least one of the first metal layer, the second metal layer, and the third metal layer is a copper foil. Claim 6 A method for manufacturing a package substrate for mounting a semiconductor device according to claim 1 or 2, wherein at least one of the core resin layer, the first insulating resin layer, and the second insulating resin layer is a prepreg formed by impregnating a resin into a substrate. Claim 7 delete Claim 8 delete

Images