DC offset cancellation circuit in op amp

Abstract

A DC offset removal circuit for an operational amplifier is disclosed. The DC offset removal circuit comprises: a first sampling capacitor connected between a non-inverting input terminal of the operational amplifier and an input terminal to which the input voltage is input; a second sampling capacitor connected between an inverting input terminal of the operational amplifier and the input terminal; a first switch connected in parallel to the first sampling capacitor; a second switch controlling the connection between the input terminal and the second sampling capacitor; a third switch controlling the connection between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; and a fourth switch controlling the connection between the input terminal and the output terminal of the operational amplifier.

Description

Technology Field

[0001] The present invention relates to a DC offset removal technique for transmitting the input voltage of an operational amplifier (unit gain buffer) for driving low impedance directly to the output. Background Technology

[0003] Generally, circuits based on sampling techniques suffer from residual DC offset issues caused by clock signal feed-through and charge injection phenomena that occur when the input signal changes. To resolve this problem, the impact can typically be reduced by increasing the sampling capacitance and extending the sampling time. Additionally, if the input signal is differential, the effect can be mitigated by using a fully differential circuit.

[0004] In particular, for buffers used in display drivers, increasing the capacitor value as resolution increases leads to the problem of larger chip area. Furthermore, since the charge injection phenomenon caused by changes in input signals cannot be resolved, a DC offset removal loop must be activated every time the input signal changes, resulting in difficulties with high-speed operation. The problem to be solved

[0006] The objective of the present invention to solve the aforementioned problem is to provide an operational amplifier having a DC offset removal circuit capable of minimizing errors caused by DC offset influence and charge injection phenomena for high-speed operation. means of solving the problem

[0008] A DC offset removal circuit of an operational amplifier according to the present invention for achieving the above-mentioned purpose comprises: a first sampling capacitor connected between a non-inverting input terminal of the operational amplifier and an input terminal to which the input voltage is input; a second sampling capacitor connected between an inverting input terminal of the operational amplifier and the input terminal; a first switch connected in parallel to the first sampling capacitor; a second switch controlling the connection between the input terminal and the second sampling capacitor; a third switch controlling the connection between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; and a fourth switch controlling the connection between the input terminal and the output terminal of the operational amplifier. Effects of the invention

[0010] According to the present invention, by simultaneously designing sampling capacitors in two input terminals included in the differential input terminal of an operational amplifier (or unit gain buffer), the residual DC offset error caused by charge injection due to the transition of the input signal due to differential characteristics is minimized, thereby enabling high-speed operation. Additionally, in a structure that requires the use of a large number of buffers, such as a display driver, there is an advantage of enabling accurate signal transmission by using small-sized capacitors. Brief explanation of the drawing

[0012] FIG. 1 is a circuit diagram and timing diagram of an operational amplifier having an Auto zero DC offset removal circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of an operational amplifier having an Auto zero DC offset removal circuit according to a second embodiment of the present invention. FIG. 3 is a circuit diagram of an operational amplifier having a DC offset removal circuit according to a third embodiment of the present invention. Figure 4 is a graph showing the characteristics of charge injection according to the auto zero DC offset removal circuit illustrated in Figure 1. Figure 5 is a graph showing the characteristics of charge injection according to the auto zero DC offset removal circuit illustrated in Figure 2. FIG. 6 is a graph showing the characteristics of charge injection according to the auto zero DC offset removal circuit illustrated in FIG. 3. Specific details for implementing the invention

[0013] The terms used in this specification are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “comprising” or “having” are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0014] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0015] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. In order to facilitate an overall understanding of the present invention, the same reference numerals are used for identical components in the drawings, and redundant descriptions of identical components are omitted.

[0016] The auto-zero DC offset removal method is a type of dynamic offset removal method that measures the offset using sampling techniques and removes it by subtracting the DC offset value stored in a capacitor from the input signal during the operating interval. In order to accurately extract the DC offset using sampling techniques, the size of the capacitor used and the sampling time must be sufficiently large.

[0017] FIG. 1 is a circuit diagram and timing diagram of an operational amplifier having an Auto zero DC offset removal circuit according to a first embodiment of the present invention.

[0018] Referring to (A) of FIG. 1, the operational amplifier (30) applicable to the present invention has an Auto zero DC offset removal circuit.

[0019] The operational amplifier (30) receives an input voltage (V) through the input terminal (10). IN It is an amplifier that transmits ) directly to the output terminal (20), and can be called a unit gain buffer. The DC offset removal circuit consists of first to third switches (SW1, SW2 and SW3) and a sampling capacitor (C S1 Includes ).

[0020] Sampling capacitor (C S1 One electrode of ) is connected to the non-inverting terminal (+) of the operational amplifier (30), and the sampling capacitor (C S1 The other electrode of ) is connected to the third switch (SW3) through the first node (N1). Accordingly, the sampling capacitor (C S1) and the third switch (SW3) are connected in series.

[0021] The third switch (SW3) performs a switching operation according to the second clock signal (φ2), and the input voltage (V IN ) input terminal (10) into which input is received and sampling capacitor (C S1 Controls the electrical connection of the other electrode of ).

[0022] The first switch (SW1) is connected in series with a sampling capacitor (C S1 It is connected in parallel to the ) and the third switch (SW3). The first switch (SW1) performs a switching operation according to the first clock signal (φ1), and the input voltage (V IN The input terminal (V) where ) is input IN ) and sampling capacitor (C S1 Controls the electrical connection of one electrode of ).

[0023] The second switch (SW2) performs a switching operation according to the first clock signal (φ1) to control the electrical connection between the first node (N1) and the second node (N2). The output of the operational amplifier (30) is fed back to the inverting terminal (-) of the operational amplifier (30) via the second node (N2).

[0024] Meanwhile, V in (A) of Fig. 1 OS represents the offset voltage.

[0025] The operation process of an operational amplifier having such an Auto zero DC offset removal circuit is explained as follows with reference to the timing diagram shown in (B) of Fig. 1.

[0026] First, the sampling interval (T S In ), a high-level first clock signal (φ1) and a low-level second clock signal (φ2) are applied to the first to third switches (SW1, SW2, and SW3), so that the first and second switches (SW1 and SW2) are turned on and the third switch (SW3) is turned off. Accordingly, the output voltage (V OUT ) is 'VOUT = V IN + V OS It is determined as such, and while the first and second switches (SW1 and SW2) are turned on, the sampling capacitor (C S1 The DC offset voltage (Vc) stored in ) is 'Vc = V IN - V OUT = -V OS It is determined as follows.

[0027] In the operating period (TH) of the actual operational amplifier (30), the first clock signal (φ1) is transitioned to a low level and the second clock signal (φ2) is transitioned to a high level, so that the first and second switches (SW1 and SW2) are turned off and the third switch (SW3) is turned on. Accordingly, the output voltage is determined as follows by the DC offset voltage stored in the sampling capacitor (Cs).

[0028] V OUT = V IN + V c + V OS = V IN - V OS + V OS =V IN

[0029] That is, while the first and second switches (SW1 and SW2) are turned off and the third switch (SW3) is turned on, the output voltage (V OUT ) offset voltage (V c ) is removed. Therefore, even if a DC offset voltage occurs in the actual output voltage, the input voltage (V IN ) is passed as is, so errors caused by DC offset can be eliminated.

[0031] FIG. 2 is a circuit diagram of an operational amplifier having an Auto zero DC offset removal circuit according to a second embodiment of the present invention.

[0032] Referring to FIG. 2, in an operational amplifier having an Auto zero DC offset removal circuit according to a second embodiment of the present invention, a sampling capacitor (C S2 There are differences from the first embodiment of FIG. 1 described above in that the ) is connected to the inverting terminal (-) of the operational amplifier (30) and in the connection structure of the first to third switches. The description of their specific connection structure is omitted, and the operating principle is described as follows.

[0033] First, the sampling interval (T S In ), a high-level first clock signal (φ1) and a low-level second clock signal (φ2) are applied to the first to third switches (SW1, SW2, and SW3), and accordingly, an output voltage (V OUT ) is 'V OUT = V IN + V OS = V IN + V c It is determined as ', and the sampling capacitor (C S2 The voltage (Vc) stored in ) is 'Vc = V OUT - V IN = V OS It can be decided as follows.

[0034] In the operating period (TH) of the actual operational amplifier (30), the first clock signal (φ1) transitions to a low level and the second clock signal (φ2) transitions to a high level, so that the sampling capacitor (C s2 The output voltage is determined as follows by the DC offset voltage stored in ).

[0035] V OUT = V IN + V OS - Vc = V IN

[0036] Accordingly, the operational amplifier having an Auto zero DC offset removal circuit according to the second embodiment of the present invention also [remains] the input voltage (V) even if a DC offset voltage occurs in the actual output voltage. IN ) is passed as is, so errors caused by DC offset can be eliminated.

[0038] Meanwhile, in the case of the auto zero DC offset structure of Figures 1 and 2, distortion of the output signal due to the influence of DC offset occurs at the moment when the input signal (input voltage) transitions from a low level to a high level or from a high level to a low level due to the charge injection phenomenon.

[0039] In addition, the phenomenon may be significantly apparent when the input signal (input voltage) changes from low to high in the case of the structure of Fig. 1, and may be significantly apparent when the input signal (input voltage) changes from high to low in the case of the structure of Fig. 2.

[0041] In the third embodiment of the present invention described below with reference to FIG. 3, a circuit structure is proposed to minimize errors caused by DC offset effects and charge injection phenomena regardless of the transition direction (L→H or H→L) of the input signal. Accordingly, the problem of having to increase the size of the sampling capacitor or periodically operate the DC offset removal circuit to reduce the effect of DC offset is solved.

[0043] FIG. 3 is a circuit diagram of an operational amplifier having a DC offset removal circuit according to a third embodiment of the present invention.

[0044] Referring to FIG. 3, the operational amplifier having a DC offset removal circuit according to the third embodiment of the present invention is a combined structure of the DC offset removal circuits shown in FIG. 1 and FIG. 2.

[0045] Specifically, the DC offset removal circuit applied to the operational amplifier (30) according to the third embodiment of the present invention comprises first to fourth switches (SW1, SW2, SW3 and SW4) and first and second sampling capacitors (C S1 and C S2 Includes ).

[0046] First sampling capacitor (C S1 ) is connected to the non-inverting terminal (+) of the operational amplifier (30), and the second sampling capacitor (C S2 ) is connected to the inverting terminal (-) of the operational amplifier (30).

[0047] Specifically, the first sampling capacitor (C S1 One electrode of ) is connected to the non-inverting terminal (+) of the operational amplifier (30), and the first sampling capacitor (C S1 The other electrode of ) is the input voltage (V IN ) is connected to an input terminal (10) into which input is received. And, the first switch (SW1) performs a switching operation according to the first clock signal (φ1), and the first sampling capacitor (C S1 It is connected in parallel to ).

[0048] Second sampling capacitor (C S2 One electrode of ) is connected to the inverting terminal (-) of the operational amplifier (30), and the second sampling capacitor (C S2 The other electrode of ) is connected to the input terminal (10) by a second switch (SW1) that performs a switching operation according to the first clock signal (φ1).

[0049] The third switch (SW3) controls the connection between the output of the operational amplifier (30) and the inverting terminal (-) of the operational amplifier (30) according to the first clock signal (φ1), and the fourth switch (SW4) controls the connection between the output of the operational amplifier (30) and the second switch (SW2) according to the second clock signal (φ2).

[0050] To eliminate the DC offset, the transition process of the clock signal applied to each switch is the same as the transition process described in FIGS. 1 and 2. That is, during the sampling interval (Ts in (B) of FIG. 1), the first clock signal (φ1) is at a high level and the second clock signal (φ2) is at a low level. And, during the operating interval of the actual operational amplifier (30) (T in (B) of FIG. 1) H In ), the first clock signal (φ1) is transitioned from a high level to a low level, and the second clock signal (φ2) is transitioned from a low level to a high level.

[0051] As such, in the DC offset removal circuit according to the third embodiment of the present invention, a sampling capacitor is connected to either the non-inverting terminal (+) or the inverting terminal (-) of an operational amplifier (30) used as a buffer, and the input signal (V IN Unlike the embodiments of FIG. 1 and 2, in which distortion of the output signal due to the DC offset effect occurs according to the charge injection phenomenon in either transition direction (L→H or H→L), sampling capacitors (C) are installed at both the non-inverting terminal (+) and the inverting terminal (-) of the operational amplifier (30). S1 and C S2 The presence of ) cancels out the charge injection characteristics of the input signal, allowing for the implementation of a DC offset structure with higher accuracy.

[0052] FIG. 4 is a graph showing the characteristics of charge injection according to the auto zero DC offset removal circuit shown in FIG. 1, and FIG. 5 is a graph showing the characteristics of charge injection according to the auto zero DC offset removal circuit shown in FIG. 2. FIG. 6 is a graph showing the characteristics of charge injection according to the auto zero DC offset removal circuit shown in FIG. 3.

[0053] The graphs shown in Figures 4 and 5 are examples of input / output characteristics according to DC offset removal characteristics, representing the results of simulating the error of the output signal according to the change in the input signal after sampling from 1 μs to 0.5 μs. In the DC offset removal circuits according to Figures 1 and 2, it can be seen from the simulation results in Figures 4 and 5 that a residual offset error always occurs due to the charge injection phenomenon as the input signal changes.

[0054] Figure 6 shows the simulation results under the same input conditions as the structure of Figure 3 when two sampling capacitors of the same size (capacitance) are added to both terminals of the operational amplifier. From the simulation results of Figure 6, the characteristics of the proposed auto zero DC offset structure, which is hardly affected by residual DC offset due to changes in the input signal, can be confirmed. In addition, the size of the sampling capacitor used can be reduced to approximately 1 / 10 of its original size, making it a very useful structure, especially when applied to a display driver.

[0055] As described above, the present invention relates to a method for removing DC offset to transmit the input voltage of a unit gain buffer for driving low impedance directly to the output.

[0056] DC offset always occurs in operational amplifier circuits due to device mismatch, and specifically, depending on the input offset characteristics, a difference arises between the output voltage and the input voltage of a unit gain buffer composed of operational amplifiers.

[0057] Particularly in the case of display panel source drivers, changes in output voltage caused by DC offset errors alter the voltage delivered to the display panel, resulting in signal distortion and failure to achieve the desired resolution characteristics. Therefore, the method for removing the input DC offset of the operational amplifier is highly sensitive. Specifically, this study proposes a new structure to improve the characteristics of the auto-zero DC offset removal method, which stores the input offset in a capacitor and removes it during actual operation.

[0058] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

Claims

Claim 1 A DC offset removal circuit for an operational amplifier that outputs an input voltage as is, comprising: a first sampling capacitor connected between a non-inverting input terminal of the operational amplifier and an input terminal to which the input voltage is input; a second sampling capacitor connected between an inverting input terminal of the operational amplifier and an input terminal; a first switch connected in parallel to the first sampling capacitor; a second switch controlling the connection between the input terminal and the second sampling capacitor; a third switch controlling the connection between the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier; and a fourth switch controlling the connection between the input terminal and the output terminal of the operational amplifier, wherein the first switch, the second switch, and the third switch perform a switching operation according to a first clock signal, and the fourth switch performs a switching operation according to a second clock signal. Claim 2 delete Claim 3 In claim 1, the fourth switch is a DC offset removal circuit of an operational amplifier that controls the connection between the output of the operational amplifier and the second switch according to the second clock signal. Claim 4 A DC offset removal circuit of an operational amplifier according to claim 1, wherein in the sampling interval, the first clock signal is at a high level and the second clock signal is at a low level. Claim 5 A DC offset removal circuit of an operational amplifier according to claim 1, wherein during the operation period of the operational amplifier, the first clock signal is transitioned from a high level to a low level and the second clock signal is transitioned from a low level to a high level. Claim 6 A DC offset removal circuit for an operational amplifier according to claim 1, wherein the first sampling capacitor and the second sampling capacitor are respectively connected to the non-inverting terminal and the inverting terminal of the operational amplifier, so as to cancel out the voltage injection (charge injection) characteristics for the input voltage. Claim 7 In claim 1, the DC offset removal circuit of the operational amplifier is a DC offset removal circuit of the operational amplifier that is applied to a display driver.

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