Manufacturing method and manufacturing device for superconducting qubit devices

Abstract

A superconducting qubit device and manufacturing method according to the present invention relate to a periphery gap structure that structurally avoids contact between a Josephson junction and an insulating layer, and a method for manufacturing the same. A Josephson junction comprising first and second superconducting electrodes and an insulating film between them is formed on a substrate, and a process flow including a sacrificial layer spacer, deposition angle control, ion milling, and lift-off / selective etching is applied to leave a gap between the junction and an insulating layer disposed on the side or periphery of the junction. The gap includes at least one of a sidewall gap, an overhang lower undercut gap, and an upper trench-type gap, and forms a continuous or functionally continuous blocking path around the junction.

Description

Technology Field

[0001] The present disclosure relates to a method and apparatus for manufacturing a superconducting qubit device. Background Technology

[0002] A quantum computer is an information processing system that performs calculations using quantum mechanical phenomena such as quantum superposition and quantum entanglement. Since a qubit, the basic unit of information, can be represented in a superposition state, N qubits form a 2^N state space. To ensure this scalability, superconductor-based qubits, which are easy to control at high frequencies and can be manufactured using integrated technology, have been actively researched.

[0003] Superconducting qubits are generally composed of Josephson junctions with a superconducting-insulator-superconducting (SIS) structure, capacitors, and inductors. Type 1 superconductors, such as Al / AlOx / Al and Nb, are used as representative material systems, and the critical current, capacitance, and impedance of the junction are determined by the oxidation process, deposition conditions, and lithography geometry. To satisfy high-quality requirements, ultra-high vacuum-based thin film deposition and microfabrication technologies are required.

[0004] Conventional technologies have attempted to reduce noise through junction dimension miniaturization, layout optimization, the introduction of low-loss materials, cryogenic line filtering, and electromagnetic shielding. However, it is difficult to simultaneously satisfy the fundamental reduction of losses at the junction-insulator interface and the management of losses and noise in superconducting vertical connections and cross-wiring within stacked structures. Furthermore, from the perspective of manufacturing equipment, there is a need for equipment configurations capable of continuous operation without atmospheric exposure between processes, as well as uniform oxidation control, precise alignment, and fine undercut control capabilities. The problem to be solved

[0005] The present disclosure aims to provide a method and apparatus for manufacturing a superconducting qubit device. means of solving the problem

[0006] A superconducting qubit device according to the present embodiment comprises: a substrate; a Josephson junction comprising a first superconducting electrode and a second superconducting electrode formed on the substrate and an insulating film disposed between the electrodes; an insulating layer disposed on the side or periphery of the Josephson junction, formed to have a gap between it and the Josephson junction to avoid direct contact with the active region of the Josephson junction; and wiring electrically connected to the electrodes of the Josephson junction; wherein the gap is formed to minimize the contact surface between the insulating layer and the Josephson junction.

[0007] A superconducting qubit device according to one embodiment may be formed such that air gaps face each other with the Josephson junction in between. The insulating layer may be arranged so that it faces each other with the air gap in between.

[0008] The above gap and the above insulating layer can have the same height.

[0009] The insulating layer may have a structure sandwiched between the first superconducting electrode and the second superconducting electrode.

[0010] The above gap may form a continuous or functionally continuous blocking path along the perimeter of the Josephson junction.

[0011] A method for manufacturing a superconducting qubit device according to the present embodiment comprises: a step of forming a superconducting layer on a substrate; a step of depositing a photosensitive material and securing a space for depositing a sacrificial material; a step of depositing a sacrificial material to form a sacrificial layer; a step of depositing an insulator on the side of the sacrificial layer; a step of depositing a first superconducting layer in a space formed by etching the photosensitive material; a step of oxidizing the surface of a superconductor to form an insulating film; a step of depositing a second superconducting layer to form a Josephson junction; a step of forming an insulating layer around the Josephson junction; and a step of etching and removing the sacrificial layer to form a void between the Josephson junction and the insulating layer. A method for manufacturing a superconducting qubit device according to the present embodiment comprises: a step of forming a superconducting layer on a substrate; a step of depositing a photosensitive material and securing a space for depositing a sacrificial material; a step of depositing a sacrificial material to form a sacrificial layer; a step of depositing an insulator on the side of the sacrificial layer; a step of depositing a first superconducting layer in a space formed by etching the photosensitive material; and a step of oxidizing the surface of a superconductor to form an insulating film. The method may include the steps of: depositing a second superconducting layer to form a Josephson junction; forming an insulating layer around the Josephson junction; and etching and removing a sacrificial layer to form a void between the Josephson junction and the insulating layer.

[0012] The step of forming the sacrificial layer may be a step of forming the sacrificial layer so as to face with respect to the region where the Josephson junction is to be formed.

[0013] The step of forming the insulating layer may be a step of forming them so that they face each other with the sacrificial layer in between.

[0014] The first and second superconducting layers may be formed to have a step difference in an uneven shape toward the central portion where the Josephson junction is located.

[0015] By controlling the thickness of the sacrificial layer and the deposition thickness of the insulating layer, the height of the void formed by the removal of the sacrificial layer can be the same as the height of the insulating layer.

[0016] The method may further include a step of adjusting the pattern of the sacrificial layer so that the voids form a continuous or functionally continuous blocking path along the perimeter of the Josephson junction. Effects of the invention

[0017] The method for manufacturing a superconducting qubit and the superconducting qubit device according to the present invention have the effect of effectively reducing external noise by forming a gap between the Josephson junction and the insulating layer to minimize the contact surface. Accordingly, the relaxation time and dephasing time of the qubit can be improved by suppressing charge transfer caused by internal defects in the substrate or coupling with the TLS (two-level system). Additionally, unlike conventional Josephson junctions which are formed in a horizontal direction, the present invention enables the implementation of a stacked quantum processor by manufacturing it in a vertical structure.

[0018] In addition, the method for manufacturing a superconducting qubit according to the present invention and the superconducting qubit device according thereto are characterized by having a Josephson junction structure formed through an insulating layer formed in the middle, wherein a first superconducting layer (110d) with a central portion protruding upward in an uneven shape and a second superconducting layer (110u) with a central portion protruding downward in an uneven shape face each other, and by having an air gap structure in the left and right opposing layers surrounding the Josephson junction, external noise suppression, preservation of junction characteristics, wiring stabilization, and manufacturing process compatibility can be achieved.

[0019] In short, the method for manufacturing a superconducting qubit according to the present invention and the superconducting qubit device according thereto provide a combination of advantages such as suppressing external noise, preserving junction characteristics, stabilizing wiring, and manufacturing process compatibility, thereby improving the coherence time and reliability of the superconducting qubit and enabling a stacked structure, so that it can be utilized as a core foundational technology for realizing a large-scale quantum computer. Brief explanation of the drawing

[0020] FIG. 1 is a cross-sectional view of a superconducting qubit according to the prior art. FIG. 2 is a cross-sectional view of a Josephson junction structure of a superconducting qubit according to the present invention. FIGS. 3 to 10 are drawings sequentially illustrating the process of manufacturing a superconducting qubit according to FIG. 2. FIG. 11 is a flowchart illustrating a superconducting qubit process according to the present invention. Specific details for implementing the invention

[0021] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the attached drawings. However, the technical concept of the present invention is not limited to the following embodiments but can be implemented in various different forms. The following embodiments are provided merely to complete the technical concept of the present invention and to fully inform those skilled in the art of the scope of the present invention, and the technical concept of the present invention is defined only by the scope of the claims.

[0022] It should be noted that when assigning reference numerals to the components of each drawing, the same components are assigned the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present invention, if it is determined that a detailed description of related known components or functions could obscure the essence of the invention, such detailed description is omitted.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. The terms used herein are for describing embodiments and are not intended to limit the present invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text.

[0024] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present invention. These terms are intended merely to distinguish the components from other components, and the nature, order, or sequence of the components is not limited by such terms. Where it is stated that a component is "connected," "combined," or "joined" to another component, it should be understood that the component may be directly connected or joined to the other component, but that another component may also be "connected," "combined," or "joined" between each component.

[0025] As used in the present invention, "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements.

[0026] Components included in any one embodiment and components having common functions may be described using the same names in other embodiments. Unless otherwise stated, the descriptions in any one embodiment may also apply to other embodiments, and specific descriptions may be omitted within the scope of overlap or within the scope that is obvious to a person skilled in the art.

[0027] Hereinafter, several embodiments of the present invention will be described in detail with reference to the attached drawings.

[0028] Hereinafter, the present invention will be described in detail with reference to preferred embodiments of the present invention and the accompanying drawings.

[0029] Referring to FIG. 1, a conventional structure (100') includes an insulating layer (110') formed on an insulating substrate (SUB) and a Josephson junction electrode (120') deposited thereon. The Josephson junction is typically implemented as a superconducting-insulator-superconducting stack, and upper and lower superconducting electrodes and an ultrathin insulating film between them are formed. In the conventional process, the area around the junction active region is directly filled or in contact with the interlayer insulating layer (110'), resulting in a shape where the electric field is concentrated at the junction edge and the lower interface.

[0030] As shown in FIG. 1, process-origin defects, surface roughness, non-stoichiometric oxides, dangling bonds, etc. may exist within the substrate (SUB) or at the boundary between the substrate and the insulating layer (110'), and these act as charge traps, causing localized charge accumulation (yellow symbols in the figure). These charge traps charge and discharge over time and cause accidental charge fluctuations near the junction active region. Consequently, unintended paths for supercurrents flowing through the junction are formed (red arrows in the figure), or instantaneous fluctuations in the junction critical current increase, which can destabilize the junction characteristics.

[0031] Additionally, at the junction edge of FIG. 1, the electric field leaks strongly in the direction of the insulating layer (110') and the substrate (SUB), and combines with a set of two-level systems (TLS) distributed within and at the interface of these dielectrics. TLS are quantum defects sensitive to electric fields and are the primary cause of dielectric loss and charge noise (1 / f noise), resulting in energy loss (T1 degradation) and phase disturbance (T2, particularly dephasing time reduction) in the qubit. In conventional structures, the junction active region and the insulating layer are in direct contact or very close to each other, which increases the interaction between the electric field around the junction and the TLS, resulting in complex degradation mechanisms such as increased dielectric loss tangent, critical current flicker noise, and residual quasiparticle-induced noise.

[0032] Furthermore, local impedance non-uniformity is prone to occur near the bottom and corners of the junction due to step-coverage non-uniformity, partial retention of native oxide film, and plasma / etching damage, which causes fluctuations in contact resistance and an increase in parasitic capacitance at the wiring-junction joint. These parasitic components can be observed as phenomena such as drift of the resonant frequency, absorption dips in the spectrum, and micro-resonator splitting, which ultimately degrade the operational stability and reproducibility of the qubit.

[0033] Referring to FIG. 2, the device (100) comprises an insulating substrate (SUB), a first superconducting layer (110d) formed on the substrate, and a Josephson junction (120) disposed above a protruding central portion of the first superconducting layer (110d). The Josephson junction (120) has a superconducting-insulator-superconducting structure composed of an ultrathin insulating film mediated between the first superconducting layer (110d) and the second superconducting layer (110u).

[0034] A feature of this embodiment is that a void space (a gap) is formed within the insulating layer (220) so that the side and perimeter of the Josephson junction (120) do not come into direct contact with the insulating layer (220). That is, the insulating layer (220) surrounds the junction active region, but is processed to leave a space with a predetermined gap between the edge of the junction and the insulating layer (220), thereby structurally separating the junction active region from the dielectric.

[0035] A superconducting qubit device including the above-mentioned void structure can be formed by the following process.

[0036] A superconducting layer can be formed on a substrate (sub), a photosensitive material (210) can be deposited, and a space can be secured through lithography to form a sacrificial layer corresponding to the location of the void. Subsequently, a sacrificial material is deposited to form a sacrificial layer (230l, 230r), which may be located at a position immediately separated from the area where the Josephson junction is to be formed. Next, an insulator (220) can be deposited on the side of the sacrificial layer, and a first superconducting layer can be deposited in the central space formed by etching the photosensitive material. At this time, the additionally deposited first superconducting layer (110d) may be deposited only up to an intermediate position at the height of the insulating layer (220), taking into consideration the location of the formation of the Josephson junction (see FIG. 7). An insulating film (120) can be formed by oxidizing the surface of the superconductor. A second conductive layer (110u) can be deposited on the insulating film (120) to form the Josephson junction. The second conductive layer (110u) can be deposited to cover the upper surface of the insulating layer (120), the sacrificial layer (230l, 230r), and the upper surface of the insulating layer (220). Finally, the sacrificial layer (230l, 230r) can be etched away to form a void between the Josephson junction (120) and the insulating layer (220).

[0037] The device utilizes Josephson energy through an ultrathin insulating film (120) between the first superconducting layer (110d) and the second conductive layer (110u). The configuration is based on a structure in which an insulating layer (220) surrounding the junction is defined and has a gap arranged so as not to come into direct contact with the edge of the junction. The gap can be formed continuously along the sidewall and perimeter of the junction and can be extended into a multi-gap structure including one or more of a sidewall gap, an undercut gap, and a trench-type gap. If necessary, the first and second superconducting layers may additionally include a connection pad, a ground plane, a shunt capacitor electrode, a read resonator electrode, and a control line electrode.

[0038] The air gap around the junction reduces the electric field participation ratio of the dielectric, thereby suppressing loss due to the dielectric loss tangent. Accordingly, the qubit's energy relaxation time and phase consistency time This has an increasing effect. The air gap alleviates electric field concentration at the junction edge, thereby reducing leakage current caused by edge defects and microcracks, and the junction's critical current It reduces inter-chip dispersion of junction resistance. Additionally, since parasitic capacitance around the junction is replaced by air / vacuum media via the air gap, the reproducibility of design values ​​is improved and frequency drift is reduced.

[0039] Voids reduce 1 / f noise by weakening the coupling of two-level system (TLS) defects and surface spin noise that are activated at low temperatures. By mechanically separating the junction from the dielectric, the transfer of thermal and mechanical stress is mitigated, and the degradation of junction properties caused by residual stress between stacked films with different coefficients of thermal expansion is suppressed. Phonon coupling and quasiparticle inflow pathways around the junction are reduced, thereby decreasing non-equilibrium quasiparticle-induced loss.

[0040] This structure increases the degree of freedom in the design of shunt capacitors and coupled capacitors. Since the effective capacitance can be finely tuned by adjusting the width and depth of the gap between the junction and the insulating layer (220), it is suitable for various qubit architectures such as transmon and fluxsonium. The ratio can be set using only process parameters. Since the electrical coupling strength with the reading resonator or control line can also be adjusted by the gap dimensions and the continuity of the gap, the process tolerance for over-coupling and under-coupling is expanded.

[0041] As a process variation example, the pattern of the sacrificial layer (230l, 230r) can be changed to form a sidewall gap with a certain width along the junction sidewall, or the area below the first superconducting layer (110d) can be selectively retracted to form an undercut gap. Additionally, a trench-type void that opens to the top of the insulating layer (220) can be formed to facilitate plasma cleaning and residual gas discharge. The void dimensions can be set, for example, in the range of 10 nm to 500 nm, and the sacrificial layer material is selected from polyimide, PMMA, SiO2, Al₂O₃, etc., and can be removed by selective wet or dry etching of the material. The junction insulating film can be replaced with MgO, Nb2, O5, etc., in addition to the native oxide film of Al (AlO).

[0042] In terms of integration, junction structures containing air gaps can be implemented in parallel with air-bridges and through-insulation vias to suppress cross-parasitic modes and parasitic capacitance while maintaining wiring density. Since dielectric contact around the junction is minimized even in a flip-chip 3D stacking environment, the increase in packaging-derived losses is mitigated and wafer-scale yield is improved.

[0043] Figures 3 through 11 illustrate a process flow according to a preferred embodiment of the present invention, and each figure schematically represents the key steps of a sequential process. The figures are schematic diagrams for convenience of explanation and may differ from actual dimensions or proportions. The materials, thicknesses, and process conditions at each step can be modified according to design requirements.

[0044] Referring to FIG. 3, a superconducting layer (110d) can be deposited on a substrate (SUB). A lower superconducting layer (110d) is deposited on the substrate (SUB). The substrate may be one of Si, sapphire, high-resistance Si, or SiC. The lower superconducting layer may be formed with a thickness of 30 to 300 nm by sputtering or electron beam deposition using materials such as Al, Nb, NbN, or MoRe. Before deposition, O2 plasma cleaning or Ar ion milling may be performed to remove organic contaminants from the surface. After deposition, marks for photo-alignment are exposed and patterned to ensure subsequent alignment precision.

[0045] Referring to FIG. 4, a photosensitive layer (210) is deposited on a superconducting layer (110d), and then an aperture can be formed through lithography. A photosensitive layer (210) is applied to the lower superconducting layer (110d) with a thickness of 200 to 1000 nm. An aperture is formed at a location where Josephson junctions and voids are to be formed through photolithography (or electron beam lithography). After development, low-power O2 plasma decum can be performed to remove residual resist. Since the width of the aperture serves as a reference for defining the void width thereafter, it is designed in the range of 20 to 500 nm.

[0046] Referring to FIG. 5, a sacrificial layer (230l, 230r) can be deposited in the opening. A sacrificial layer (230l, 230r) is deposited inside the opening. The sacrificial layer material may be one of polyimide, PMMA, LOR, SiO2, or Al₂O₃, which can be selectively removed later. After spin coating or deposition, the left and right separated sacrificial layers (230l, 230r) are formed by lift-off or patterning. The thickness of the sacrificial layer defines the width and depth of the final void and is set in the range of 10 to 500 nm.

[0047] Referring to FIG. 6, the photosensitive layers on the left and right sides of the sacrificial layers (230l, 230r) are removed, and an insulating layer (220) is deposited. The photosensitive layers (210) on the left and right sides of the sacrificial layers (230l, 230r) are removed, and an insulating layer (220) is deposited in the exposed area. The insulating layer is SiO 2, It can be composed of SiN, Al₂O₃, HfO₂, etc., and is formed to a thickness of 50 to 500 nm by PVD, PECVD, or ALD. At this stage, the insulating layer (220) surrounds the perimeter of the junction active region and is formed to be in direct contact with the sacrificial layer so that a gap remains between the junction and the insulating layer when the sacrificial layer is subsequently removed.

[0048] Referring to FIG. 7, the photosensitive layer in the middle of the sacrificial layers (230l, 230r) is etched away and a superconducting layer is deposited. The photosensitive layer (210) in the central part between the sacrificial layers (230l, 230r) is selectively etched away and the central upper surface of the exposed lower superconducting layer (110d) is revealed. If necessary, the oxide film is thinly removed by low-power Ar milling to ensure the cleanliness of the metal-insulating film interface. Subsequently, a shallow reinforcing film (e.g., 5 to 50 nm of the same material as 110d) can be locally deposited to match the height of the junction lower electrode.

[0049] Referring to FIG. 8, the surface of the superconducting layer deposited in the sacrificial layer (230l, 230r) is oxidized to form an insulating layer, thereby forming part of the Josephson junction (120) structure. The surface of the lower electrode exposed in FIG. 7 is oxidized to form an ultrathin insulating film (120). For example, in the case of an Al lower electrode, natural oxidation or accelerated oxidation can be performed for several seconds to several minutes in a purified oxygen atmosphere (several mTorr to several hundred mTorr) to form AlO with a thickness of 0.5 to 2.5 nm. In the case of Nb-based materials, NbO can be formed by plasma oxidation or annealing after oxygen injection. The thickness and uniformity of the insulating film are related to the junction critical current Since it directly affects noise characteristics, process parameters are controlled in a closed loop.

[0050] Referring to FIG. 9, an upper superconducting layer (110u) is deposited to complete the Josephson junction (120) structure. An upper superconducting layer (110u) is deposited on the junction insulating film (120). The upper electrode material may be the same as or different from the lower electrode and is deposited with a thickness of 30 to 300 nm. The upper superconducting layer is formed to completely cover the upper surface of the insulating film (120) and simultaneously continuously cover the upper surface of the sacrificial layer (230l, 230r) and the upper surface of the insulating layer (220) to ensure electrical continuity between the junction electrodes. If necessary, the upper electrode pattern is defined by lift-off or dry etching.

[0051] Referring to FIG. 10, a sacrificial layer is etched to form a void structure. By selectively etching and removing the sacrificial layer (230l, 230r), a void is formed between the Josephson junction (120) and the insulating layer (220). If the sacrificial layer is a polymer, it can be removed by O2 plasma or an organic solvent (e.g., NMP), and if it is an inorganic sacrificial layer (e.g., SiO2), it can be removed by hydrofluoric acid-based wet etching or gaseous HF. After removal, air or vacuum is present in the void, and a continuous gap is formed between the junction sidewall / perimeter and the insulating layer (220). If necessary, residual solvent / gas is removed by low-temperature baking (<150 °C) or cryopumping to ensure the cleanliness of the inside of the void.

[0052] The following variations may be implemented in a superconducting qubit device manufactured according to this process.

[0053] One or more of the sidewall gaps, undercut gaps, and trench-type gaps can be selectively implemented by adjusting the thickness and pattern of the sacrificial layer and the taper angle of the sidewall of the insulating layer (220).

[0054] The pore width can be set to 10–500 nm and the depth to 20–800 nm.

[0055] A modified example is possible in which a thin cap layer (e.g., 2-5 nm Al) is deposited and then removed to protect the junction active region before removing the sacrificial layer.

[0056] After forming pores, surface organic residues can be removed using a low-power O2 / Ar mixed plasma to reduce TLS defect density.

[0057] A resonator / control line electrode and a shunt capacitor electrode are integrally formed on the upper superconducting layer (110u), and the design ensures that parasitic capacitance around the junction is replaced by an air / vacuum medium due to the air gap, thereby fine-tuning the coupling strength and Ej / Ec ratio as process parameters.

[0058] Hereinafter, FIG. 11 is said to be a flowchart illustrating a method for manufacturing a superconducting qubit according to a preferred embodiment of the present invention. Each step is for convenience of explanation and may be omitted, modified, or performed in parallel depending on process equipment and design conditions.

[0059] In step S101, a superconducting layer is formed on a substrate. The substrate may be an insulating or semi-insulating material such as sapphire or silicon, and the superconducting material is a metal film such as aluminum or niobium, deposited with a uniform thickness by sputtering, evaporation, or atomic layer deposition (ALD). Surface cleaning (plasma / ion milling) and moisture and temperature control are preferred prior to deposition.

[0060] In step S102, a photosensitive material is deposited, and lithography is used to create space for placing the sacrificial material. An aperture is formed by exposing and developing the spin-coated resist, and the sidewall slope or undercut of the aperture is designed to provide a shielding effect during subsequent angle deposition. This pattern defines the trench / spacer region where the sacrificial layer and adjacent insulator will be located.

[0061] In step S103, a sacrificial material is deposited. The sacrificial layer can be implemented as a lift-off resist (LOR), an organic resist, or an inorganic film with excellent selective etching properties (such as SiO2 or Al₂O₃), and tilt-controlled deposition or frontal deposition can be applied so that it is locally embedded within the opening. The sacrificial layer functions as a shielding structure to form a void through a subsequent removal process.

[0062] In step S104, lithography is used to create spaces for placing insulating materials on both sides of the sacrificial layer. An opening for the insulating material is defined through additional exposure and development, and the spacing with respect to the sacrificial layer is set considering the target width of the void around the junction and the dielectric participation rate.

[0063] In step S105, an insulating material is deposited on both sides of the sacrificial layer. Low-loss dielectrics such as SiN, SiO₂, and Al₂O₃ can be used as the insulator, and sidewall coverage and film quality (loss tangent) are secured by selecting PVD, ALD, or CVD. This insulating layer contributes to subsequent wiring / junction protection and impedance control.

[0064] In step S106, the photoresist is etched to create a qubit manufacturing space. By removing the resist through lift-off or dry / wet etching, an opening (manufacturing space) to be deposited with superconducting junctions and wiring is exposed. If necessary, low-energy plasma cleaning is performed to remove fine contamination.

[0065] In step S107, a superconductor is deposited in the qubit manufacturing space. Overgrowth is suppressed using a deposition angle and a shielding structure (sacrificial layer / insulating layer) so that the superconducting metal, which functions as a bottom electrode, grows locally in the active region of the bottom of the aperture.

[0066] In step S108, the superconducting surface is oxidized through an oxidation process. The thickness and uniformity of the tunnel insulation film are controlled by exposure to an oxygen atmosphere or plasma oxidation, which are key parameters determining the junction critical current (Ic) and steady-state resistance (Rn).

[0067] In step S109, a superconductor is deposited on a superconducting oxide, an insulator, and a sacrificial material. The upper electrode is deposited to overlap the lower electrode with the oxide interposed between them, and the shielding effect of the surrounding insulator and sacrificial layer suppresses film bridging in the sidewall direction. This completes the Josephson junction of the superconducting / oxide / superconducting (SIS) stack.

[0068] In step S110, the sacrificial layer is etched away. Removing the sacrificial material by selective wet or dry etching creates a void between the junction and the insulating layer. The void structurally blocks direct contact between the junction active part and the dielectric, thereby reducing the dielectric participation rate and TLS (dual-level system) coupling, and contributing to noise reduction and improved dephasing time. If necessary, the process is terminated through subsequent via / trench machining, passivation, and electrical characteristic testing.

[0069] As described above, exemplary embodiments have been invented in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used merely for the purpose of explaining the technical concept of the invention and are not intended to limit the meaning or the scope of the invention as described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the invention should be determined by the technical concept of the appended claims.

Claims

Claim 1 A superconducting qubit device comprising: a substrate; a Josephson junction including a first superconducting electrode formed on the substrate, a second superconducting electrode perpendicularly opposite to the direction in which the first superconducting electrode and the substrate extend, and an insulating film disposed between the electrodes; an insulating layer disposed on the side or periphery of the Josephson junction, formed to have a gap between it and the Josephson junction to avoid direct contact with the active region of the Josephson junction; and wiring electrically connected to the electrodes of the Josephson junction; wherein the gap is interposed between the active region of the Josephson junction and the insulating layer. Claim 2 A superconducting qubit device according to claim 1, characterized in that the above-mentioned gaps are formed to face each other with the Josephson junction in between. Claim 3 A superconducting qubit device according to paragraph 2, characterized in that the insulating layers are arranged to face each other with the air gap in between. Claim 4 A superconducting qubit device according to paragraph 3, characterized in that the above-mentioned gap and the above-mentioned insulating layer have the same height. Claim 5 A superconducting qubit device according to claim 1, characterized in that the insulating layer has a structure sandwiched between the first superconducting electrode and the second superconducting electrode. Claim 6 A superconducting qubit device according to claim 1, wherein the air gap forms a continuous or functionally continuous blocking path along the circumference of the Josephson junction. Claim 7 A method for manufacturing a superconducting qubit device, comprising: a step of forming a superconducting layer on a substrate; a step of depositing a photosensitive material and securing a space for depositing a sacrificial material; a step of depositing a sacrificial material to form a sacrificial layer; a step of depositing an insulator on the side of the sacrificial layer to form an insulating layer; a step of etching the photosensitive material to form a first superconducting layer in the space formed; a step of oxidizing the surface of a superconductor to form an insulating film; a step of depositing a second superconducting layer to form a Josephson junction; and a step of etching and removing the sacrificial layer to form a void between the Josephson junction and the insulating layer. Claim 8 A method for manufacturing a superconducting qubit device according to claim 7, wherein the step of forming the sacrificial layer is a step of forming the sacrificial layer so as to be opposite with respect to the region where the Josephson junction is to be formed. Claim 9 A method for manufacturing a superconducting qubit device according to claim 8, wherein the step of forming the insulating layer is a step of forming them so as to face each other with the sacrificial layer in between. Claim 10 A method for manufacturing a superconducting qubit device according to claim 7, wherein the first superconducting layer and the second superconducting layer are formed to have a step difference in an uneven shape toward the central portion where the Josephson junction is located.

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