Memory module and method of manufacturing the same

Abstract

The present invention relates to an electronic device, wherein a memory module according to the present invention comprises a substrate, eight or sixteen stacked memory devices mounted on the front and rear surfaces of the substrate, respectively, and a host die mounted on the substrate and communicating with the eight or sixteen stacked memory devices, and the substrate may include a connection portion comprising pin blocks corresponding to each of the eight or sixteen stacked memory devices.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory module and a method for manufacturing the same. Background Technology

[0002] As semiconductor technology advances rapidly, there is an increasing demand for higher integration and performance in packaging technology for semiconductor devices. Consequently, technologies regarding three-dimensional structures in which multiple semiconductor chips are vertically stacked are developing in various ways, moving away from two-dimensional structures in which semiconductor chips containing integrated circuits are arranged planarly on a printed circuit board (PCB) using wires or bumps. The problem to be solved

[0003] An embodiment of the present invention provides a memory module for a cache memory or main memory that provides increased memory capacity while using the same form factor, and a method for manufacturing the same. means of solving the problem

[0004] A memory module according to an embodiment of the present invention comprises a substrate, eight or sixteen stacked memory devices mounted on the front and rear surfaces of the substrate, respectively, and a host die mounted on the substrate and communicating with the eight or sixteen stacked memory devices, wherein the substrate may include a connection portion comprising pin blocks corresponding to each of the eight or sixteen stacked memory devices.

[0005] In an embodiment, the stacked memory device may be a High Bandwidth Memory (HBM).

[0006] In the embodiment, the substrate may be a glass core substrate.

[0007] In an embodiment, the 8 or 16 stacked memory devices can each be connected to the substrate through 1,024 or 2,048 pins.

[0008] In an embodiment, each of the 8 or 16 stacked memory devices includes 16 DRAM core dies stacked in a vertical direction and can be connected to the substrate through 1,024 (or 2,048) pins.

[0009] In an embodiment, the pin block may include a plurality of pins arranged in an array form in 8 rows and 8 columns.

[0010] In an embodiment, the pin block may include a plurality of pins arranged in an array form in 16 rows and 16 columns.

[0011] In an example, the number of pin blocks included in the substrate may be 256.

[0012] In an example, the number of pin blocks included in the substrate may be 1,024.

[0013] In an embodiment, the memory module may have a DIMM (Dual In-Line Memory Module) form factor. Effects of the invention

[0014] According to the present technology, a cache memory or main memory of an electronic device that provides high capacity in a von Neumann architecture computing system or in the on-device AI domain is provided. Brief explanation of the drawing

[0015] FIG. 1 is a block diagram illustrating an electronic device according to one embodiment of the present invention. Figure 2 is a diagram illustrating a memory module. Figure 3 is a diagram showing the structure of one side of a memory module. Figure 4 is a diagram illustrating the structure of the substrate of Figure 2. Figure 5 is a diagram illustrating the structure of a conventional memory module. FIG. 6 is a drawing for explaining the structure of a memory module according to an embodiment of the present invention. Figure 7 is a drawing for explaining the pin block of Figure 6 in more detail. Figure 8 is a diagram illustrating the process of forming pins on the top surface of a substrate. Specific details for implementing the invention

[0016] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0018] FIG. 1 is a block diagram illustrating an electronic device according to one embodiment of the present invention.

[0019] Referring to FIG. 1, the electronic device (1) may include one of the following: a computer, a portable computer, a UMPC (Ultra Mobile PC), a workstation, a server computer, a net-book, a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, and various electronic devices that constitute a home network.

[0020] The electronic device (1) may include a main memory device (100), a CPU (200), and a system management bus (300). In various embodiments, the electronic device (1) may further include an input device (400), a display device (500), a network device (600), and a storage device (700).

[0021] The main memory device (100) can store data processed by the CPU (200) or operate as the CPU (200)'s working memory. In the embodiment, the main memory device (100) may be a DRAM such as DDR SDRAM (double data rate synchronous dynamic random access memory), LPDDR (low power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus DRAM), etc., or any volatile memory device that requires a refresh operation.

[0022] The main memory device (100) can be manufactured using a semiconductor. The main memory device (100) may have a faster processing speed than the storage device (700). In an embodiment, the main memory device (100) may be a volatile memory.

[0023] A CPU (Central Processing Unit, 200) may be a device that decodes instructions and performs arithmetic logic operations or data processing. The CPU (200) may include an ALU (arithmetic and logic unit, 210), a control unit (220), and a register (230). Although the CPU (200) in FIG. 1 is depicted as including only an ALU (arithmetic and logic unit, 210), a control unit (220), and a register (230), this is merely an exemplary configuration, and the CPU (200) may further include a counter, a cache memory, an instruction decoder, a timing generation circuit, etc.

[0024] The ALU (210) can perform arithmetic logic operations to execute instructions of the electronic device (1).

[0025] The register (230) can store logs related to the operating status of the electronic device (1). The control unit (220) can write a log of the operating status of the electronic device (1) to the register (230) in real time while performing the operation of the electronic device (1). The register (230) may also store time information of the timing of the log operation. The register (230) may, for example, be a polling register of the BIOS, or a register that stores system event logs in the BMC (Board Manage Control).

[0026] The CPU (200) may include a single processor core or multiple processor cores to process data. For example, the CPU (200) may include a multi-core such as a dual-core, quad-core, or hexa-core. Additionally, the CPU (200) may further include a cache memory located internally or externally.

[0027] The input device (400) includes various devices for inputting data or commands into the electronic device (1). For example, the input device (400) may be user input devices such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, temperature sensor, biometric sensor, etc.

[0028] The display device (500) includes various devices that output data to the outside. For example, the display device (500) may include user output devices such as an LCD (Liquid Crystal Display), an OLED (Organic Light Emitting Diode) display device, an AMOLED (Active Matrix OLED) display device, an LED, a speaker, a motor, etc.

[0029] The network device (600) may be a transceiver that enables communication with a device outside the electronic device (1). The network device (600) may be a wired transceiver according to some embodiments, or a wireless transceiver according to some embodiments.

[0030] A storage device (700) can be used to supplement the limited memory capacity of a main memory device (100). The storage device (700) may be non-volatile memory. The storage device (700) may be relatively slower than the main memory device (100). However, it can store a large amount of data semi-permanently.

[0031] The bus (300) can be any various communication links. The bus (300) can be a system management bus (SMBus), an interconnected integrated circuit (I2C) bus, an intelligent platform management interface (IPMI) compatible bus, or a mod bus, etc.

[0032] In an embodiment, the main memory device (100) can be mounted on the electronic device (1) in the form of a memory module.

[0034] Figure 2 is a diagram illustrating a memory module.

[0035] Figure 3 is a diagram showing the structure of one side of a memory module.

[0036] The main memory device (100) described with reference to FIG. 1 can be mounted on an electronic device (1) in the form of a memory module.

[0037] Referring to FIGS. 2 and 3, the memory module (1000) may be a Dual In-line Memory Module (DIMM). In various embodiments, the memory module (1000) may be a Registered DIMM (RDIMM), Load Reduced DIMM (LRDIMM), Unbuffered DIMM (UDIMM), Fully Buffered DIMM (FB-DIMM), Small Outline DIMM (SO-DIMM), or the memory module (1000) may be a Single In-line Memory Module (SIMM). For convenience of explanation, the memory module (1000) is assumed to be a DIMM in this specification.

[0038] The memory module (1000) may include a substrate (110), a host die (120), and a stacked memory device (130).

[0039] The substrate (110) may be a glass core substrate that uses an oxide film and a nitride film as insulating films and forms conductive lines by applying a damascene technique thereon. Generally, the process of applying the damascene technique to an insulating film is a method carried out in the semiconductor front-end process, specifically the FAB process. The substrate (110) included in the memory module (1000) according to the present embodiment can be manufactured by performing Cu plating on an insulating film, which is a glass core substrate, and flattening it through CMP (Chemical Mechanical Polishing) during the back-end process after the semiconductor FAB process is completed.

[0040] The host die (120) can communicate with the stacked memory device (130). In an embodiment, the host die (120) may be a controller that controls the stacked memory device (130). The host die (120) can communicate with the stacked memory device (130) according to the DIMM standard.

[0041] The host die (120) can communicate with the CPU (200) described with reference to FIG. 1. In an embodiment, the host die (120) receives a command and an address from the CPU (200) and can control the stacked memory device (130) to execute the received command on the stacked memory device (130) corresponding to the address.

[0042] The stacked memory device (130) may include a plurality of volatile memories. Each volatile memory may be a Dynamic Random Access Memory (DRAM) core die. That is, the stacked memory device (130) may be a memory device that stacks a plurality of DRAM chips vertically and includes a Through Silicon Via (TSV) that penetrates them.

[0043] A stacked memory device (130) may include a lower chip that is vertically stacked and one or more upper chips. A stacked memory device (130) formed by stacking a plurality of chips in this manner may be a High Bandwidth Memory (HBM). In an embodiment, the lower chip may be an interface die (132). The upper chips may be DRAM core dies (131). The number of DRAM core dies (131) included in the stacked memory device (130) may vary depending on the type of product, capacity, etc. FIG. 2 illustrates an example in which the first to sixteenth DRAM core dies (131) are stacked on the interface die (132).

[0044] Through-silicon vias (TSVs) are formed between the stacked first to sixth DRAM core dies (131), and signals (i.e., commands, addresses, and data) can be transmitted between the first to sixth DRAM core dies (131) and the interface die (132). Meanwhile, a plurality of inter-die microbumps may be disposed between the first to sixth DRAM core dies (131), that is, between the through-electrodes (TSVs). The inter-die microbumps may electrically connect the through-silicon vias (TSVs). The inter-die microbumps may include solder balls or metallic bumps.

[0045] In an embodiment, the stacked memory device (130) can be connected to a substrate through 1,024 pins.

[0046] The interface die (132) may include an interface circuit for communication with the host die (120). The interface circuit of the interface die (132) may be electrically connected to the host die (120) through wiring inside the substrate (110). In an embodiment, the interface die (132) may be a base die. In an embodiment, the substrate (110) and the interface die (132) may be directly connected without an interposer.

[0047] In an embodiment, a plurality of stacked memory devices (130) on a substrate (110) may be integrated on the back side as well as the front side of the substrate (110). The substrate (110) may include a plurality of inner bumps. The plurality of bumps may include solder balls or metallic bumps. For example, the plurality of bumps may include solder balls for supplying power to the stacked memory device (130) and the host die (120), and solder balls for communicating with the outside. The plurality of bumps may include solder balls or metallic bumps that electrically connect the substrate (110) and the interface die (132).

[0048] According to an embodiment of the present invention, the memory module (1000) may include eight stacked memory devices (130) integrated on the front side and eight stacked memory devices (130) integrated on the back side. Alternatively, the memory module (1000) may include 16 stacked memory devices (130) integrated on the front side and 16 stacked memory devices (130) integrated on the back side. That is, the memory module (1000) may include eight stacked memory devices (130) on the front side and one stacked memory device (130) on the back side, or sixteen stacked memory devices (130) on each side.

[0049] When the memory module (1000) includes 8 stacked memory devices (130) on the front side and back side respectively, a total of 16 stacked memory devices (130) are included in the memory module (1000), and when the memory module (1000) includes 16 stacked memory devices (130) on the front side and back side respectively, a total of 32 stacked memory devices (130) can be included in the memory module (1000).

[0050] According to an embodiment of the present invention, the substrate (110) may include a connecting portion (111).

[0051] The connection portion (111) may be a part that connects the memory module (1000) and the electronic device (1). The connection portion (111) may be a part that is electrically connected to, for example, a main board or module board included in the electronic device (1). The connection portion (111) may be mounted by being fastened to a connection slot provided on the main board of the electronic device (1). In an embodiment, the connection portion (111) may include pins or pin blocks having a copper (Cu) or gold material. In various embodiments, the connection portion (111) may include memory gold finger pins.

[0053] Figure 4 is a diagram illustrating the structure of the substrate of Figure 2.

[0054] Referring to FIG. 4, the substrate (110) may include a first circuit layer (112), a glass core layer (113), and a second circuit layer (114). In an embodiment, the first circuit layer (112) and the second circuit layer (114) may be a Re Distribution Layer (RDL). In an embodiment, the RDL may be composed of multiple layers.

[0055] The first circuit layer (112) includes an interface circuit (e.g., RDL circuit) that is electrically connected to some of the stacked memory devices (130) described with reference to FIG. 3, and the second circuit layer (114) may include an interface circuit (e.g., RDL circuit) that is electrically connected to the remaining stacked memory devices (133) (e.g., Layer for DIMM).

[0056] The first circuit layer (112) includes copper wiring connected to the front side of the memory module (1000), and the second circuit layer (114) may include copper wiring connected to the back side of the memory module (1000).

[0057] The glass core layer (113) is a layer made of glass material and has excellent temperature stability due to minimal deformation caused by temperature changes. The glass core layer (113) has a smooth surface, which is advantageous for forming microcircuits and has excellent signal characteristics due to minimal signal loss. In addition, compared to conventional PCB substrates, it has the advantage of high rigidity and large surface area, as its Young's modulus (elastic modulus) is four times that of conventional materials, making it resistant to bending. Although not shown in the drawing, the substrate (110) may further include through glass vias (TGV) that penetrate the first circuit layer (112), the glass core layer (113), and the second circuit layer (114) for interconnection.

[0059] Figure 5 is a diagram illustrating the structure of a conventional memory module.

[0060] Referring to FIG. 5, among the memory modules (50) installed in a conventional PC, the DIMM may include a plurality of DRAM chips (DRAM) integrated on the front side and the back side, and may include a logic die that communicates with a host or communicates with the DRAM chips (DRAM). Generally, in a conventional DIMM, 8 or 16 unstacked single DRAM chips (DRAM) may be integrated on the front side and the back side, respectively.

[0061] For example, the connection portion (51) of a substrate equipped with 16 DRAM chips (DRAM) may include 256 pins connected to the DRAM chips (DRAM) (16 data input / output pins and a plurality of control pins per DRAM chip). In this case, one data input / output pin or control pin may correspond to one gold finger pin, and the connection portion (51) may include a total of 256 gold finger pins. The connection portion (51) can communicate with a host through the 256 pins. The number of pins included in the connection portion (51) may increase or decrease depending on the number of DRAM chips (DRAM) included in the memory module.

[0063] FIG. 6 is a drawing for explaining the structure of a memory module according to an embodiment of the present invention.

[0064] Referring to FIG. 6, a memory module (1000) according to an embodiment of the present invention may include a plurality of high-bandwidth memories (HBM), such as a stacked memory device (130) described with reference to FIG. 2, instead of a plurality of DRAM chips (DRAM) described with reference to FIG. 5. The memory module (1000) may include stacked memory devices (130) integrated with 8 or 16 units each on the front side and the back side.

[0065] The connection portion (111) of the memory module (1000) may include 16,384 (or 32,768) pins connected to the high-bandwidth memory (HBM). Specifically, the connection portion (111) may include a plurality of pin blocks (Pin Block #1 to Pin Block #256) or (Pin Block #1 to Pin Block #512). Each pin block may include 64 pins. The plurality of pin blocks ((Pin Block #1 to Pin Block #256) or (Pin Block #1 to Pin Block #512)) may be placed on both sides (Front / Back Side) of the substrate. In an embodiment, the pins may be bumps, microbumps, solder balls, or metallic bumps. In an embodiment, the pins may be DQ pins or control pins, which are terminals for the stacked memory device (130) to receive or transmit data. The connection portion (111) of the memory module (1000) may have pin blocks added along the vertical axis (column axis), and, for example, if expanded fourfold, may include 65,536 (or 131,072) pins connected to high-bandwidth memory (HBM). At this time, the plurality of pin blocks placed on both sides (Front / Back Side) of the substrate may be 1,024: Pin Block #1 to Pin Block #1,024 (or 2,048: Pin Block #1 to Pin Block #2,048).

[0066] One or two pin blocks may correspond to a single conventional Gold Finger Pin. Accordingly, the memory module (1000) may include High Bandwidth Memory (HBM) instead of a single DRAM chip, while using the same width as the width of the horizontal axis (row axis) occupied by 256 Gold Finger Pins as described with reference to FIG. 5. In the embodiment, the footprint area of ​​the High Bandwidth Memory (HBM) may be larger than the footprint area of ​​the single DRAM chip, and accordingly, the PCB area of ​​the DIMM may be expanded.

[0068] Figure 7 is a drawing for explaining the pin block of Figure 6 in more detail.

[0069] Referring to FIG. 7, the first pin block (Pin Block #1) may include the first pin (Pin #1) to the 64th pin (Pin #64). The second pin block (Pin Block #2) may include the 65th pin (Pin #65) to the 128th pin (Pin #128).

[0070] The first pin (Pin #1) to the 64th pin (Pin #64) included in the first pin block (Pin Block #1) may be in the form of an array where pins are placed at points where 8 rows and 8 columns intersect. The 65th pin (Pin #65) to the 128th pin (Pin #128) included in the second pin block (Pin Block #2) may be in the form of an array where pins are placed at points where 8 rows and 8 columns intersect (8 x 8). In the embodiment, the total length of the 8 rows and 8 columns may each be 500 µm. Therefore, the spacing between pins may be approximately 60 µm.

[0071] In various embodiments, the pins included in the pin block may be placed at the intersection of 16 rows and 16 columns. In this case, the spacing between pins may be about 30 µm.

[0073] A single pin block connected to a connection portion (111) of a memory module according to an embodiment of the present invention may include a total of 64 (or 256) pins by determining the pin pitch, which is the width in the vertical or horizontal direction between a plurality of pins included in the single pin block, to be 60 (or 30) µm, reducing the diameter of the head of each pin to 30 µm (or 15 µm), and arranging the pins in the x-axis and y-axis respectively with 8 (or 16) pins.

[0074] The first circuit layer (112) and the second circuit layer (114) may be formed on the front side and back side of the glass core layer (113). Odd pin blocks, for example, pins 1 through 64 included in the first pin block (Pin Block #1), may be connected to the host die (120) described with reference to FIG. 2 via a copper line (Cu Line) inside the first circuit layer (112). Even pin blocks, for example, pins 65 through 128 included in the second pin block (Pin Block #2), may be connected to the host die (120) described with reference to FIG. 2 via a copper line (Cu Line) and TGV inside the second circuit layer (114).

[0075] A single pin block has a rectangular structure when viewed in a planar view, and can take on a T-shape when viewed in a vertical plane. The pin block is double-stepped, and the planar space occupied by the upper part of the T-shape is 30x30 µm. 2 (or 15x15um) 2 ) and the planar space occupied by the bottom part is 15x15um 2 (or 7.5x7.5um) 2 ) and the height of the top and bottom layers can be 15 µm (or 7.5 µm) each.

[0076] The input / output pins of the high-bandwidth memory (HBM) and the connection part (111) of the substrate can be connected through the method described with reference to FIG. 7.

[0078] Figure 8 is a diagram illustrating the process of forming pins on the top surface of a substrate.

[0079] Referring to FIG. 8, in step S810, a primary insulating film can be formed on a glass substrate. The primary insulating film can generally be SiO2.

[0080] In step S820, a process for etching the location where the pins are joined can be performed (1st Etching).

[0081] In step S830, a process for forming a secondary insulating film may be performed. The secondary insulating film may be a SiNx-based material. Preferably, the secondary insulating film may be silicon nitride (Si3N4).

[0082] In step S840, a process of etching the upper part of the location where the pin is joined can be performed (secondary etching).

[0083] In step S850, a process of applying copper to the etched location can be performed (Cu Plating).

[0084] In step S860, CMP and etching processes can be performed to remove the copper remaining on the top layer and the secondary insulating film.

[0085] Through this, the connection part of the high-bandwidth memory and the substrate are combined, and the connection part of the substrate is connected to a connection slot provided on the main board via a pin, thereby forming a part that can be mounted.

[0087] The embodiment of the present invention described above can be used as a cache-memory product capable of providing high capacity, replacing the existing memory module with a low-capacity cache function (e.g., DRAM module) that has been responsible for the cache memory function in a von Neumann architecture computing system.

[0088] Specifically, the present invention may be a DI-HBM (Dual In-Line HBM) module capable of providing high capacity by mounting HBM instead of a conventional DIMM that is modularized by mounting DRAM. An embodiment of the present invention can be utilized as a new memory semiconductor solution capable of resolving the data shortage required in the field of on-device AI.

[0089] In addition, the present invention relates to a memory module and a method thereof that achieves structural simplification, a low-cost structure through material reduction, and improved yield by mounting HBM instead of DRAM in a conventional DIMM PCB form factor structure and changing the Gold Finger structure of the organic-PCB to a Pin Block with a glass core substrate to sufficiently secure the data I / O required by HBM, while simultaneously eliminating the interposer layer that is essential between the HBM and the organic PCB.

[0090] In addition, to facilitate HBM mounting, the layout of the glass core substrate is designed to match the number of TSVs of the logic IC located in the bottom layer of the HBM, and to connect the TSV interconnection at the bottom of the HBM to the glass core substrate, the existing technology of Cu-Cu direct bonding technology is used, and the Cu layer wiring (e.g., RDL) on the glass core substrate can be applied similarly to the wiring technology of the interposer layer.

[0091] In addition, the TSV technology applied to HBM is applied as TGV (Through Glass Via) technology between the layers of the glass core substrate, thereby enabling the securing of vias that can pass vertically from the top layer DRAM core die of the HBM to the bottom layer of the glass core substrate.

[0092] An embodiment of the present invention relates particularly to a memory module and a method for manufacturing the same, wherein a pin block is formed by expanding the number of pins (I / O pins or control pins) of the Gold Finger structure of the current organic-PCB by 64 times, thereby securing 16,384 (or 32,768) pins (I / O pins or control pins) of a glass core substrate required for mounting 16 (or 32) HBMs, with the current number of 200 to 256 PCB pins (I / O pins or control pins). Furthermore, the invention relates to a memory module and a method for manufacturing the same, wherein if the number of pin blocks is increased fourfold along the column axis, the total number of pins of the glass core substrate is secured to be 65,636 (or 131,072 in the case where the pin pitch is 30 µm).

[0093] In addition, an embodiment of the present invention uses an oxide film and a nitride film as insulating films on a glass core substrate and applies a damascene technique thereon to form conductive pins, and introduces Cu Plating and CMP on the insulating film during the post-processing stage. Explanation of the symbols

[0094] 1: Electronic device 100: Main memory device 200: CPU 210: ALU 220: Control unit 230: Register 240: BUS I / F 300: Bus 400: Input device 500: Display device 600: Network device 700: Storage device

Claims

Claim 1 A memory module comprising: a substrate; eight or sixteen stacked memory devices mounted respectively on the front and rear surfaces of the substrate; and a host die mounted on the substrate and communicating with the eight or sixteen stacked memory devices; wherein the substrate comprises a connection portion including pin blocks corresponding to each of the eight or sixteen stacked memory devices, and the pin block comprises a plurality of pins arranged in an array form in eight rows and eight columns or sixteen rows and sixteen columns. Claim 2 In claim 1, the stacked memory device is a memory module that is High Bandwidth Memory (HBM). Claim 3 In claim 1, the substrate is a memory module that is a glass core substrate. Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 A memory module according to claim 1, wherein the number of pin blocks included in the substrate is 256. Claim 9 A memory module according to claim 1, wherein the number of pin blocks included in the substrate is 1,024. Claim 10 In claim 1, the memory module is a memory module having a DIMM (Dual In-Line Memory Module) form factor.

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