Device for dynamically allocating memory, and operating method thereof

Abstract

The present disclosure provides a semiconductor test device for dynamically allocating memory and a method of operating the same, comprising: a fail memory including a plurality of memory regions for storing fail data generated as a test result for a semiconductor device; a memory allocator that allocates the plurality of memory regions to at least one memory region for each of the at least one test item for storing the fail data based on at least one test item of an allocation request signal input from the outside; and a test controller that controls the fail memory to store the fail data in the at least one allocated memory region.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to an electronic device and a method of operating the same, and more specifically, to a semiconductor test device for dynamically allocating memory according to the type of test and a method of operating the same. Background Technology

[0002] In order to ensure the quality and reliability of chips manufactured in the semiconductor industry, semiconductor test equipment (also referred to as ATE (Automatic Test Equipment)) is an essential facility. Semiconductor test equipment applies various electrical signals and patterns to a chip to be tested (e.g., referred to as DUT (Device Under Test)), and measures and analyzes the response to inspect for functional and electrical defects of the chip.

[0003] Semiconductor test devices are equipped with high-speed digital signal generation and response analysis capabilities. Recently, Field Programmable Gate Arrays (FPGAs) have been utilized to flexibly and rapidly implement functions such as test pattern generation, DUT control, and data processing. FPGAs provide the flexibility to quickly change hardware configurations in response to changes in test requirements and improve test speed by processing test algorithms in parallel. Semiconductor test devices capture information such as the time, location (address), and data of a DUT failure and store it in an internal fail memory. The fail data stored in the fail memory is used to analyze the type of chip defect and its cause.

[0004] Conventional fail memory is allocated in an even or fixed size within the total resources of a semiconductor test device, regardless of the type of test currently being performed (i.e., referred to as a test item). Some test items generate an unexpectedly large amount of fail data, but because the allocated memory size is limited, critical fail data may overflow and be lost. Conversely, some test items rarely fail, so most of the allocated memory space may be wasted. This loss of fail data impairs the accuracy of failure analysis and reduces test efficiency, which can consequently hinder the improvement of production yield.

[0005] Therefore, there is a need to develop new technology that can improve resource utilization efficiency and prevent the loss of failed data by dynamically or differentially allocating fail memory resources based on the characteristics of test items or the predicted amount of failures. Prior art literature

[0006] Registered Patent Publication No. 10-2800269 (Published Jan. 11, 2024) The problem to be solved

[0007] These conventional methods have problems such as failure data loss, wasted memory space, impaired accuracy of failure analysis, increased test time, and reduced test efficiency, which ultimately hinders mass production, because they cannot dynamically allocate fail memory space according to test items.

[0008] The embodiments of the present disclosure aim to provide an electronic device for dynamically allocating memory and a method of operating the same to solve various problems, including the problems mentioned above.

[0009] However, these tasks are exemplary and do not limit the scope of the present disclosure. means of solving the problem

[0010] According to one aspect of the present disclosure, a semiconductor test device is provided, comprising: a fail memory including a plurality of memory regions for storing fail data generated as a test result for a semiconductor device; a memory allocator that allocates the plurality of memory regions to at least one memory region for each at least one test item for storing fail data based on at least one test item of an allocation request signal input from the outside; and a test controller that controls the fail memory to store fail data in at least one allocated memory region.

[0011] According to the present embodiment, the memory allocator can allocate a plurality of memory regions as regions to store first fail data for the first test item based on the first test item of the first allocation request signal.

[0012] According to the present embodiment, the memory allocator can allocate a plurality of memory regions allocated to store first fail data as regions to store second fail data for the second test item based on the second test item of the second allocation request signal input to the semiconductor test device after the first allocation request signal.

[0013] According to the present embodiment, the memory allocator may allocate at least one first memory area to store first fail data for the first test item among a plurality of memory areas based on a first test item of an allocation request signal, and, based on a second test item of an allocation request signal, allocate at least one second memory area to store second fail data for the second test item among memory areas excluding at least one first memory area among a plurality of memory areas.

[0014] According to the present embodiment, the size of at least one first memory region may be different from the size of at least one second memory region.

[0015] According to the present embodiment, the size of at least one first memory region may be the same as the size of at least one second memory region.

[0016] According to the present embodiment, at least one test item may include an address failure, a data failure, a history failure, and a capture failure.

[0017] According to the present embodiment, an allocation request signal may be provided to a semiconductor test device before a test of the semiconductor device begins.

[0018] According to the present embodiment, the test controller may include a pattern generator that generates at least one test pattern data corresponding to at least one test item, a driver that provides the test pattern data to a semiconductor device, and a comparator that generates failure data based on the data provided from the semiconductor device and provides the failure data to a fail memory.

[0019] According to one aspect of the present disclosure, a method of operation of a semiconductor test device for dynamically allocating a fail memory is provided, comprising the steps of: receiving an allocation request signal pointing to at least one test item; allocating at least one memory area for each of at least one test item from a plurality of memory areas included in the fail memory based on at least one test item; and storing fail data generated as a test result for a semiconductor device in the allocated at least one memory area.

[0020] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention.

[0021] In addition, these general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0022] According to an exemplary embodiment of the present disclosure, by dynamically allocating the memory space of a fail memory according to a test item, there are effects such as preventing the loss of fail data, efficiently utilizing memory space, improving the accuracy of failure analysis, reducing test time, increasing test efficiency, and increasing mass production capability.

[0023] Of course, the scope of the present disclosure is not limited by these effects. Brief explanation of the drawing

[0024] FIG. 1 is a block diagram of a semiconductor system according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram of a semiconductor test device according to an exemplary embodiment of the present disclosure. FIGS. 3a and FIGS. 3b are drawings for illustrating a fail memory according to a comparative example and an exemplary embodiment of the present disclosure, respectively. FIGS. 4a, FIGS. 4b, and FIGS. 4c are drawings for explaining the operation of allocating a plurality of memory regions of a fail memory according to an exemplary embodiment of the present disclosure. FIGS. 5A, FIGS. 5B, FIGS. 5C, and FIGS. 5D are drawings illustrating the operation of storing fail data per test item. FIG. 6 is a diagram illustrating the operation of storing fail data for each test item of a semiconductor test device according to an exemplary embodiment of the present disclosure. FIG. 7 is a flowchart illustrating a method of operation of a semiconductor test device according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0025] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments.

[0026] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0027] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0028] In the following embodiments, terms such as "comprising" or "having" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0029] In the following embodiments, when a part such as a layer, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another region, component, etc. is interposed in between.

[0030] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present disclosure is not necessarily limited to what is depicted.

[0031] Where an embodiment can be implemented differently, a specific sequence of operations may be performed differently from the order described. For example, two steps described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0032] In this specification, “A and / or B” indicates the case where it is A, B, or both A and B. Additionally, phrases such as “at least one of A and B,” “at least one of A or B,” “at least one of A, B and C,” and “at least one of A, B, or C” may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. For example, “at least one of A and B” indicates the case where it is A, B, or both A and B.

[0033] In the following embodiments, when layers, regions, components, etc. are described as being connected, this includes cases where the layers, regions, components are directly connected, or / or cases where other layers, regions, components are interposed between the layers, regions, components to form an indirect connection. For example, when layers, regions, components, etc. are described as being electrically connected in this specification, it indicates cases where the layers, regions, components, etc. are directly electrically connected, and / or cases where other layers, regions, components, etc. are interposed between them to form an indirect electrical connection.

[0034] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0035] The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure is complete and to fully inform those skilled in the art of the scope of the present disclosure, and the present disclosure is defined only by the scope of the claims.

[0036] The terms used in this disclosure are for describing the embodiments and are not intended to limit this disclosure. In this disclosure, the singular form may include the plural form unless specifically stated otherwise in the text. The terms “comprises” and / or “comprising” used in this disclosure do not exclude the presence or addition of one or more other components in addition to the components mentioned. Throughout the disclosure, the same reference numerals refer to the same components, and “and / or” may include each of the mentioned components and all combinations of one or more. Although terms such as “first,” “second,” etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this disclosure.

[0037] The word "exemplary" is used in this disclosure to mean "used as an example or illustration." Any embodiment described as "exemplary" in this disclosure should not be interpreted as being preferred or having an advantage over other embodiments.

[0038] Embodiments of the present disclosure may be described in terms of a function or a block performing a function.

[0039] The term “module” in this disclosure may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A “module” may be a component formed integrally or a minimum unit of a component or part thereof that performs one or more functions. For example, according to one embodiment, a “module” may be implemented in the form of an application-specific integrated circuit (ASIC).

[0040] The term “part” in this disclosure refers to a software or hardware component, such as an FPGA or ASIC, and the “part” performs certain roles. However, the “part” is not limited to software or hardware. The “part” may be configured to reside in an addressable storage medium or configured to operate one or more processors. For example, the “part” may include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and “parts” may be combined into a smaller number of components and “parts” or further separated into additional components and “parts.” Furthermore, the components and “parts” may be implemented to operate one or more CPUs within a device or secure multimedia card. Additionally, "~part" may include one or more processors.

[0041] Embodiments of the present disclosure may be implemented using at least one software program running on at least one hardware device and may perform network management functions to control elements.

[0042] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one component and other components as illustrated in the drawings. Spatially relative terms should be understood as encompassing different orientations of components during use or operation, in addition to the orientations depicted in the drawings. For example, if a component depicted in a drawing is inverted, a component described as "below" or "beneath" of another component may be placed "above" of that component. Therefore, the exemplary term "below" may encompass both the lower and upper directions. Components may also be oriented in other directions, and accordingly, spatially relative terms may be interpreted according to the orientation.

[0043] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which this disclosure pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0044] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0045] FIG. 1 is a block diagram of a semiconductor system (100) according to an exemplary embodiment of the present disclosure.

[0046] Referring to FIG. 1, the semiconductor system (100) may include a semiconductor test device (110) and a semiconductor device (120).

[0047] A semiconductor test device (110) is a device for testing a semiconductor device (120). In an exemplary embodiment, the semiconductor test device (110) may include a fail memory (110), a memory allocator (112), and a test controller (113). Although not illustrated, the semiconductor test device (110) may further include a memory controller and / or memory management unit that communicates with and controls the operation of external memory, and a buffer memory that stores duplicated fail data.

[0048] The fail memory (110) can store fail data generated as a result of a test on a semiconductor device (120). To this end, the fail memory (110) includes a plurality of memory regions, and fail data generated for each test item can be stored in a memory region allocated according to a specific test item among the plurality of memory regions. In an exemplary embodiment, the fail memory (110) can store fail data in an interleave manner, which is distributed and stored in an alternating pattern across a plurality of volatile memories (e.g., registers, DRAMs, etc.) to write fail data at high speed without delay.

[0049] The memory allocator (120) may allocate a plurality of memory regions of the fail memory (110) to at least one memory region for each at least one test item to store fail data, based on at least one test item of an allocation request signal received from the outside. An allocation request signal may be generated, for example, by setting a test item for a test to be performed by a user and inputting it into the semiconductor test device (110). In an exemplary embodiment, the allocation request signal may be input into the semiconductor test device (110) before the start of the test for the semiconductor device (120). The test item of the allocation request signal may be one or more. The test item may include an address fail, a data fail, a history fail, and a capture fail, as shown below in FIG. 3a.

[0050] The test controller (113) can perform the test operation overall. In an exemplary embodiment, the test controller (113) can control the fail memory to store fail data in at least one allocated memory area. Although not illustrated, the test controller (113) may further include configurations for generating a test signal for the semiconductor device (120) and providing the test signal to the semiconductor device (120). For example, the test controller (113) may further include an Algorithmic Pattern Generator (ALPG), a timing generator and / or a clock generator, and Pin Electronics. Additionally, the test controller (113) may further include a test analysis module, etc., for performing Redundancy Analysis (RA) to extract defects from the test results of the semiconductor device (120).

[0051] In an exemplary embodiment, the memory allocator (112) and the test controller (113) may be designed and implemented as a programmable non-memory semiconductor, for example, a Field Programmable Gate Array (FPGA), and the fail memory (110) and the FPGA may be mounted on a Printed Circuit Board, and the semiconductor test device (110) may be designed as a single chip.

[0052] The semiconductor device (120) may be a device to be tested by the semiconductor test device (110). The semiconductor device (120) being tested may be referred to as a DUT (Device Under Test) or often a UUT (Unit Under Test).

[0053] FIG. 2 is a block diagram of a semiconductor test device (200) according to an exemplary embodiment of the present disclosure.

[0054] Referring to FIGS. 1 and 2, the semiconductor test device (200) may correspond to the semiconductor test device (110) of FIG. 1. The semiconductor test device (200) may include a fail memory (210), a memory allocator (220), a pattern generator (231), a driver (232), and a comparator (233). The pattern generator (231), the driver (232), and the comparator (233) may be included in the test controller (113) of FIG. 1. The fail memory (210) and the memory allocator (220) may correspond to the fail memory (111) and the memory allocator (112) of FIG. 1.

[0055] The pattern generator (231) can generate at least one test pattern data corresponding to at least one test item. For example, if the test item is an address failure, the pattern generator (231) can generate a first test pattern data for testing the address failure. If the test item is a data failure, the pattern generator (231) can generate a second test pattern data for testing the data failure. Likewise, if the test item is a history failure, the pattern generator (231) can generate a third test pattern data for testing the history failure and a fourth test pattern data for testing the capture failure.

[0056] The driver (232) can provide test pattern data generated by the pattern generator (231) to the semiconductor device (120). The semiconductor device (120) can store the test pattern data and provide the data to the comparator (233) as a result of the test.

[0057] The comparator (233) can generate failure data based on data provided from the semiconductor device (120) and provide the failure data to the fail memory (210). For example, the comparator (233) can generate failure data using expected data corresponding to the test pattern data of the pattern generator (231) and data provided from the semiconductor device (120).

[0058] FIGS. 3a and FIGS. 3b are drawings for illustrating a fail memory according to a comparative example and an exemplary embodiment of the present disclosure, respectively. Specifically, FIG. 3a is a drawing for illustrating a fail memory (310a) according to a comparative example, and FIG. 3b is a drawing for illustrating a fail memory (310b) according to an exemplary embodiment of the present disclosure.

[0059] Referring to FIG. 3a, the fail memory (310a) according to the comparative example may include a plurality of memory regions (311a, 312a, 313a, 314a, 315a). Each of the plurality of memory regions (311a, 312a, 313a, 314a, 315a) may be allocated equally regardless of the test item of the test currently to be performed. For example, if the size of the fail memory (310a) is 10 MB (Megabyte), the size of each of the multiple memory regions (311a, 312a, 313a, 314a, 315a) may be allocated as 2 MB, and the memory region (311a) may be allocated to store first fail data for an address fail, the memory region (312a) may be allocated to store second fail data for a data fail, the memory region (313a) may be allocated to store third fail data for a history fail, the memory region (314a) may be allocated to store fourth fail data for a capture fail, and the memory region (315a) may be allocated to store fail data for other fail. However, the present disclosure is not limited to the examples described above. If a relatively large amount of memory is required to store fail data for a specific test item during testing, the capacity of that memory area may be insufficient because the memory area corresponding to that test item is pre-allocated as a fixed value. Consequently, test operations for the same test item may be performed repeatedly, which can increase test time and reduce mass production efficiency.The memory area related to address failure can be referred to as AFM (Address Fail Memory), the memory area related to data failure can be referred to as DFM (Data Fail Memory), the memory area related to history failure can be referred to as HFM (History Fail Memory), and the memory area related to capture failure can be referred to as CFM (Capture Fail Memory).

[0060] Referring to FIG. 3b, a fail memory (310b) according to an exemplary embodiment of the present disclosure may include a plurality of memory regions (311b, 312b, 313b, 314b, 315b) that are freely assignable to each test item. At least one of the plurality of memory regions (311b, 312b, 313b, 314b, 315b) may be assigned according to the test item of the test currently to be performed. For example, if the size of the fail memory (310a) is 10MB and the size of the AFM is required to be 10MB, the plurality of memory regions (311b, 312b, 313b, 314b, 315b) may be assigned to the AFM. However, the present disclosure is not limited to the examples described above. Multiple memory areas (311b, 312b, 313b, 314b, 315b) may be referred to as Flexible Fail Memory (FFM). Since the FFM can be changed according to the test situation, it can be selected and used in a form suitable for the purpose before the start of the test for a specific test item.

[0061] According to the aforementioned embodiment, since the capacity of the memory area (e.g., AFM) corresponding to a specific existing item is insufficient, the number of test operations is reduced (e.g., one test operation) instead of performing multiple test operations for the same type of test item, thereby reducing test time and improving mass production capabilities. For example, if 10MB of AFM is required, five test operations must be performed according to the comparative example of FIG. 3a, but according to the exemplary embodiment of FIG. 3b, the necessary data can be obtained with only one test operation.

[0062] FIGS. 4a, FIGS. 4b, and FIGS. 4c are drawings for explaining the operation of allocating a plurality of memory regions (411 to 415) of a fail memory (410) according to an exemplary embodiment of the present disclosure.

[0063] Referring to FIG. 2 and FIG. 4a, in an exemplary embodiment, when a memory area for a first test item is relatively large during testing and a memory area for a test item other than the first test item is not used, the memory allocator (220) may allocate a plurality of memory areas (411 to 415) as areas to store first fail data for the first test item based on the first test item of the first allocation request signal. Referring to FIG. 4a, for example, if the first test item is an address fail, a plurality of memory areas (411a to 415a) of the fail memory (410) may be allocated as AFM. Subsequently, when only a memory area for a second test item different from the first test item is needed, after the test operation for the first test item is terminated, the user may provide a second allocation request signal to the semiconductor test device (200) to allocate a memory area for the second test item. The memory allocator (220) may allocate a plurality of memory regions (411~415) allocated to store the first fail data as a region to store the second fail data for the second test item, based on the second test item of the second allocation request signal input to the semiconductor test device after the first allocation request signal. For example, if the second test item is a data fail, the plurality of memory regions (411a~415a) of the fail memory (410) may be allocated from AFM to DFM. However, it is not limited to the examples described above.

[0064] Referring to FIG. 2 and FIG. 4b, in an exemplary embodiment, when a memory area for a first test item is partially required during testing, the allocation request signal may include two or more test items. In this case, the memory allocator (220) may allocate at least one first memory area among a plurality of memory areas (411 to 415) to store first fail data for the first test item based on the first test item of the allocation request signal. Additionally, the memory allocator (220) may allocate at least one second memory area among the memory areas excluding at least one first memory area from the plurality of memory areas (411 to 415) to store second fail data for the second test item based on the second test item of the allocation request signal. For example, referring to FIG. 4b, the size of the fail memory (410) may be 10MB, and 6MB of AFM may be required, 2MB of DFM may be required, and 2MB of CFM may be required. In this case, among the multiple memory regions (411 to 415), memory regions (411b to 413b) may be allocated as AFM, among the multiple memory regions (411 to 415), memory region (414b) may be allocated as DFM, and among the multiple memory regions (411 to 415), memory region (415b) may be allocated as CFM. However, it is not limited to the examples described above. The size of the first memory region may be the same as or different from the size of the second memory region. For example, the size of the AFM in FIG. 4b is different from the size of the DFM and / or CFM in FIG. 4b, and the size of the DFM in FIG. 4b is the same as the size of the CFM.

[0065] Referring to FIG. 2 and FIG. 4c, similar to the embodiment described above with reference to FIG. 4b, if the size of the fail memory (410) is 10MB and 2MB of HFM and CFM are required and 6MB of DFM is required, the memory area (411c) can be allocated as DFM, the memory areas (412c to 414c) can be allocated as HFM, and the memory area (415c) can be allocated as CFM.

[0066] FIGS. 5A, FIGS. 5B, FIGS. 5C, and FIGS. 5D are drawings for explaining the operation of storing fail data for each test item. Specifically, FIG. 5A is a drawing for explaining the operation of storing fail data in the AFM, FIG. 5B is a drawing for explaining the operation of storing fail data in the DFM, FIG. 5C is a drawing for explaining the operation of storing fail data in the HFM, and FIG. 5D is a drawing for explaining the operation of storing fail data in the CFM.

[0067] Referring to FIG. 5a, the semiconductor test device (500) can generate data having a DUT address (or an address signal for the semiconductor device), a fail signal, and a logic value '1' as fail data. The pattern generator (510) of the semiconductor test device (500) can provide the DUT address to the address input of the block memory (530). The comparator (520) of the semiconductor test device (500) can provide the fail signal to the write enable input of the block memory (530) and provide data having a logic value '1' to the data input of the block memory (530). That is, when a failure of the AFM test occurs, '1' at the corresponding address can be stored in the block memory (530).

[0068] Referring to FIG. 5b, the comparator (520) of the semiconductor test device (500) can generate a fail signal, expect data, and read data as fail data. The fail signal of the comparator (520) is input to an adder (540) and incremented by 1, and the fail signal incremented by 1 can be provided as an address to the address input of the block memory (530). The fail signal of the comparator (520) can be provided to the write enable input of the block memory (530). The expect data and read data of the comparator (520) can be provided to the data input of the block memory (530). That is, when a failure of the DFM test occurs, the corresponding address is incremented by 1, and the expect data and read data can be stored in the block memory (530).

[0069] Referring to FIG. 5c, the semiconductor test device (500) can generate a DUT address, a fail signal, prediction data, and read data as fail data. The DUT address of the pattern generator (510) can be provided to the address input of the block memory (530). The fail signal of the comparator (520) can be input to the logical OR gate (550), the output of the logical OR gate (550) is provided to the write enable input of the block memory (530), and the output of the logical OR gate (550) can be fed back to the input terminal of the logical OR gate (550). The prediction data and read data of the comparator (520) can be provided to the data input of the block memory (530). That is, if a failure of the HFM test occurs, the prediction data and read data can be stored at all subsequent addresses.

[0070] Referring to FIG. 5d, the semiconductor test device (500) can generate a capture command, prediction data, and read data as fail data. The pattern generator (510) can generate a capture command, and the capture command is input to an adder (560) and incremented by 1, and the capture command incremented by 1 can be provided as an address to the address input of the block memory (530). The capture command can be provided to the write enable input of the block memory (530). The prediction data and read data of the comparator (520) can be provided to the data input of the block memory (530). That is, through the CFM capture command, the prediction data and read data at that time can be stored in the block memory (530), and the address can be incremented by 1 in response to the capture command.

[0071] FIG. 6 is a diagram illustrating the operation of storing fail data for each test item of a semiconductor test device (600) according to an exemplary embodiment of the present disclosure.

[0072] Referring to FIG. 6, the semiconductor test device (600) may include a pattern generator (610), a comparator (620), a block memory (630), a first adder (640), a logical OR gate (650), a second adder (660), an address select register (671), a write enable select register (672), a data select register (673), and a plurality of multiplexers (681, 682, 683). In an exemplary embodiment, the pattern generator (610) and the comparator (620) may be included in the test controller (113) of FIG. 1. The block memory (630) may correspond to the fail memory (111) of FIG. 1 and / or the fail memory (210) of FIG. 2.

[0073] The pattern generator (610), comparator (620), first and second adders (640, 660), and logical OR gate (650) can operate as described above with reference to FIGS. 5a through 5d.

[0074] The multiplexer (681) can select one of the DUT address, a capture command increasing by 1, and a fail signal increasing by 1 according to the signal of the address selection register (671) and provide it to the address input of the block memory (530). The multiplexer (682) can select one of the capture command, the output of the logical OR gate (650), and a fail signal according to the signal of the write enable selection register (672) and provide it to the write enable input of the block memory (530). The multiplexer (683) can select the predicted data and read data or data having a logical value '1' according to the signal of the data selection register (673) and provide it to the data input of the block memory (530). The DUT address, fail signal, and data having a logic value '1', prediction data and read data, and capture command input to the plurality of multiplexers (681, 682, 683) can operate as described above with reference to FIGS. 5a to 5d.

[0075] The address selection register (671), the write enable selection register (672), and the data selection register (673) may be included in the memory allocator (112) of FIG. 1 and / or the memory allocator (220) of FIG. 2. In an exemplary embodiment, a first adder (640), a logical OR gate (650), a second adder (660), and / or a plurality of multiplexers (681, 682, 683) may be further included in the memory allocator (112) of FIG. 1 and / or the memory allocator (220) of FIG. 2. The address selection register (671), the write enable selection register (672), and the data selection register (673) may each output a signal to indicate the selection of the multiplexer according to the currently set test item.

[0076] Referring to FIGS. 5a and FIGS. 6, for example, in the case of an AFM, the multiplexer (681) selects the DUT address in response to a signal from the address select register (671), the multiplexer (682) selects a fail signal in response to a signal from the write enable select register (672), and the multiplexer (683) selects data having a logic value '1' in response to a signal from the data select register (673).

[0077] Referring to FIGS. 5b and FIGS. 6, for example, in the case of DFM, the multiplexer (681) selects a fail signal incremented by 1 in response to a signal from the address select register (671), the multiplexer (682) selects a fail signal in response to a signal from the write enable select register (672), and the multiplexer (683) selects predicted data and read data in response to a signal from the data select register (673).

[0078] Referring to FIG. 5c and FIG. 6, for example, in the case of HFM, the multiplexer (681) selects the DUT address in response to the signal of the address select register (671), the multiplexer (682) selects the output of the logic OR gate (550) in response to the signal of the write enable select register (672), and the multiplexer (683) selects the predicted data and the read data in response to the signal of the data select register (673).

[0079] Referring to FIG. 5d and FIG. 6, for example, in the case of a CFM, the multiplexer (681) selects a capture command incremented by 1 in response to a signal from the address select register (671), the multiplexer (682) selects a capture command in response to a signal from the write enable select register (672), and the multiplexer (683) selects prediction data and read data in response to a signal from the data select register (673).

[0080] FIG. 7 is a flowchart illustrating a method of operation of a semiconductor test device according to an exemplary embodiment of the present disclosure.

[0081] Referring to FIG. 7, a method of operating a semiconductor test device for dynamically allocating fail memory may include steps S100, S110, and S120.

[0082] In step S100, the semiconductor test device may receive an assignment request signal pointing to at least one test item. The assignment request signal may be generated by user input.

[0083] In step S110, the semiconductor test device can allocate at least one memory region per at least one test item from a plurality of memory regions included in the fail memory based on at least one test item.

[0084] In step S120, the semiconductor test device can store fail data generated as a test result for the semiconductor device in at least one allocated memory area.

[0085] According to the aforementioned embodiment, by sufficiently securing the capacity of the memory area corresponding to a specific item and reducing the number of test operations for the same type of test item (e.g., one test operation), the test time can be reduced and mass production efficiency can be improved accordingly.

[0086] Although the present disclosure has been described with reference to the embodiments illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0087] 100: Semiconductor System 110: Semiconductor test device 111: Fail memory 112: Memory allocator 113: Test controller

Claims

Claim 1 A semiconductor test device comprising: a fail memory including a plurality of memory regions for storing fail data generated as a test result for a semiconductor device; a memory allocator that allocates the plurality of memory regions to at least one memory region for each of the at least one test item for storing the fail data based on at least one test item of an allocation request signal input from the outside; and a test controller that controls the fail memory to store the fail data in the allocated at least one memory region, wherein the at least one test item includes an address fail and a data fail, and the memory allocator is characterized by allocating the fail memory to store data having a logical value of 1 at a location corresponding to an address signal for the semiconductor device when the at least one test item is an address fail, and allocating the fail memory to store predicted data and read data at a location corresponding to an address to which a fail signal is added when the at least one test item is a data fail. Claim 2 A semiconductor test device according to claim 1, wherein the memory allocator allocates the plurality of memory regions as regions to store first fail data for the first test item based on the first test item of the first allocation request signal. Claim 3 A semiconductor test device according to claim 2, wherein the memory allocator allocates the plurality of memory regions allocated to store the first fail data as regions to store the second fail data for the second test item based on the second test item of the second allocation request signal input to the semiconductor test device after the first allocation request signal. Claim 4 A semiconductor test device according to claim 1, wherein the memory allocator allocates at least one first memory area to store first fail data for the first test item among the plurality of memory areas based on the first test item of the allocation request signal, and allocates at least one second memory area to store second fail data for the second test item among the memory areas excluding the at least one first memory area among the plurality of memory areas based on the second test item of the allocation request signal. Claim 5 A semiconductor test device according to claim 4, characterized in that the size of at least one first memory region is different from the size of at least one second memory region. Claim 6 A semiconductor test device according to claim 4, characterized in that the size of at least one first memory region is the same as the size of at least one second memory region. Claim 7 A semiconductor test device according to claim 1, wherein at least one test item comprises an address fail, a data fail, a history fail, and a capture fail. Claim 8 A semiconductor test device according to claim 1, wherein the allocation request signal is provided to the semiconductor test device before the test for the semiconductor device begins. Claim 9 A semiconductor test device according to claim 1, wherein the test controller comprises: a pattern generator that generates at least one test pattern data corresponding to at least one test item; a driver that provides the test pattern data to the semiconductor device; and a comparator that generates the fail data based on the data provided from the semiconductor device and provides the fail data to the fail memory. Claim 10 A method of operating a semiconductor test device for dynamically allocating a fail memory, comprising: receiving an allocation request signal indicating at least one test item including an address fail and a data fail; allocating at least one memory area for each of the at least one test item among a plurality of memory areas included in the fail memory based on the at least one test item; and storing fail data generated as a test result for a semiconductor device in the allocated at least one memory area, wherein the allocating step comprises: when the at least one test item is an address fail, allocating data having a logical value 1 to be stored in the fail memory at a location corresponding to an address signal for the semiconductor device; or when the at least one test item is a data fail, allocating predicted data and read data to be stored in the fail memory at a location corresponding to an address to which a fail signal is added.

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