Memory device and method of driving same

Abstract

A memory device comprises: an array of multiple memory cells each connected to one pair of word lines among a plurality of pairs of word lines arranged in a row, and to one of a plurality of bit lines or a reference column line among a plurality of bit lines arranged in a column; and a plurality of power supplies each connected between a first word line of each pair of the plurality of word lines and a second word line arranged adjacent to and below the first word line, wherein each of the plurality of memory cells comprises a first resistor connected to one of the plurality of bit lines and the first word line, and a second resistor connected to one of the plurality of bit lines and the second word line; or a third resistor connected to the reference column line and the first word line, and a fourth resistor connected to the reference column line and the second word line, and performs operations based on the voltage of the plurality of bit lines and the voltage of the reference column line, and only one of the plurality of power supplies is grounded.

Description

Technology Field

[0001] The present invention relates to a memory device that performs operations based on bit line voltage and a method for driving the same. Background Technology

[0002] Processing-in-Memory (PIM) is a circuit that improves computation speed and power consumption by adding computational functions within memory, moving away from the conventional Von Neumann architecture where data is read from memory, processed by a processor, and then stored back in memory. In particular, when Resistive Random Access Memory (RRAM) is used, it is called RRAM PIM. Conventional RRAM PIMs could perform multiplication and accumulation (MAC) operations by utilizing the characteristics that each memory cell has low resistance and a large current flows when driven at high voltage, and the result of the overall operation could be determined through the combined current of each memory cell in the bit line.

[0003] FIGS. 1A and 1B are diagrams schematically illustrating a portion of a memory cell array according to the prior art. Referring to FIG. 1A, in an example memory cell array according to the prior art, the resistance value (R0...R) of each memory cell n-1 Let ) be the weight, then the voltage (V0...V n-1 The result of the MAC operation based on the authorization of ) It is similar to that. In other words, conventional RRAM PIMs utilized a current sensing method that estimates computation results through the current of the bit line. In order for the current flowing through each cell to remain constant according to the computation result, a Transimpedance Amplifier (TIA) had to be used to fix the voltage of the bit line output terminal; however, the TIA causes a degradation in stability and speed due to the feedback path. Therefore, a memory device that eliminates this TIA and estimates computation results through the voltage of the bit line output terminal rather than the current has been discussed.

[0004] Referring to FIG. 1b, another example of a memory cell array according to the prior art eliminates TIA and obtains the operation result through the voltage of the output terminal of the bit line rather than the current. Referring to FIG. 1b, in the memory cell array according to the prior art, the resistance value (R0...R) of each memory cell n-1 Let ) be the weight, then the voltage (V0...V n-1 The result of the MAC operation based on the authorization of ) It is equal to. Here, the multiplied to the left side Since the resistance depends on the state of the stored weights, there is a problem in that the resistance value seen on the bit line varies depending on the state of the weights. When the resistance value changes, the bit line voltage may be the same even though the result of the operation is different, so the result of the operation cannot be determined based on the voltage of the output terminal of the bit line. In other words, according to the conventional structure, the bit line voltage and the MAC operation result do not correspond 1:1, making estimation impossible. The problem to be solved

[0005] The present invention aims to provide a memory device capable of operating quickly and stably by eliminating the transimpedance amplifier (TIA) and performing calculations based on the bit line voltage.

[0006] In addition, the memory device according to the present invention aims to enable the use of a conventional memory cell array as is without modification.

[0007] In addition, the memory device according to the present invention aims to reduce the overall area of ​​the circuit because no amplifier, including TIA, is used.

[0008] In addition, the memory device according to the present invention is designed to reduce the burden on the power supply by generating less current compared to conventional structures, since the load resistance of the power supply is relatively large.

[0009] However, the technical problem that the present invention aims to solve is not limited to the technical problem described above, and other technical problems may exist. means of solving the problem

[0010] A memory device according to one embodiment of the present invention comprises: an array of multiple memory cells each connected to one pair of word lines among a plurality of pairs of word lines arranged in a row, and to one of a plurality of bit lines or a reference column line among a plurality of bit lines arranged in a column; and a plurality of power supplies each connected between a first word line of each pair of the plurality of word lines and a second word line arranged adjacent to and below the first word line, wherein each of the plurality of memory cells comprises a first resistor connected to one of the plurality of bit lines and the first word line, and a second resistor connected to one of the plurality of bit lines and the second word line; or a third resistor connected to the reference column line and the first word line, and a fourth resistor connected to the reference column line and the second word line, and performs operations based on the voltage of the plurality of bit lines and the voltage of the reference column line, and only one of the plurality of power supplies is grounded.

[0011] In some embodiments, the equivalent resistance viewed from the output terminal of each of the plurality of bit lines may be constant regardless of the resistance state of the first and second resistors.

[0012] In some embodiments, the voltage of each output terminal of the plurality of bit lines may be constant according to the result of the operation.

[0013] In some embodiments, one of the first resistor and the second resistor may have a high resistance state and the other may have a low resistance state.

[0014] In some embodiments, the first resistor may have a resistance state corresponding to a set weight value.

[0015] In some embodiments, the third resistor may have a first reference resistor state for the operation, and the fourth resistor may have a second reference resistor state for the operation.

[0016] In some embodiments, when the operation is an AND operation, the first reference resistance state may be a high resistance state and the second reference resistance state may be a low resistance state.

[0017] In some embodiments, when the operation is a encoding operation based on the sign of the input value of the plurality of power sources and the sign of the set weight value, the first reference resistance state may be a high resistance state and the second reference resistance state may be a high resistance state.

[0018] In some embodiments, the operation may be performed based on the difference between the voltage at the output terminal of each of the plurality of bit lines and the voltage at the output terminal of the reference column line.

[0019] In some embodiments, the difference between the voltage at the output terminal of each of the plurality of bit lines and the voltage at the output terminal of the reference column line may correspond 1:1 with the result of the operation.

[0020] In some embodiments, the operation is performed according to the following Equation 1, and

[0021] [Equation 1]

[0022]

[0023] Here, V out is the voltage at the output terminal of each of the plurality of bit lines, and V ref is the voltage at the output terminal of the above-mentioned reference heat line, and V IN_i is the input voltage applied to the i-th power source among the plurality of power sources, and R i is the resistance state of the i-th first resistor, and R ref_i,a is the resistance state of the i-th third resistor, and R ref_i,b is the resistance state of the i-th fourth resistor, and R H is a resistance value having a high resistance state, and R L It can be a resistance value that has a low resistance state.

[0024] In some embodiments, each of the plurality of power sources may be placed between the first resistor and the second resistor.

[0025] In some embodiments, the number of the plurality of power sources may be equal to the number of the first resistors connected to one of the plurality of bit lines.

[0026] A method for driving a memory device according to an embodiment of the present invention comprises: a step of setting the resistance state of a first resistor to one of a high resistance state or a low resistance state corresponding to a set weight value; a step of setting the resistance state of a second resistor to the other of the high resistance state or the low resistance state; and a step of performing an operation based on the input of the plurality of power sources and the voltage of the plurality of bit lines and the voltage of the reference column line according to the resistance states of the first to fourth resistors.

[0027] In some embodiments, the equivalent resistance viewed from the output terminal of each of the plurality of bit lines may be constant regardless of the resistance state of the first and second resistors.

[0028] In some embodiments, the voltage of each output terminal of the plurality of bit lines may be constant according to the result of the operation.

[0029] In some embodiments, the method may further include the step of setting the resistance state of the third resistor to a first reference resistance state for the operation and setting the resistance state of the fourth resistor to a second reference resistance state for the operation.

[0030] In some embodiments, the operation may be performed based on the difference between the voltage at the output terminal of each of the plurality of bit lines and the voltage at the output terminal of the reference column line.

[0031] In some embodiments, the difference between the voltage at the output terminal of each of the plurality of bit lines and the voltage at the output terminal of the reference column line may correspond 1:1 with the result of the operation.

[0032] In some embodiments, the operation is performed according to the following Equation 1, and

[0033] [Equation 1]

[0034]

[0035] Here, V out is the voltage at the output terminal of each of the plurality of bit lines, and V ref is the voltage at the output terminal of the above-mentioned reference heat line, and V IN_i is the input voltage applied to the i-th power source among the plurality of power sources, and R i is the resistance state of the i-th first resistor, and R ref_i,a is the resistance state of the i-th third resistor, and R ref_i,b is the resistance state of the i-th fourth resistor, and R H is a resistance value having a high resistance state, and R LIt can be a resistance value that has a low resistance state. Effects of the invention

[0036] The memory device according to the present invention can operate quickly and stably by eliminating the transimpedance amplifier (TIA) and performing calculations based on the bit line voltage.

[0037] In addition, the memory device according to the present invention can be used as is without modifying the conventional memory cell array, which is advantageous for technical applications.

[0038] In addition, since no amplifier, including TIA, is used in the memory device according to the present invention, the overall area of ​​the circuit can be reduced.

[0039] In addition, since the memory device according to the present invention has a relatively large load resistance of the power supply, less current is generated compared to conventional structures, and thus the burden on the power supply can be reduced. Brief explanation of the drawing

[0040] FIGS. 1a and FIGS. 1b are diagrams schematically illustrating a portion of a memory cell array according to the prior art. FIG. 2 is a diagram schematically illustrating a memory device according to one embodiment of the present invention. FIG. 3 is a diagram for explaining the resistance state of a memory cell set for a first operation of a memory device according to an embodiment of the present invention. FIG. 4 is a diagram for explaining the resistance state of a memory cell set for a second operation of a memory device according to an embodiment of the present invention. FIG. 5 is a diagram for explaining the equivalent resistance viewed from the power supply of a memory device according to one embodiment of the present invention. FIG. 6 is a flowchart of a method for driving a memory device according to an embodiment of the present invention. FIG. 7 is a graph comparing the operating speed of a memory device according to the prior art and a memory device according to an embodiment of the present invention. FIG. 8 is another graph comparing the operating speed of a memory device according to the prior art and a memory device according to an embodiment of the present invention. FIG. 9a is a graph showing the simulation results of the current of the power supply of a memory device according to the prior art. FIG. 9b is a graph illustrating the simulation results of the current of a power supply of a memory device according to one embodiment of the present invention. Specific details for implementing the invention

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0042] It should be noted that the drawings are schematic and not drawn to scale. The relative dimensions and proportions of parts in the drawings are exaggerated or reduced in size for clarity and convenience, and any dimensions are illustrative only and not limiting. Additionally, the same reference numerals are used to denote similar features for the same structure, element, or part appearing in two or more drawings.

[0043] The embodiments of the present invention specifically illustrate ideal embodiments of the present invention. As a result, various variations of the illustration are expected. Accordingly, the embodiments are not limited to the specific form of the illustrated area and include, for example, variations in form resulting from manufacturing.

[0044] In this specification, terms such as first, second, third, etc., may be used to describe various components, but these components are not limited by said terms. These terms are used for the purpose of distinguishing one component from other components. For example, without departing from the scope of the present invention, the first component may be named the second or third component, and similarly, the second or third component may be named alternately.

[0045] Furthermore, all technical and scientific terms used in this specification, unless otherwise defined, have the meaning generally understood by those skilled in the art to which the present invention pertains. All terms used in this specification are selected for the purpose of further clarifying the present invention and are not selected to limit the scope of rights according to the present invention.

[0046] Additionally, expressions such as “comprising,” “having,” and “having” used in this specification should be understood as open-ended terms that imply the possibility of including other embodiments, unless otherwise stated in the phrase or sentence containing such expressions.

[0047] Additionally, singular expressions described in this specification may include the meaning of the plural form unless otherwise stated, and this applies likewise to singular expressions described in the claims.

[0048] In the present invention, the memory device has a processing-in-memory (PIM) structure, so that the memory device can perform computational functions. For example, the memory device according to an embodiment of the present invention may be a resistive random access memory (RRAM) having a PIM structure. However, the embodiments of the present invention are not limited thereto, and as long as it does not contradict the purpose of the present invention, some components may be connected outside the memory device, and may be applied to memory devices other than RRAM.

[0049] The memory device according to the present invention can be applied to an artificial intelligence system. The computation of the artificial intelligence model may use a MAC (multiplication and accumulation) operation in which input signals are multiplied by weights and added. That is, the memory device according to the present invention can perform MAC operations for an artificial intelligence system. However, embodiments of the present invention are not limited thereto, and the memory device according to the present invention may be used without limitation in any field requiring memory, and may perform other operations other than MAC operations as long as it does not contradict the purpose of the present invention.

[0050] FIG. 2 is a diagram schematically illustrating a memory device according to one embodiment of the present invention.

[0051] Referring to FIG. 2, a memory device (10) according to one embodiment of the present invention has a plurality of word lines (WL 0,a , WL 0,b , WL 1,a , WL 1,b , ... WL n-1,a , WL n-1,b , hereinafter "WL"), multiple bit lines (BL0, BL1... BL m-1It includes a memory cell array (100), a power supply unit (200), and a control unit (300) connected to the , hereinafter "BL" and a reference column line (RL).

[0052] Referring to FIG. 2, the memory cell array (100) comprises a plurality of pairs of word lines (WL) arranged in rows. 0,a and WL 0,b , WL 1,a and WL 1,b , ... WL n-1,a and WL n-1,b , below "WL i,a , WL i,b A pair of word lines (WL) of ") i,a , WL i,b In ), and one bit line (BL) among a plurality of bit lines (BL) arranged in a column j It may include a plurality of memory cells each connected to a ) or a reference column line (RL). In FIG. 2, a plurality of pairs of word lines (WL i,a , WL i,b ) is illustrated as comprising n pairs of word lines (WL) and a plurality of bit lines (BL) comprising m bit lines, wherein n is an integer greater than or equal to 2 and m may be an integer greater than or equal to 2, but embodiments of the present invention are not limited thereto, and at least one of n and m may be 1. In one embodiment, a plurality of pairs of word lines (WL i,a , WL i,b Each pair (WL) among ) i,a , WL i,b ) is the first word line (WL 0,a , WL 1,a , ... WL n-1,a , below "WL i,a ") and the first word line (WL i,a A second word line (WL) placed below and adjacent to ) 0,b , WL 1,b , ... WL n-1,b , below "WL i,b It can include ")

[0053] In one embodiment, each of the plurality of memory cells is one of the plurality of bit lines (BL) (BL j ) and the first word line (WL i,a The first resistor (R) connected to ) 0,0 , R 0,1 , ... R 0,m-1 , R 1,0 , R 1,1 , ... R 1,m-1 , ... R n-1,0 , R n-1,1 ... R n-1,m-1 , below "R i,j " or "R i "), and one of a plurality of bit lines (BL) and a second word line (WL i,b A second resistor (connected to ) , , ... , ... , ... , ... , below " Includes ")", or the reference column line (RL) and the first word line (WL i,a A third resistor (R) connected to ) ref_0,a , R ref_1,a , ... R ref_n-1,a , below "R ref_i,a "), and reference column line (RL) and second word line (WL i,b The fourth resistor (R) connected to ) ref_0,b , R ref_1,b , ... R ref_n-1,b , below "R ref_i,b It can include "). That is, one memory cell can include two resistors.

[0054] In one embodiment, the first resistor (R i,j ) and second resistor( ) can store a 1-bit weight. Also, the third resistor (R ref_i,a ) and the fourth resistor (R ref_i,b) can also store 1 bit of data (e.g., weight, reference resistance status). Here, the weight value may be set in advance according to the purpose and conditions of use of the memory device, or may be set and changed by input from a user or an external system.

[0055] In one embodiment, the first to fourth resistors (R i,j , , R ref_i,a , R ref_i,b ) may have two different resistance states, for example, a high resistive state (HRS) and a low resistive state (LRS). However, embodiments of the present invention are not limited thereto, and unless contrary to the purpose of the present invention, the first to fourth resistors (R i,j , , R ref_i,a , R ref_i,b Each of ) may have three or more resistance states.

[0056] In one embodiment, the first resistor (R i,j ) and second resistor( If one of them is in a high resistance state (HRS), the other may be in a low resistance state (LRS). Also, the first resistor (R i,j ) and second resistor( If one of them is in a low resistance state (LRS), the other can be in a high resistance state (HRS). For example, R i,j Resistance state (R) having this high resistance state (HRS) H In the case of ), is the opposite state, that is, the resistance state (R) of the low resistance state (LRS). L With ), R i,j Resistance state (R) having this low resistance state (LRS) L In the case of ), is the opposite state, that is, the resistance state (R) of the high resistance state (HRS). LIt may have ). In one example, when the weight value set on one of the plurality of memory cells is 1, the first resistor (R i,j ) has a low resistance state (LRS), and the second resistor ( ) may have a high resistance state (HRS). In another example, when the weight value set to one of the multiple memory cells is 0, the first resistor (R i,j ) has a high resistance state (HRS), and the second resistor ( ) can have a low resistance state (LRS). That is, the first resistor (R i,j ) has a resistance state corresponding to the actual weight value to be set in the corresponding memory cell, and the second resistor ( ) is the first resistor (R i,j It may have a resistance state opposite to that of ). However, embodiments of the present invention are not limited thereto, and unless contrary to the purpose of the present invention, the second resistor ( ) has a resistance state corresponding to the actual weight value to be set in the corresponding memory cell, and the first resistor (R i,j ) is the second resistor ( It may also have a resistance state opposite to ).

[0057] In this way, the first resistor (R i,j ) and second resistor( As ) have different resistance states, each output terminal (V) of a plurality of bit lines (BL) 0,out , V 1,out ... V m-1,out , below "V out The equivalent resistance viewed from ") is the first resistor (R i,j ) and second resistor( It can be constant regardless of the resistance state of ). For example, each of a plurality of bit lines (BL) (BL j The output terminal (V) of ) out The equivalent resistance viewed from ) is for each bit line (BL j The first resistor (R) sharing )i,j ) and second resistor( It can be constant regardless of the resistance state of ).

[0058] In one embodiment, the power supply unit (200) can apply voltage to the memory cell array (100). Referring to FIG. 2, the power supply unit (200) has a plurality of pairs of word lines (WL i,a , WL i,b The first word line (WL) of each pair among ) i,a ) and the second word line (WL i,b Multiple power sources (V) each connected between ) IN_0 , V IN_1 , ... V IN_n-1 , below "V IN_i It may include "). For example, multiple power sources (V IN_i ) can be a voltage source. Multiple power sources (V IN_i ) is the first resistor (R i,j ) and the second resistor ( Connected between ) and the first resistor (R i,j ) and the second resistor ( A voltage difference can be created between ). For example, multiple power sources (V IN_i The number of ) is the first resistor (R) connected to one of the plurality of bit lines (BL). i,j Equal to the number of ), or the second resistor ( It can be equal to the number of ). For example, multiple power sources (V IN_i The number of ) is the number of word line pairs (WL i,a , WL i,b The number may be equal to the number of ) or half (1 / 2) of the total number of word lines (WL). However, embodiments of the present invention are not limited thereto, and a plurality of power sources (V IN_i ) is the first resistor (R i,j ) or second resistor ( It may also include additional power sources that are not connected to ).

[0059] In one embodiment, a plurality of power sources (V) of the power supply unit (200) IN_iOnly one of ) can be grounded. For example, a plurality of power supplies (V) of the power supply unit (200). IN_i Only one of them is connected to the ground, and the rest are not connected to the ground. In Fig. 2, the lower power supply (V IN_n-1 Although it is illustrated as being grounded, embodiments of the present invention are not limited thereto, and a plurality of power sources (V IN_i Any one of ) may be grounded. In addition, embodiments of the present invention are not limited to a grounding part, and a plurality of power sources (V IN_i A grounding section to which only one of the following is connected can be a reference power source.

[0060] Referring to FIG. 2, a plurality of power sources (V) of the power supply unit (200) IN_i Each of the above may have a switching capacitor structure including a voltage source, a capacitor, and a switch. However, the power supply unit (200) according to the present invention is not limited to the switching capacitor structure of FIG. 2 and may have any structure including a power source and a switch that apply voltage to the memory cell array (100). For example, the power supply unit (200) may be connected to a power control unit (not shown) that controls the power supply unit (200) and may apply voltage to the memory cell array (100) according to a voltage application signal, and the power control unit may be mounted on the memory device (10) or provided externally.

[0061] In one embodiment, the control unit (300) can drive the memory cell array (100) and control the operation of the memory cell array (100). Referring to FIG. 2, the control unit (300) may include a word line driving unit (310) and a bit line driving unit (320). However, the embodiments of the present invention are not limited thereto, and the control unit (300) may further include configurations such as a control circuit (not shown) and an operation unit (not shown).

[0062] Referring to FIG. 2, the word line driver (310) can apply a signal to a plurality of word lines (WL). For example, the word line driver (310) is connected to the word line (WL) through a switch, and the first to fourth resistors (R) of the memory cell array (100) connected to the word line (WL) i,j , , R ref_i,a , R ref_i,b A signal can be applied to ).

[0063] Referring to FIG. 2, the bit line driver (320) can apply signals to a plurality of bit lines (BL). For example, the bit line driver (320) is connected to the bit line (BL) through a switch, and the first to fourth resistors (R) of the memory cell array (100) connected to the bit line (BL) i,j , , R ref_i,a , R ref_i,b A signal can be applied to ).

[0064] In one embodiment, the word line driver (310) and the bit line driver (320) are first to fourth resistors (R i,j , , R ref_i,a , R ref_i,b The first to fourth resistors (R) so that ) has a predetermined resistance state (HRS, LRS) i,j , , R ref_i,a , R ref_i,b A signal can be applied to ). For example, the first to fourth resistors (R i,j , , R ref_i,a , R ref_i,b ) may have two different resistance states, for example, a high resistance state (HRS) and a low resistance state (LRS), depending on the signal applied from the word line driver (310) and the bit line driver (320).

[0065] In one embodiment, the word line driver (310) and the bit line driver (320) have first and second resistors (R i,j , The first and second resistors (R) such that ) have a predetermined resistance state (HRS, LRS) according to the weighting value i,j , A signal can be applied to ). For example, the word line driver (310) and the bit line driver (320) have a first resistor (R i,j ) has a resistance state (HRS or LRS) according to the weighting value, and the second resistor ( The first and second resistors (R) such that ) has a resistance state (LRS or HRS) opposite to this. i,j , A signal can be applied to ). Here, the weight value may be pre-set according to the purpose and conditions of use of the memory device, or may be set and changed by input from a user or an external system.

[0066] In one embodiment, the word line driver (310) and the bit line driver (320) have a third resistor (R) depending on the type of operation performed by the memory device (10). ref_i,a ) and the fourth resistor (R ref_i,b A third resistor (R) so that ) has a predetermined resistance state (HRS, LRS). ref_i,a ) and the fourth resistor (R ref_i,b A signal can be applied to ). For example, the word line driver (310) and the bit line driver (320) may apply a signal to the third resistor (R) depending on the type of operation performed by the memory device (10). ref_i,a ) has a first reference resistance state (HRS or LRS), and the fourth resistor (R ref_i,b A third resistor (R) so that ) has a second reference resistance state (HRS or LRS). ref_i,a ) and the fourth resistor (R ref_i,bA signal can be applied to ). Here, the type of operation may be pre-set according to the purpose and conditions of use of the memory device, or may be set and changed by input from a user or an external system. In addition, a third resistor (R) according to the type of operation ref_i,a The first reference resistance state (HRS or LRS) of ) and the fourth resistor (R ref_i,b The second reference resistance state (HRS or LRS) of the memory device may be pre-set according to the purpose and conditions of use, or may be set and changed by input from a user or an external system.

[0067] In one embodiment, the control unit (300) of the memory device (10) may further include a control circuit (not shown) that controls the word line driver (310) and the bit line driver (320). For example, the control circuit (not shown) includes first and second resistors (R i,j , Determine the weighting value of ), and the first resistor (R i,j ) and second resistor( The word line driver (310) and the bit line driver (320) can be controlled to apply a signal that causes ) to have a predetermined resistance state according to a determined weight value. For example, a control circuit (not shown) determines the type of operation performed by the memory device (10) and the third resistor (R ref_i,a ) and the fourth resistor (R ref_i,bThe word line driver (310) and the bit line driver (320) can be controlled to apply a signal that causes the word line driver (310) to have a predetermined resistance state according to the type of operation determined. Here, the weight value may be pre-set in the control circuit (not shown) according to the purpose and conditions of use of the memory device, or may be input to the control circuit (not shown) from a user or an external system and changed. In addition, the type of operation may be pre-set in the control circuit (not shown) according to the purpose and conditions of use of the memory device, or may be input to the control circuit (not shown) from a user or an external system and changed. However, embodiments of the present invention are not limited thereto, and the word line driver (310) and the bit line driver (320) may directly perform the role of the control circuit (not shown), or the control circuit (not shown) may be provided outside the memory device (10) to apply a control signal to the memory device (10).

[0068] In one embodiment, the memory device (10) has each output terminal (V) of a plurality of bit lines (BL). out A result value can be output by performing calculations based on the voltage of ). For example, the memory device (10) can output a result value by each output terminal (V) of a plurality of bit lines (BL). out The voltage of ) and the output terminal (V) of the reference column line (RL). ref It is possible to perform calculations based on the voltage of ) and output a result value. For example, each output terminal (V) of a plurality of bit lines (BL) out The voltage of ) and the output terminal (V) of the reference column line (RL). ref The voltage of ) is the input power supply (V IN_i ) and the first to fourth resistors (R i,j , , R ref_i,a , R ref_i,bDepending on the respective resistance state of the memory device (10), the memory device (10) can perform operations based on the output voltages of a plurality of bit lines (BL) and reference column lines (RL). For example, the memory device (10) can perform Multiply-And-Accumulate (MAC) operations, but embodiments of the present invention are not limited thereto.

[0069] In one embodiment, the memory device (10) has an output terminal (V) for each of a plurality of bit lines (BL). out The voltage of ) and the output terminal (V) of the reference column line (RL). ref The difference in voltage (V) out -V ref The calculation result can be estimated based on ). In this way, the difference (V) between the output voltage of multiple bit lines (BL) and the output voltage of the reference column line (RL) out -V ref As operations are performed based on ), offsets resulting from the operation can be removed.

[0070] For example, the output voltage of each of the multiple bit lines (BL) may be constant according to the estimated result of the operation of the memory device (10). For example, the estimated result of the operation of the memory device (10) may be constant according to the output voltage of each of the multiple bit lines (BL). This is, for example, each output terminal (V) of the multiple bit lines (BL). out The equivalent resistance viewed from ) is the first and second resistors (R i,j , This may be because it is constant regardless of the resistance state of ). For example, the output voltage of each of the plurality of bit lines (BL) may correspond 1:1 with the estimated value of the result of the operation of the memory device (10). For example, the output voltage of each of the plurality of bit lines (BL) may correspond linearly 1:1 with the estimated value of the result of the operation of the memory device (10). For example, the output voltage of each of the plurality of bit lines (BL) corresponds to the first and second resistors (Ri,j , Regardless of the resistance state of the memory device (10), it can correspond linearly in a 1:1 manner with the estimated result of the operation of the memory device (10). For example, the output voltage of each of the multiple bit lines (BL) can increase linearly in proportion to the estimated result of the operation of the memory device (10).

[0071] For example, the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL). out -V ref ) may be constant depending on the estimated result of the operation of the memory device (10). For example, the estimated result of the operation of the memory device (10) is the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL). out -V ref It can be constant depending on ). For example, the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL). out -V ref ) can correspond 1:1 with the estimated result of the operation of the memory device (10). For example, the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL). out -V ref ) can correspond linearly 1:1 with the estimated result of the operation of the memory device (10). For example, the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL) out -V ref ) is the first and second resistors (R i,j , Regardless of the resistance state of ), it can linearly correspond 1:1 with the estimated value of the result of the operation of the memory device (10). For example, the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL). out -V ref) can increase linearly in proportion to the estimated result of the operation of the memory device (10).

[0072] In this way, the memory device (10) includes a reference column line (RL) and a first resistor (R i,j ) and second resistor( Multiple power sources (V) placed between ) IN_i Ground only one of them, and the first resistor (R i,j ) and second resistor( In a state where ) is configured to have different resistance states (HRS or LRS), multiple power sources (V IN_i Depending on the application of ), the difference (V) between the output voltage of multiple bit lines (BL) and the output voltage of the reference column line (RL) out -V ref As the operation is performed based on ), the operation result of the memory device (10) can be determined as a unique value. That is, the operation result of the memory device (10) corresponding to the output voltage of each of the multiple bit lines (BL) can be determined as a unique value. For example, according to the estimated operation result value of the memory device (10), the first resistor (R) of the multiple cells of the memory cell array (100) i,j ) and second resistor( The resistance state of ) can be estimated.

[0073] For example, the operation performed by the memory device (10) may follow the following Equation 1.

[0074] [Equation 1]

[0075]

[0076] Here, V out is each output terminal (V) of a plurality of bit lines (BL). out It is the voltage of ), and V ref is the output terminal (V) of the reference column line (RL). ref It is the voltage of ), and V IN_i is an input voltage applied to the i-th power supply of the power supply unit (200), and Ri is the resistance state of the i-th first resistor, and R ref_i,a is the resistance state of the i-th third resistor, and R ref_i,b is the resistance state of the i-th fourth resistor, and R H is a resistance value having a high resistance state, and R L is a resistance value that has a low resistance state.

[0077] In Equation 1, the numerator of the right-hand side " "is V IN_i , R i , R ref_i,a and R ref_i,b It is an estimated value of the result of the calculation of the memory device (10) calculated based on the above.

[0078] According to Equation 1, the denominator on the right side " " is the first and second resistors (R i,j , Since it has a constant value (e.g., a constant) regardless of the resistance state of the memory device (10), the result of the operation of the memory device (10) can be determined as a unique value.

[0079] For example, each output terminal (V) of a plurality of bit lines (BL). out The voltage of ) and the output terminal (V) of the reference column line (RL). ref The difference in voltage (V) out -V ref ) is the estimated result of an operation of the memory device (10), for example, " Depending on the, it can correspond 1:1, for example.

[0080] In one embodiment, the control unit (300) of the memory device (10) may further include an operation unit (not shown) that performs operations of the memory device (10) as described above. For example, the operation unit (not shown) may each output terminal (V) of a plurality of bit lines (BL). out The voltage of ) and the output terminal (V) of the reference column line (RL). refIt can receive the voltage of ) and, based on this, perform the operation as described above to output the result value.

[0081] Here, the word line driving unit (310), bit line driving unit (320), and the operation unit (not shown) and control circuit (not shown) of the control unit (300) have been described as separate components, but this is for convenience of explanation and the embodiments of the present invention are not limited thereto. For example, some of the respective functions of the word line driving unit (310), bit line driving unit (320), operation unit (not shown), and control circuit (not shown) of the control unit (300) as described above may be performed in other components among the word line driving unit (310), bit line driving unit (320), operation unit (not shown), and control circuit (not shown) of the control unit (300). In addition, each of the word line driving unit (310), bit line driving unit (320), operation unit (not shown), and control circuit (not shown) of the control unit (300) may be implemented as two or more components, or two or more may be combined to be implemented as a single component.

[0082] A memory device (10) according to one embodiment of the present invention has a processing-in-memory (PIM) structure, so that a memory cell array (100), a power supply unit (200), and a control unit (300) may be placed on a single base (e.g., a substrate). However, the embodiments of the present invention are not limited thereto, and as long as it does not contradict the purpose of the present invention, some components may be placed outside the memory device (10) and electrically connected to or communicate with the memory device (10). For example, only the memory cell array (100) and the operation unit (not shown) of the control unit (300) may be formed on a single base, and other components may be placed outside the memory device (10), that is, outside the base (e.g., a substrate) on which the memory cell array (100) and the operation unit (not shown) are placed, and electrically connected to or communicate with the memory cell array (100) and the operation unit (not shown). At this time, the word line driving unit (310), bit line driving unit (320), operation unit (not shown) and control circuit (not shown) of the memory cell array (100), power supply unit (200) and control unit (300) may be electrically connected to each other or connected via a network to exchange signals.

[0083] As the memory device (10) is configured in this manner, the memory device (10) according to one embodiment of the present invention does not include a transimpedance amplifier (TIA) that was provided in a conventional memory device, and can perform calculations based on the output voltage of the bit line (BL).

[0084] That is, a memory device (10) according to one embodiment of the present invention can perform calculations using a voltage sensing method. In addition, a memory device (10) according to one embodiment of the present invention can be configured by adding only a reference column line (RL) while using the conventional memory cell array configuration as is without changing the configuration.

[0085] FIG. 3 is a diagram for explaining the resistance state of a memory cell set for a first operation of a memory device according to an embodiment of the present invention.

[0086] Referring to FIG. 3, in one example, the first operation performed by the memory device (10) is an AND operation. For example, as shown in FIG. 3, for the AND operation of the memory device (10), a third resistor (R) connected to the reference column line (RL) is used. ref_i,a ) is a high resistance state (HRS, hereinafter "R H (also called) and the fourth resistor (R ref_i,b ) is the low resistance state (LRS, hereinafter "R L Can have (also called)

[0087] For example, the AND operation performed by the memory device (10) can follow the following Equation 2.

[0088] [Equation 2]

[0089]

[0090] Here, V out is each output terminal (V) of a plurality of bit lines (BL). out It is the voltage of ), and V ref is the output terminal (V) of the reference column line (RL). ref It is the voltage of ), and V IN_i is an input voltage applied to the i-th power supply of the power supply unit (200), and R i is the resistance state of the i-th first resistor, and R H is a resistance value having a high resistance state, and R L is a resistance value that has a low resistance state.

[0091] Referring to Equation 2, the numerator of the right-hand side " "is V IN_i , R i , resistance state of the third resistor (R ref_i,a ) and the resistance state of the fourth resistor (R ref_i,bIt is the estimated result of the AND operation of the memory device (10) calculated based on ).

[0092] According to Equation 2, the denominator on the right side " " is the first to fourth resistors (R i,j , , R ref_i,a , R ref_i,b Regardless of the resistance state of ), more specifically, the first and second resistors (R i,j , Since it always has a constant value (e.g., a constant) regardless of the resistance state of the memory device (10) according to one embodiment of the present invention, the result of the AND operation of the memory device (10) can be determined as a unique value.

[0093] For example, each output terminal (V) of a plurality of bit lines (BL). out The voltage of ) and the output terminal (V) of the reference column line (RL). ref The difference in voltage (V) out -V ref ) is the estimated result of the AND operation of the memory device (10), for example, " Depending on the, it can be constant, for example, with a 1:1 correspondence.

[0094] For example, when the input voltage input to the power supply unit (200) is 1, V IN_i Having this high voltage; when the input voltage input to the power supply (200) is 0, V IN_i It has this low voltage (low); and the first resistor (R i When the weight of ) is 1, the first resistor (R i The resistance state of ) is the low resistance state (R L ) and; the first resistor (R i When the weight of ) is 0, the first resistor (R i The resistance state of ) is the high resistance state (R H If we assume ), then Equation 2's " " can have a significantly larger value than in other cases when both the input voltage and the weight are 1. That is, the memory device (10) has an estimated value of the calculation result (V) only when both the input voltage and the weight are 1. out -V ref ) can perform an AND operation where one has a high voltage (high) and the other has a low voltage (low).

[0095] For example, the result of the AND operation of the memory device (10) according to one embodiment of the present invention may be as shown in Table 1 below.

[0096] V IN =High V IN =Low First resistor: R L Second resistor: R H Calculation Result: High Calculation Result: Low First resistor: R H Second resistor: R L Calculation Result: Low Calculation Result: Low

[0097] FIG. 4 is a diagram illustrating the resistance state of a memory cell set for a second operation of a memory device according to an embodiment of the present invention. Referring to FIG. 4, in one example, the second operation performed by the memory device (10) is a plurality of power supplies (V) of a power supply unit (200). IN_i The sign of the input value of ) and the first and second resistors (R i,j , It is a coding operation (signed input / signed weight) based on the sign of the weight values ​​of ). For example, in the coding operation, multiple power sources (V IN_i The sign of the input value of ) and the first resistor (R i,j The operation result may increase or decrease depending on the sign of the weight value of ). For example, referring to FIG. 4, for the encoding operation of the memory device (10), a third resistor (R) connected to the reference column line (RL) ref_i,a ) is a high resistance state (R H ) having, the fourth resistor (R ref_i,b ) also high resistance state (R H Can have ).

[0098] For example, the encoding operation performed by the memory device (10) may follow the following Equation 3.

[0099] [Equation 3]

[0100]

[0101] Here, V out is each output terminal (V) of a plurality of bit lines (BL). out It is the voltage of ), and V ref is the output terminal (V) of the reference column line (RL). ref It is the voltage of ), and V IN_i is an input voltage applied to the i-th power supply of the power supply unit (200), and R i is the resistance state of the i-th first resistor, and R H is a resistance value having a high resistance state, and R L is a resistance value that has a low resistance state.

[0102] In Equation 3, the numerator of the right-hand side " "is V IN_i , R i , resistance state of the third resistor (R ref_i,a ) and the resistance state of the fourth resistor (R ref_i,b It is an estimated value of the result of the encoding operation of the memory device (10) calculated based on ).

[0103] In Equation 3, the denominator on the right side " " is the first to fourth resistors (R i,j , , R ref_i,a , R ref_i,b Regardless of the resistance state of ), more specifically, the first and second resistors (R i,j , Since it always has a constant value (e.g., a constant) regardless of the resistance state of the memory device (10), the result of the encoding operation of the memory device (10) can be determined as a unique value.

[0104] For example, each output terminal (V) of a plurality of bit lines (BL). out The voltage of ) and the output terminal (V) of the reference column line (RL). ref The difference in voltage (V) out -V ref) is the estimated result of the encoding operation of the memory device (10), for example, " Depending on the, it can be constant, for example, with a 1:1 correspondence.

[0105] In Equation 3, the numerator of the right-hand side " " is, R i Resistance state with a high value of (R H In the case of ), approximately and R i Resistance state with a low value (R L In the case of ), approximately It can be. For example, the first resistor (R i The resistance state of ) is a low resistance state (R) with a weight of 1. L ) and input voltage (V IN_i If ) is positive, the estimated result of the operation (V out -V ref ) can increase. For example, the first resistor (R i The resistance state of ) is a high resistance state (R) with a weight of -1. H ) and input voltage (V IN_i If ) is negative, the estimated value of the operation result (V out -V ref ) can increase. For example, the first resistor (R i The resistance state of ) is a low resistance state (R) with a weight of 1. L ) and input voltage (V IN_i If ) is negative, the estimated result of the operation (V out -V ref ) can be reduced. For example, the first resistor (R i The resistance state of ) is a high resistance state (R) with a weight of -1. H ) and input voltage (V IN_i If ) is positive, the estimated result of the operation (V out -V ref ) can be reduced. That is, the memory device (10) has a plurality of power supplies (VIN_i The sign of the input value of ) and the first resistor (R i A encoding operation can be performed in which the result of the operation increases or decreases depending on the sign of the weight value of ).

[0106] For example, the result of the encoding operation of the memory device (10) according to one embodiment of the present invention may be as shown in Table 2 below.

[0107] V IN = positive V IN = negative First resistor: R L Second resistor: R H Operation result: Increment(+) Operation result: Decrease(-) First resistor: R H Second resistor: R L Operation result: Decrease(-) Operation result: Increment(+)

[0108] FIG. 5 is a diagram for explaining the equivalent resistance viewed from the power supply of a memory device (10) according to one embodiment of the present invention.

[0109] In one embodiment, a plurality of power sources (V) of the voltage section (200) IN_i The equivalent resistance viewed from each of the ) (e.g., load resistance) is the resistance (R) in the high resistance state (HRS). H ) and resistance (R) of the low resistance state (LRS) L ) may appear to be connected in series. As such, according to the present invention, a plurality of power sources (V IN_i The equivalent resistance viewed from each of the ) can have a relatively large resistance value. For example, compared to the case where a single resistor connected to each power source in a conventional memory device has a low resistance state, it can have a significantly large resistance value. In the memory device (10) according to one embodiment of the present invention, since the resistance value is relatively large in this way, the voltage unit (200) can drive a relatively small current, and as a result, the burden on the voltage unit (200) can be reduced.

[0110] FIG. 6 is a flowchart of a method for driving a memory device according to an embodiment of the present invention. For example, the method for driving a memory device according to the present embodiment is a method for driving the memory device (10) of FIG. 2.

[0111] Referring to FIG. 2 and 6, according to a method for driving a memory device according to an embodiment of the present invention, a first resistor (R) is set to one of a high resistance state (HRS) or a low resistance state (LRS) corresponding to a set weight value. i,j The resistance state of ) is set (S100). Here, the set weight value may be set in advance according to the purpose and conditions of use of the memory device, or may be set and changed by input from a user or an external system.

[0112] Additionally, referring to FIGS. 2 and 6, according to a method for driving a memory device according to an embodiment of the present invention, a second resistor ( The resistance state of ) is set (S200). For example, the first resistor (R i,j ) and the second resistor ( ) can have different resistance states.

[0113] Then, referring to FIGS. 2 and 6, depending on the type of operation performed by the memory device (10), a third resistor (R ref_i,a ) and the fourth resistor (R ref_i,b The resistance state of ) is set (S300). For example, depending on the type of operation performed by the memory device (10), the third resistor (R) is set to the first reference resistance state for the operation. ref_i,a The resistance state of ) is set, and the fourth resistor (R) is set to the second reference resistance state for calculation. ref_i,b The resistance state of ) is set.

[0114] Then, referring to FIGS. 2 and 6, a plurality of power sources (V) of the power supply unit (200) IN_i The input voltage of ) and the first to fourth resistors (R i,j , , R ref_i,a , R ref_i,bBased on the output voltage of the bit line (BL) and the output voltage of the reference column line (RL) according to the resistance state of ), an operation is performed and a result value is output (S400). For example, the memory device (10) can perform an operation based on the difference between the output voltage of the bit line (BL) and the output voltage of the reference column line (RL) and output a result value.

[0115] According to a method for driving a memory device according to an embodiment of the present invention, each output terminal (V) of a plurality of bit lines (BL) out The equivalent resistance viewed from ) is the first and second resistors (R i,j , It can be constant regardless of the resistance state of ). In addition, the operation result of the memory device (10) corresponding to the output voltage of each of the multiple bit lines (BL) can be determined as a unique value. For example, the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL) out -V ref ) may be constant depending on the estimated value of the result of the operation of the memory device (10). For example, the difference (V) between the output voltage of each of the multiple bit lines (BL) and the output voltage of the reference column line (RL). out -V ref ) can correspond 1:1 with the estimated result of the operation of the memory device (10).

[0116] Meanwhile, for convenience of explanation, the method for driving a memory device according to one embodiment of the present invention has been described as having steps S100, S200, S300, and S400 performed in sequence, but the embodiments of the present invention are not limited thereto. For example, each of the steps (S100, S200, S300, S400) of the method for driving a memory device according to one embodiment of the present invention may be performed in a different order or simultaneously. For example, the first resistor (R i,j S100 and the second resistor ( that set the resistance state of ) S200, which sets the resistance state of ), may substantially be performed simultaneously. In addition, the third resistor (R ref_i,a ) and the fourth resistor (R ref_i,b The step S300 in which the resistance state of ) is set is the first resistor (R i,j ) and second resistor( It may be performed before S100 and S200, which set the resistance state of ). Alternatively, S100, S200, and S300 may be performed substantially simultaneously.

[0117] FIG. 7 is a graph comparing the operating speed of a memory device according to the prior art and a memory device according to an embodiment of the present invention.

[0118] Specifically, FIG. 7 is a graph of the output voltage of a bit line representing a sweep from 0 to 15. In FIG. 7, the blue line represents the output voltage (V) of the bit line over time (ns) of a memory device including a conventional TIA (e.g., a memory device including a memory cell of FIG. 1a), and the red line represents the output voltage (V) of the bit line over time (ns) of a memory device (10) of FIG. 2 that does not include a TIA according to an embodiment of the present invention.

[0119] Referring to FIG. 7, in a memory device including a conventional TIA, it took more than 20 ns, for example, about 23.6 ns, for the output of the TIA to stabilize. On the other hand, in a memory device (10) according to one embodiment of the present invention, it can be seen that the voltage stabilized in about 0.5 ns. In addition, in a memory device (10) according to one embodiment of the present invention, it can be seen that the output voltage of the bit line increases linearly according to the operation result.

[0120] FIG. 8 is another graph comparing the operating speed of a memory device according to the prior art and a memory device according to an embodiment of the present invention.

[0121] In FIG. 8, the blue line represents the output voltage (V) of the bit line over time (ns) of a memory device including a conventional TIA (e.g., a memory device including a memory cell of FIG. 1a), and the red line represents the output voltage (V) of the bit line over time (ns) of a memory device (10) of FIG. 2 that does not include a TIA according to an embodiment of the present invention. FIG. 8 is, for example, a power supply unit of a conventional memory device (V0...V of FIG. 1a). n-1 Resistors (R0... R) connected to ) n-1 This indicates a case where all ) have a low resistance state, and also represents the first resistor (R) of the memory device (10) according to one embodiment of the present invention. i This represents the case where all resistors connected to the power supply have a low resistance state. In this way, when all resistors connected to the power supply have a low resistance state, the calculation result changes relatively significantly, and the stabilization time may increase relatively.

[0122] Referring to FIG. 8, in a memory device including a conventional TIA, when all resistors have a low resistance state, it takes about 49.1 ns for the output of the TIA to stabilize. However, in a memory device (10) according to an embodiment of the present invention, the first resistor (R i It can be seen that the voltage stabilizes in about 0.45 ns even when all of them have a low resistance state. That is, according to one embodiment of the present invention, the memory device (10) has a first resistor (R i It can be seen that the voltage stabilizes within a certain time, for example, about 0.5 ns, regardless of the resistance state of the device, that is, regardless of the operation result. In other words, the time required for the output voltage to stabilize has been reduced by more than 90% compared to conventional memory devices.

[0123] FIG. 9a is a graph showing the simulation results of the current of the power supply unit of a memory device according to the prior art. FIG. 9b is a graph showing the simulation results of the current of the power supply unit of a memory device according to an embodiment of the present invention.

[0124] FIGS. 9a and 9b show the current (μA) generated in the power supply unit over time (ns) when a memory device according to the prior art and a memory device according to one embodiment of the present invention each have 16 power supplies and perform the same operation.

[0125] Referring to FIG. 9a, a maximum current of approximately 68 μA was generated in 16 power supplies of a memory device including a conventional TIA (e.g., a memory device including a memory cell of FIG. 1a). On the other hand, referring to FIG. 9b, a maximum current of approximately 19 μA was generated in 16 power supplies of a memory device (10) of FIG. 2 according to an embodiment of the present invention. As such, according to an embodiment of the present invention, it can be confirmed that the amount of current generated from the power supplies is significantly reduced compared to the conventional structure.

[0126] Thus, according to one embodiment of the present invention, the memory device (10) can operate quickly and stably by removing the TIA and estimating the computation result of the memory device (10) through the bit line voltage. In addition, the memory device (10) according to one embodiment of the present invention can be used as is without modifying the conventional memory cell array, which is advantageous for technical applications. Furthermore, since no amplifier including the TIA is used in the memory device (10) according to one embodiment of the present invention, the overall area of ​​the circuit can be reduced. In addition, since the load resistance of the power supply unit in the memory device (10) according to one embodiment of the present invention is relatively large, less current is generated compared to the conventional structure, and thus the burden on the power supply unit can be reduced.

[0127] Those skilled in the art will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. The embodiments described above should be understood as illustrative in all respects and not restrictive, and the scope of the present invention is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalents thereof should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0128] 10: Memory device 100: Memory cell array 200: Power supply unit 300: Control unit V IN : Power WL: Word Line BL: Bit line RL: Reference column line R i,j : 1st resistor : 2nd resistor R ref_i,a : 3rd resistor R ref_i,b : 4th resistor

Claims

Claim 1 An array of multiple memory cells, each connected to one pair of word lines among a plurality of pairs of word lines arranged in a row, and to one of a plurality of bit lines or a reference column line among a plurality of bit lines arranged in a column; and a plurality of power supplies each connected between a first word line of each pair of the plurality of word lines and a second word line arranged adjacent to and below the first word line, wherein each of the plurality of memory cells includes a first resistor connected to one of the plurality of bit lines and the first word line, and a second resistor connected to one of the plurality of bit lines and the second word line; or a third resistor connected to the reference column line and the first word line, and a fourth resistor connected to the reference column line and the second word line, and performs operations based on the voltage of the plurality of bit lines and the voltage of the reference column line, and only one of the plurality of power supplies is grounded. Claim 2 A memory device according to claim 1, wherein the equivalent resistance viewed from each output terminal of the plurality of bit lines is constant regardless of the resistance state of the first and second resistors. Claim 3 A memory device according to claim 1, wherein the voltage of each output terminal of the plurality of bit lines is constant according to the result value of the operation. Claim 4 A memory device according to claim 1, wherein one of the first resistor and the second resistor has a high resistance state and the other has a low resistance state. Claim 5 In paragraph 4, the memory device, wherein the first resistor has a resistance state corresponding to a set weight value. Claim 6 A memory device according to claim 5, wherein the third resistor has a first reference resistor state for the operation and the fourth resistor has a second reference resistor state for the operation. Claim 7 A memory device according to claim 6, wherein when the above operation is an AND operation, the first reference resistance state is a high resistance state and the second reference resistance state is a low resistance state. Claim 8 A memory device according to claim 6, wherein when the above operation is a encoding operation based on the sign of the input value of the plurality of power sources and the sign of the set weight value, the first reference resistance state is a high resistance state and the second reference resistance state is a high resistance state. Claim 9 A memory device according to claim 1, wherein the operation is performed based on the difference between the voltage of each of the output terminals of the plurality of bit lines and the voltage of the output terminal of the reference column line. Claim 10 A memory device according to claim 1, wherein the difference between the voltage of each of the output terminals of the plurality of bit lines and the voltage of the output terminal of the reference column line corresponds 1:1 with the result of the operation. Claim 11 In claim 1, the above operation is performed according to the following Equation 1, [Equation 1] Here, V out is the voltage at the output terminal of each of the plurality of bit lines, and V ref is the voltage at the output terminal of the above-mentioned reference heat line, and V IN_i is the input voltage applied to the i-th power source among the plurality of power sources, and R i is the resistance state of the i-th first resistor, and R ref_i,a is the resistance state of the i-th third resistor, and R ref_i,b is the resistance state of the i-th fourth resistor, and R H is a resistance value having a high resistance state, and R L A memory device, wherein is a resistance value having a low resistance state and n is the number of pairs of the word lines. Claim 12 A memory device according to claim 1, wherein each of the plurality of power sources is disposed between the first resistor and the second resistor. Claim 13 A memory device according to claim 1, wherein the number of the plurality of power sources is equal to the number of the first resistors connected to one of the plurality of bit lines. Claim 14 A method for driving a memory device according to claim 1, comprising: a step of setting the resistance state of a first resistor to one of a high resistance state or a low resistance state corresponding to a set weight value; a step of setting the resistance state of a second resistor to the other of the high resistance state or the low resistance state; and a step of performing an operation based on the input of a plurality of power sources and the voltage of a plurality of bit lines and the voltage of a reference column line according to the resistance states of the first to fourth resistors. Claim 15 A method for driving a memory device according to claim 14, wherein the equivalent resistance viewed from each output terminal of the plurality of bit lines is constant regardless of the resistance state of the first and second resistors. Claim 16 A method for driving a memory device according to claim 14, wherein the voltage of each output terminal of the plurality of bit lines is constant according to the result of the operation. Claim 17 A method for driving a memory device according to claim 14, further comprising the step of setting the resistance state of the third resistor as a first reference resistance state for the above operation and setting the resistance state of the fourth resistor as a second reference resistance state for the above operation. Claim 18 A method for driving a memory device according to claim 14, wherein the above operation is performed based on the difference between the voltage of each of the output terminals of the plurality of bit lines and the voltage of the output terminal of the reference column line. Claim 19 A method for driving a memory device according to claim 14, wherein the difference between the voltage of each of the output terminals of the plurality of bit lines and the voltage of the output terminal of the reference column line corresponds 1:1 with the result of the operation. Claim 20 In Clause 14, the above operation is performed according to the following Equation 1, [Equation 1] Here, V out is the voltage at the output terminal of each of the plurality of bit lines, and V ref is the voltage at the output terminal of the above-mentioned reference heat line, and V IN_i is the input voltage applied to the i-th power source among the plurality of power sources, and R i is the resistance state of the i-th first resistor, and R ref_i,a is the resistance state of the i-th third resistor, and R ref_i,b is the resistance state of the i-th fourth resistor, and R H is a resistance value having a high resistance state, and R L A method for driving a memory device, wherein is a resistance value having a low resistance state and n is the number of pairs of the word lines.

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