Multi-state RF pulsing to control mask geometry and break the selectivity-to-process margin trade-off

Abstract

A method for performing an etching process on a substrate in a plasma processing system comprises the step of applying source RF power and bias RF power to an electrode, wherein the source RF power and bias RF power together are pulsed signals defining a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state, the first state is defined by source RF power having a first source RF power level and bias RF power having a first bias RF power level, the second state is defined by source RF power and bias RF power having substantially zero power levels, and the third state is defined by source RF power having a second source RF power level smaller than the first source RF power level and bias RF power having substantially zero power levels.

Description

Technology Field

[0001] Embodiments of the present disclosure relate to a multi-state RF pulsing regime for controlling mask geometry and breaking the selectivity versus process margin trade-off. Background Technology

[0002] RF pulsing technology has evolved over the past decade from operating in CW (Continuous Wave) mode to pulsing mode regimes (on-off, level-to-level). Advancements in 2-state RF pulsing have enabled high aspect ratio etching by improving process margin versus etching selectivity, profile bow, CD (Critical Dimension), and etching rate uniformity. In current 2-state RF pulsing nomenclature, "State 1" (or "S1") represents a high bias and source power state, for example, greater than 1 kW, operating at a pressure of less than 30 mTorr to obtain a narrow IADF and having an ion energy greater than 3 keV. The other state of the pulse, designated as "State 0" (or "S0"), represents a deposition step with low bias and source power, for example, less than 1 kW, and an ion energy of less than 100 eV. State 0 primarily provides passivation due to different mechanisms such as direct ion deposition and ion-activated neutral deposition. A typical pulse repetition rate for operating this 2-state RF pulsing regime is about 100 Hz to 2 kHz.

[0003] As device sizes continue to shrink and pitch sizes decrease (e.g., from 100 nm to less than 60 nm), it is difficult to break the etching selectivity versus process margin trade-off under current pulsing technology. Current technology regimes struggle to balance the integrity of high aspect ratio etching while maintaining sufficient process margins (e.g., under-etch, not open, capping).

[0004] In this context, embodiments of the present disclosure occur.

[0005] Embodiments of the present disclosure include methods and systems for a multi-state RF pulsing regime for controlling mask shape and breaking the selectivity-to-process margin trade-off.

[0006] One of the major challenges in High Aspect Ratio (HAR) contact etching is maintaining an appropriate process margin while attempting to selectively etch a stack relative to a mask (e.g., Poly). Generally, the process margin is related to the shape and size of the necking because it establishes a limiting aspect ratio during the HAR process. However, embodiments of the present disclosure provide a method to control the mask (neck) shape and improve the selectivity versus process margin trade-off.

[0007] According to embodiments of the present disclosure, multi-state RF pulsing having intermediate states based on a source power-only regime helps control the mask shape (trim the neck) without causing undesirable mask faceting. Combining this source power-only pulsing regime with conventional two-state on-off pulsing significantly improves the margin-to-selectivity trade-off to take advantage of the benefits of HAR process improvement knobs.

[0008] In some embodiments, a method for performing an etching process on a substrate in a plasma processing system is provided, the method comprises the steps of: applying source RF power to an electrode of the plasma processing system; and applying bias RF power to the electrode, wherein the source RF power and the bias RF power are pulsed signals together defining a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state, the first state is defined by a source RF power having a first source RF power level and a bias RF power having a first bias RF power level, the second state is defined by a source RF power having a substantially zero power level and a bias RF power having a substantially zero power level, and the third state is defined by a source RF power having a second source RF power level smaller than the first source RF power level and a bias RF power having a substantially zero power level.

[0009] In some implementation examples, the first state is configured to affect the etching of a feature on the surface of the substrate.

[0010] In some implementation examples, the second state is configured to affect the passivation of features on the surface of the substrate.

[0011] In some implementation examples, the third state is configured to affect the removal of material forming the neck in the feature.

[0012] In some implementation examples, the bias RF power has a frequency of less than about 10 MHz.

[0013] In some implementation examples, the source RF power has a frequency greater than about 20 MHz.

[0014] In some implementation examples, the third state has a duration of approximately 1 to 5 times the duration of the first state.

[0015] In some implementation examples, the second state has a duration nearly identical to the duration of the first state.

[0016] In some implementation examples, the first source RF power level is in the range of approximately 1 to 6 kW, and the first bias RF power level is in the range of approximately 5 to 20 kW.

[0017] In some implementation examples, the second source RF power level is in the range of approximately 100 W to 6 kW.

[0018] In some implementation examples, in each cycle, the third state immediately follows the second state.

[0019] In some implementation examples, in each cycle, the second state leads directly to the third state.

[0020] In some embodiments, a controller device is provided and configured to allow a plasma processing system to perform an etching process on a substrate in the plasma processing system, and the method comprises: applying source RF power to an electrode of the plasma processing system; and applying bias RF power to the electrode, wherein the source RF power and the bias RF power are pulsed signals together defining a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state, the first state is defined by a source RF power having a first source RF power level and a bias RF power having a first bias RF power level, the second state is defined by a source RF power having a substantially zero power level and a bias RF power having a substantially zero power level, and the third state is defined by a source RF power having a second source RF power level smaller than the first source RF power level and a bias RF power having a substantially zero power level.

[0021] It will be recognized that the foregoing represents a summary of specific, non-limiting embodiments of the present disclosure. Additional embodiments will be obvious to those skilled in the art within the scope of the present disclosure. Brief explanation of the drawing

[0022] FIG. 1a conceptually illustrates a cross-sectional perspective view of a conventional DRAM device (100) according to embodiments of the present disclosure. FIG. 1b conceptually illustrates a cross-sectional perspective view of high aspect ratio etched features according to embodiments of the present disclosure. FIG. 2a is a graph of RF power versus time for a single pulsed RF cycle for an etching process according to embodiments of the present disclosure. FIGS. 2b and 2c conceptually illustrate cross-sectional views of etched features according to the S1 state and S0 state, respectively, of the level-to-level pulsing process described above. Figure 3 conceptually illustrates the trade-offs of current RF pulsing technology. FIGS. 4a, 4b, and 4c conceptually illustrate RF power versus time for a multi-state pulsed RF cycle according to embodiments of the present disclosure. FIGS. 4d, FIGS. 4e, and FIGS. 4f conceptually illustrate cross-sections of etched features illustrating the effects of each state of the multi-state pulsed RF cycle described herein. FIG. 5 conceptually illustrates varying the length of state S2 over time during the etching of a feature according to embodiments of the present disclosure. FIGS. 6a, 6b, and 6c illustrate graphs illustrating RF power versus time for a multi-state RF pulsing cycle according to embodiments of the present disclosure. FIGS. 6d, 6e, and 6f conceptually illustrate cross-sections of etched features demonstrating the effects of states S1, S2, and S0 according to the implementation examples of FIGS. 6a, 6b, and 6c. FIG. 7 conceptually illustrates the expansion of the process window by using the multi-state RF pulsing regime described in this specification. FIG. 8 illustrates an exemplary ICP deposition system according to embodiments of the present disclosure. FIG. 9 illustrates a control module for controlling the systems described above, according to embodiments of the present disclosure. Specific details for implementing the invention

[0023] In the description above, numerous specific details have been provided to provide a complete understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other examples, known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. It will be understood that while the disclosed embodiments have been described together with specific embodiments, this is not intended to limit the disclosed embodiments.

[0024] Currently, modern dielectric etching processes rely on implementations of one or two RF regimes supported by on / off or level-to-level RF pulsing to combine the benefits of high vertical etching rates and appropriate sidewall passivation. However, according to the embodiments of the present disclosure, additional regimes are identified that can independently recover or add greater margins in the process. The embodiments are provided based on these regimes, which incorporate suitable intermediate states based on implementing a multi-state RF pulsing scheme that overcomes fundamental process development limitations and barriers in existing etching technologies. The intermediate states are based on the preferential trimming of the mask neck polymer in a low ion energy state to facilitate a more aggressive high energy state (On / High state) and a more polymerizing passivation state (Off / Low state). Introducing these low-ion energy states using source power helps only control the neck / mask geometry. Combining this approach with on-off pulsing instead of level-to-level pulsing drives more polymer deposition on the top of the mask, passivates the top of the mask, and controls the mask etching rate. This approach fundamentally enables the breaking of the trade-off between mask neck / process margin and selectivity.

[0025] FIG. 1a conceptually illustrates a cross-sectional perspective view of a conventional DRAM device (100) according to embodiments of the present disclosure. A conventional DRAM device may be composed of stacks with a height of 1 to 1.5 μm, and the fabrication of such DRAM devices involves the fabrication of capacitors (102) involving a capacitor etching process. Capacitor etching is an example of a dielectric etching process that requires suitable etching of very high aspect ratio features (conceptually illustrated in reference numeral 104), which is, for example, approximately 60 to 100 to 1 depending on the node. Furthermore, as pitch sizes are scaled to become progressively smaller and aspect ratios increase, there is a smaller tolerance for defects in the etching process. For capacitor etching, the pitch size may be smaller than 50 nm, for example, without limitation. Although embodiments of the present disclosure are described with reference to capacitor etching, it will be recognized that the principles of the present disclosure can be applied to any high aspect ratio dielectric etching (e.g., 3D NAND, e.g., memory hole etching) in any applicable device context.

[0026] FIG. 1b conceptually illustrates a cross-sectional perspective view of high aspect ratio etched features according to embodiments of the present disclosure. Some problems that may occur in high aspect ratio etching are conceptually further illustrated, such as in the context of manufacturing DRAM capacitors as described above. The problems include: bowing of a feature where part of the etching profile becomes reentrant; twisting of a feature where the etching direction deviates laterally from a straight vertical direction; critical dimensional variation from top to bottom, such as the feature being wider at the top than at the bottom; incomplete etching where the feature fails to be completely etched to reach a target endpoint; and poor selectivity of the hard mask, which can etch the hard mask so that the hard mask becomes facet and exacerbate the bowing problem.

[0027] Therefore, in high aspect ratio etching, it is desirable to achieve profile control to enable bow-free, straight-profile etching with minimal twisting and minimum aspect ratio dependent etch (ARDE). Selectivity for the hard mask, such as preventing incomplete etching (under-etch), is targeted. Furthermore, uniformity across the wafer, as well as the maintenance of the integrity of the bottom layer, is sought.

[0028] FIG. 2a is a graph of RF power versus time for a single pulsed RF cycle for an etching process according to embodiments of the present disclosure. Bias RF power and source RF power over time during a single pulsed RF cycle are plotted. Under current RF pulsing technology, a two-state pulsing regime using level-to-level or on-off pulsing is employed. In this two-state pulsing regime, State 1 (S1) is a high ion energy generating state where the source RF and bias RF are in high power states, whereas State 0 (S0) is a low ion energy generating state where the source RF and bias RF are in low power or completely off states. Since S1 generates high-energy ions directed to activate the surface and etch the film, the function of S1 is to etch the dielectric material. The main role of S0 is passivation, but since S0 is primarily driven neutrally, it drives passivation in the etched features, but there may still be some low energy to maintain the etching.

[0029] FIGS. 2b and 2c conceptually illustrate cross-sectional views of etched features according to the S1 and S0 states, respectively, of the level-to-level pulsing process described above. As illustrated, S1 primarily enables the etching of high aspect ratio features, but may also induce sputtering of the mask and the formation of a "neck" profile. S0 primarily enables passivation, mask protection via direct ion deposition, and ion-assisted neutral deposition.

[0030] Therefore, when using level-to-level (L2L) pulsed RF, S1 provides high aspect ratio etching but also sputters and forms a neck; S0 provides ion-assisted neutral deposition. However, both induce some degree of necking, and as one moves toward higher AR and smaller pitches, opening the neck becomes difficult. With L2L, the tightest critical dimension occurs at the neck, which tends to throttle the etching when going toward very small feature sizes or pitch sizes. For example, the neck AR can be nearly twice the feature AR. This also limits the types of chemicals that can be applied and the amount of energy that can be applied into the structure to be etched, and thus acts as a limiter in high aspect ratio etching.

[0031] Figure 3 conceptually illustrates the trade-offs of current RF pulsing technology. For example, in dielectric high aspect ratio contact etching (e.g., in DRAM and 3DNAND), there are several limitations and constraints when utilizing the current level-to-level RF pulsing regime. For State 1, under current level-to-level pulsing, a high power bias (e.g., 400 kHz frequency) is desirable, but it is not practically usable due to hole clogging at a high 400 kHz:60 MHz ratio. Furthermore, chemical tuning to compensate for this results in excessive bow. For State 0, low power is used to maintain mask selectivity and bow. Higher power can improve clogging but compromises mask selectivity. Given these constraints, it is difficult to overcome the trade-offs of two-state pulsing.

[0032] Therefore, current technology faces limitations in terms of scaling. As stacks become increasingly longer, the aspect ratio grows, and the etching rate decreases more steeply across features as a function of aspect ratio-dependent etching (ARDE). Thus, to maintain the profile at deeper aspect ratios, the conventional trade-off is the stack etching rate due to ARDE. To protect against bowing at increasingly tighter pitches, high ion energies are used to facet the mask. That is, S1 operates to generate a high ion energy state, causing mask faceting. Meanwhile, to reduce costs at lower pitch sizes, manufacturers seek to reduce the amount of mask material. As the industry moves toward increasingly lower pitches, given the mask and the stack underneath, cost reduction is sought by using less mask material. Therefore, selectivity for the mask is important. However, to improve selectivity at high aspect ratios, the trade-off is clogging. Holes clog each other, which leads to device failure.

[0033] Therefore, under the current RF pulsing regime, these trade-offs are visible, and it is difficult to break the trade-offs to improve the profile in any one direction.

[0034] However, according to embodiments of the present disclosure, a multi-state RF pulsing regime is introduced as an intermediate state based on a source power-only regime. This multi-state RF pulsing regime significantly improves the margin-to-selectivity trade-off to enable improved etching of high aspect ratio features with suitable profile and mask selectivity.

[0035] FIGS. 4a, 4b, and 4c conceptually illustrate RF power versus time for a multi-state pulsed RF cycle according to embodiments of the present disclosure. FIG. 4a illustrates both bias RF power and source RF power. For additional clarity, FIG. 4b illustrates only bias RF power over time, and FIG. 4c illustrates only source RF power over time. FIGS. 4d, 4e, and 4f conceptually illustrate cross-sections of etched features illustrating the effects of each state of the multi-state pulsed RF cycle described herein. The pulsed RF cycle may be characterized as tri-level pulsed RF employing three distinct RF states. As illustrated in the illustrated embodiments, S1 is configured to provide high source power and high bias power. As illustrated in FIG. 4d, this generates a high aspect ratio (HAR) etch but also sputters the mask to form a neck. S0 is configured in an off state with no source or bias power applied. As illustrated in FIG. 4e, S0 drives more neutral deposition from the top to protect the mask. In some embodiments, S0 is configured to provide direct ion deposition and ion-assisted neutral deposition.

[0036] The intermediate state S2 (State 2) is configured as a source power-only state (e.g., 60 MHz, high frequency) using low source power and zero bias power. As shown in Fig. 4f, S2 helps to open the neck by inducing dissociation and etching all necks that are formed. Thus, state S2 is configured to open the neck.

[0037] Accordingly, according to embodiments of the present disclosure, S1 forming the neck uses high-energy ions, while S2 opens the neck, and S0 provides a lot of passivation. The resulting feature has an open neck and also has more masks due to the more passivation. This resolves the neck-to-selectivity trade-off problem.

[0038] In contrast, in a level-to-level RF pulsing regime where only S1 and S0 are executed, there is a lot of passivation, but there will also be a blocked neck. However, using a 3-level RF pulsing regime employing S1, S0, and S2 provides open necks and passivation that destroys the selectivity versus cap margin trade-off. Generally speaking, state S0 provides selectivity, while state S2 improves the cap margin.

[0039] Generally speaking, in some implementations, the bias power is at a frequency of about 10 MHz or less. In some implementations, the bias power is at a frequency of about 400 kHz.

[0040] In some implementations, the source power is at a frequency of about 10 MHz or higher. In some implementations, the source power is at a frequency greater than about 20 MHz. In some implementations, the source power is at a frequency of about 60 MHz.

[0041] In some implementation examples, the bias frequency and source frequency are applied to the chuck using different generators.

[0042] In various implementation examples, it will be recognized that specific parameters of bias power and source power may vary in each of the states.

[0043] In some embodiments, the S1 bias power is in the range of about 5 to 20 kW. In some embodiments, the S1 source power is in the range of about 1 to 6 kW. In some embodiments, one or both of the S1 bias power and the S1 source power may vary over time, for example, depending on the elapsed time of etching within the feature, the current depth of the feature, or the current aspect ratio of the feature. In some embodiments, the S1 bias power and / or the S1 source power are configured to increase as the elapsed etching time, depth, or aspect ratio increases.

[0044] Generally speaking, the S0 state is considered to be an off state where both the bias power and the source power are substantially at or near zero levels.

[0045] In some embodiments, the S2 bias power is substantially zero or nearly zero. In some embodiments, the S2 source power is in the range of about 100 W to 6 kW. In some embodiments, the S2 source power may vary over time depending, for example, the elapsed time of etching within the feature, the current depth of the feature, or the current aspect ratio of the feature. In some embodiments, the S2 source power is configured to increase as the elapsed etching time, depth, or aspect ratio increases.

[0046] It will be recognized that the relative durations of S1, S0, and S2 may also be configured to provide suitable etching profiles and etching rates according to embodiments of the present disclosure. In some embodiments, the ratio of the durations of S2 to S1 is in the range of about 1 to 1 (1:1) to 5 to 1 (5:1).

[0047] In some implementations, the ratio of the durations of S0 to S1 is approximately 1 to 1 (1:1). In some implementations, this ratio may vary.

[0048] It will be recognized that the relative durations of the various states may depend on the pitch, etching depth, and parameters to be controlled. For example, for a relatively shallow AR etch, S2 does not need to be very long to open the neck because AR does not play a significant role at the start of the etch. However, as the etch becomes deeper and higher AR etching is required, S2 plays a significant role in opening the neck to enable higher aspect ratio etching.

[0049] FIG. 5 conceptually illustrates varying the length of state S2 over time during the etching of a feature according to embodiments of the present disclosure. In the illustrated graph (500), the duration of S2 versus the etching depth / time / aspect ratio is illustrated. As indicated, the duration of S2 increases as the current etching depth within the feature, or the etching time of the feature, or the current aspect ratio of the feature increases. Without limitation, for example, if the feature has a relatively shallow depth and consequently a lower aspect ratio (conceptually illustrated in reference no. 502), the source RF power profile may appear as illustrated by graph (504) with a relatively short duration of S2, as this may be the case during the initial etching of the feature. In contrast, if the feature has a relatively deep depth and consequently a higher aspect ratio (conceptually illustrated in reference number 506), the source RF power profile may appear as illustrated by graph (504) with a relatively long period of S2, as this may be the case for the late etching of the feature.

[0050] Therefore, as the neck opening step becomes more critical for maintaining the etching profile, the higher the aspect ratio, the longer the S2 duration. The durations of S1, S0, and S1 are all scalable, and there may also be a dependency of S2 on S1 and S0. The source RF power is configured to passivate following the removal of the neck.

[0051] In the implementation examples described above, various states were executed in the order S1-S0-S2 (and repeated). Generally speaking, this provides etching (provided by S1), followed by passivation (provided by S0), followed by neck opening (provided by S2).

[0052] However, in other implementation examples, S2 may occur between S1 and S0 such that the sequence of states is S1-S2-S0 (and is repeated). This provides etching (provided by S1), followed by neck opening (provided by S2), followed by passivation (provided by S0).

[0053] FIGS. 6a, 6b, and 6c illustrate graphs illustrating RF power versus time for a multi-state RF pulsing cycle according to embodiments of the present disclosure. FIG. 6a illustrates both bias RF power and source RF power over time. For further clarity, FIG. 6b illustrates bias RF power over time alone, and FIG. 6c illustrates source RF power over time alone. In the illustrated embodiments, the states are executed in the order S1-S2-S0. As in the previously described embodiments, S1 is a high ion energy state employing high bias power and high source power. S2 is a source power only state employing substantially zero bias power and low source power. S0 is an off state employing substantially zero bias power and substantially zero source power.

[0054] FIGS. 6d, 6e, and 6f conceptually illustrate cross-sections of etched features demonstrating the effects of states S1, S2, and S0 according to embodiments of FIGS. 6a, 6b, and 6c. As shown in FIG. 6d, state S1 generates high ion energy to enable etching of high aspect ratio features, but also generates sputtering of the mask and causes a neck to form within the feature. As shown in FIG. 6e, state S2 generates low ion energies at intermediate ion energies that open the neck. As shown in FIG. 6f, state S0 protects the mask by enabling direct ion deposition and ion-assisted neutral deposition.

[0055] Embodiments of the present disclosure are applicable to dielectric etching. In some embodiments, fluorine-based chemicals, e.g., fluorocarbons, hydrofluorocarbons, etc. are employed.

[0056] When the RF pulsing regime was initiated, it operated in on-off pulsing (S1S0). However, this generated a significant amount of passivation, and thus the industry shifted to level-to-level pulsing where some power was in S0. However, this resulted in a loss of the advantage of greater selectivity because supplying more power introduced ions that sputtered the passivation. However, using the 3-level multi-state RF pulsing provided herein, a new source-only state is used where the neck is open while passivation is still in use. This destroys the conventional process trade-off between selectivity and neck.

[0057] FIG. 7 conceptually illustrates the expansion of the process window by using the multi-state RF pulsing regime described herein. In particular, there is a trade-off between the not-open margin and bridging. The not-open state, where HAR etching fails due to the construction of a neck at the feature opening, is illustrated by reference numeral 700. However, the trade-off for the not-open state is the bowing of the feature, which bridges the features to each other, creating open contacts that potentially cause device failure. Thus, while a process window exists between the not-open state and the bridging state, it becomes narrower as the CD / pitch size decreases with each new / advanced technology node. Therefore, the primary process objective is to achieve bow reduction without sacrificing the not-open margin in order to expand high aspect ratio contact etching capabilities. Improvement of the not-open margin is sought through a smaller neck / larger capping margin; And improvement of the bridge margin for bow reduction is also pursued.

[0058] Graph (704) shows a plot of defect versus post-etching inspection, illustrating process windows under continuous wave (Ref. 706), level-to-level (Ref. 708), and the currently described 3-level (Ref. 710) RF pulsing regimes.

[0059] From previous Continuous Wave (CW) regimes, as the pitch size decreases, the technology moves to level-to-level pulsing, where pulsing proceeds between the etching state and the passivation state, which improves the process window for high aspect ratio etching. However, the technology has now advanced to the point where the pitch size determines how well high aspect ratio features can be etched. As illustrated, the 3-level RF pulsing regime introduced herein widens the window for process operation, enabling etching without device failure. As can be seen, the process window is now wider, and it becomes possible to control defects within this window.

[0060] As described, clogging can occur when there is too much polymer on the neck and the feature opening is blocked, or bridging can occur due to a very large bowing where holes are bridging into one (creating an open contact). Under continuous wave mode, a profile as shown in reference no. 712 may be observed, which primarily clogs the neck. Under level-to-level mode, a profile as shown in reference no. 714 is provided, with a larger neck and a smaller bow, so clogging is controlled but the process window is very short. However, using 3-level pulsing according to embodiments of the present disclosure, a profile as shown in reference no. 716 provides a much wider open neck and a much better process window. As the neck ARDE is relaxed, faster etching rates and better selectivity are possible.

[0061] Another advantage is that the 3-level RF pulsing regime enables a wider selection of chemicals. While it is usually difficult to introduce new chemicals as pitch sizes become smaller, providing a wider process window opens up not only the RF regime but also the chemical regime, enabling the application of more passivating chemicals to passivate the sidewalls.

[0062] Various embodiments described herein may be performed in a plasma processing system. Referring to FIG. 8, an exemplary plasma processing system or apparatus may include a chamber (801) having a gas injector / showerhead / nozzle (803) for dispensing gases (805, 807, 809) (e.g., reactive material gas and purge gas) or other chemicals into the chamber (801), chamber walls (811), and a chuck (813) for holding a substrate or wafer (815) to be processed, which may include electrostatic electrodes for chucking and dechucking the wafer. The chuck (813) is heated for thermal control and enables the substrate (815) to be heated to a target temperature. In some embodiments, the chuck (813) may be electrically charged using an RF power supply (817) to provide a bias voltage according to embodiments of the present disclosure.

[0063] A source RF power supply (819) is configured to supply source RF power to an electrode in a chuck (813) to generate plasma (825) in a process space on a substrate (815). In some embodiments, the chamber walls are heated to support thermal management and efficiency. A vacuum source (827) provides a vacuum to exhaust gases from the chamber (801). The system or device may include a system controller (829) for controlling some or all of the operations of the chamber or device, such as controlling chamber pressure, inert gas flow, plasma source power, plasma source frequency, reactive gas flow; bias power, bias frequency, temperature, vacuum settings; and other process conditions.

[0064] In some implementation examples, the system / device may include one or more chambers for processing substrates.

[0065] FIG. 9 illustrates a control module (900) for controlling the systems described above, according to embodiments of the present disclosure. For example, the control module (900) may include a processor, memory, and one or more interfaces. The control module (900) may be employed to control the devices of the system based partially on sensed values. For example, the control module (900) may control one or more of valves (902), filter heaters (904), pumps (906), and other devices (908) based on sensed values ​​and other control parameters. The control module (900) receives sensed values ​​from, for example, pressure manometers (910), flow meters (912), temperature sensors (914), and / or other sensors (916). The control module (900) may also be employed to control process conditions during reaction mass transfer and plasma processing. The control module (900) will typically include one or more memory devices and one or more processors.

[0066] The control module (900) may control the activities of the reaction mass transfer system and the plasma processing device. The control module (900) executes computer programs that include sets of instructions for controlling process timing, transfer system temperature, pressure differences across filters, valve positions, mixture of gases, chamber pressure, chamber temperature, wafer temperature, RF power levels, wafer ESC or pedestal position, and other parameters of a specific process. The control module (900) may also monitor pressure differences and automatically switch vapor reaction mass transfer from one or more paths to one or more other paths. Other computer programs stored on memory devices associated with the control module (900) may be employed in some embodiments.

[0067] Typically, there will be a user interface associated with the control module (900). The user interface may include a display (918) (e.g., a display screen of device and / or process conditions and / or graphic software displays), and user input devices (920) such as pointing devices, keyboards, touch screens, microphones, etc.

[0068] Computer programs for controlling the transfer of reactants, plasma processing, and other processes in a process sequence may be written in any conventional computer-readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. Compiled object code or scripts are executed by a processor to perform tasks identified in the program.

[0069] Control module parameters are related to plasma conditions such as filter pressure differences, process gas composition and flow rates, temperature, pressure, RF power levels and RF frequency, cooling gas pressure, and process conditions such as chamber wall temperature.

[0070] System software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control the operation of chamber components necessary to perform the deposition processes of the present invention. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code.

[0071] Although the foregoing embodiments have been described in some detail for the sake of clarity of understanding, it will be apparent that specific changes and modifications may be made within the scope of the disclosed embodiments. It should be noted that there are many alternative ways to implement the processes, systems, and devices of these embodiments. Accordingly, these embodiments are to be considered exemplary and not limiting, and the embodiments are not to be limited to the details given herein.

Claims

Claim 1 A method for performing an etching process for etching features having a high aspect ratio on a substrate in a plasma processing system, comprising the step of applying source RF power to an electrode of the plasma processing system; and the method comprises the step of applying bias RF power to the electrode, wherein the source RF power and the bias RF power are pulsed signals together defining a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state, wherein the first state is defined by the source RF power having a first source RF power level and the bias RF power having a first bias RF power level, the second state is defined by the source RF power having a zero power level and the bias RF power having a zero power level, and the third state is defined by the source RF power having a second source RF power level smaller than the first source RF power level and the bias RF power having a zero power level, wherein the first state is configured to affect the etching of a feature on the surface of the substrate, and the second state is configured to affect the passivation of the feature on the surface of the substrate, and the A method for performing an etching process for etching features having a high aspect ratio, wherein the 3rd state is configured to affect the removal of the material forming the neck in the above feature. Claim 2 delete Claim 3 A method for performing an etching process for etching features having a high aspect ratio, wherein, in claim 1, the high aspect ratio for the features etched on the substrate is defined as 100 to 1. Claim 4 A method for performing an etching process for etching features having a high aspect ratio, wherein, in claim 1, the high aspect ratio for the features etched on the substrate is defined between 60 and 100 to 1. Claim 5 A method for performing an etching process for etching high aspect ratio features, wherein the bias RF power has a frequency smaller than 10 MHz in claim 1. Claim 6 A method for performing an etching process for etching high aspect ratio features, wherein the source RF power has a frequency greater than 20 MHz in claim 1. Claim 7 A method for performing an etching process for etching features having a high aspect ratio, wherein the third state has a duration that is 1 to 5 times the duration of the first state. Claim 8 A method for performing an etching process for etching high aspect ratio features, wherein, in claim 1, the second state has a duration equal to the duration of the first state. Claim 9 A method for performing an etching process for etching features having a high aspect ratio, wherein, in claim 1, the first source RF power level is in the range of 1 to 6 kW and the first bias RF power level is in the range of 5 to 20 kW. Claim 10 A method for performing an etching process for etching features having a high aspect ratio, wherein, in claim 1, the second source RF power level is in the range of 100 W to 6 kW. Claim 11 A method for performing an etching process for etching features having a high aspect ratio, wherein, in each of the cycles, the third state immediately follows the second state. Claim 12 A method for performing an etching process for etching features having a high aspect ratio, wherein, in each of the cycles, the second state immediately follows the third state. Claim 13 A controller device configured to enable a plasma processing system to perform an etching process for etching features having a high aspect ratio on a substrate in the plasma processing system, wherein the etching process comprises: an operation of applying source RF power to an electrode of the plasma processing system; and includes an operation of applying bias RF power to the electrode, wherein the source RF power and the bias RF power are pulsed signals together defining a plurality of multi-state pulsed RF cycles, each cycle having a first state, a second state, and a third state, wherein the first state is defined by the source RF power having a first source RF power level and the bias RF power having a first bias RF power level, the second state is defined by the source RF power having a zero power level and the bias RF power having a zero power level, and the third state is defined by the source RF power having a second source RF power level smaller than the first source RF power level and the bias RF power having a zero power level, wherein the first state is configured to affect the etching of a feature on the surface of the substrate, the second state is configured to affect the passivation of the feature on the surface of the substrate, and the third state is A controller device configured to affect the removal of the material forming the neck in the above feature. Claim 14 delete Claim 15 A controller device according to claim 13, wherein the high aspect ratio for features etched on the substrate is defined as 100 to 1. Claim 16 A controller device according to claim 13, wherein the high aspect ratio for features etched on the substrate is defined between 60 and 100 to 1. Claim 17 In claim 13, the controller device wherein the bias RF power has a frequency smaller than 10 MHz. Claim 18 In claim 13, the controller device wherein the source RF power has a frequency greater than 20 MHz. Claim 19 A controller device according to claim 13, wherein the third state has a duration that is 1 to 5 times the duration of the first state. Claim 20 A controller device according to claim 13, wherein the second state has a duration equal to the duration of the first state. Claim 21 A controller device according to claim 13, wherein the first source RF power level is in the range of 1 to 6 kW and the first bias RF power level is in the range of 5 to 20 kW. Claim 22 A controller device according to claim 13, wherein the second source RF power level is in the range of 100 W to 6 kW. Claim 23 In claim 13, a controller device wherein, in each of the cycles, the third state immediately follows the second state. Claim 24 In claim 13, a controller device wherein, in each of the cycles, the second state immediately follows the third state.

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