Imaging devices and electronic devices

Abstract

An imaging device capable of high-speed operation and having an image processing function is provided. The imaging device has additional functions such as image processing, maintains analog data acquired through the imaging operation in a pixel, and can extract data obtained by multiplying the analog data by an arbitrary weighting factor. In addition, the imaging device generates a portion of the potential used for operations in the pixel by redistributing the charge stored in the wiring. Therefore, operations can be performed at a high speed and with low power consumption compared to when the potential is supplied to the pixel from another circuit.

Description

Technology Field

[0001] One embodiment of the present invention relates to an imaging device.

[0002] Furthermore, one embodiment of the present invention is not limited to the technical fields described above. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, a method, or a method of manufacturing. Alternatively, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a capacitor, a memory device, an imaging device, a method of operating the same, or a method of manufacturing the same.

[0003] In addition, the term "semiconductor device" in this specification and others refers to any device capable of functioning by utilizing semiconductor characteristics. Transistors and semiconductor circuits are forms of semiconductor devices. Additionally, memory devices, display devices, imaging devices, and electronic devices may have semiconductor devices. Background Technology

[0004] A technology for constructing a transistor using an oxide semiconductor thin film formed on a substrate is attracting attention. For example, an imaging device configured to use a transistor with a very low off-current using an oxide semiconductor in a pixel circuit is disclosed in Patent Document 1.

[0005] In addition, a technology for adding a computational function to an imaging device is disclosed in Patent Document 2. Prior art literature

[0006] Japanese Patent Publication No. JP 2011-119711 and Japanese Patent Publication No. JP 2016-123087 The problem to be solved

[0007] With imaging devices equipped with solid-state imaging elements such as CMOS image sensors, it has become possible to easily capture high-quality images due to technological advancements. In the next generation, there is a demand to equip imaging devices with more intelligent functions.

[0008] Image data (analog data) acquired by an imaging device is converted into digital data and, after being extracted externally, image processing is performed as needed. If the above processing can be performed within the imaging device, connection with external devices becomes faster and user convenience is improved. In addition, the load on peripheral devices and power consumption can be reduced. Furthermore, if complex data processing can be performed in the state of analog data, the time required for data conversion can also be shortened.

[0009] Accordingly, in one embodiment of the present invention, one of the objectives is to provide an imaging device capable of performing image processing. Or, one of the objectives is to provide an imaging device capable of high-speed operation. Or, one of the objectives is to provide an imaging device with low power consumption. Or, one of the objectives is to provide an imaging device with high reliability. Or, one of the objectives is to provide a novel imaging device, etc. Or, one of the objectives is to provide a method for driving the imaging device. Or, one of the objectives is to provide a novel semiconductor device, etc.

[0010] Furthermore, the description of these problems does not prevent the existence of other problems. Also, one embodiment of the present invention is not required to solve all of these problems. Furthermore, problems other than these become naturally apparent from the description in the specification, drawings, claims, etc., and problems other than these can be derived from the description in the specification, drawings, claims, etc. means of solving the problem

[0011] One embodiment of the present invention relates to an imaging device capable of high-speed operation and having an image processing function.

[0012] One embodiment of the present invention is an imaging device having a first pixel, a second pixel, and a first transistor, wherein each of the first pixel and the second pixel has a second transistor and a capacitor, one of the source and drain of the second transistor is electrically connected to one electrode of the capacitor, one electrode of the capacitor having the first pixel is electrically connected to one of the source and drain of the first transistor, and one electrode of the capacitor having the second pixel is electrically connected to the other of the source and drain of the first transistor.

[0013] Each of the first pixel and the second pixel further has a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a photoelectric conversion device, and the other electrode of the capacitor is electrically connected to the gate of the third transistor, one of the source and drain of the fourth transistor, and one of the source and drain of the fifth transistor, and one of the source and drain of the third transistor is electrically connected to one of the source and drain of the sixth transistor, and the other of the source and drain of the fifth transistor can be electrically connected to one electrode of the photoelectric conversion device.

[0014] The photoelectric conversion device may have a photoelectric conversion layer having photosensitivity to infrared light. A compound semiconductor may be used for the photoelectric conversion layer.

[0015] The imaging device further has a first circuit, the first circuit has the function of outputting a first potential or a second potential, and the first circuit may be electrically connected to the other side of the source and drain of the second transistor having the first pixel and the second pixel, respectively.

[0016] The imaging device further has a second circuit, the second circuit has the function of a correlated double sampling circuit, and the second circuit may be electrically connected to the other side of the source and drain of the sixth transistor having the first pixel and the second pixel, respectively.

[0017] One or more of the first to sixth transistors have a metal oxide in the channel forming region, and the metal oxide preferably has In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

[0018] In addition, another embodiment of the present invention is an imaging device having a pixel block, a first circuit, and a second circuit, wherein the pixel block has n (where n is a natural number greater than or equal to 2) pixels, the first circuit has a function of supplying any two or more potentials selected from a first potential, a second potential, and a third potential to each of the n pixels, each of the n pixels has a function of acquiring first image data, each of the n pixels has a function of adding any one of a first potential, a second potential, and a third potential to the first image data to generate second image data, the pixel block has a function of generating a fourth potential by adding all of the first potential, the second potential, or the third potential supplied from the first circuit to each of the m pixels and dividing by n, for m (where m is a natural number from 1 to n) pixels selected from the n pixels, and each of the n pixels adds the fourth potential to the first image data. The imaging device has a function to generate 3 image data, and the second circuit has a function to generate 5 image data corresponding to the difference between the sum of 2 image data output by n pixels and the sum of 3 image data output by n pixels. Effects of the invention

[0019] According to one embodiment of the present invention, an imaging device capable of performing image processing may be provided. Alternatively, an imaging device capable of high-speed operation may be provided. Alternatively, an imaging device with low power consumption may be provided. Alternatively, an imaging device with high reliability may be provided. Alternatively, a novel imaging device, etc. may be provided. Alternatively, a method for driving the imaging device may be provided. Alternatively, a novel semiconductor device, etc. may be provided. Brief explanation of the drawing

[0020] Figure 1 is a block diagram illustrating an imaging device. FIG. 2 is a drawing illustrating a pixel block (200) and a circuit (201). Figures 3 (A) and (B) are drawings illustrating a pixel (100). Figures 4 (A) and (B) are drawings illustrating a pixel (100). Figures 5 (A) to (C) are drawings illustrating a filter. FIG. 6 is a drawing illustrating a pixel block (200). Figures 7 (A) and (B) are diagrams illustrating a filter. Figure 8 is a timing chart explaining the operation of the imaging device. FIG. 9 is a diagram illustrating an example of a circuit (304). FIG. 10 is a timing chart explaining the operation of the circuit (304). FIG. 11 is a timing chart explaining the operation of the circuit (304). Figures 12 (A) and (B) are drawings illustrating circuit (301) and circuit (302). Figure 13 is a diagram illustrating a memory cell. Figures 14 (A) and (B) are diagrams showing examples of neural network configurations. Figures 15 (A) to (D) are diagrams illustrating the configuration of pixels of an imaging device. Figures 16 (A) to (C) are diagrams illustrating the configuration of a photoelectric conversion device. Figure 17 is a cross-sectional view illustrating a pixel. Figures 18 (A) to (C) are diagrams illustrating a Si transistor. Figure 19 is a cross-sectional view illustrating a pixel. Figure 20 is a cross-sectional view illustrating a pixel. Figures 21 (A) to (D) are diagrams illustrating an OS transistor. Figure 22 is a cross-sectional view illustrating a pixel. Figures 23 (A) to (C) are perspective views (cross-sectional views) illustrating pixels. Figures (A1) to (A3) and (B1) to (B3) of Figure 24 are perspective views of a package and module containing an imaging device. Figures 25 (A) to (F) are drawings illustrating electronic devices. Figure 26 is a drawing illustrating a car. Figure 27 (A) is a schematic diagram showing the driver's forward view as seen from inside the vehicle, and Figure 27 (B) is a drawing showing the exterior of the vehicle. FIG. 28 is a diagram showing an example of a block diagram of a display system. FIG. 29 is a diagram showing an example of a block diagram of a system. Figures 30 (A) and (C) are photographs, and Figures 30 (B) and (D) are data. Figure 31 (A) is a photograph, and Figure 31 (B) is data. Specific details for implementing the invention

[0021] Embodiments are described in detail using drawings. However, the present invention is not limited to the description below, and it is readily understood by those skilled in the art that various changes to its form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the contents of the embodiments described below. Furthermore, in the configuration of the invention described below, the same reference numerals are commonly used across different drawings for identical parts or parts having the same function, and their repeated description may be omitted. Additionally, the hatching of the same elements constituting the drawings may be appropriately omitted or changed across different drawings.

[0022] Furthermore, even if an element is depicted as a single element in a circuit diagram, it may be configured in multiple units as long as there are no functional issues. For example, multiple transistors acting as switches may be connected in series or parallel. Additionally, capacitors may be divided and placed at multiple locations.

[0023] In addition, a single conductor may combine multiple functions, such as wiring, electrodes, and terminals, and multiple designations may be used for the same element in this specification. Furthermore, even when elements are depicted as being directly connected in a circuit diagram, they may actually be connected through one or more conductors, and in this specification, such configurations are also included within the category of direct connection.

[0024] (Embodiment 1)

[0025] In this embodiment, an imaging device, which is one form of the present invention, will be described with reference to the drawings.

[0026] One embodiment of the present invention is an imaging device having additional functions such as image processing. The imaging device retains analog data (image data) acquired through an imaging operation in pixels and can extract data obtained by multiplying the analog data by an arbitrary weighting factor.

[0027] By inputting the above data into a neural network or the like, processing such as image recognition can be performed. Since massive amounts of image data can be maintained in pixels in the state of analog data, processing can be performed efficiently.

[0028] In addition, in one embodiment of the imaging device of the present invention, some potential used for computation in the pixel is generated by redistributing the charge charged in the wiring. Therefore, computation can be performed at a high speed and with low power consumption compared to when the potential is supplied to the pixel from another circuit.

[0029] Imaging device

[0030] FIG. 1 is a block diagram illustrating an imaging device of one embodiment of the present invention. The imaging device has a pixel array (300), a circuit (201), a circuit (301), a circuit (302), a circuit (303), a circuit (304), a circuit (305), and a circuit (306). Additionally, each of the circuit (201) and circuits (301) to (306) may be configured as a combination of multiple circuits, rather than being limited to a single circuit configuration. Alternatively, any of the above multiple circuits may be integrated. Additionally, circuits other than those mentioned above may be connected.

[0031] The pixel array (300) has an imaging function and a computation function. Circuits (201, 301) have a computation function. Circuit (302) has a computation function or a data conversion function. Circuits (303, 304, 306) have a selection function. Circuit (305) has a function of supplying a potential for a product-sum operation to the pixel. A shift register or a decoder, etc., may be used for the circuit having the selection function. Additionally, circuits (301, 302) may be provided externally.

[0032] The pixel array (300) has a plurality of pixel blocks (200). As shown in FIG. 2, the pixel blocks (200) have a plurality of pixels (100) arranged in a matrix, and each pixel (100) is electrically connected to a circuit (201) through a wiring (112). Additionally, the circuit (201) may be provided within the pixel blocks (200).

[0033] In addition, the pixel (100) is electrically connected to an adjacent pixel (100) through a transistor (150) (transistors (150a to 150j)). The function of the transistor (150) will be described later.

[0034] In the pixel (100), image data can be acquired, and data can be generated by adding a weighting factor to the image data. Also, in FIG. 2, the number of pixels in the pixel block (200) is set to 3×3 as an example, but it is not limited thereto. For example, it can be 2×2, 4×4, etc. Or the number of pixels in the horizontal direction and the vertical direction may be different. Also, some pixels may be shared with adjacent pixel blocks.

[0035] The pixel block (200) and circuit (201) can be operated as a red-coding operation circuit.

[0036] Pixel Circuit

[0037] As shown in (A) of FIG. 3, the pixel (100) may have a photoelectric conversion device (101), a transistor (102), a transistor (103), a transistor (104), a transistor (105), a transistor (106), and a capacitor (107).

[0038] One electrode of the photoelectric conversion device (101) is electrically connected to one of the source and drain of the transistor (102). The other of the source and drain of the transistor (102) is electrically connected to one of the source and drain of the transistor (103), the gate of the transistor (104), and one electrode of the capacitor (107). One of the source and drain of the transistor (104) is electrically connected to one of the source and drain of the transistor (105). The other electrode of the capacitor (107) is electrically connected to one of the source and drain of the transistor (106).

[0039] The other electrode of the photoelectric conversion device (101) is electrically connected to the wiring (114). The other side of the source and drain of the transistor (103) is electrically connected to the wiring (115). The other side of the source and drain of the transistor (105) is electrically connected to the wiring (112). The other side of the source and drain of the transistor (104) is electrically connected to the GND wiring, etc. The other side of the source and drain of the transistor (106) is electrically connected to the wiring (111). The other electrode of the capacitor (107) is electrically connected to the wiring (117).

[0040] The gate of the transistor (102) is electrically connected to the wiring (121). The gate of the transistor (103) is electrically connected to the wiring (122). The gate of the transistor (105) is electrically connected to the wiring (123). The gate of the transistor (106) is electrically connected to the wiring (124).

[0041] Here, the electrical connection point (wiring) between the other side of the source and drain of the transistor (102), one side of the source and drain of the transistor (103), one electrode of the capacitor (107), and the gate of the transistor (104) is designated as a node (FD). Additionally, the electrical connection point (wiring) between the other electrode of the capacitor (107) and one side of the source and drain of the transistor (106) is designated as a node (FDW).

[0042] Wiring (114, 115) can function as power lines. For example, wiring (114) can function as a high-potential power line, and wiring (115) can function as a low-potential power line. Wiring (121, 122, 123, 124) can function as signal lines that control the conduction of each transistor. Wiring (111) can function as a wiring that supplies a potential corresponding to a weighting factor to the pixel (100). Wiring (112) can function as a wiring that electrically connects the pixel (100) and the circuit (201). Wiring (117) can function as a wiring that electrically connects the other electrode of the capacitor (107) of the pixel (100) and the other electrode of the capacitor (107) of another pixel (100) through the transistor (150) (see FIG. 2).

[0043] In addition, an amplification circuit or a gain adjustment circuit may be electrically connected to the wiring (112).

[0044] A photodiode can be used as the photoelectric conversion device (101). Regardless of the type of photodiode, a Si photodiode having silicon in the photoelectric conversion layer, an organic photodiode having an organic photoconductive film in the photoelectric conversion layer, etc., can be used. In addition, if you want to increase the light detection sensitivity at low light levels, it is preferable to use an avalanche photodiode.

[0045] The transistor (102) may have the function of controlling the potential of the node (FD). The transistor (103) may have the function of initializing the potential of the node (FD). The transistor (104) may have the function of controlling the current flowing through the circuit (201) according to the potential of the node (FD). The transistor (105) may have the function of selecting a pixel. The transistor (106) may have the function of supplying a potential corresponding to a weighting factor to the node (FDW).

[0046] In addition, as shown in (B) of FIG. 3, one of the source and drain of the transistor (104) may be electrically connected to one of the source and drain of the transistor (105), the other of the source and drain of the transistor (104) may be connected to the wiring (112), and the other of the source and drain of the transistor (105) may be electrically connected to the GND wiring, etc.

[0047] In addition, as shown in (A) and (B) of FIG. 4, the direction of connection of the photoelectric conversion device (101) may be reversed. In this case, the wiring (114) may function as a low-potential power line and the wiring (115) may function as a high-potential power line.

[0048] When using an avalanche photodiode as the photoelectric conversion device (101), a high voltage may be applied, so it is desirable to use a high-voltage transistor as the transistor connected to the photoelectric conversion device (101). As a high-voltage transistor, for example, a transistor using a metal oxide in the channel forming region (hereinafter OS transistor) can be used. Specifically, it is desirable to apply an OS transistor to the transistor (102).

[0049] In addition, the OS transistor has the characteristic of having a very low off-current. By using the OS transistor as the transistor (102, 103, 106), the period for maintaining charge at the node (FD) and node (FDW) can be extended significantly. Therefore, a global shutter method can be applied to perform charge accumulation operations simultaneously at all pixels without complicating the circuit configuration or operation method. Additionally, while maintaining image data at the node (FD), multiple operations using the image data can be performed.

[0050] On the other hand, there are cases where the transistor (104) is required to have excellent amplification characteristics. Also, as for the transistor (106), it is desirable to use a transistor capable of high-speed operation and high mobility. Therefore, for the transistors (104, 106), a transistor (hereinafter Si transistor) using silicon in the channel forming region may be applied.

[0051] Furthermore, not limited to the above, a combination of OS transistors and Si transistors may be applied. Additionally, all transistors may be OS transistors. Alternatively, all transistors may be Si transistors. Examples of Si transistors include transistors having amorphous silicon, transistors having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single-crystal silicon), etc.

[0052] The potential of the node (FD) in the pixel (100) is determined by adding the reset potential supplied from the wiring (115) and the potential (image data) generated by photoelectric conversion by the photoelectric conversion device (101). Alternatively, a potential corresponding to a weighting factor supplied from the wiring (111) is capacitively coupled to this potential to determine it. Thus, current can flow through the transistor (105) according to the data in which an arbitrary weighting factor is applied to the image data.

[0053] In addition, the above is an example of a circuit configuration of a pixel (100), and the photoelectric conversion operation may be performed with a different circuit configuration.

[0054] <Circuit (201)>

[0055] As shown in FIG. 2, each pixel (100) is electrically connected to each other by wiring (112). The circuit (201) can perform calculations using the sum of the currents flowing through the transistors (104) of each pixel (100).

[0056] The circuit (201) has a capacitor (202), a transistor (203), a transistor (204), a transistor (205), a transistor (206), and a resistor element (207).

[0057] One electrode of the capacitor (202) is electrically connected to one of the source and drain of the transistor (203). One of the source and drain of the transistor (203) is electrically connected to the gate of the transistor (204). One of the source and drain of the transistor (204) is electrically connected to one of the source and drain of the transistor (205). One of the source and drain of the transistor (205) is electrically connected to one of the source and drain of the transistor (206). One electrode of the resistor element (207) is electrically connected to the other electrode of the capacitor (202).

[0058] The other electrode of the capacitor (202) is electrically connected to the wiring (112). The other side of the source and drain of the transistor (203) is electrically connected to the wiring (218). The other side of the source and drain of the transistor (204) is electrically connected to the wiring (219). The other side of the source and drain of the transistor (205) is electrically connected to a reference power line, such as a GND wire. The other side of the source and drain of the transistor (206) is electrically connected to the wiring (212). The other electrode of the resistor element (207) is electrically connected to the wiring (217). The gate of the transistor (203) is electrically connected to the wiring (216). The gate of the transistor (205) is electrically connected to the wiring (215). The gate of the transistor (206) is electrically connected to the wiring (213).

[0059] Wiring (217, 218, 219) can function as power lines. For example, wiring (218) can function as wiring that supplies a dedicated potential for reading. Wiring (217, 219) can function as high-potential power lines. Wiring (213, 215, 216) can function as signal lines that control the conduction of each transistor. Wiring (212) is an output line and can be electrically connected to, for example, the circuit (301) shown in FIG. 1.

[0060] The transistor (203) may have the function of resetting the potential of the wiring (211) to the potential of the wiring (218). The transistors (204, 205) may have the function of a source follower circuit. The transistor (206) may have the function of controlling the reading. Additionally, the circuit (201) may have the function of a correlated double sampling circuit (CDS circuit) and may be replaced with a circuit of a different configuration having this function. Also, the wiring (211) is a wiring that electrically connects one electrode of the capacitor (202), one of the source and drain of the transistor (203), and the gate of the transistor (204).

[0061] In one embodiment of the present invention, an offset component other than the product of image data (X) and a weighting factor (W) is removed to extract the target WX. WX can be calculated using data when imaging is performed and data when imaging is not performed for the same pixel, and data when weights are applied to each of these.

[0062] When an image is taken, the current (I) flowing through the pixel (100) p The sum of ) is kΣ(XV th ) 2 , current (I) flowing in the pixel (100) when weight is applied p The sum of ) is kΣ(W+XV th ) 2 This becomes. Also, when imaging is not performed, the current (I) flowing through the pixel (100) ref The sum of ) is kΣ(0-V th ) 2 , current (I) flowing in the pixel (100) when weight is applied ref The sum of ) is kΣ(WV th ) 2 This becomes. Here, k is a constant, and V th is the threshold voltage of the transistor (105).

[0063] First, the difference (Data A) between the data obtained by performing the image and the data to which weights have been applied is calculated. This is kΣ((XV th ) 2 -(W+XV th ) 2 )=kΣ(-W 2 -2W·X+2W·V th It becomes.

[0064] Next, the difference (Data B) between the data when no imaging was performed and the data to which weights were applied to the above data is calculated. This is kΣ((0-V th ) 2 -(WV th ) 2 )=kΣ(-W2 +2W·V th It becomes.

[0065] Then, take the difference between data A and data B. This is kΣ(-W 2 -2W·X+2W·V th -(-W 2 +2W·V th ))=kΣ(-2W·X). That is, offset components other than the product of image data (X) and weighting factor (W) can be removed.

[0066] In the circuit (201), data A and data B can be read. Additionally, the difference operation between data A and data B can be performed, for example, by the circuit (301).

[0067] Filter

[0068] Here, the weight supplied to the entire pixel block (200) functions as a filter. For example, a convolutional filter of a convolutional neural network (CNN) can be used as the filter. Alternatively, an image processing filter such as an edge extraction filter can be used. Examples of edge extraction filters include the Laplacian filter shown in FIG. 5 (A), the Prewitt filter shown in FIG. 5 (B), and the Sobel filter shown in FIG. 5 (C).

[0069] When the number of pixels (100) in the pixel block (200) is 3×3, the elements of the edge extraction filter can be assigned to each pixel (100) as weights and supplied. As described above, in order to calculate data A and data B, data when imaging is performed, data when imaging is not performed, and data when weights are applied to each of these can be used. Here, data without weights applied can be rephrased as data with a weight of 0 applied to all pixels (100).

[0070] The edge extraction filter exemplified in FIG. 5 (A) to (C) is a filter in which the sum of the elements (weights: ΔW) of the filter (ΣΔW / N, where N is the number of elements) becomes zero. Therefore, even without performing an operation to supply ΔW=0 from a new circuit, if an operation to acquire ΣΔW / N is performed, data with ΔW=0 applied to all pixels (100) can be acquired.

[0071] The above operation corresponds to conducting the transistor (150) (transistors (150a to 150j)) provided between pixels (100) (see FIG. 2). By conducting the transistor (150), the nodes (FDW) of each pixel (100) are all short-circuited through the wiring (117). At this time, the charge accumulated in the nodes (FDW) of each pixel (100) is redistributed, and when using the edge extraction filter exemplified in FIG. 5 (A) to (C), the potential (ΔW) of the nodes (FDW) becomes 0 or substantially 0. Thus, data equivalent to ΔW=0 can be obtained.

[0072] In addition, when rewriting the weight (ΔW) by supplying charge from a circuit outside the pixel array (300), time is required until the rewriting is completed due to the capacity of the long wiring (111), etc. Meanwhile, the pixel block (200) is a small area, and the distance of the wiring (117) is short and the capacity is small. Therefore, in the operation of redistributing the charge accumulated in the node (FDW) within the pixel block (200), the weight (ΔW) can be rewritten at high speed.

[0073] In the pixel block (200) shown in FIG. 2, a configuration is shown in which transistors (150a to 150j) are each electrically connected to different gate lines (wires (113a to 113j)). In the above configuration, since the conduction of the transistors (150a to 150j) can be controlled independently, the operation of acquiring ΣΔW / N can be selectively performed.

[0074] For example, when using the filters shown in (B), (C), etc. of FIG. 5, there are pixels where ΔW=0 is initially supplied. Assuming that ΣΔW / N=0, pixels where ΔW=0 is supplied may be excluded from the pixels subject to agreement. By excluding the above pixels, the supply of potential to operate some of the transistors (150a to 150j) becomes unnecessary, so power consumption can be suppressed.

[0075] In addition, when performing the operation to acquire ΣΔW / N for all pixels, as shown in FIG. 6, the transistors (150a to 150j) may be configured to be electrically connected to a single gate line (wire (113)). In the above configuration, the gate line can be reduced, so the control can be simplified.

[0076] Additionally, FIGS. 2 and 6 show an example in which nine transistors (150) (transistors (150a to 150j)) are provided between pixels (100), but the number of transistors (150) may be increased. Also, some of the transistors (150g to 150j) may be omitted to eliminate parallel paths.

[0077] In addition, although an example using a filter where ΣΔW / N=0 was shown above, a filter where ΣΔW / N≠0 can also be used. For example, as shown in (A) of FIG. 7, in a filter where the center is 1 and the 8 directions starting from the center are 0, the weight (ΔW) supplied initially is 0 or 1 and ΣΔW / N=1 / 9. When the difference is taken according to the operation described above, the center has 8 elements and the 8 directions have -1 elements, which is equivalent to the operation using a constant multiple of the Laplacian filter shown in (A) of FIG. 5.

[0078] In addition, as shown in (B) of FIG. 7, in a filter having rows 0, 1, and 2 sequentially, ΣΔW / N=1. When the difference is taken in the manner described above, each row becomes a row of -1, a row of 0, and a row of 1. This is equivalent to the operation using the Prewitt filter shown in (B) of FIG. 5.

[0079] Although two examples, (A) and (B) of Fig. 7, were described above, filters are basically arbitrary and can perform various operations in addition to known filters.

[0080] <Image Motion>

[0081] Next, the imaging operation and the redundancy operation will be described using the timing chart shown in FIG. 8. Additionally, the pixel block (200) described herein is assumed to have the configuration shown in FIG. 6, and the pixel (100) is assumed to have the configuration shown in (A) or (B) of FIG. 3. Furthermore, a predetermined positive potential is supplied to the power line, etc. Also, in the following description, the high potential is referred to as "H" and the low potential as "L".

[0082] At time (T1), if the potential of wiring (121) is set to "H", the potential of wiring (122) is set to "H", and the potential of wiring (124) is set to "H", then transistors (102, 103) conduct, and the potential of node (FD) becomes the reset potential (potential of wiring (115)) "V" RES "It becomes. Also, the transistor (106) conducts, and the potential of the node (FDW) becomes "L"=0.

[0083] At time (T2), if the potential of wiring (121) is set to "L", the potential of wiring (122) to "L", and the potential of wiring (124) to "H", the transistors (102, 103) become non-conductive, and the reset potential "V" at node (FD) RES "is maintained.

[0084] At time (T3), if the potential of wiring (121) is set to "H", the potential of wiring (122) to "L", and the potential of wiring (124) to "H", the transistor (102) conducts, and the potential of the node (FD) becomes "V" due to the operation of the photoelectric conversion device (101). RES It changes to +ΔX".

[0085] At time (T4), if the potential of wiring (121) is set to "L", the potential of wiring (122) is set to "L", and the potential of wiring (124) is set to "L", then transistors (102, 106) become non-conductive, and the potential "V" at node (FD) RES +ΔX" is maintained. "ΔX" is a potential corresponding to image data, and up to this point corresponds to the basic operation of imaging.

[0086] <Redout Operation>

[0087] Next, the operation of producing the aforementioned data A and data B by means of the redrawing operation in the pixel (100) and circuit (201) will be described. Additionally, although the operation of a single pixel was described above, the pixel block (200) has multiple pixels (100). Therefore, after the imaging operation of all pixels (100) within the pixel block (200) is completed, the operation described below can be performed.

[0088] At time (T5), when a potential "ΔW" corresponding to a weight is supplied to the wiring (111) and the potential of the wiring (124) is set to "H", the transistor (106) conducts, and the potential "ΔW" is recorded at the node (FDW). In addition, accordingly, the change in potential of the node (FDW) is added to the node (FD) by the capacitive coupling of the capacitor (107), and the potential of the node (FD) becomes "V RES It changes to +ΔX+ΔW'". Also, if the capacitance of the capacitor (107) is sufficiently larger than the capacitance of the node (FD), "ΔW" and "ΔW'" will have nearly the same value.

[0089] At time (T6), if the potential of the wiring (124) is set to "L", the transistor (106) becomes non-conductive, and the potential at node (FDW) is "ΔW", and the potential at node (FD) is "V". RES +ΔX+ΔW'" is maintained.

[0090] At time (T7), when the potential of the wiring (123) is set to "H" and the potential of the wiring (216) (see FIG. 2) is set to "H", the transistor (105) conducts, and current flows from the wiring (112) to the transistor (104) according to the potential of the node (FD). Also, in circuit (201), the transistor (203) conducts, and the potential of the wiring (211) becomes the potential "Vr" of the wiring (218). That is, when the potential of the other electrode of the capacitor (202) is the output potential when a weight is added to the image data acquired by the pixel (100), one electrode of the capacitor (202) is initialized to the potential "Vr".

[0091] At time (T8), when the potential of the wiring (113) (see FIG. 6) is set to "H", the transistors (150a to 150j) conduct, the node (FDW) of each pixel (100) is short-circuited, and the charge is redistributed, so that the potential of the node (FDW) becomes "ΣΔW / N". In addition, accordingly, the change in the potential of the node (FDW) is added to the node (FD) by the capacitive coupling of the capacitor (107), and the potential of the node (FD) becomes "V" RES It changes to +ΔX+(ΣΔW / N)'". Here, if the capacitance of the capacitor (107) is sufficiently larger than the capacitance of the node (FD), "ΣΔW / N" and "(ΣΔW / N)'" become nearly the same value. That is, if "ΣΔW / N"=0, then "(ΣΔW / N)'"=0.

[0092] At time (T9), the potential of the wiring (113) is "L", the potential of the wiring (123) is "H", the potential of the wiring (213) is "H", and the potential of the wiring (215) is "V". biasWhen an appropriate analog potential is set, the potentials of the nodes (FDW) and (FD) are maintained. Additionally, the transistor (105) conducts, and current flows from the wiring (112) to the transistor (104) according to the potential of the node (FD). Here, the potential of the other electrode of the capacitor (202) changes according to the current flowing through the wiring (112), and the change Y is added to the potential "Vr" of the wiring (211) through capacitive coupling.

[0093] Therefore, the potential of the wiring (211) becomes "Vr+Y". Here, if we assume that Vr=0, Y is the difference itself, and data A is produced. Additionally, the circuit (201) can output a signal potential according to data A through source follower operation.

[0094] By going through the same steps, the difference (data B) between the data in which imaging is not performed and the data to which weights are applied can be calculated. Also, since imaging is not performed, the accumulation operation is not performed. For example, when wiring (121) is "H," wiring (122) is also set to "H," so that the reset potential can be maintained at the node (FD). Alternatively, the operation may be performed without providing a period during which the potential of wiring (121) is set to "H."

[0095] Data A and data B output from the circuit (201) by the above operation are input to the circuit (301). In the circuit (301), an operation to take the difference between data A and data B is performed, and unnecessary offset components other than the product of the image data and the weighting factor can be removed. In addition to a configuration having an operation circuit like the circuit (201), the circuit (301) may also be configured to take the difference using a memory circuit (also called a memory circuit) and software processing.

[0096] The weighting factor can be output to the wiring (111) from the circuit (305) shown in FIG. 1, and it is desirable to rewrite the weighting factor at least once within the frame period. A decoder may be used as the circuit (305). Additionally, the circuit (305) may have a D / A converter or an SRAM.

[0097] Additionally, the wiring (124) for selecting the pixel (100) that inputs the weighting coefficient can output a signal potential from the circuit (303). A decoder or a shift register can be used as the circuit (303).

[0098] In addition, a signal potential can be output from the circuit (304) to the wiring (123), etc., connected to the gate of the transistor (105) of the pixel (100). A decoder or a shift register can be used as the circuit (304).

[0099] Additionally, a signal potential can be output from a circuit (306) to a wiring (113) connected to the gate of a transistor (150) of a pixel block (200). A decoder or a shift register can be used as the circuit (306).

[0100] In addition, although the processing of captured image data was described above, in one form of the imaging device of the present invention, image data may be extracted without processing.

[0101] In the redrawing operation, it is desirable to be able to simultaneously select pixels in multiple rows. On the other hand, when extracting only image data, it is desirable to extract data from pixels in a single row. In one embodiment of the present invention, a circuit (304) for selecting pixels (100) is provided with a function to switch the number of rows of pixels to be selected.

[0102] Shift Register

[0103] FIG. 9 is an example of a circuit that can be used as a circuit (304). The circuit is a shift register circuit, and a plurality of logic circuits (SR) are electrically connected. Signal lines such as wiring (RES), wiring (VSS_RDRS), wiring (RPWC_SE[0:3]), wiring (RCLK[0:3]), and wiring (RSP) are connected to each logic circuit (SR), and by inputting an appropriate signal potential to each signal line, the output of a selected signal potential can be sequentially performed from the logic circuit (SR).

[0104] Additionally, the circuit (170) is electrically connected to the logic circuit (SR). The circuit (170) is provided with a plurality of transistors, and signal lines such as wiring (SE_SW[0:2]) and wiring (SX[0:2]) are connected, and the conduction of the transistors is controlled by inputting an appropriate signal potential to each signal line. By controlling the circuit (170), the number of rows of selected pixels can be switched.

[0105] One of the source and drain of a transistor is electrically connected to the output terminal of a logic circuit (SR), and a wire (SE) is connected to the other of the source and drain of the transistor. The wire (SE) is electrically connected to a wire (122) that selects a pixel (100).

[0106] The gate of the transistor connected to the wiring (SE[0]) can be input with a signal potential supplied from the wiring (SE_SW[0]). The gate of the transistor connected to the wiring (SE[1]) can be input with a signal potential supplied from the wiring (SE_SW[1]). The gate of the transistor connected to the wiring (SE[2]) can be input with a signal potential supplied from the wiring (SE_SW[2]). The gate of the transistor connected after the wiring (SE[3]) can be input with a signal potential supplied from any of the wirings (SE_SW[0:2]) in the same order as above.

[0107] Additionally, adjacent wiring (SE) is electrically connected through a single transistor, and wiring (SE[0]) is electrically connected to the power line (VSS) through a single transistor.

[0108] The gate of the transistor electrically connecting the power line (VSS) and the wiring (SE[0]) can be input with a signal potential supplied from the wiring (SX[0]). The gate of the transistor electrically connecting the wiring (SE[0]) and the wiring (SE[1]) can be input with a signal potential supplied from the wiring (SX[1]). The gate of the transistor electrically connecting the wiring (SE[1]) and the wiring (SE[2]) can be input with a signal potential supplied from the wiring (SX[2]). Subsequently, the gate of the transistor electrically connecting the wirings (SE) can be input with a signal potential supplied from either of the wirings (SX[0:2]) in the same order as above.

[0109] FIG. 10 is a timing chart illustrating the operation of simultaneously selecting multiple rows (3 rows) by the circuit shown in FIG. 9. (0) to (161) correspond to the timing at which the logic circuit (SR) outputs a signal potential to the wiring (SE).

[0110] At timing (0), when the potential of wire (SX[0]) becomes "L", the potential of wire (SX[1]) becomes "H", the potential of wire (SX[2]) becomes "H", the potential of wire (SE_SW[0]) becomes "H", the potential of wire (SE_SW[1]) becomes "L", and the potential of wire (SE_SW[2]) becomes "L", the conduction of each transistor is controlled, and "H" is output to wire (SE[0]), "H" to wire (SE[1]), and "H" to wire (SE[2]). "L" is output to the other wire (SE).

[0111] Therefore, three rows can be selected simultaneously, and for example, a redundancy operation can be performed on pixels in row 3, column 3.

[0112] At timing (1), when the potential of wire (SX[0]) becomes "H", the potential of wire (SX[1]) becomes "L", the potential of wire (SX[2]) becomes "H", the potential of wire (SE_SW[0]) becomes "L", the potential of wire (SE_SW[1]) becomes "H", and the potential of wire (SE_SW[2]) becomes "L", the conduction of each transistor is controlled, and "L" is output to wire (SE[0]), "H" to wire (SE[1]), "H" to wire (SE[2]), and "H" to wire (SE[3]). "L" is output to other wires (SE).

[0113] That is, at timing (1), a stride of 1, which is one row moved from timing (0), can be performed.

[0114] Figure 11 is a timing chart illustrating the operation of selecting one row by the circuit shown in Figure 9.

[0115] In the operation according to the above timing chart, the potential of the wire (SE_SW[0:2]) is always "H" and the potential of the wire (SX[0:2]) is always "L". Therefore, since the output of the logic circuit (SR) appears as is in each wire (SE), selection is possible one row at a time.

[0116] <Circuit(301, 302)>

[0117] FIG. 12 (A) is a diagram illustrating circuit (301) and circuit (302) connected to circuit (201). Data of the redundancy calculation result output from circuit (201) is sequentially input into circuit (301). Circuit (301) may have various calculation functions in addition to the function of calculating the difference between data A and data B described above. For example, circuit (301) may have a configuration equivalent to circuit (201). Alternatively, the function of circuit (301) may be replaced by software processing.

[0118] Additionally, the circuit (301) may have a circuit that performs the operation of an activation function. For example, a comparator circuit may be used as the circuit. The comparator circuit outputs the result of comparing input data with a set threshold value as binary data. That is, the pixel block (200) and the circuit (301) can function as elements of a neural network.

[0119] Additionally, the circuit (301) may have an A / D converter. When outputting image data externally without redundancy processing, the circuit (301) can convert analog data into digital data.

[0120] In addition, the data output by the pixel block (200) corresponds to image data of multiple bits, but if it can be binaryized by the circuit (301), it can also be said that the image data is compressed.

[0121] Data output from the circuit (301) is sequentially input into the circuit (302). The circuit (302) may be configured to include, for example, a latch circuit and a shift register. By configuring it in this way, parallel-to-serial conversion becomes possible, so data input in parallel can be output as serial data to the wiring (311). The connection target of the wiring (311) is not limited. For example, it may be connected to a neural network, a memory device, a communication device, etc.

[0122] Additionally, as shown in (B) of FIG. 12, the circuit (302) may have the configuration of a neural network. The neural network has memory cells arranged in a matrix, and each memory cell maintains a weighting coefficient. Data output from the circuit (301) is input into each memory cell (320) and can perform a redundancy operation. Also, the number of memory cells shown in (B) of FIG. 12 is an example and is not limited thereto.

[0123] The neural network shown in (B) of FIG. 12 has memory cells (320) and reference memory cells (325) installed on a matrix, circuits (330), circuits (350), circuits (360), and circuits (370).

[0124] An example of a memory cell (320) and a reference memory cell (325) is shown in FIG. 13. The reference memory cell (325) is provided in any one column. The configuration of the memory cell (320) and the reference memory cell (325) is as described above, and includes a transistor (161), a transistor (162), and a capacitor (163).

[0125] One of the source and drain of the transistor (161) is electrically connected to the gate of the transistor (162). The gate of the transistor (162) is electrically connected to one electrode of the capacitor (163). Here, the point where one of the source and drain of the transistor (161), the gate of the transistor (162), and one electrode of the capacitor (163) are connected is designated as the node (NM).

[0126] The gate of the transistor (161) is electrically connected to the wiring (WL). The other electrode of the capacitor (163) is electrically connected to the wiring (RW). One of the source and drain of the transistor (162) is electrically connected to a reference potential wiring, such as a GND wiring.

[0127] In the memory cell (320), the other end of the source and drain of the transistor (161) is electrically connected to the wiring (WD). The other end of the source and drain of the transistor (162) is electrically connected to the wiring (BL).

[0128] In the reference memory cell (325), the other end of the source and drain of the transistor (161) is electrically connected to the wiring (WDref). The other end of the source and drain of the transistor (162) is electrically connected to the wiring (BLref).

[0129] The wiring (WL) is electrically connected to the circuit (330). As the circuit (330), a decoder or a shift register, etc., can be used.

[0130] The wiring (RW) is electrically connected to the circuit (301). Two values ​​of data output from the circuit (301) are recorded in each memory cell. Additionally, a sequence circuit, such as a shift register, may be provided between the circuit (301) and each memory cell.

[0131] Wiring (WD) and wiring (WDref) are electrically connected to the circuit (350). As the circuit (350), a decoder or a shift register, etc., may be used. Additionally, the circuit (350) may have a D / A converter or an SRAM. The circuit (350) can output a weighting factor that is recorded in the node (NM).

[0132] Wiring (BL) and wiring (BLref) are electrically connected to circuit (360). Circuit (360) can be configured to be equivalent to circuit (201). Through circuit (360), a signal potential can be obtained by removing the offset component from the redundancy operation result.

[0133] Circuit (360) is electrically connected to circuit (370). Circuit (370) can also be referred to as an activation function circuit. The activation function circuit has the function of performing operations to transform the signal potential input from circuit (360) according to a predefined activation function. Examples of activation functions may include a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, etc. The signal potential transformed by the activation function circuit is output externally as output data.

[0134] As shown in (A) of FIG. 14, a neural network (NN) can be composed of an input layer (IL), an output layer (OL), and an intermediate layer (hidden layer) (HL). The input layer (IL), the output layer (OL), and the intermediate layer (HL) each have one or more neurons (units). Additionally, the intermediate layer (HL) may have one layer or two or more layers. A neural network having two or more intermediate layers (HL) may be called a DNN (deep neural network). Furthermore, learning using a deep neural network may be called deep learning.

[0135] Input data is input to each neuron in the input layer (IL). Output signals from neurons in the preceding or succeeding layer are input to each neuron in the intermediate layer (HL). Output signals from neurons in the preceding layer are input to each neuron in the output layer (OL). Additionally, each neuron may be connected to all neurons in the preceding and succeeding layers (fully connected) or to some of the neurons.

[0136] Figure 14 (B) shows an example of an operation by a neuron. Here, a neuron (N) and two neurons of the preceding layer that output signals to the neuron (N) are shown. The output x1 of the neuron of the preceding layer and the output x2 of the neuron of the preceding layer are input to the neuron (N). Then, the total sum x1w1+x2w2 of the result of multiplying the output x1 and weight w1 (x1w1) and the result of multiplying the output x2 and weight w2 (x2w2) is calculated in the neuron (N), and a bias b is added as needed to obtain the value a=x1w1+x2w2+b. Then, the value a is transformed by the activation function h, and the output signal y=ah is output from the neuron (N).

[0137] In this way, the operation by the neuron includes an operation of adding the product of the output of the neuron in the previous layer and the weight, i.e., an integration operation (x1w1+x2w2 above). This integration operation may be performed in software using a program or may be performed by hardware.

[0138] In one embodiment of the present invention, an analog circuit is used as hardware to perform a redundancy operation. By using an analog circuit as the redundancy operation circuit, it is possible to reduce the circuit size of the redundancy operation circuit or the number of memory accesses, thereby enabling an improvement in processing speed and a reduction in power consumption.

[0139] It is preferable to configure the redundancy operation circuit with OS transistors. Since the off-current of OS transistors is very small, they are suitable as transistors for constituting the analog memory of the redundancy operation circuit. Additionally, the redundancy operation circuit may be constructed using both Si transistors and OS transistors.

[0140] This embodiment can be appropriately combined with the description of other embodiments.

[0141] (Embodiment 2)

[0142] In this embodiment, an example of the structure of an imaging device of one form of the present invention is described.

[0143] <Structural Example>

[0144] Figure 15 (A) is a drawing showing an example of the structure of a pixel of an imaging device, and can be a stacked structure of layers (561) and layers (563).

[0145] Layer (561) has a photoelectric conversion device (101). The photoelectric conversion device (101) may have layers (565a) and (565b), as shown in (A) of FIG. 16. Also, in some cases, layers may be referred to as regions.

[0146] The photoelectric conversion device (101) shown in (A) of FIG. 16 is a pn-junction type photodiode, and for example, a p-type semiconductor can be used in layer (565a) and an n-type semiconductor in layer (565b). Alternatively, an n-type semiconductor can be used in layer (565a) and a p-type semiconductor in layer (565b).

[0147] The above pn junction type photodiode can be formed using single-crystal silicon as a representative example. Since a photodiode using single-crystal silicon as a photoelectric conversion layer has a relatively wide spectral sensitivity characteristic ranging from ultraviolet light to near-infrared light, it can detect light of various wavelengths by combining it with the optical conversion layer described later.

[0148] In addition to this, a compound semiconductor may be used as the photoelectric conversion layer of a pn-junction type photodiode. Examples of the compound semiconductors that may be used include gallium-arsenic-phosphorus compound (GaAsP), gallium-phosphorus compound (GaP), indium-gallium-arsenic compound (InGaAs), lead-sulfur compound (PbS), lead-selenium compound (PbSe), indium-arsenic compound (InAs), indium-antimony compound (InSb), mercury-cadmium-tellurium compound (HgCdTe), etc.

[0149] As a compound semiconductor, a compound semiconductor having a group 13 element (aluminum, gallium, indium, etc.) and a group 15 element (nitrogen, phosphorus, arsenic, antimony, etc.) (also called a group 3-5 compound semiconductor), or a compound semiconductor having a group 12 element (magnesium, zinc, cadmium, mercury, etc.) and a group 16 element (oxygen, sulfur, selenium, tellurium, etc.) (also called a group 2-6 compound semiconductor) is preferred.

[0150] Since compound semiconductors can change their band gap depending on the combination of constituent elements or the ratio of their atoms, they can form photodiodes that are sensitive to a wide range of wavelengths from ultraviolet to infrared light.

[0151] In addition, generally, the wavelength of ultraviolet light can be defined as being around 0.01 μm to 0.38 μm, the wavelength of visible light as being around 0.38 μm to 0.75 μm, the wavelength of near-infrared light as being around 0.75 μm to 2.5 μm, the wavelength of mid-infrared light as being around 2.5 μm to 4 μm, and the wavelength of far-infrared light as being around 4 μm to 1000 μm.

[0152] For example, to form a photodiode with photosensitivity from ultraviolet to visible light, GaP or the like can be used in the photoelectric conversion layer. Additionally, to form a photodiode with photosensitivity from ultraviolet to near-infrared light, the aforementioned silicon or GaAsP or the like can be used in the photoelectric conversion layer. Furthermore, to form a photodiode with photosensitivity from visible to mid-infrared light, InGaAs or the like can be used in the photoelectric conversion layer. Additionally, to form a photodiode with photosensitivity from near-infrared to mid-infrared light, PbS or InAs or the like can be used in the photoelectric conversion layer. Furthermore, to form a photodiode with photosensitivity from mid-infrared to far-infrared light, PbSe, InSb, or HgCdTe or the like can be used in the photoelectric conversion layer.

[0153] In addition, the photodiode using the above-mentioned compound semiconductor may be a pin junction as well as a pn junction. Furthermore, the pn junction and pin junction are not limited to a homojunction structure and may be a heterojunction structure.

[0154] For example, in a heterojunction, a first compound semiconductor may be used in one layer of a pn junction structure, and a second compound semiconductor different from the first compound semiconductor may be used in the other layer. In addition, a first compound semiconductor may be used in either one or two layers of a pin junction structure, and a second compound semiconductor different from the first compound semiconductor may be used in the remaining layer. Furthermore, either the first compound semiconductor or the second compound semiconductor may be a single semiconductor such as silicon.

[0155] In addition, different materials may be used for each pixel and a photoelectric conversion layer of the photodiode may be formed. By using the above configuration, an imaging device having any two or three types of pixels, such as pixels that detect ultraviolet light, pixels that detect visible light, and pixels that detect infrared light, can be formed.

[0156] In addition, the photoelectric conversion device (101) having layer (561) may be formed by stacking layer (566a), layer (566b), layer (566c), and layer (566d), as shown in (B) of FIG. 16. The photoelectric conversion device (101) shown in (B) of FIG. 16 is an example of an avalanche photodiode, layer (566a) and layer (566d) correspond to electrodes, and layers (566b, 566c) correspond to photoelectric conversion parts.

[0157] The layer (566a) is preferably made of a low-resistance metal layer, etc. For example, aluminum, titanium, tungsten, tantalum, silver, or a stack thereof may be used.

[0158] For the layer (566d), it is preferable to use a conductive layer having high transparency to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene may be used. Additionally, the layer (566d) may be omitted.

[0159] The layers (566b, 566c) of the photoelectric conversion section can be configured as a pn-junction type photodiode, for example, using a selenium-based material as the photoelectric conversion layer. It is preferable to use a selenium-based material that is a p-type semiconductor for layer (566b) and gallium oxide or the like that is an n-type semiconductor for layer (566c).

[0160] Photoelectric conversion devices using selenium-based materials possess the characteristic of high external quantum efficiency for visible light. In the said photoelectric conversion device, electron amplification relative to the amount of incident light can be significantly increased by utilizing avalanche multiplication. Furthermore, since selenium-based materials have a high light absorption coefficient, they offer production advantages, such as the ability to fabricate the photoelectric conversion layer as a thin film. Thin films of selenium-based materials can be formed using methods such as vacuum deposition or sputtering.

[0161] As selenium-based materials, crystalline selenium (single-crystal selenium, polycrystalline selenium) and amorphous selenium can be used. These exhibit photosensitivity from ultraviolet to visible light. Additionally, compounds of copper, indium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium (CIGS) can be used. These exhibit photosensitivity from ultraviolet to near-infrared light.

[0162] It is desirable to form n-type semiconductors using materials that have a wide band gap and are transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or oxides mixed with these can be used. In addition, these materials can function as a hole injection blocking layer and can also reduce dark current.

[0163] In addition, the photoelectric conversion device (101) having layer (561) may be formed by stacking layers (567a), layer (567b), layer (567c), layer (567d), and layer (567e) as shown in (C) of FIG. 16. The photoelectric conversion device (101) shown in (C) of FIG. 16 is an example of an organic photoconductive film, layer (567a) is a lower electrode and layer (567e) is a light-transmitting upper electrode, and layers (567b, 567c, 567d) correspond to photoelectric conversion parts.

[0164] One of the layers (567b, 567d) of the photoelectric conversion section may be a hole transport layer and the other may be an electron transport layer. Additionally, layer (567c) may be a photoelectric conversion layer.

[0165] For example, molybdenum oxide can be used as the hole transport layer. For example, C can be used as the electron transport layer. 60 , C 70 Fullerenes such as the above, or derivatives thereof, may be used.

[0166] A mixed layer of n-type and p-type organic semiconductors (bulk heterojunction structure) can be used as the photoelectric conversion layer. There are various types of organic semiconductors, and it is advisable to select a material that has photosensitivity at the desired wavelength as the photoelectric conversion layer.

[0167] As for the layer (563) shown in (A) of FIG. 15, for example, a silicon substrate may be used. The silicon substrate may have Si transistors, etc. By using the Si transistors, in addition to the pixel circuit, circuits for driving the pixel circuit, circuits for reading image signals, image processing circuits, neural networks, communication circuits, etc. may be formed. In addition, memory circuits such as DRAM (Dynamic Random Access Memory), CPU (Central Processing Unit), MCU (Micro Controller Unit), etc. may also be formed. In addition, the circuits other than the pixel circuit are referred to as functional circuits in this embodiment.

[0168] For example, in the transistor having the pixel circuit (pixel (100)) and functional circuit (circuit (201, 301, 302, 303, 304, 305, 306) etc.) described in embodiment 1, some or all of them may be provided in the layer (563).

[0169] In addition, the layer (563) may be a stack of multiple layers as shown in (B) of FIG. 15. Although three layers (563a, 563b, 563c) are exemplified in (B) of FIG. 15, two layers may also be used. Alternatively, the layer (563) may be a stack of four or more layers. These layers can be stacked using, for example, a bonding process. By configuring the above, the pixel circuit and the functional circuit can be distributed across multiple layers, and the pixel circuit and the functional circuit can be provided in an overlapping manner, thereby enabling the production of a compact and high-performance imaging device.

[0170] In addition, the pixel may have a stacked structure of layers (561), layers (562), and layers (563) as shown in (C) of FIG. 15.

[0171] Layer (562) may have an OS transistor. One or more of the above-described functional circuits may be formed using an OS transistor. Alternatively, one or more of the functional circuits may be formed using a Si transistor of layer (563) and an OS transistor of layer (562). Alternatively, layer (563) may be a supporting substrate such as a glass substrate, and a functional circuit may be formed using an OS transistor of layer (562).

[0172] For example, a normally off CPU (also called "NoffCPU" (registered trademark)) can be realized by using OS transistors and Si transistors. Also, NoffCPU refers to an integrated circuit containing a normally off type transistor that is in a non-conducting state (also called an off state) even when the gate voltage is 0V.

[0173] NoffCPU can stop the power supply to circuits within the NoffCPU that do not require operation, thereby putting said circuits into a standby state. Since no power is consumed by circuits that are in a standby state with the power supply stopped, NoffCPU can minimize power consumption. Furthermore, NoffCPU can maintain information necessary for operation, such as setting conditions, for an extended period even when the power supply is stopped. To return from the standby state, it is sufficient to simply resume the power supply to said circuits, and rewriting of setting conditions is unnecessary. In other words, high-speed return from the standby state is possible. In this way, NoffCPU can reduce power consumption without significantly lowering the operating speed.

[0174] Additionally, the layer (562) may be a stack of multiple layers as shown in (D) of FIG. 15. Although two layers of layers (562a, 562b) are illustrated in (D) of FIG. 15, it may be a stack of three or more layers. These layers may be formed, for example, by stacking on top of layer (563). Alternatively, the layer formed on top of layer (563) and the layer formed on top of layer (561) may be formed by joining them.

[0175] As a semiconductor material used for OS transistors, metal oxides having an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more may be used. Representative examples include oxide semiconductors containing indium, and, for instance, CAAC-OS or CAC-OS described later may be used. CAAC-OS is suitable for transistors where reliability is important, as the atoms constituting the crystal are stable. Furthermore, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors that perform high-speed operation.

[0176] Due to the large energy gap of the semiconductor layer, OS transistors exhibit very low off-current characteristics of several yA / μm (current value per 1 μm channel width). Furthermore, OS transistors possess characteristics distinct from Si transistors, such as the absence of impact ionization, avalanche breakdown, and short-channel effects, enabling the formation of circuits with high breakdown voltage and high reliability. Additionally, deviations in electrical characteristics caused by crystallinity non-uniformity, which are problematic in Si transistors, are less likely to occur in OS transistors.

[0177] The semiconductor layer of the OS transistor can be a film represented as an In-M-Zn-based oxide containing, for example, indium, zinc, and M (one or more selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, and hafnium). The In-M-Zn-based oxide can typically be formed by sputtering. Alternatively, it may be formed using the ALD (Atomic layer deposition) method.

[0178] It is preferable that the atomic ratio of metal elements in the sputtering target used to form In-M-Zn oxides by sputtering satisfies In ≥ M and Zn ≥ M. Preferably, such atomic ratios of metal elements in the sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. Furthermore, the atomic ratio of the semiconductor layer to be deposited includes a variation of ±40% of the atomic ratio of metal elements contained in the sputtering target.

[0179] Oxide semiconductors with low carrier density are used as the semiconductor layer. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 Below, preferably 1×10 15 / cm 3 Below, more preferably 1×10 13 / cm 3 Below, more preferably 1×10 11 / cm 3 Below, more preferably 1×10 10 / cm 3 Less than and 1×10 -9 / cm 3An oxide semiconductor of the above characteristics may be used. Such an oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The above oxide semiconductor can be described as an oxide semiconductor having a low defect level density and stable characteristics.

[0180] Furthermore, not limited to these, it is preferable to use a composition having an appropriate structure depending on the required semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In addition, to obtain the required semiconductor characteristics of the transistor, it is desirable to set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, and density of the semiconductor layer to appropriate values.

[0181] If silicon or carbon, which are Group 14 elements, are included in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase, leading to n-type transformation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 The following applies.

[0182] Furthermore, when alkali metals and alkaline earth metals are combined with oxide semiconductors, they can generate carriers, which may increase the transistor's off-current. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 1 × 10⁻⁶ 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 The following applies.

[0183] Furthermore, if nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electron carriers are generated, increasing carrier density and making it prone to n-type transformation. Consequently, transistors using oxide semiconductors containing nitrogen are prone to exhibiting normaly-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 18 atoms / cm 3 It is desirable to do it below.

[0184] Furthermore, if hydrogen is present in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen bonded to metal atoms to form water, which can lead to the formation of oxygen vacancies within the oxide semiconductor. If oxygen vacancies are present in the channel-forming region of the oxide semiconductor, the transistor may exhibit normaly-on characteristics. Additionally, defects where hydrogen enters the oxygen vacancies can function as donors, generating electron carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms, thereby generating electron carriers. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen are prone to exhibiting normaly-on characteristics.

[0185] Defects in which hydrogen enters oxygen vacancies can function as donors in oxide semiconductors. However, it is difficult to quantitatively evaluate such defects. Therefore, in oxide semiconductors, the carrier concentration is sometimes evaluated rather than the donor concentration. Accordingly, in this specification and others, the carrier concentration, which assumes a state where no electric field is applied, is sometimes used as a parameter of the oxide semiconductor rather than the donor concentration. That is, the "carrier concentration" described in this specification and others may be replaced with "donor concentration."

[0186] Therefore, it is desirable to reduce hydrogen within the oxide semiconductor as much as possible. Specifically, the hydrogen concentration obtained by Secondary Ion Mass Spectrometry (SIMS) in the oxide semiconductor is 1×10⁻⁶ 20 atoms / cm 3 Less than, preferably 1×10 19 atoms / cm 3 Less than, more preferably 5×10 18 atoms / cm 3 Less than, more preferably 1×10 18 atoms / cm 3 It is set to less than. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0187] In addition, the semiconductor layer may have a non-single crystal structure, for example. Non-single crystal structures include, for example, C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) having crystals oriented along the c-axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single crystal structures, the amorphous structure has the highest defect level density, while the CAAC-OS has the lowest defect level density.

[0188] An oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and does not possess crystalline components. Alternatively, an oxide film with an amorphous structure has, for example, a completely amorphous structure and does not possess crystalline regions.

[0189] In addition, the semiconductor layer may be a mixed film having two or more of the following: an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single-crystal structure region. For example, the mixed film may have a single-layer structure or a stacked structure including two or more of the regions described above.

[0190] The configuration of CAC (Cloud-Aligned Composite)-OS, a form of non-monocrystalline semiconductor layer, is described below.

[0191] CAC-OS is, for example, a composition of a material in which elements constituting an oxide semiconductor are localized in sizes ranging from 0.5 nm to 10 nm, preferably from 1 nm to 2 nm, or in the vicinity thereof. Additionally, below, a state in which one or more metal elements are localized in an oxide semiconductor, and regions having said metal elements are mixed in sizes ranging from 0.5 nm to 10 nm, preferably from 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic pattern or a patch pattern.

[0192] In addition, it is preferable that the oxide semiconductor contains at least indium. In particular, it is preferable that it contains indium and zinc. In addition to these, one or more types selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium may be included.

[0193] For example, CAC-OS in In-Ga-Zn oxide (among CAC-OS, In-Ga-Zn oxide may specifically be called CAC-IGZO) refers to indium oxide (hereinafter InO X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) and gallium oxide (hereinafter GaO X3 (X3 is a real number greater than 0) or gallium zinc oxide (hereinafter Ga X4 Zn Y4 O Z4 A mosaic pattern is formed as the material is separated (where X4, Y4, and Z4 are real numbers greater than 0), and the InO of the mosaic patternX1 or In X2 Zn Y2 O Z2 It is a composition uniformly distributed within the membrane (hereinafter also referred to as a cloud-like structure).

[0194] In other words, CAC-OS is GaO X3 This main component region and, In X2 Zn Y2 O Z2 or InO X1 This is a composite oxide semiconductor having a mixed composition of regions that are the main components. In addition, in this specification, for example, when the ratio of the number of atoms of In to the element M of the first region is greater than the ratio of the number of atoms of In to the element M of the second region, it is said that "the first region has a higher concentration of In compared to the second region."

[0195] In addition, IGZO is a general term and sometimes refers to a single compound composed of In, Ga, Zn, and O. A representative example is InGaO3(ZnO). m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 Examples of crystalline compounds can be found as (-1 ≤ x0 ≤ 1, where m0 is an arbitrary number).

[0196] The above-mentioned crystalline compound has a single-crystal structure, a polycrystalline structure, or a CAAC structure. Furthermore, a CAAC structure refers to a crystal structure in which multiple IGZO nanocrystals are connected with c-axis orientation and are not oriented in the ab plane.

[0197] Meanwhile, CAC-OS relates to the material composition of oxide semiconductors. CAC-OS refers to a composition in which, within a material composition containing In, Ga, Zn, and O, regions observed as nanoparticles with Ga as the main component and regions observed as nanoparticles with In as the main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0198] In addition, CAC-OS does not include a stacked structure of two or more types of films with different compositions. For example, it does not include a structure consisting of two layers, such as a film with In as the main component and a film with Ga as the main component.

[0199] Also GaO X3 This main component region and, In X2 Zn Y2 O Z2 or InO X1 There are cases where the boundaries of this principal component region cannot be clearly observed.

[0200] In addition, when one or more types selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are included instead of gallium, CAC-OS refers to a composition in which regions observed as nanoparticles with the above metal elements as the main component are observed in some parts, regions observed as nanoparticles with In as the main component are observed in some parts, and each is randomly dispersed in a mosaic pattern.

[0201] CAC-OS can be formed, for example, by a sputtering method under conditions where the substrate is not intentionally heated. In addition, when forming CAC-OS by a sputtering method, it is preferable to use one or more selected from inert gas (typically argon), oxygen gas, and nitrogen gas as the film-forming gas. Furthermore, it is desirable for the ratio of the oxygen gas flow rate to the total flow rate of the film-forming gas during film formation to be as low as possible, for example, it is desirable to have the oxygen gas flow rate ratio at 0% or more and less than 30%, preferably at 0% or more and less than 10%.

[0202] CAC-OS is characterized by the fact that no clear peaks are observed when measured using an θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. In other words, it can be seen that the orientation in the ab-plane and c-axis directions of the measurement region is not visible in the X-ray diffraction measurement.

[0203] In addition, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam (also called a nano-beam electron beam) having a probe diameter of 1 nm, a ring-shaped region of high brightness (ring region) is observed, and multiple bright spots are observed in this ring region. Therefore, based on this electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has a nano-crystal (nc) structure that does not have orientation in the planar direction and cross-sectional direction.

[0204] Also, for example, in CAC-OS on In-Ga-Zn oxide, GaO X3 This main component region and, In X2 Zn Y2 O Z2 or InO X1 It can be confirmed that this main component region has a localized and mixed structure.

[0205] CAC-OS has a structure different from IGZO compounds in which metal elements are uniformly distributed, and possesses properties different from IGZO compounds. That is, CAC-OS is GaO X3 Regions where the back is the main component, and In X2 Zn Y2 O Z2 or InO X1 It has a structure in which the regions with these main components are phase-separated from each other, and the regions with each element as the main component form a mosaic pattern.

[0206] Here In X2 ZnY2 O Z2 or InO X1 The region that is the main component is GaO X3 It is a region with high conductivity compared to regions where the main components are, etc. In other words, In X2 Zn Y2 O Z2 or InO X1 Conductivity as an oxide semiconductor appears as carriers flow through this main component region. Therefore, In X2 Zn Y2 O Z2 or InO X1 By distributing this main component region in a cloud-like manner within the oxide semiconductor, high field-effect mobility (μ) can be realized.

[0207] On the other hand, GaO X3 The region where the back is the main component is In X2 Zn Y2 O Z2 or InO X1 This is a region with high insulation properties compared to the region where it is the main component. In other words, GaO X3 By distributing the region in which the main component is distributed within the oxide semiconductor, leakage current is suppressed, thereby enabling good switching operation.

[0208] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation properties attributable to the back, and In X2 Zn Y2 O Z2 or InO X1 As the conductivity attributed to acts complementarily, a high on-current (I on It is possible to realize ) and high electric field effect mobility (μ).

[0209] Furthermore, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0210] <Laminated Structure 1>

[0211] Next, the stacked structure of the imaging device will be described using a cross-sectional view. Furthermore, elements such as insulating layers and conductive layers presented below are examples, and other elements may be included. Alternatively, some of the elements presented below may be omitted. Additionally, the stacked structure presented below can be formed using bonding processes, polishing processes, etc., as necessary.

[0212] FIG. 17 is an example of a cross-sectional view of a laminate having layers (560), layers (561), and layers (563), and having a bonding surface between layers (563a) and layers (563b) that constitute layers (563).

[0213] <Floor(563b)>

[0214] Layer (563b) has a functional circuit provided on a silicon substrate (611). Here, a capacitor (202), a transistor (203), and a transistor (204) are shown as part of the functional circuit. One electrode of the capacitor (202), one of the source and drain of the transistor (203), and the gate of the transistor (204) are electrically connected.

[0215] Layer (563b) is provided with a silicon substrate (611) and insulating layers (612, 613, 614, 615, 616, 617, 618). The insulating layer (612) functions as a protective film. The insulating layers (613, 613, 616, 617) function as interlayer insulating films and planarizing films. The insulating layer (615) functions as a dielectric layer of the capacitor (202). The insulating layer (618) and the conductive layer (619) function as junction layers. The conductive layer (619) is electrically connected to one electrode of the capacitor (202).

[0216] As a protective film, for example, silicon nitride films, silicon oxide films, aluminum oxide films, etc., can be used. As an interlayer insulating film and a planarization film, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin, can be used. As a dielectric layer of a capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc., can be used. The junction layer will be described later.

[0217] In addition, for conductors that can be used as wiring, electrodes, and plugs for electrical connection between devices, it is preferable to appropriately select and use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy having the above-mentioned metal elements as components or an alloy combining the above-mentioned metal elements. The above-mentioned conductor is not limited to a single layer and may be a plurality of layers composed of other materials.

[0218] <Layer (563a)>

[0219] Layer (563a) has elements of a pixel (100). Here, transistors (102) and transistors (105) are shown as part of the elements of the pixel (100). In the cross-sectional view shown in FIG. 17, their electrical connections are not shown.

[0220] Layer (563a) is provided with a silicon substrate (632) and insulating layers (631, 633, 634, 635, 637, 638). Additionally, conductive layers (636, 639) are provided.

[0221] The insulating layer (631) and the conductive layer (639) function as bonding layers. The insulating layers (634, 635, 637) function as interlayer insulating films and planarizing films. The insulating layer (633) functions as a protective film. The insulating layer (638) functions to insulate the silicon substrate (632) and the conductive layer (639). The insulating layer (638) can be formed from the same material as the other insulating layers. Additionally, the insulating layer (638) may be formed from the same material as the insulating layer (631).

[0222] The conductive layer (639) is electrically connected to the other side of the source and drain of the transistor (105) and to the conductive layer (619). Additionally, the conductive layer (636) is electrically connected to the wiring (114) (see (A) in FIG. 3).

[0223] The Si transistor (transistor (102, 105, 203, 204)) shown in FIG. 17 is a Fin type having a channel forming region on a silicon substrate (silicon substrate (611, 632)). A cross-section in the channel width direction (a cross-section of A1-A2 shown in layer (563a) of FIG. 17) is shown in FIG. 18 (A). Additionally, the Si transistor may be Planar type as shown in FIG. 18 (B).

[0224] Alternatively, as shown in (C) of FIG. 18, the transistor may have a semiconductor layer (545) of a silicon thin film. The semiconductor layer (545) may be, for example, single-crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer (546) on a silicon substrate (632).

[0225] Floor (561)

[0226] Layer (561) has a photoelectric conversion device (101). The photoelectric conversion device (101) can be formed on layer (563a). FIG. 17 shows a configuration in which the organic photoconductive film shown in (C) of FIG. 16 is used in the photoelectric conversion layer as the photoelectric conversion device (101). Also, in this case, layer (567a) is the cathode and layer (567e) is the anode.

[0227] Layer (561) is provided with insulating layers (651, 652, 653, 654) and a conductive layer (655).

[0228] The insulating layers (651, 653, 654) function as interlayer insulating films and planarizing films. Additionally, the insulating layer (654) is provided to cover the end of the photoelectric conversion device (101) and also has the function of preventing a short circuit between layer (567e) and layer (567a). The insulating layer (652) functions as a device isolation layer. It is preferable to use an organic insulating film or the like as the device isolation layer.

[0229] The layer (567a) corresponding to the cathode of the photoelectric conversion device (101) is electrically connected to one of the source and drain of the transistor (102) having the layer (563a). The layer (567e) corresponding to the anode of the photoelectric conversion device (101) is electrically connected to the conductive layer (636) having the layer (563a) through the conductive layer (655).

[0230] <Floor (560)>

[0231] Layer (560) is formed on top of layer (561). Layer (560) has a light-blocking layer (671), an optical conversion layer (672), and a micro-lens array (673).

[0232] The light-blocking layer (671) can suppress the inflow of light into adjacent pixels. A metal layer such as aluminum or tungsten may be used for the light-blocking layer (671). Additionally, a dielectric film having a function as an anti-reflection film may be laminated with the metal layer.

[0233] When the photoelectric conversion device (101) is sensitive to visible light, a color filter can be used in the optical conversion layer (672). By assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel, a color image can be obtained. For example, as shown in the perspective view (including cross-section) of FIG. 23 (A), each of the color filter (672R) (red), color filter (672G) (green), and color filter (672B) (blue) can be assigned to different pixels.

[0234] In addition, if a wavelength cut filter is used in the optical conversion layer (672) in a suitable combination of the photoelectric conversion device (101) and the optical conversion layer (672), it can be made into an imaging device capable of obtaining images in various wavelength ranges.

[0235] For example, if an infrared filter that blocks light with a wavelength less than or equal to that of visible light is used in the optical conversion layer (672), it can be made into an infrared imaging device. Also, if a filter that blocks light with a wavelength less than or equal to that of near-infrared light is used in the optical conversion layer (672), it can be made into a far-infrared imaging device. Additionally, if an ultraviolet filter that blocks light with a wavelength greater than or equal to that of visible light is used in the optical conversion layer (672), it can be made into an ultraviolet imaging device.

[0236] In addition, multiple different optical conversion layers may be arranged within a single imaging device. For example, as shown in (B) of FIG. 23, each of the color filter (672R) (red), color filter (672G) (green), color filter (672B) (blue), and infrared filter (672IR) can be assigned to different pixels. In the above configuration, visible light images and infrared light images can be acquired simultaneously.

[0237] Alternatively, as shown in (C) of FIG. 23, each of the color filter (672R) (red), color filter (672G) (green), color filter (672B) (blue), and ultraviolet filter (672UV) can be assigned to a different pixel. In the above configuration, visible light images and ultraviolet light images can be acquired simultaneously.

[0238] In addition, if a scintillator is used in the optical conversion layer (672), an imaging device can be obtained that visualizes the intensity of radiation used in X-ray imaging devices, etc. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is acquired by detecting the light by the photoelectric conversion device (101). In addition, an imaging device with this configuration may be used in a radiation detector, etc.

[0239] Scintillators contain materials that absorb energy and emit visible or ultraviolet light when irradiated with radiation such as X-rays or gamma rays. For example, materials such as Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc., dispersed in resin or ceramic can be used.

[0240] By performing imaging using infrared or ultraviolet light, inspection functions, security functions, sensor functions, etc., can be provided to the imaging device. For example, by performing imaging using infrared light, non-destructive inspection of products, sorting of agricultural products (such as refractometer functions), vein authentication, medical inspection, etc., can be performed. In addition, by performing imaging using ultraviolet light, ultraviolet light emitted from a light source or flame can be detected, thereby enabling management of light sources, heat sources, production devices, etc.

[0241] A micro-lens array (673) is provided on the optical conversion layer (672). Light passing through each lens of the micro-lens array (673) passes through the optical conversion layer (672) directly below and is irradiated onto the photoelectric conversion device (101). By providing the micro-lens array (673), the concentrated light can be incident on the photoelectric conversion device (101), thereby enabling efficient photoelectric conversion. It is preferable that the micro-lens array (673) be formed of a resin or glass, etc., which has high light transmittance for light of the desired wavelength.

[0242] <Joining>

[0243] Next, the connection between layer (563b) and layer (563a) will be explained.

[0244] Layer (563b) is provided with an insulating layer (618) and a conductive layer (619). The conductive layer (619) has an area embedded in the insulating layer (618). Additionally, the surfaces of the insulating layer (618) and the conductive layer (619) are each flattened so that their heights match.

[0245] Layer (563a) is provided with an insulating layer (631) and a conductive layer (639). The conductive layer (639) has a region embedded in the insulating layer (631). Additionally, the surfaces of the insulating layer (631) and the conductive layer (639) are each flattened so that their heights match.

[0246] Here, it is preferable that the conductive layer (619) and the conductive layer (639) have the same main component as a metal element. Additionally, it is preferable that the insulating layer (618) and the insulating layer (631) are composed of the same component.

[0247] For example, the conductive layer (619, 639) may use Cu, Al, Sn, Zn, W, Ag, Pt, or Au. Preferably, Cu, Al, W, or Au is used for ease of bonding. Additionally, the insulating layer (618, 631) may use silicon oxide, silicon nitride, silicon nitride, silicon nitride, titanium nitride, etc.

[0248] That is, it is preferable to use the same material among the metal materials described above for each of the conductive layer (619) and the conductive layer (639). Also, it is preferable to use the same material among the insulating materials described above for each of the insulating layer (618) and the insulating layer (631). By making the above configuration, a bonding can be performed with the boundary between layer (563b) and layer (563a) as the bonding location.

[0249] In addition, the conductive layer (619) and the conductive layer (639) may have a multilayer structure consisting of multiple layers, and in that case, the surface layer (bonding surface) may be formed of the same metal material. In addition, the insulating layer (618) and the insulating layer (631) may also have a multilayer structure consisting of multiple layers, and in that case, the surface layer (bonding surface) may be formed of the same insulating material.

[0250] By the above bonding, an electrical connection between the conductive layer (619) and the conductive layer (639) can be obtained. Additionally, a connection having mechanical strength between the insulating layer (618) and the insulating layer (631) can be obtained.

[0251] For bonding metal layers, a surface activation bonding method can be used, in which surface oxide films and adsorbed impurity layers are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method can be used, which bonds surfaces by applying both temperature and pressure. In either method, since bonding occurs at the atomic level, excellent bonding can be obtained not only electrically but also mechanically.

[0252] In addition, for bonding the insulating layers, a hydrophilic bonding method can be used, in which surfaces that have been treated to be hydrophilic using oxygen plasma or the like are brought into contact to achieve high flatness through polishing, etc., temporarily bonded, and then finally bonded by dehydration through heat treatment. Since atomic-level bonding occurs in the hydrophilic bonding method as well, mechanically excellent bonding can be obtained.

[0253] When joining layers (563b) and (563a), since an insulating layer and a metal layer are mixed on each joining surface, it is preferable to perform the process by combining, for example, a surface-activated joining method and a hydrophilic joining method.

[0254] For example, a method may be used in which the surface is cleaned after polishing, an anti-oxidation treatment is performed on the surface of the metal layer, and then a hydrophilic treatment is performed to form the bond. Alternatively, the surface of the metal layer may be treated with a non-oxidizing metal such as Au and then a hydrophilic treatment may be performed. Furthermore, bonding methods other than those described above may also be used.

[0255] By the above bonding, the circuit (201) of the layer (563b) and the element of the pixel (100) of the layer (563a) can be electrically connected.

[0256] <Variation of Laminated Structure 1>

[0257] FIG. 19 is a modified example of the stacked structure shown in FIG. 17, in which the configuration of the photoelectric conversion device (101) having layer (561) and part of the configuration of layer (563a) are different, and there is also a bonding surface between layer (561) and layer (563a).

[0258] Layer (561) has a photoelectric conversion device (101), an insulating layer (661, 662, 664, 665), and a conductive layer (135, 136).

[0259] The photoelectric conversion device (101) is a pn-junction photodiode and has a layer (565b) corresponding to a p-type region and a layer (565a) corresponding to an n-type region. Additionally, an example is shown here in which a pn-junction photodiode is formed on a silicon substrate. The photoelectric conversion device (101) is an embedded photodiode and can reduce noise by suppressing dark current through a thin p-type region (part of layer (565b)) provided on the surface side (current extraction side) of layer (565a).

[0260] The insulating layer (661) and the conductive layer (135, 136) function as a junction layer. The insulating layer (662) functions as an interlayer insulating film and a planarization film. The insulating layer (664) functions as a device isolation layer. The insulating layer (665) functions to suppress the leakage of carriers.

[0261] A groove for separating pixels is provided in the silicon substrate, and an insulating layer (665) is provided on the upper surface of the silicon substrate and in the groove. By providing the insulating layer (665), carriers generated within the photoelectric conversion device (101) can be prevented from leaking to adjacent pixels. Additionally, the insulating layer (665) also has the function of preventing the intrusion of stray light. Thus, color mixing can be prevented by the insulating layer (665). Furthermore, an anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer (665).

[0262] The device isolation layer can be formed using the LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using the STI (Shallow Trench Isolation) method. As for the insulating layer (665), for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide or acrylic may be used. In addition, the insulating layer (665) may be composed of multiple layers.

[0263] A layer (565a) (n-type region, corresponding to the cathode) of the photoelectric conversion device (101) is electrically connected to a conductive layer (135). A layer (565b) (p-type region, corresponding to the anode) is electrically connected to a conductive layer (136). The conductive layers (135, 136) have regions embedded in an insulating layer (661). Additionally, the surfaces of the insulating layer (661) and the conductive layers (135, 136) are each flattened so that their heights match.

[0264] In layer (563a), an insulating layer (638) is formed on top of the insulating layer (637). Additionally, a conductive layer (133) electrically connected to one of the source and drain of the transistor (102), and a conductive layer (134) electrically connected to the conductive layer (636) are formed.

[0265] The insulating layer (638) and the conductive layer (133, 134) function as bonding layers. The conductive layer (133, 134) has an area embedded in the insulating layer (638). Additionally, the surfaces of the insulating layer (638) and the conductive layer (133, 134) are flattened so that their heights match.

[0266] Here, the conductive layer (133, 134, 135, 136) is a bonding layer similar to the conductive layer (619, 639) described above. Also, the insulating layer (638, 661) is a bonding layer similar to the insulating layer (618, 631) described above.

[0267] Accordingly, by joining the conductive layer (133) and the conductive layer (135), the layer (565a) (n-type region, corresponding to the cathode) of the photoelectric conversion device and one of the source and drain of the transistor (102) can be electrically connected. Additionally, by joining the conductive layer (134) and the conductive layer (136), the layer (565b) (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring (114) (see (A) in FIG. 3) can be electrically connected. Furthermore, by joining the insulating layer (638) and the insulating layer (661), electrical and mechanical connections between the layer (561) and the layer (563a) can be performed.

[0268] <Laminated Structure 2>

[0269] FIG. 20 is an example of a cross-sectional view of a laminate having layers (560, 561, 562, 563) and no bonding surface. A Si transistor is provided in layer (563). An OS transistor is provided in layer (562). Also, since the configuration of layers (563), layer (561), and layer (560) is the same as the configuration of layers (563b), layer (561), and layer (560) shown in FIG. 17, a description is omitted here.

[0270] <Floor (562)>

[0271] Layer (562) is formed on layer (563). Layer (562) has an OS transistor. Here, transistors (102) and transistor (105) are shown as part of the elements of the pixel (100). In the cross-sectional view shown in FIG. 20, their electrical connections are not shown.

[0272] In the layer (562), insulating layers (621, 622, 623, 624, 625, 626, 628) are provided. A conductive layer (627) is also provided. The conductive layer (627) can be electrically connected to the wiring (114) (see (A) in FIG. 3).

[0273] The insulating layer (621) functions as a blocking layer. The insulating layers (622, 623, 625, 626, 628) function as interlayer insulating films and planarizing films. The insulating layer (624) functions as a protective film.

[0274] As a blocking layer, it is desirable to use a film that has the function of preventing hydrogen diffusion. In Si devices, hydrogen is necessary to terminate dangling bonds, but hydrogen near OS transistors becomes one of the factors generating carriers in the oxide semiconductor layer, thereby degrading reliability. Therefore, it is desirable to provide a hydrogen blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0275] As the above blocking film, examples include aluminum oxide, aluminum nitride, gallium oxide, gallium nitride, yttrium oxide, yttrium nitride, hafnium oxide, hafnium nitride, yttria-stabilized zirconia (YSZ), etc.

[0276] The other end of the source and drain of the transistor (105) is electrically connected to one electrode of the capacitor (202) through a plug. Additionally, the conductive layer (627) is electrically connected to the wiring (114) (see (A) in FIG. 3).

[0277] One of the source and drain of the transistor (102) is electrically connected to the cathode of the photoelectric conversion device (101) having the layer (561). The conductive layer (627) is electrically connected to the anode of the photoelectric conversion device (101) having the layer (561).

[0278] An OS transistor is shown in detail in (A) of FIG. 21. The OS transistor shown in (A) of FIG. 21 has a self-aligning configuration that forms a source electrode (705) and a drain electrode (706) by providing an insulating layer on top of a stack of an oxide semiconductor layer and a conductive layer, and providing an opening that reaches the oxide semiconductor layer.

[0279] The OS transistor may be configured to have a gate electrode (701) and a gate insulating film (702) in addition to a channel forming region, a source region (703), and a drain region (704) formed in an oxide semiconductor layer. At least the gate insulating film (702) and the gate electrode (701) are provided in the opening. An oxide semiconductor layer (707) may be further provided in the opening.

[0280] As shown in (B) of FIG. 21, the OS transistor may be configured as a self-aligned type in which a source region (703) and a drain region (704) are formed in the semiconductor layer using a gate electrode (701) as a mask.

[0281] Alternatively, as shown in (C) of FIG. 21, it may be a non-self-aligned top-gate type transistor having an overlapping region between the source electrode (705) or drain electrode (706) and the gate electrode (701).

[0282] Although the OS transistor has been shown having a structure with a back gate (535), it may also have a structure without a back gate. The back gate (535) may be electrically connected to the front gate of the transistor provided oppositely, as shown in the cross-sectional view in the channel width direction of the transistor in (D) of FIG. 21. Also, FIG. 21 (D) shows the B1-B2 cross-section of the transistor in (A) of FIG. 21 as an example, but the same applies to transistors of other structures. Additionally, the back gate (535) may be configured to supply a fixed potential different from that of the front gate.

[0283] <Variation of Laminated Structure 2>

[0284] FIG. 22 is a modified example of the stacked structure shown in FIG. 20, wherein the configuration of the photoelectric conversion device (101) having layer (561) and part of the configuration of layer (562) are different, and the configuration has a bonding surface between layer (561) and layer (562).

[0285] The photoelectric conversion device (101) having the layer (561) is a pn-junction type photodiode and is the same as the configuration shown in FIG. 19.

[0286] In layer (562), an insulating layer (648) is formed on top of the insulating layer (628). Additionally, a conductive layer (138) electrically connected to one of the source and drain of the transistor (102), and a conductive layer (139) electrically connected to the conductive layer (627) are formed.

[0287] The insulating layer (648) and the conductive layer (138, 139) function as bonding layers. The conductive layer (138, 139) has an area embedded in the insulating layer (648). Additionally, the surfaces of the insulating layer (648) and the conductive layer (138, 139) are flattened so that their heights match.

[0288] Here, the conductive layer (138, 139) is a bonding layer similar to the conductive layer (619, 639) described above. Also, the insulating layer (648) is a bonding layer similar to the insulating layer (618, 631) described above.

[0289] Accordingly, by joining the conductive layer (138) and the conductive layer (135), the layer (565a) (n-type region, corresponding to the cathode) of the photoelectric conversion device and one of the source and drain of the transistor (102) can be electrically connected. Additionally, by joining the conductive layer (139) and the conductive layer (136), the layer (565b) (p-type region, corresponding to the anode) of the photoelectric conversion device and the wiring (114) (see (A) in FIG. 3) can be electrically connected. Furthermore, by joining the insulating layer (648) and the insulating layer (661), electrical and mechanical connections between the layer (561) and the layer (562) can be performed.

[0290] When stacking multiple Si devices, it is necessary to perform polishing or bonding processes multiple times. Consequently, there are challenges such as a large number of process steps, the need for dedicated equipment, and low yield, as well as high manufacturing costs. OS transistors can be formed by stacking on a semiconductor substrate on which devices are formed, thereby reducing the bonding process.

[0291] <Package, Module>

[0292] (A1) of FIG. 24 is an external perspective view of the upper side of a package containing an image sensor chip. The package has a package substrate (410) that fixes the image sensor chip (450) (see (A3) of FIG. 24), a cover glass (420), and an adhesive (430) that bonds them together.

[0293] (A2) of FIG. 24 is an external perspective view of the lower side of the package. The lower side of the package has a Ball Grid Array (BGA) with solder balls as bumps (440). In addition, it is not limited to a BGA and may have a Land Grid Array (LGA) or a Pin Grid Array (PGA), etc.

[0294] (A3) of FIG. 24 is a perspective view of a package with parts of the cover glass (420) and adhesive (430) omitted. An electrode pad (460) is formed on the package substrate (410), and the electrode pad (460) and the bump (440) are electrically connected through a through hole. The electrode pad (460) is electrically connected to an image sensor chip (450) by a wire (470).

[0295] Also, (B1) of FIG. 24 is an external perspective view of the upper side of a camera module in which an image sensor chip is embedded in a lens-integrated package. The camera module has a package substrate (411) that fixes an image sensor chip (451) (see (B3) of FIG. 24), a lens cover (421), and a lens (435), etc. Additionally, between the package substrate (411) and the image sensor chip (451), an IC chip (490) (see (B3) of FIG. 24) having functions such as a driving circuit and a signal conversion circuit of an imaging device is also provided, and it has a configuration as a SiP (System in package).

[0296] (B2) of FIG. 24 is an external perspective view of the lower side of the camera module. The lower and side of the package substrate (411) have a configuration of a QFN (Quad flat no-lead package) in which mounting lands (441) are provided. In addition, the above configuration is an example, and a QFP (Quad flat package) or the above-described BGA may be provided.

[0297] (B3) of FIG. 24 is a perspective view of a module with parts of the lens cover (421) and lens (435) omitted. The land (441) is electrically connected to the electrode pad (461), and the electrode pad (461) is electrically connected to the image sensor chip (451) or IC chip (490) by a wire (471).

[0298] By embedding an image sensor chip in a package of the form described above, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be provided to various semiconductor devices and electronic devices.

[0299] This embodiment can be appropriately combined with the description of other embodiments.

[0300] (Embodiment 3)

[0301] Electronic devices capable of using an imaging device according to one embodiment of the present invention include display devices, personal computers, image memory devices or image playback devices having a recording medium, mobile phones, game consoles including portable devices, portable information terminals, e-book terminals, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), photocopiers, fax machines, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIG. 25 (A) to (F).

[0302] Figure 25 (A) is an example of a mobile phone and has a housing (981), a display (982), an operation button (983), an external connection port (984), a speaker (985), a microphone (986), a camera (987), etc. The mobile phone has a touch sensor on the display (982). Various operations, such as making a call or entering text, can be performed by touching the display (982) with a finger or a stylus. An imaging device and a method of operation thereof, in one form of the present invention, can be applied to the mobile phone.

[0303] Figure 25 (B) is a portable information terminal and has a housing (911), a display unit (912), a speaker (913), a camera (919), etc. Information input and output can be performed by the touch panel function of the display unit (912). In addition, characters of an image acquired by the camera (919) can be recognized, and these characters can be output as voice from the speaker (913). An imaging device and a method of operation thereof in one form of the present invention can be applied to the portable information terminal.

[0304] (C) of FIG. 25 is a surveillance camera and has a support (951), a camera unit (952), a protective cover (953), etc. The camera unit (952) is provided with a rotating mechanism, etc., and by installing it on the ceiling, it is possible to capture images in all directions. An image device and a method of operation thereof of one form of the present invention can be applied to the elements for acquiring images in the camera unit. Furthermore, "surveillance camera" is a conventional name and does not limit its use. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0305] (D) of FIG. 25 is a video camera and has a first housing (971), a second housing (972), a display unit (973), an operation key (974), a lens (975), a connection unit (976), a speaker (977), a microphone (978), etc. The operation key (974) and the lens (975) are provided in the first housing (971), and the display unit (973) is provided in the second housing (972). An imaging device and a method of operation thereof, in one form of the present invention, can be applied to the video camera.

[0306] (E) of FIG. 25 is a digital camera and has a housing (961), a shutter button (962), a microphone (963), a light-emitting part (967), a lens (965), etc. An imaging device and a method of operation thereof in one form of the present invention can be applied to the digital camera.

[0307] (F) of FIG. 25 is a wristwatch-type information terminal and has a display unit (932), a housing and wristband (933), a camera (939), etc. The display unit (932) has a touch panel for performing operations of the information terminal. The display unit (932) and the housing and wristband (933) are flexible and have excellent wearability on the body. An imaging device and a method of operation thereof, in one form of the present invention, can be applied to the information terminal.

[0308] FIG. 26 illustrates an external view of a vehicle as an example of a moving body. The vehicle (890) has a plurality of cameras (891), etc. An imaging device of one form of the present invention and a method of operation thereof can be applied to the cameras (891). In addition, the vehicle (890) has various sensors (not shown), such as infrared radar, millimeter wave radar, laser radar, etc.

[0309] The vehicle (890) can perform automatic driving by analyzing images acquired by the camera (891) for multiple imaging directions (892) and determining surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians. Additionally, the camera (891) can be used in a system that performs road guidance, danger prediction, etc.

[0310] In one embodiment of the imaging device of the present invention, by performing computational processing such as a neural network on the obtained image data, processing such as increasing the resolution of the image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for automatic driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration of a lensless image sensor, position determination, character recognition, and reduction of reflection can be performed.

[0311] Furthermore, although automobiles were described above as an example of a mobile body, the automobile may be any of the following: an automobile having an internal combustion engine, an electric vehicle, a hydrogen vehicle, etc. Moreover, the mobile body is not limited to automobiles. For example, mobile bodies may include subways, monorails, ships, and aircraft (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and a system utilizing artificial intelligence can be provided by applying a computer of one form of the present invention to these mobile bodies.

[0312] This embodiment can be appropriately combined with the description of other embodiments.

[0313] (Embodiment 4)

[0314] By using the circuit according to embodiment 1 or the imaging device according to embodiment 2, an imaging device suitable for a vehicle performing semi-automatic driving is provided.

[0315] In Japan, the level of automation for driving systems of vehicles, such as automobiles, is classified and defined into four stages, from Level 1 to Level 4. Level 1 involves automating acceleration, steering, or braking, and is called a safe driving resource system. Level 2 involves automating multiple operations simultaneously among acceleration, steering, and braking, and is called a semi-automatic driving system (also called semi-automatic driving). Level 3 involves automating acceleration, steering, and braking, with the driver responding only in emergencies, and is also called a semi-automatic driving system (also called semi-automatic driving). Level 4 involves automating acceleration, steering, and braking, with minimal driver involvement, and is called fully automatic driving.

[0316] In this embodiment, a new configuration or a new system is proposed based on the main premise of semi-automatic operation at level 2 or level 3.

[0317] In order to display warnings of danger to the driver based on conditions obtained from various cameras or sensors, an area of ​​the display corresponding to the number of cameras or sensors is required.

[0318] FIG. 27 (A) is a schematic diagram illustrating the driver's forward view as seen from inside the vehicle. A windshield (10) is located at the top of the driver's field of vision, and a display device (11) having a display screen is installed at the bottom of the field of vision. Additionally, the windshield (10) is located between the pillars (12). FIG. 27 (B) also shows the exterior view of the vehicle (20).

[0319] The driver primarily performs acceleration, steering, and braking while looking at the display device (11), and secondarily checks the outside of the vehicle through the windshield. For the display device (11), it is preferable to use any one of a liquid crystal display, an EL (Electro Luminescence) display, or a micro LED (Light Emitting Diode) display. Here, a side dimension of the LED chip exceeding 1 mm is called a macro LED, a side dimension greater than 100 μm and less than 1 mm is called a mini LED, and a side dimension less than 100 μm is called a micro LED. It is particularly desirable to use a micro LED as the LED element applied to the pixel. By using a micro LED, a display device with very high precision can be realized. The higher the precision of the display device (11), the more desirable it is. The pixel density of the display device (11) can be 100 ppi or more and 5000 ppi or less, preferably 200 ppi or more and 2000 ppi or less.

[0320] For example, the central part (11a) of the display screen of the display device displays an image acquired from an imaging device installed in front of the vehicle outside. In addition, parts (11b, 11c) of the display screen display speed, estimated driving distance, abnormal warning indicators, and meters. In addition, the lower left part (11L) of the display screen displays an image of the vehicle outside in the left direction, and the lower right part (11R) of the display screen displays an image of the vehicle outside in the right direction.

[0321] By digitizing the side mirror (also called a door mirror) in the lower left (11L) and lower right (11R) of the display screen, the side mirror protrusion that protrudes significantly from the outside of the vehicle can be eliminated.

[0322] By configuring the display screen of the display device (11) to allow touch input operation, it is possible to perform enlargement or reduction of a part of the image, change the display position, or expand the area of ​​the display region.

[0323] Also, FIG. 28 shows an example of a block diagram of a display system including a display device (11).

[0324] The image of the display screen of the display device (11) is created using an image signal processing device (13), such as a GPU, because it is a composite of data from multiple imaging devices or sensors.

[0325] The image signal processing device (13) can process signals from multiple imaging devices or sensors in parallel.

[0326] In FIG. 28, the image signal processing device (13) is electrically connected to a front image sensor (14a), a rear image sensor (14b), a left-direction image sensor (14L), and a right-direction image sensor (14R). Also, FIG. 27 (B) shows an example of the installation location of the front image sensor (14a) and the left-direction image sensor (14L). FIG. 27 (B) shows an example of installing the front image sensor (14a) in a location close to the driver's line of sight, but it is not particularly limited and may be installed on the radiator grille or the front bumper. Also, in this embodiment, a vehicle with a right-hand drive is described as an example, but it is not particularly limited, and in the case of a left-hand drive vehicle, it may be installed according to the driver's position.

[0327] It is preferable to use the image sensor chip described in Embodiment 2 in at least one of these image sensors.

[0328] In addition, the image signal processing device (13) is shown as being electrically connected to a sensor (15) for an instrument (meter), but is not specifically limited to this configuration. Furthermore, it may be configured to be electrically connected to a plurality of sensors, such as a temperature sensor, an acceleration sensor, a battery level gauge, etc.

[0329] In addition, while FIG. 28 shows an example of a display system, FIG. 29 shows a block diagram of a new system using AI (Artificial Intelligence) to provide more information to the driver and realize semi-autonomous driving. Also, in FIG. 29, the same reference numerals are used for elements identical to those in FIG. 28.

[0330] In FIG. 29, the neural network unit (16) is electrically connected to the front image sensor (14a), the rear image sensor (14b), the left direction image sensor (14L), and the right direction image sensor (14R). Additionally, the instrument (meter) sensor (15) is also electrically connected to the neural network unit (16).

[0331] The neural network section (16) is electrically connected to the display device (11) through the image signal processing device (13).

[0332] By using the system shown in Fig. 29, it is possible to individually extract objects and backgrounds in an image and detect the movement of objects, thereby enabling the practical application of motion recognition.

[0333] For example, a black-and-white image with a wide dynamic range can be acquired using an image sensor without a color filter, and a clear image can be synthesized by using a neural network unit (16) to colorize it, and then displayed on a display device (11). For example, an image that recognizes dark shadows can be synthesized even inside a tunnel.

[0334] In addition, segmentation may be performed using a neural network unit (16). Segmentation refers to the process of identifying which object each pixel of an input image belongs to. It is also called semantic segmentation. Software for generating multiple image segments for use in image analysis is executed in the neural network unit (16). Specifically, segmentation is performed based on the content trained using image processing and U-net, which is a type of Convolutional Neural Network (CNN).

[0335] FIG. 30 (A) shows an image captured using a CMOS sensor, and FIG. 30 (B) shows an example of performing segmentation on the image using a neural network unit (16). In addition, the labels of the segmentation are distinguished as vehicle, sky, plant, ground, etc. In reality, FIG. 30 (B) is color-coded in pink, sky blue, green, and gray depending on the distance. FIG. 30 (B) is in a state where at least a car is identified.

[0336] In addition, (C) of FIG. 30 shows an image captured using a CMOS sensor, and (D) of FIG. 30 shows an example in which depth estimation is performed on the image using a neural network unit (16). FIG. 30 (D) is a result obtained using known depth estimation software. In reality, FIG. 30 (D) is colored blue, sky blue, yellow, and red depending on the distance.

[0337] In addition, (A) of FIG. 31 shows an image captured using a CMOS sensor, and (B) of FIG. 31 shows an example in which contour extraction is performed on the image using a neural network unit (16).

[0338] By appropriately utilizing one or more of these AI-based means, the driver can operate the vehicle primarily while viewing images from a display device—specifically, images generated by image sensors and AI—making looking at the windshield a secondary function. Operating the vehicle while viewing AI-generated images can result in safer driving than driving relying solely on the driver's eyes. Furthermore, the driver can operate the vehicle with a sense of security.

[0339] In addition, the display device can be applied to the driver's seat area (also called the cockpit) of various types of vehicles, including large, medium, and small vehicles. It can also be applied to the driver's seat area of ​​vehicles such as aircraft and ships.

[0340] In addition, as an imaging device, if the circuit of Embodiment 1 and the imaging device of Embodiment 2 are used, a part of the AI ​​computation can be performed. In addition, if the circuit of Embodiment 1 and the imaging device of Embodiment 2 are used, it is possible to colorize a black-and-white image, equalize brightness, selective detection, quantify the degree of depth perception, convert to a natural image, process for focusing over a wide range, extract partial displays, and synthesize intermediate images of multiple images.

[0341] Also, in FIG. 29, the image signal processing device (13) and the neural network unit (16) are shown separately, but they are not specifically limited and may be integrated.

[0342] In addition, a transistor using an oxide semiconductor (OS transistor) may be used in part of the image signal processing device (13) or part of the neural network part (16). By using an OS transistor, it is possible to achieve even lower power consumption.

[0343] This embodiment can be freely combined with other embodiments. Explanation of the symbols

[0344] 10: Windshield, 11: Display unit, 11a: Central part, 11b: Part, 11c: Part, 11L: Lower left, 11R: Lower right, 12: Pillar, 13: Image signal processing unit, 14a: Front image sensor, 14b: Rear image sensor, 14L: Left-facing image sensor, 14R: Right-facing image sensor, 15: Sensor for instrument (meter), 16: Neural network unit, 20: Vehicle, 100: Pixel, 101: Photoelectric conversion device, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Transistor, 107: Capacitor, 111: Wiring, 112: Wiring, 113: Wiring, 113a: Wiring, 113b: Wiring, 113c: Wiring, 113d: Wiring, 113e: Wiring, 113f: Wiring, 113g: Wiring, 113h: Wiring, 113i: Wiring, 113j: Wiring, 114: Wiring, 115: Wiring, 117: Wiring, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 133: Conductive layer, 134: Conductive layer, 135: Conductive layer, 136: Conductive layer, 138: Conductive layer, 139: Conductive layer, 150: Transistor, 150a: Transistor, 150b: Transistor, 150c: Transistor, 150d: Transistor, 150e: Transistor, 150f: Transistor, 150g: Transistor, 150h: Transistor, 150i: Transistor, 150j: Transistor, 161: Transistor, 162: Transistor, 163: Capacitor, 170: Circuit, 200: Pixel block, 201: Circuit, 202: Capacitor, 203: Transistor, 204: Transistor, 205: Transistor, 206: Transistor, 207: Resistor, 211: Wiring, 212: Wiring, 213: Wiring, 215: Wiring, 216: Wiring, 217: Wiring, 218: Wiring, 219: Wiring, 300: Pixel array, 301: Circuit, 302: Circuit, 303: Circuit, 304: Circuit, 305: Circuit, 306: Circuit, 311: Wiring, 320: Memory cell,325: Reference memory cell, 330: Circuit, 350: Circuit, 360: Circuit, 370: Circuit, 410: Package substrate, 411: Package substrate, 420: Cover glass, 421: Lens cover, 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image sensor chip, 451: Image sensor chip, 460: Electrode pad, 461: Electrode pad, 470: Wire, 471: Wire, 490: IC chip, 535: Back gate, 545: Semiconductor layer, 546: Insulating layer, 560: Layer, 561: Layer, 562: Layer, 562a: Layer, 562b: Layer, 563: Layer, 563a: Layer, 563b: Layer, 563c: Layer, 565a: Layer, 565b: Layer, 566a: Layer, 566b: Layer, 566c: Layer, 566d: Layer, 567a: Layer, 567b: Layer, 567c: Layer, 567d: Layer, 567e: Layer, 611: Silicon substrate, 612: Insulating layer, 613: Insulating layer, 614: Insulating layer, 615: Insulating layer, 616: Insulating layer, 617: Insulating layer, 618: Insulating layer, 619: Conductive layer, 621: Insulating layer, 622: Insulating layer, 623: Insulating layer, 624: Insulating layer, 625: Insulating layer, 626: Insulating layer, 627: Conductive layer, 628: Insulating layer, 631: Insulating layer, 632: Silicon substrate, 633: Insulating layer, 634: Insulating layer, 635: Insulating layer, 636: Conductive layer, 637: Insulating layer, 638: Insulating layer, 639: Conductive layer, 648: Insulating layer, 651: Insulating layer, 652: Insulating layer, 653: Insulating layer, 654: Insulating layer, 655: Conductive layer, 661: Insulating layer, 662: Insulating layer, 664: Insulating layer, 665: Insulating layer, 671: Light-blocking layer, 672: Optical conversion layer, 672B: Color filter, 672G: Color filter, 672IR: Infrared filter, 672R: Color filter, 672UV: Ultraviolet filter, 673: Micro-lens array, 701: Gate electrode, 702: Gate insulating film, 703: Source region, 704: Drain region, 705: Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer,890: Vehicle, 891: Camera, 892: Imaging Direction, 911: Housing, 912: Display, 913: Speaker, 919: Camera, 932: Display, 933: Housing and Wrist Band, 939: Camera, 951: Support, 952: Camera Unit, 953: Protective Cover, 961: Housing, 962: Shutter Button, 963: Microphone, 965: Lens, 967: Light Emitting Unit, 971: First Housing, 972: Second Housing, 973: Display, 974: Operation Key, 975: Lens, 976: Connection Unit, 977: Speaker, 978: Microphone, 981: Housing, 982: Display, 983: Operation Button, 984: External Connection Port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

Claim 1 An imaging device comprising a first transistor, a first pixel, and a second pixel, wherein the first pixel and the second pixel each comprise a second transistor, a photoelectric conversion device, and a capacitor, wherein one of the source and drain of the second transistor is electrically connected to one electrode of the capacitor, and the other electrode of the capacitor is electrically connected to one electrode of the photoelectric conversion device, and the other of the source and drain of the second transistor is electrically connected to a first wiring, and the first wiring has the function of supplying a potential corresponding to a weighting factor, wherein one electrode of the capacitor of the first pixel and one of the source and drain of the second transistor of the first pixel are electrically connected to one of the source and drain of the first transistor, and one electrode of the capacitor of the second pixel and one of the source and drain of the second transistor of the second pixel are electrically connected to the other of the source and drain of the first transistor. Imaging device. Claim 2 An imaging device comprising a first transistor, a first pixel, and a second pixel, wherein the first pixel and the second pixel each comprise a second transistor and a capacitor, one of the source and drain of the second transistor is electrically connected to one electrode of the capacitor, one electrode of the capacitor of the first pixel and one of the source and drain of the second transistor of the first pixel are electrically connected to one of the source and drain of the first transistor, one electrode of the capacitor of the second pixel and one of the source and drain of the second transistor of the second pixel are electrically connected to the other of the source and drain of the first transistor, wherein the first pixel and the second pixel each further comprise a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a photoelectric conversion device, wherein the other electrode of the capacitor is the gate of the third transistor and among the source and drain of the fourth transistor An imaging device having one side and one of the source and drain of the fifth transistor electrically connected, one of the source and drain of the third transistor electrically connected to one of the source and drain of the sixth transistor, and the other of the source and drain of the fifth transistor electrically connected to one electrode of the photoelectric conversion device. Claim 3 An imaging device according to claim 1 or 2, further comprising a first circuit, wherein the first circuit has the function of outputting a potential to the first pixel and the second pixel, and the first circuit is electrically connected to the other side of the source and drain of the second transistor of the first pixel and the other side of the source and drain of the second transistor of the second pixel. Claim 4 An imaging device according to claim 2, further comprising a second circuit, wherein the second circuit is a correlated double sampling circuit, and the second circuit is electrically connected to the other side of the source and drain of the sixth transistor of the first pixel and the other side of the source and drain of the sixth transistor of the second pixel. Claim 5 An imaging device according to claim 2, wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprises a metal oxide in a channel forming region, and the metal oxide comprises In. Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete

Images