Traffic signal control apparatus and operation method thereof for detecting overlapping of option boards

Abstract

A system is disclosed. A traffic signal control device according to one embodiment of the present disclosure includes a CPU board configured to process data within an address range included in each bus data provided from a plurality of slots and at least two option boards, and configured to output a board recognition signal including the number of IDs of the option boards based on the address range of the data processed through VME communication; and an MMI configured to detect at least two slots among a plurality of slots in which at least two option boards are mounted, and configured to determine whether there is a duplicate setting of the ID of the option boards based on at least two detection signals and a board recognition signal generated from the at least two slots, and configured to perform a notification operation according to the determination result.

Description

Technology Field

[0001] The present disclosure relates to an electronic device. More specifically, the present disclosure relates to a traffic signal control device for detecting whether there is a duplicate ID of an option board and a method of operating the same. Background Technology

[0002] The traffic signal control device is separated into a Main Control Unit (MCU, hereinafter referred to as the Main Control Unit or MCU) and a Signal Control Unit (SCU, hereinafter referred to as the Signal Control Unit or SCU), and each adopts a separate Central Processing Unit (CPU). The Main Control Unit may include a CPU board, a detector board, and an option board. The CPU board can exchange information with the detector board and the option board via VME (VERSA Module Eurocard) communication using address space data of the VME bus.

[0003] The detector board has a device ID for managing the VME bus address range by dividing it into eight sections, and the option board has a device ID for managing the VME bus address range by dividing it into seven sections. To this end, the detector board and the option board may each be equipped with a device ID selection switch. The option boards can be manufactured by different users, and a specific user may install a specific option board on a traffic signal control device. It is assumed that each option board performs a different function from the outset. In this case, by the user operating the device ID selection switch of the option board, each option board uses a specific address range among the VME bus address ranges. If multiple option boards are installed on the traffic signal control device and the same device ID is set, when the CPU board reads or writes data at a specific address, multiple option boards using the same ID will respond simultaneously, causing the traffic signal control device to malfunction, such as providing incorrect information. The option board that is plugged in first is assigned number 1 (not based on slot order), and a problem can arise if a non-expert in floor traffic lights plugs the option board into number 1 again exactly as it was received. Detector boards and option boards must be configured so that their device IDs do not overlap. However, there is no conventional technology to software-identify when option boards with duplicate device IDs are installed in a traffic signal control device, nor is there technology to allow an operator to easily detect whether duplicate installations have occurred. The problem to be solved

[0004] The embodiment disclosed in this disclosure is intended to construct a traffic system for smoothly performing traffic signal control by notifying the user that there are duplicate device IDs.

[0005] The problems that this disclosure aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0006] A traffic signal control device according to one aspect of the present disclosure for achieving the aforementioned technical problem comprises: a CPU (Central Processing Unit) board configured to process data within an address range included in each bus data provided from a plurality of slots and at least two option boards, and configured to output a board recognition signal including the number of IDs of the option boards based on the address range of the data processed via VME (VERSA Module Eurocard) communication; and a MMI (Man-Machine Interface) configured to detect at least two slots among the plurality of slots in which the at least two option boards are mounted, configured to determine whether the option boards are incorrectly inserted based on at least two detection signals generated from the at least two slots and the board recognition signal, and configured to perform a notification operation according to the determination result.

[0007] A method of operation of a traffic signal control device according to another aspect of the present disclosure comprises: detecting at least two slots among a plurality of slots in which at least two option boards are mounted; outputting a board recognition signal including the number of IDs of the option boards based on the address range of the processed data during a data processing period in which data within an address range included in each bus data provided from at least two option boards is processed; determining whether the option boards are incorrectly inserted based on the detection signal of each of the at least two detected slots and the board recognition signal; and performing a notification operation according to the determination result. Effects of the invention

[0008] According to the aforementioned means for solving the problem of the present disclosure, by notifying that there are duplicate device IDs, there is an effect of facilitating traffic signal control operations and preventing malfunction of the traffic signal control device.

[0009] The effects of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below. Brief explanation of the drawing

[0010] FIG. 1 is a drawing illustrating an exemplary traffic signal control device of the present disclosure. FIG. 2 is a block diagram exemplarily illustrating the subject matter of the present disclosure. FIG. 3 is a block diagram illustrating an exemplary MMI of the present disclosure. FIG. 4 is a drawing for explaining the operation of determining whether an option board is incorrectly inserted according to exemplary embodiments of the present disclosure. FIG. 5 is a flowchart for explaining the operation method of a traffic signal control device of the present disclosure. FIG. 6 is a flowchart illustrating some embodiments of step S100 of FIG. 5. FIG. 7 is a flowchart illustrating some embodiments of step S200 of FIG. 5. FIG. 8 is a flowchart illustrating some embodiments of step S400 of FIG. 5. Specific details for implementing the invention

[0011] Throughout this disclosure, the same reference numerals denote the same components. This disclosure does not describe all elements of the embodiments, and general content in the art to which this disclosure pertains or content that overlaps between embodiments is omitted. The terms 'part, module, component, block' as used in the specification may be implemented in software or hardware, and depending on the embodiments, a plurality of 'parts, modules, components, blocks' may be implemented as a single component, or a single 'part, module, component, block' may include a plurality of components.

[0012] Throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are directly connected but also cases where they are indirectly connected, and indirect connections include connections made via a wireless communication network.

[0013] Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0014] Throughout the specification, when it is stated that a component is located "on" another component, this includes not only cases where a component is in contact with another component, but also cases where another component exists between the two components.

[0015] Terms such as "first," "second," etc., are used to distinguish one component from another, and the components are not limited by the aforementioned terms.

[0016] Singular expressions include plural expressions unless there is an obvious exception in the context.

[0017] In each step, identification codes are used for convenience of explanation and do not describe the order of the steps; the steps may be performed differently from the specified order unless a specific order is clearly indicated in the context.

[0018] The operating principles and embodiments of the present disclosure will be described below with reference to the attached drawings.

[0019] In this specification, the "system according to the present disclosure" includes all various devices capable of performing computational processing and providing results to a user. For example, the "system according to the present disclosure" may include all of a computer, a server device, and a portable terminal, or may be in the form of any one of them.

[0020] Here, the computer may include, for example, a notebook, desktop, laptop, tablet PC, slate PC, etc. equipped with a web browser.

[0021] A portable terminal is a wireless communication device that ensures portability and mobility, and may include all kinds of handheld-based wireless communication devices such as PCS (Personal Communication System), GSM (Global System for Mobile communications), PDC (Personal Digital Cellular), PHS (Personal Handyphone System), PDA (Personal Digital Assistant), IMT (International Mobile Telecommunication)-2000, CDMA (Code Division Multiple Access)-2000, W-CDMA (W-Code Division Multiple Access), WiBro (Wireless Broadband Internet) terminals, smartphones, etc., as well as wearable devices such as watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs).

[0022] FIG. 1 is a drawing illustrating an exemplary traffic signal control device of the present disclosure.

[0023] Referring to FIG. 1, the traffic signal control device (10) may be referred to as a traffic signal controller or a traffic signal device. The traffic signal control device (10) may include a main control unit (110), a signal driving unit (120), and other device units (130). The size of the main control unit (110) may be 6U, the size of the signal driving unit (120) may be 3U, and the size of the other device unit (130) may be 3U. However, it is not limited thereto. The main control unit (110), the signal driving unit (120), and the other device unit (130) may be installed in a different order depending on the installation conditions at the site (such as the height of the base). Although not shown, the traffic signal control device (10) may further include a terminal block box (T / F). The terminal portion of the terminal block box (T / F) may be arranged in various ways internally within the range satisfying the specifications of the entire enclosure and is located at the bottom. Depending on the convenience of maintenance according to on-site installation conditions such as the height of the base and the design form of the controller enclosure, the location of internal components (main control unit, signal driving unit, other device unit, etc.) can be appropriately arranged.

[0024] The main control unit (110) may be referred to as a signal main control unit or an MCU (Main Control Unit). The main control unit (110) may be a unit computing system that serves as the central component of a traffic signal control device (10), and may be a device in which one or more central processing unit boards, multiple loop detector boards and DC power supplies, and, if necessary, a communication modem and various option boards are connected as a single bus system. The main control unit (110) may include a power supply (PWR) (111), a man-machine interface (MMI) (112), a modem (modulator-demodulator) (113), a central processing unit (CPU) board (114), first to N detector boards (DET) (115_1~115_N), and first to M option boards (OPT).

[0025] The PWR (111) can receive an externally supplied alternating current (or AC power) and convert it into a stable direct current (or DC power) to operate the device, and supply it to the traffic signal control device (10). Heat dissipation by natural ventilation is possible in the PWR (111), and the PWR (111) can operate stably in response to input fluctuations and load fluctuations. The PWR (111) can be mounted on the front, and space can be secured so that an MMI (112) and a power status display panel can be mounted on the front. Additionally, the power status display panel may include a power switch and a power indicator lamp.

[0026] The MMI (112) may be a device that allows an operator to input or modify data required for the traffic signal control device (10) by operating a keyboard installed on the front. The MMI (112) may allow the operator to easily check data through a screen display. Additionally, the MMI (112) should be ergonomically designed to facilitate maintenance and display the operating status of the traffic signal through a status indicator lamp or a screen display. The information may be displayed in the form of text or graphics.

[0027] The modem (113) is a card-type communication device that enables data communication between the central control center unit and the traffic signal as a frequency modulation / demodulation device. The modem (113) is mounted on a 19" standard rack and modulates a digital transmission signal from the main control unit (110) into an analog signal and transmits it over a dedicated line, and can demodulate a received analog signal into a digital signal and transmit it to the CPU board (114). A microprocessor may be used in the modem (113) to provide high reliability.

[0028] The CPU board (114) refers to a controller board mounted on the main control unit (110), and performs a pivotal role responsible for creating and operating signal plans, managing databases, processing detection information, and communicating with external devices, and can always maintain important data related to signal operation even in the event of a power outage through a memory backup function.

[0029] The first to Nth detector boards (115_1 to 115_N) may be control devices that detect the presence, speed, and other information of a vehicle and input it into a traffic signal after installing a vehicle detection sensor by methods such as burying it on the road surface or roadside or installing a structure. The number of detector boards is N, and N may be a natural number greater than or equal to 2. For example, N may be 8, but is not limited thereto. Loop, image, ultrasonic, radar detectors, etc., may be used in the first to Nth detector boards (115_1 to 115_N). The configuration and specifications for the loop detector, which is currently the most commonly used, shall be adopted as a standard, and the specifications for other detectors shall be defined in a standard proposed in the future. In addition, the interface with the controller board must be processed via the VME (VERSA Module Eurocard) bus. A plurality of slots may be provided in the main control unit (110) for mounting or inserting the first to Nth detector boards (115_1~115_N) into the main control unit (110). For example, one detector board may be inserted into one slot.

[0030] The first to M option boards (116_1 to 116_M) may be various VME bus compatible control boards that can be additionally mounted in addition to the first to N detector boards (115_1 to 115_N) so that the main control unit (110) can perform additional functions considering future expandability and compatibility as well as control functions. The number of option boards is M, and M may be a natural number greater than or equal to 2. The first to M option boards (116_1 to 116_M) must comply with standard VME bus protocols and may be manufactured in SLAVE mode if there is an independent process. Functions applicable as option cards of the option board may include, for example, a Time Signal Receiving Unit that receives a time signal frequency generated from a radio to set an internal timer of a traffic signal, a Voice Generator Unit having a voice transmission function for the visually impaired, a pedestrian push button input device having a button input function for pedestrian detection, a Serial Input / Output Unit (SIO) supporting up to 8 channels for extended serial communication functions, an RF Module (Radio Frequency module) including a vehicle detection / recognition device or a wireless input / output device using wireless, and other devices developed to increase control efficiency or implement functions necessary for traffic light operation. Multiple slots for inserting the first to M option boards (116_1~116_M) into the main control unit (110) may be provided in the main control unit (110). For example, one option board may be inserted into one slot.

[0031] The signal driving unit (120) may be referred to as a signal light driving unit or a Signal Control Unit (SCU). The signal driving unit (120) is responsible for turning the signal light on and off according to the command of the main control unit (110), and enhances the stability of the system through a fail-safe control function that performs basic signal output control when a failure occurs in the main control unit (110). The signal driving unit (120) may be a series of devices that receive a signal progression command from the main control unit (110), perform electrical output of the signal light, and monitor the output results. The signal driving unit (120) is a device in which a CPU board (114) that directs the light output according to time progression and a flasher that can control and monitor the output for driving the signal light and perform flashing control in case of emergency are connected by a single system bus. Although not illustrated, the signal driving unit (120) may include a controller board, a flasher, a light driving device, and an expansion board.

[0032] The other device section (130) may be a mounting space where a control device equipped with an independent computing system can be located inside the traffic signal. The independent control device that can be mounted in the other device section (130) may include a control device for functions related to signal control functions, such as a wireless input / output device, an independent image processing system, an alternative detector control system, and an independent real-time control system, as well as equipment used as field devices in Intelligent Transportation Systems (ITS), such as a wireless vehicle information collection device, a vehicle recognition system, and other devices. The devices mounted in the other device section (130) may share power and communication lines with the traffic signal. Although not illustrated, the other device section (130) may include an image detector, a wireless IO device, an alternative detector, and an ITS field device.

[0033] FIG. 2 is a block diagram exemplarily illustrating the subject matter of the present disclosure.

[0034] Referring to FIG. 2, the main control unit (200) is a device that plays a pivotal role in the traffic signal control device (10), and exchanges data between the central control center device and the traffic signal, and incorporates a real-time timer to ensure the accurate detection cycle of the vehicle detector that identifies the traffic status of the intersection and the accurate progress of the signal time, and enables internal communication with the signal drive unit and the setting of a database and various parameters through an operator input device.

[0035] The main control unit (200) may include a VME bus (210), a CPU board (220), an MMI (230), a DET (240), and an OPT (250).

[0036] The CPU board (220), DET (240), and OPT (250) can communicate with each other via the VME bus (210). The VME bus (210) is a 32-bit and 64-bit system standard for small computers developed by private companies in the United States and France, and was recognized as an international standard after being standardized as IEC 821 and IEEE 1014 by the International Electrotechnical Commission (IEC) and the Institute of Electrical and Electronics Engineers (IEEE) in 1986 and 1987, respectively. In the main control unit (200), power supply and signal transmission between the CPU board (220), DET (240), and OPT (250) are performed via the VME bus, which is designed to be suitable for industrial devices and has proven stability. The VME bus (210) can be divided into a J1 section, which is enforced for stable operation of the bus and compatibility with the signaling system, and a J2 section, which can be redefined and operated according to independent functions and purposes. J1 uses the VME standard 24-bit bus specification, and J2 follows the contents defined in this specification according to the function of the traffic signal. The VME bus (210) must use an industrial standard VME compatible backplane. The VME bus (210) must support a 24-bit address (Standard VME) (however, the detector board uses a 16-bit short I / O address, the CPU uses a 24-bit address, and the option board can use up to 24 bits). The starting address is set to 0000:0000, and the base address of the bus data is set to 0000:0000. The address delay of all slave boards inserted into the BUS must be within a maximum of 5μsecs. The CPU board (220) supports up to A24 so that OPT (250) can be used. DET (240) uses A0 to A15. DET (240) and OPT (250) may decode only the lower 2 Bytes of the address value. The Data Access Size of DET (240) is set to 16 Bits from D0 to D15.The addressing ranges of DET (240) and OPT (250) follow [Table 1] below, and device ID selection switches must be provided in DET (240) and OPT (250).

[0037] Device ID Address Range Address Type Size Remark Detector board 1 FFFF0000-FFFF001F Short I / O 32 Bytes 256 Bytes Detector Board 2 FFFF0020-FFFF003F 32 Bytes Detector board 3 FFFF0040-FFFF005F 32 Bytes Detector board 4 FFFF0060-FFFF007F 32 Bytes Detector board 5 FFFF0080-FFFF009F 32 Bytes Detector board 6 FFFF00A0-FFFF00BF 32 Bytes Detector Board 7 FFFF00C0-FFFF00DF 32 Bytes Detector board 8 FFFF00E0-FFFF00FF 32 Bytes Option Board 1 FFFF0100-FFFF02FF Short I / O 512 Bytes Option Board 2 FFFF0300-FFFF04FF Short I / O 512 Bytes Option Board 3 FFFF0500-FFFF06FF Short I / O 512 Bytes Option Board 4 FFFF0700-FFFF08FF Short I / O 512 Bytes Option Board 5 FFFF0900-FFFF0AFF Short I / O 512 Bytes Option Board 6 FFFF0B00-FFFF0CFF Short I / O 512 Bytes Option Board 7 FFFF0D00-FFFF0EFF Short I / O 512 Bytes

[0038] In [Table 1] above, “FFFF : xxxx” indicates the SHORT I / O area (A0-A15). When a processor is applied to the OPT (250) (e.g., image detector controller and CPU-equipped option board in Slave mode), it is allocated from the Standard Address area, and the specifications related to detailed addressing must be reported to the standard specification management agency to obtain permission. The address range of the VME is FFFF0000 ~ FFFF0EFF, and a total of 3840 bytes of data can be used. Up to 8 detector boards can be installed in the slots of the main control unit (200), and up to 7 option boards can be installed in the slots of the main control unit (200). A total of 15 detector boards and option boards must have a unique address range. To this end, the detector board and the option board are equipped with a device ID switch for selecting an address area. The CPU board (220) is equipped with a high-performance microprocessor to perform the central processing function of the main control unit (200) and runs hardware in a 32-bit operating system (OS) environment. The CPU board (220) is equipped with a memory device for executing a real-time signal control program that performs high-performance detector information processing and signal time operation, and performs control of the main board system bus and the serial communication device. The CPU board (220) may include a control circuit unit using a CPU of 32-bit class or higher, an OS and application program, a ROM for storing an initial database, a RAM for storing various signal time data and executing an operation program and application program, a Real Time Clock (RTC) for real-time time progress processing, a communication circuit for serial communication, a data backup circuit capable of preserving data in the event of a power outage, and a VME I / F.The CPU board (220) is a core part of the traffic signal and must have the function of exchanging data with the central control center unit through a communication device, receiving and analyzing information from each module such as vehicle detectors and operator input devices, performing central control mode, uploading and downloading databases, signal control function based on built-in signal time data in local control mode, processing of detector data of 64 channels or more, memory backup function in case of power outage, power management function for monitoring abnormal operation of the CPU and DC (+5V) voltage, real-time time management function, and hardware and software interrupt function. The CPU board (220) controls the traffic signal according to the software control function specified in other function specifications and the data processing method specified in the communication protocol section.

[0039] The CPU board (220) must be able to automatically recognize the option board type and process it according to the instructions in the option board bus protocol header. The CPU (MCU) must poll the option board header at intervals of 200 msec or less to process it and determine the RUN status.

[0040] The CPU board (220) can process bus data provided from the OPT (250). For example, the CPU board (220) can process data within an address range included in the bus data of the OPT (250). The address range of the bus data may be, for example, the Address Range of [Table 1] mentioned above. Referring to [Table 1] mentioned above, for example, if the device ID of the OPT (250) is “Option Board 1”, the CPU board (220) can process data corresponding to an address included within “FFFF0100-FFFF02FF”.

[0041] The CPU board (220) can process data within the address range included in each bus data provided from at least two OPTs (250). For example, if the device ID of the first OPT is “Option Board 1” and the device ID of the second OPT is “Option Board 2”, the CPU board (220) can process data corresponding to the addresses included within “FFFF0100-FFFF02FF” of the first OPT and data corresponding to the addresses included within “FFFF0300-FFFF04FF” of the second OPT.

[0042] The CPU board (220) can output a board recognition signal including the number of IDs of the OPT (250) based on the address range of the data processed through VME communication.

[0043] For example, if the number of OPTs (250) inserted into each of the slots of the main control unit (200) is two or more, and the device ID of the first OPT and the device ID of the second OPT are “Option Board 1,” then both the first OPT and the second OPT may use the same address range, “FFFF0100-FFFF02FF.” That is, the address corresponding to the data transmitted by the first OPT and the second OPT via VME communication may be included within “FFFF0100-FFFF02FF.” The CPU board (220) processes the data corresponding to the address included within “FFFF0300-FFFF04FF” of each of the first OPT and the second OPT, respectively, and at this time, the number of IDs of the OPT (250) of the board recognition signal output by the CPU board (220) may be one. That is, even if the number of OPTs (250) inserted into the slots of the main control unit (200) is 2 or more, if at least two OPTs have the same device ID, the CPU board (220) can recognize the OPTs using the same device ID as one device. As another example, if the number of OPTs (250) inserted into each of the slots of the main control unit (200) is 3, and the device ID of the first OPT and the device ID of the second OPT are “Option Board 1” and the device ID of the third OPT is “Option Board 2”, the CPU board (220) can process data corresponding to the address included within “FFFF0300-FFFF04FF” of each of the first OPT and the second OPT, and data corresponding to the address included within “FFFF0300-FFFF04FF” of the third OPT. At this time, the number of IDs of the OPT (250) of the board recognition signal output by the CPU board (220) may be 2.

[0044] The MMI (230) can perform functions such as checking the status of traffic signals, inputting or modifying necessary data, and adjusting the status of traffic signals by operating buttons installed on the front. The MMI (230) can be designed so that all operations can be performed even without a PC with a built-in simulation program at the site. The operator can easily enter sub-menus using arrow keys from the main menu via the MMI (230)'s Menu Drive method and select and display items corresponding to each menu. However, it is clear that the functions of the MMI (230) are not performed within the MMI (230) itself, but are defined as required functions of the MMI console corresponding program on the CPU board, and the MMI (230) is mostly defined as a key input device and a console output device for the MMI corresponding program within the CPU board.

[0045] The MMI (230) can detect at least two slots among the multiple slots of the main control unit (200) in which the at least two OPTs (250) are mounted. For example, if one specific OPT (250) is mounted in one specific slot, the MMI (230) can generate one detection signal. As many detection signals as there are OPTs (250) and slots mounted to each other, detection signals may be generated. In some embodiments, the MMI (230) can generate at least two detection signals. The MMI (230) can receive a board recognition signal from the CPU board (220). Based on the at least two detection signals generated from the at least two slots and the board recognition signal, the MMI (230) can determine whether the ID of the OPT (250) is incorrectly set. This will be described later with reference to FIG. 4. MMI (230) can perform a notification action based on the result of determining whether OPT (250) is incorrectly inserted.

[0046] The DET (240) may be referred to as a detector board. There may be one or more DETs (240). The DET (240) is a system capable of detecting vehicles on the road and actively processing them according to traffic conditions, and may include loop, image, ultrasonic, and radar detectors. The configuration and specifications of the loop detector (LDU; Loop Detection Unit), which is currently the most commonly used, are adopted as a standard, and the specifications of other detectors are to be defined in a standard proposed in the future. In addition, the interface with the CPU board (220) must be processed via the VME bus (210). This device is connected to a loop coil buried in the road and detects electrical changes in the loop coil to detect the presence and passage of a vehicle. This device consists of a loop coil, a lead-in, and an amplifier. Traffic variables (traffic volume, occupancy rate, speed, etc.) used for signal control and traffic condition indicators are calculated based on data obtained from vehicle detectors installed on the road. The vehicle detector presented in this specification is the most common inductive loop detector currently in use. The DET (240) can supply energy to the loop sensor, monitors the loop sensor and inductance, and the output detecting the passage and presence of a vehicle in the detection area responds to a decrease in the set inductance. An electromagnetic field is generated around the loop detector by the current flowing through the loop line provided by the DET (240). This can be represented as an energetic flux, and if a vehicle enters the electromagnetic field, an eddy current is induced (absorbed) in the vehicle body, which has the effect of reducing the magnetic field lines. A decrease in the self-inductance of the loop detector increases the frequency so that the loop line can resonate.The amplifier responds to this frequency by using a feedback circuit that increases its own oscillation frequency or by using a circuit that generates a frequency phase difference. Such frequency conversion or phase shifting forms the basis for obtaining detection data. In addition to the resonant circuit, the amplifier must be equipped with a switch for adjusting sensitivity, a switch for selecting the detection method (Presence Mode, Pulse Mode, Loop Check, etc.), a frequency adjustment switch, a reset switch, and a call indication lamp.

[0047] The OPT (250) may be referred to as an option board. There may be one or more OPTs (250). The main control unit (200) adopts a structure that allows for the additional installation of various VME Modules to perform not only control functions but also additional functions considering future scalability and compatibility, thereby enabling the development and installation of devices that perform various additional functions. The OPT (250) must specify the type of board in the bus data header to support interfacing the bus memory in a defined format. Even if the type is specified, such as a communication board, devices that perform unique functions specific to each manufacturer are distinguished by inputting the manufacturer's unique code through the VENDER CODE of the header. The CPU board (220) must scan the Option addressing range specified in the standard specification to recognize whether the device is mounted and the type of the device. If the ReqSigInfo value in the header is specified, this indicates a device requesting a signal operation status, so the CPU board (220) provides the signal operation status to the OPT (250).

[0048] FIG. 3 is a block diagram illustrating an exemplary MMI of the present disclosure.

[0049] Referring to FIG. 3, the MMI (300) can determine the number of IDs from VME information received through the VME bus (390) and the CPU board (380). Then, the MMI (300) can compare the number of installed option boards (and / or detector boards) with the number of IDs, and if the numbers are different, it can induce the operator to correctly set the IDs by alerting them through a warning sound that the ID settings are duplicated. To this end, the MMI (300) may include an input unit (310), a first buffer unit (310), VME interface logic (330), a sensor unit (340), a processor (350), an alert unit (360), and a second buffer unit (370).

[0050] The input unit (310) may be for receiving information from a user. Such input unit (310) may include a hardware physical key (e.g., button, dome switch, jog wheel, jog switch, etc.) and / or a software touch key.

[0051] The first buffer unit (310) may temporarily store input data, input information, or input signals output from the input unit (310). The first buffer unit (310) may be implemented as a volatile memory such as RAM (random access memory; RAM), SRAM (static random access memory), or a register, etc. However, the present disclosure is not limited thereto.

[0052] The VME interface logic (330) can interface data through the CPU board (380). The VME interface logic (330) can be implemented via RS232, but the present disclosure is not limited thereto. Input data stored in the first buffer unit (310) can be provided to the VME interface logic (330). The VME interface logic (330) receives data through the CPU board (380), and the data received through the VME interface logic (330) can be transmitted to the processor (350). Data output from the processor (350) is transmitted to the VME interface logic (330), and the VME interface logic (330) can transmit data through the CPU board (380). Data stored in the second buffer unit (370) can be provided to the VME interface logic (330).

[0053] The sensor unit (340) may output a detection signal in response to an option board (e.g., OPT (250)) being mounted in a slot. The sensor unit (340) may output a detection signal by measuring a current generated in a portion of the slot that is in contact with the option board. In some embodiments, the detection signal may have a first level or a second level. For example, the first level of the detection signal may be the level of the detection signal generated when the option board is mounted in the slot. The second level of the detection signal may be the level of the detection signal generated when the option board is removed from the slot. However, the present disclosure is not limited thereto. The sensor unit (340) may output at least two detection signals corresponding to each of the at least two slots in response to each of at least two option boards being mounted in each of the at least two slots. For example, when each of three option boards is mounted in a slot, the sensor unit (340) may output three detection signals.

[0054] The processor (350) can receive the at least two detection signals and the board recognition signal. Here, the at least two detection signals received by the processor (350) may be signals that are generated or activated when the option board is mounted in the slot. The processor (350) can determine whether the option board is incorrectly inserted by checking whether the number of IDs of the board recognition signal matches the number of detection signals. The processor (350) can output a control signal based on the determination result.

[0055] The notification unit (360) can perform a notification operation in response to a control signal from the processor (350). In some embodiments, the notification unit (360) can perform at least one of a notification sound output operation that outputs a notification sound and a display operation that displays notification image information. To this end, the notification unit (360) may be equipped with a speaker and / or a display unit. The speaker may emit a warning sound. The display unit may display an error through an LCD window.

[0056] The second buffer unit (370) may temporarily store data processed by the processor (350) and / or notification information output from the notification unit (360). The second buffer unit (370) may be implemented as volatile memory or a register, etc. However, the present disclosure is not limited thereto.

[0057] FIG. 4 is a diagram illustrating an operation for determining whether there is an ID duplication of an option board according to exemplary embodiments of the present disclosure.

[0058] Referring to FIG. 4, the main control unit (400) may include a CPU board (410), first to third slots (420, 430, 440), and an MMI (450). In FIG. 4, the number of slots included in the main control unit (400) is illustrated as three as an example, but the number of slots is not limited thereto.

[0059] The CPU board (410) may correspond to the CPU board (220) of FIG. 2. The CPU board (410), the first option board (421), and the second option board (431) can exchange information with each other through address range data of the VME bus (460). The first option board (421) and the second option board (431) have device IDs for managing the address range of the VME bus (460) by dividing it into seven parts, and for this purpose, the first option board (421) and the second option board (431) may each be equipped with a device ID selection switch. The device ID selection switch may be implemented, for example, as a dial, and a user may specify a number of a specific device ID by operating the dial. Accordingly, the device ID of each option board may be designated or assigned, and each option board may use an address range corresponding to the assigned device ID. It is presupposed that each option board performs a different function from the outset. To this end, each option board must have a unique address range. For example, each of the first option board (421) and the second option board (431) must have different device IDs to have different addresses. That is, for the first option board (421) to be assigned an address range of FFFF0100 - FFFF02FF, the device ID of the first option board (421) must be “Option Board 1,” and for the second option board (431) to be assigned an address range of FFFF0300 - FFFF04FF, the device ID of the second option board (431) must be “Option Board 2.” At this time, the CPU board (410) uses data in the address range FFFF0100 - FFFF02FF set in the first option board (421) to communicate with the first option board (421), and the first option board (421) must respond to the address range FFFF0100 - FFFF02FF.In order for the CPU board (410) to communicate with the second option board (431), it uses data in the address range FFFF0300-FFFF04FF set in the second option board (431), and the second option board (431) must respond to the address range FFFF0300-FFFF04FF. However, if the same device ID is set in two or more option boards and installed in a slot, a problem occurs. For example, with reference to FIG. 4, the device IDs of the first option board (421) and the second option board (431) can each be set to the first ID (ID 1), for example, “Option Board 1”. That is, one user may set the device ID selection switch of the first option board (421) to “Option Board 1” and mount the first option board (421) in the first slot (420), and another user may set the device ID selection switch of the second option board (431) to “Option Board 1” and mount the second option board (431) in the second slot (430). If multiple option boards are each mounted in the slot and at least some of the option boards use the same device ID, when the CPU board (410) reads or writes data at a specific address, multiple option boards using the same device ID respond simultaneously, causing multiple option boards using the same device ID to malfunction. Therefore, it is necessary to set the device IDs of the detector board and the option board so that they do not overlap.

[0060] In FIG. 4, a first option board (421) is mounted in the first slot (420), and a second option board (431) is mounted in the second slot (430), and the device IDs of the first option board (421) and the second option board (431) can be set as the first ID (ID 1). Meanwhile, the third slot (440) may be empty. At this time, the CPU board (410) can determine the number of IDs of the option boards mounted in each slot through VME communication. Specifically, the CPU board (410) can process data within the address range included in each bus data provided from at least two option boards. And, the CPU board (410) can output a board recognition signal (ID_INFO) including the number of IDs of the option boards based on the address range of the data processed through VME communication. For example, during the data processing period, if the CPU board (410) processes data within the same address range, it may output a board recognition signal (ID_INFO) indicating this. The board recognition signal (ID_INFO) includes the number of IDs of the option boards, and in FIG. 4, the number of IDs of the option boards included in the board recognition signal (ID_INFO) may be 1. The data processing period may be the period during which the CPU board (410) processes data within the address range included in each bus data provided from at least two option boards.

[0061] The MMI (450) may correspond to the MMI (230) of FIG. 2 and / or the MMI (300) of FIG. 3. When the MMI (450) knows the number of installed detector boards and / or option boards and the number of IDs recognized by the CPU board (410) via VME communication, the MMI (450) can determine whether the device IDs are duplicated (or whether the option boards are incorrectly inserted). Specifically, the MMI (450) can detect at least two slots among a plurality of slots in which the at least two option boards are installed. For example, referring to FIG. 4, since the first and second option boards (421, 431) are installed in the first and second slots (420, 430), the MMI (450) can detect the first and second slots (420, 430) among the first to third slots (420, 430, 440). The MMI (450) can determine whether an option board is incorrectly inserted based on at least two detection signals generated from at least two slots and a board recognition signal (ID_INFO). The MMI (450) can perform a notification operation based on the determination result. For example, if the first and second option boards (421, 431) are installed and the device IDs of the first and second option boards (421, 431) are the same, the number of installed option boards is 2 and the number of IDs recognized by the CPU board (410) is 1, so the MMI (450) can determine that a duplicate ID has been used and display a warning and an error.

[0062] In some embodiments, the MMI (450) may include an I / O interface (451), a sensor unit (452), and a processor (453).

[0063] The I / O interface (451) can perform communication between the MMI (450) and the CPU board (410). The I / O interface (451) may be implemented, for example, via RS232, but is not limited thereto. In some embodiments, the I / O interface (451) may receive a board recognition signal (ID_INFO) from the CPU board (410) and transmit the board recognition signal (ID_INFO) to the processor (453).

[0064] The sensor unit (452) can output at least two detection signals corresponding to each of the at least two slots in response to each of at least two option boards being mounted in each of the at least two slots. All detector boards and option boards can receive DC power through the backplane. To determine whether an option board is mounted between a slot and a slot, the sensor unit (452) can determine the amount of current consumed supplied through the backplane. That is, when power supplied through the backplane is supplied to the MMI (450) and the sensor unit (452) measures the current, the processor (453) can determine the number of mounted option boards (and / or detector boards). In some embodiments, the sensor unit (452) may include at least one sensor. Each sensor can sense the amount of current consumed to determine whether an option board is mounted between a slot and a slot. The number of sensors may correspond to the number of slots. For example, the sensor unit (452) may include first to third sensors (452_1, 452_2, 452_3). The first sensor (452_1) may detect whether any option board is mounted in the first slot (420). In some embodiments, the first sensor (452_1) may output a first detection signal (SEN1) in response to the first option board (421) being mounted in the first slot (420). For example, when the first option board (421) is mounted in the first slot (420), the first sensor (452_1) may output the first detection signal (SEN1) to the processor (453). The second sensor (452_2) may detect whether any option board is mounted in the second slot (430). In some embodiments, the second sensor (452_2) may output a second detection signal (SEN2) in response to the second option board (431) being mounted in the second slot (430). For example, when the second option board (431) is mounted in the second slot (430), the second sensor (452_2) may output the second detection signal (SEN2) to the processor (453).The third sensor (452_3) can detect whether any option board is mounted in the third slot (440). For example, if any option board is mounted in the third slot (440), the third sensor (452_3) can output a third detection signal (SEN3) to the processor (453). In FIG. 4, since the third slot (440) is empty, the third sensor (452_3) may not output the third detection signal (SEN3). In some embodiments, when any option board is mounted in the slot, a detection signal having an activated level may be output. However, it is not limited thereto. In other embodiments, if the slot is empty, a detection signal having a first level may be output, and if any option board is mounted in the slot, a detection signal having a second level different from the first level may be output. That is, in FIG. 4, the third detection signal (SEN3) may have an inactive level.

[0065] The processor (453) can receive at least two detection signals and a board recognition signal (ID_INFO). For example, with reference to FIG. 4, the processor (453) can receive a board recognition signal (ID_INFO) generated by the CPU board (410) through the I / O interface (451). The processor (453) can also receive a board recognition signal (ID_INFO) generated by the CPU board (410) through the I / O interface (451). Furthermore, the processor (453) can receive first to third detection signals (SEN1, SEN2, SEN3) from first to third sensors (452_1, 452_2, 452_3). At this time, since the third slot (440) is empty, the first and second detection signals (SEN1, SEN2) may have an active level and the third detection signal (SEN3) may have an inactive level. The processor (453) can determine whether the ID of the option board is duplicated by checking whether the number of IDs in the board recognition signal (ID_INFO) matches the number of detection signals. At this time, the number of detection signals may be the number of detection signals having an active level. For example, referring to FIG. 4, the number of IDs in the board recognition signal (ID_INFO) is 1 and the number of detection signals having an active level is 2, so the number of IDs and the number of detection signals do not match. Therefore, the processor (453) can determine that the option board has a duplicate device ID.

[0066] In some embodiments, a detection signal may be generated when any option board is mounted in the slot, and a detection signal may not be generated when the slot is empty. In this case, the processor (453) may output a control signal when it receives a board recognition signal (ID_INFO), a first detection signal (SEN1), and a second detection signal (SEN2).

[0067] FIG. 5 is a flowchart for explaining the operation method of a traffic signal control device of the present disclosure.

[0068] Referring to FIG. 5, a step of detecting at least two slots among a plurality of slots in which at least two option boards are mounted is performed (S100). Step S100 can be performed by the sensor unit (452) of FIG. 4.

[0069] During a data processing period for processing data within an address range included in each bus data provided from at least two option boards, a step of outputting a board recognition signal including the number of IDs of the option boards based on the address range of the processed data is performed (S200). Step S200 can be performed by the CPU board (410) of FIG. 4.

[0070] A step of determining whether the option board is incorrectly inserted is performed based on the detection signal of each of the at least two detected slots and the board recognition signal (S300). Step S300 can be performed by the processor (453) of FIG. 4.

[0071] In some embodiments of step S300, step S300 outputs the control signal when it receives the board recognition signal, the first detection signal, and the second detection signal. The description thereof is the same as the example described above with reference to FIG. 4.

[0072] A step of performing a notification action based on the judgment result is performed (S400). Step S400 can be performed by the processor (453) of FIG. 4 and the notification unit (360) of FIG. 3.

[0073] FIG. 6 is a flowchart illustrating some embodiments of step S100 of FIG. 5.

[0074] Referring to FIG. 6, a step of outputting a first detection signal in response to the first option board being mounted in the first slot is performed (S110). Step S110 can be performed by the first sensor (452_1) of FIG. 4.

[0075] In response to the second option board being mounted in the second slot, a step of outputting a second detection signal is performed (S110). Step S110 can be performed by the second sensor (452_2) of FIG. 4.

[0076] FIG. 7 is a flowchart illustrating some embodiments of step S200 of FIG. 5.

[0077] Referring to FIG. 7, a step of processing data within the first address range of the first option board for a predetermined period of time or longer during the data processing period is performed (S210). For example, referring to FIG. 4, during the data processing period, the CPU board (410) can process data within the first address range of the first option board (421) for a predetermined period of time or longer.

[0078] A step of processing data within the first address range of the second option board for a certain period of time or longer is performed (S220). For example, with reference to FIG. 4, the CPU board (410) can process data within the first address range of the second option board (431) for a certain period of time or longer.

[0079] A step of outputting a board recognition signal is performed (S230). For example, referring to FIG. 4, since the CPU board (410) has processed data within the same address range (e.g., within the first address range) of the first option board (421) and the second option board (431) for a certain period of time or longer during the data processing period, the CPU board (410) may output a board recognition signal (ID_INFO). At this time, the number of IDs of the option boards included in the board recognition signal (ID_INFO) may be 1.

[0080] FIG. 8 is a flowchart illustrating some embodiments of step S400 of FIG. 5.

[0081] Referring to FIG. 8, a step of performing an alert sound output operation to output an alert sound is performed (S410). For example, referring to FIG. 3, the speaker of the alert unit (360) can perform an alert sound output operation by outputting an alert sound in response to a control signal from the processor (350).

[0082] A step of performing a display operation to display notification image information is performed (S410). For example, with reference to FIG. 3, the display unit of the notification unit (360) can perform a display operation by displaying an error through an LCD window in response to a control signal from the processor (350).

[0083] Steps S410 and S420 may be performed sequentially, or steps S410 and S420 may be performed in parallel (i.e., simultaneously).

[0084] Meanwhile, the disclosed embodiments may be implemented in the form of a recording medium that stores instructions executable by a computer. The instructions may be stored in the form of program code and, when executed by a processor, may generate a program module to perform the operation of the disclosed embodiments. The recording medium may be implemented as a computer-readable recording medium.

[0085] Computer-readable recording media include all types of recording media that store instructions that can be decoded by a computer. Examples include ROM (Read Only Memory), RAM (Random Access Memory), magnetic tape, magnetic disk, flash memory, optical data storage devices, etc.

[0086] As described above, the disclosed embodiments have been explained with reference to the attached drawings. Those skilled in the art will understand that the present disclosure may be practiced in forms different from the disclosed embodiments without changing the technical spirit or essential features of the present disclosure. The disclosed embodiments are illustrative and should not be interpreted restrictively. Explanation of the symbols delete

Claims

Claim 1 A plurality of slots; a CPU (Central Processing Unit) board configured to process data within an address range included in each bus data provided from at least two option boards, and configured to output a board recognition signal including the number of IDs of option boards based on the address range of data processed via VME (VERSA Module Eurocard) communication; A traffic signal control device comprising: a Man-Machine Interface (MMI) configured to detect at least two slots among the plurality of slots in which at least two option boards are mounted, configured to determine whether the ID of the option board is duplicated based on at least two detection signals generated from the at least two slots and the board recognition signal, and configured to perform a notification operation according to the determination result; wherein the MMI comprises: a sensor unit that outputs at least two detection signals corresponding to each of the at least two slots in response to each of the at least two option boards being mounted in each of the at least two slots; a processor that receives the at least two detection signals and the board recognition signal, determines whether the ID of the option board is duplicated by verifying whether the number of IDs in the board recognition signal matches the number of detection signals, and outputs a control signal based on the determination result; and a notification unit that performs the notification operation in response to the control signal. Claim 2 delete Claim 3 A traffic signal control device according to claim 1, wherein the sensor unit comprises: a first sensor that outputs a first detection signal in response to a first option board being mounted in a first slot; and a second sensor that outputs a second detection signal in response to a second option board being mounted in a second slot. Claim 4 A traffic signal control device according to claim 3, wherein the processor outputs the control signal when it receives the board recognition signal, the first detection signal, and the second detection signal. Claim 5 A traffic signal control device according to claim 4, wherein the notification unit performs the notification operation by performing at least one of a notification sound output operation that outputs a notification sound and a display operation that displays notification image information. Claim 6 A method of operation of a traffic signal control device comprising: detecting at least two slots equipped with at least two option boards among a plurality of slots; outputting a board recognition signal including the number of IDs of the option boards based on the address range of the processed data during a data processing period for processing data within the address range included in each bus data provided from the at least two option boards; determining whether the IDs of the option boards are duplicated based on the detection signal of each of the at least two detected slots and the board recognition signal; and performing a notification operation according to the determination result, wherein the step of determining whether the IDs are duplicated includes, for at least two detection signals and the board recognition signal, determining whether the number of IDs of the board recognition signal matches the number of detection signals, and outputting a control signal instructing a notification operation based on the determination result. Claim 7 A method of operation of a traffic signal control device according to claim 6, wherein the detecting step comprises: a step of outputting a first detection signal in response to a first option board being mounted in a first slot; and a step of outputting a second detection signal in response to a second option board being mounted in a second slot. Claim 8 A method of operation of a traffic signal control device according to claim 7, wherein the step of outputting the board recognition signal comprises: a step of processing data within the first address range of the first option board for a predetermined period of time or longer during the data processing period; a step of processing data within the first address range of the second option board for a predetermined period of time or longer; and a step of outputting the board recognition signal. Claim 9 A method of operation of a traffic signal control device according to claim 8, wherein the step of determining whether the ID is duplicated is characterized by outputting the control signal when the board recognition signal, the first detection signal, and the second detection signal are received. Claim 10 A method of operation of a traffic signal control device according to claim 6, wherein the step of performing the notification operation comprises: a step of performing a notification sound output operation for outputting a notification sound; and a step of performing a display operation for displaying notification image information.

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